IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI 256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE 'NO WAIT' STATE BUS SRAM ® JULY 2006 FEATURES DESCRIPTION • 100 percent bus utilization The 18 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M words by 18 bits, fabricated with ISSI's advanced CMOS technology. • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 165-ball PBGA and 209ball (x72) PBGA packages • Power supply: NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%) • JTAG Boundary Scan for PBGA packages Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. • Industrial temperature available • Lead-free available FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -250 2.6 4 250 -200 3.1 5 200 Units ns ns MHz Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 1 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® BLOCK DIAGRAM x 72: A [0:17] or x 36: A [0:18] or x 18: A [0:19] ADDRESS REGISTER A2-A17 or A2-A18 or A2-A19 MODE A0-A1 CLK CONTROL LOGIC K CKE WRITE ADDRESS REGISTER BURST ADDRESS COUNTER 256Kx72; 512Kx36; 1024Kx18 MEMORY ARRAY A'0-A'1 WRITE ADDRESS REGISTER K DATA-IN REGISTER K DATA-IN REGISTER CE CE2 CE2 ADV WE BWŸX } CONTROL REGISTER K CONTROL LOGIC (X=a,b,c,d or a,b) OUTPUT REGISTER BUFFER OE ZZ 72, 36 or 18 DQx/DQPx 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® Bottom View 165-Ball, 13 mm x 15mm BGA 1 mm Ball Pitch, 11 x 15 Ball Array Bottom View 209-Ball, 14 mm x 22 mm BGA 1 mm Ball Pitch, 11 x 19 Ball Array Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 3 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI PIN CONFIGURATION — 256K X 72, 209-Ball PBGA (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A DQg DQg A CE2 A ADV A CE2 A DQb DQb B DQg DQg BWc BWg NC WE A BWb BWf DQb DQb C DQg DQg BWh BWd NC CE NC BWe BWa DQb DQb D DQg DQg VSS NC NC OE NC NC VSS DQb DQb E DQPg DQPc VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPf DQPb F DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf G DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf H DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf J DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf K NC NC CLK NC VSS CKE VSS NC NC NC NC L DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa M DQh DQh VSS VSS VSS NC VSS VSS VSS DQa DQa N DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa P DQh DQh VSS VSS VSS ZZ VSS VSS VSS DQa DQa R DQPd DQPh VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPa DQPe T DQd DQd VSS NC NC MODE NC NC VSS DQe DQe U DQd DQd NC A NC A NC A NC DQe DQe V DQd DQd A A A A1 A A A DQe DQe W DQd DQd TMS TDI A A0 A TDO TCK DQe DQe ® 11 x 19 Ball BGA—14 x 22 mm2 Body—1 mm Ball Pitch PIN DESCRIPTIONS Symbol Pin Name VSS Ground A Synchronous Address Inputs MODE Burst Sequence Selection A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. OE Output Enable TCK, TDI TDO, TMS JTAG Pins ADV Synchronous Burst Address Advance VDD 3.3V/2.5V Power Supply BWa-BWh Synchronous Byte Write Enable VDDQ Isolated Output Buffer Supply: 3.3V/2.5V CE, CE2, CE2 Synchronous Chip Enable 4 CLK Synchronous Clock WE Write Enable CKE Clock Enable ZZ Snooze Enable DQx Synchronous Data Input/Output DQPx Parity Data I/O Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® PIN CONFIGURATION — 512K X 36, 165-Ball PBGA (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A CE BWc BWb CE2 CKE ADV A A NC B NC A CE2 BWd BWa CLK WE OE A A NC C DQPc NC VDDQ V SS V SS V SS V SS V SS VDDQ NC DQPb D DQc DQc VDDQ VDD V SS V SS V SS VDD VDDQ DQb DQb E DQc DQc VDDQ VDD V SS V SS V SS VDD VDDQ DQb DQb F DQc DQc VDDQ VDD V SS V SS V SS VDD VDDQ DQb DQb G DQc DQc VDDQ VDD V SS V SS V SS VDD VDDQ DQb DQb H NC VDD NC VDD V SS V SS V SS VDD NC NC ZZ J DQd DQd VDDQ VDD V SS V SS V SS VDD VDDQ DQa DQa K DQd DQd VDDQ VDD V SS V SS V SS VDD VDDQ DQa DQa L DQd DQd VDDQ VDD V SS V SS V SS VDD VDDQ DQa DQa M DQd DQd VDDQ VDD V SS V SS V SS VDD VDDQ DQa DQa N DQPd NC VDDQ V SS NC NC NC V SS VDDQ NC DQPa P NC NC A A TDI A1* TDO A A A NC R MODE NC A A TMS A0* TCK A A A A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol Pin Name MODE Burst Sequence Selection A Address Inputs JTAG Pins A0, A1 Synchronous Burst Address Inputs TCK, TDI TDO, TMS ADV Synchronous Burst Address Advance/ Load VDD 3.3V/2.5V Power Supply NC No Connect WE Synchronous Read/Write Control Input DQx Data Inputs/Outputs DQPx Parity Data I/O CLK Synchronous Clock VDDQ CKE Clock Enable Isolated output Power Supply 3.3V/2.5V VSS Ground CE, CE2, CE2 Synchronous Chip Enable BWx (x=a-d) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 5 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI 165-PIN PBGA PACKAGE CONFIGURATION ® 1024K x 18 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A BWb NC CE2 CKE ADV A NC A NC NC VDDQ BWa Vss CLK Vss WE Vss VDDQ NC NC DQPa D NC DQb VDDQ VDD Vss Vss Vss OE Vss VDD A C NC Vss A A A B CE CE2 VDDQ NC DQa E NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa F NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa G NC DQb VDDQ Vss NC NC NC ZZ J DQb NC VDDQ VDD Vss Vss VDD VDD DQa VDD Vss Vss NC NC Vss Vss VDDQ H VDD VDD Vss Vss VDD VDDQ DQa NC K DQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa L DQb NC VDDQ VDD Vss Vss VDD VDDQ DQa M DQb NC VDDQ VDD Vss Vss Vss NC NC Vss VDD VDDQ DQa NC N DQPb NC Vss NC TDO A A NC R MODE NC A A TMS A1* A0* VDDQ A NC NC NC TDI NC NC Vss A NC P VDDQ A TCK A A A A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol Pin Name MODE Burst Sequence Selection A Address Inputs JTAG Pins A0, A1 Synchronous Burst Address Inputs TCK, TDI TDO, TMS ADV Synchronous Burst Address Advance/ Load VDD 3.3V/2.5V Power Supply NC No Connect WE Synchronous Read/Write Control Input DQx Data Inputs/Outputs DQPx Parity Data I/O CLK Synchronous Clock VDDQ CKE Clock Enable Isolated output Power Supply 3.3V/2.5V VSS Ground CE, CE2, CE2 Synchronous Chip Enable 6 BWx (x=a,b) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® PIN CONFIGURATION DQb DQa DQb VDDQ VDDQ Vss DQa Vss DQb DQa DQb DQa DQa Vss DQPb NC VDDQ VDDQ DQa DQa DQPa NC NC NC Vss A ADV A OE CKE CLK WE CE2 VDD Vss BWa NC BWb NC CE2 CE A A A NC NC VDDQ Vss NC DQPa DQa DQa Vss VDDQ DQa DQa Vss VDD VDD ZZ DQa DQa VDDQ Vss DQa DQa NC NC Vss VDDQ NC NC NC A A DQa VDD Vss A DQb VDD VDD A DQb DQb Vss VDD VDD ZZ A DQb A VDDQ NC A Vss VDDQ NC DQb VDD Vss DQb Vss DQb NC NC NC NC MODE DQd DQd DQPd DQb Vss A1 A0 VDDQ DQb DQb VDDQ A DQd DQd Vss Vss NC A DQd VDDQ NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A Vss DQd DQb NC A VDDQ DQb MODE DQd DQPb A A DQd A Vss A VDD A DQc VDD VDD A DQc NC A VDDQ NC Vss VDD DQc Vss DQc NC NC DQc DQc A1 A0 Vss A VDDQ A DQc A DQc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A DQPc A A A A A ADV A OE CKE CLK WE CE2 VDD Vss BWa BWc BWb BWd CE2 CE A A 100-Pin TQFP 1M x 18 512K x 36 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A Synchronous Address Inputs CLK Synchronous Clock ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable WE Write Enable CKE Clock Enable Vss Ground for Core NC Not Connected CE, CE2, CE2 Synchronous Chip Enable OE Output Enable DQa-DQd Synchronous Data Input/Output DQPa-DQPd Parity Data I/O MODE Burst Sequence Selection VDD +3.3V/2.5V Power Supply VSS Ground for output Buffer VDDQ Isolated Output Buffer Supply: +3.3V/2.5V ZZ Snooze Enable Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 7 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® STATE DIAGRAM READ READ READ BURST WRITE BEGIN READ DS READ WRITE DESELECT BURST BURST READ BEGIN WRITE DS BURST DS BURST DS DS WRITE BURST WRITE READ WRITE WRITE BURST SYNCHRONOUS TRUTH TABLE(1) Operation Not Selected Not Selected Not Selected Not Selected Continue Begin Burst Read Continue Burst Read NOP/Dummy Read Dummy Read Begin Burst Write Continue Burst Write NOP/Write Abort Write Abort Ignore Clock Notes: Address Used CE CE2 CE CE2 ADV WE BW BWx OE CKE CLK N/A N/A N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address H X X X L X L X L X L X X X L X X H X H X H X H X X X X H X L X L X L X L X X L L L H L H L H L H L H X X X X X H X H X L X L X X X X X X X X X X L L H H X X X X X L L H H X X X X X L L L L L L L L L L L L H ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1. 2. 3. 4. "X" means don't care. The rising edge of clock is symbolized by ↑ A continue deselect cycle can only be entered if a deselect cycle is executed first. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE). 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® ASYNCHRONOUS TRUTH TABLE(1) Operation ZZ OE I/O STATUS Sleep Mode H L L L L X L H X X High-Z DQ High-Z Din, High-Z High-Z Read Write Deselected Notes: 1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time. WRITE TRUTH TABLE (x18) Operation READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE BW BWa BW BWb H L L L L X L H L H X H L L H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. WRITE TRUTH TABLE (x36) Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE BW BWa BW BWb BW BWc BW BWd H L L L L L L X L H H H L H X H L H H L H X H H L H L H X H H H L L H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 9 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® WRITE TRUTH TABLE (x72) WE BW BWa BW BWb BW BWc BW BWd BW BWe BW BWf BW BWg BW BWh READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE BYTE e WRITE BYTE f WRITE BYTE g WRITE BYTE h WRITE ALL BYTEs H L L L L L L L L L X L H H H H H H H L X H L H H H H H H L X H H L H H H H H L X H H H L H H H H L X H H H H L H H H L X H H H H H L H H L X H H H H H H L H L X H H H H H H H L L WRITE ABORT/NOP Notes: L H H H H H H H H Operation 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC) External Address A1 A0 1st Burst Address A1 A0 2nd Burst Address A1 A0 3rd Burst Address A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® LINEAR BURST ADDRESS TABLE (MODE = VSS) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TSTG PD IOUT VIN, VOUT VIN Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to VSS for I/O Pins Voltage Relative to VSS for for Address and Control Inputs Value –65 to +150 1.6 100 –0.5 to VDDQ + 0.3 –0.3 to 4.6 Unit °C W mA V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. OPERATING RANGE (IS61NLPx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C VDD 3.3V ± 5% 3.3V ± 5% VDDQ 3.3V / 2.5V ± 5% 3.3V / 2.5V ± 5% VDD 2.5V ± 5% 2.5V ± 5% VDDQ 2.5V ± 5% 2.5V ± 5% OPERATING RANGE (IS61NVPx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 11 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 3.3V 2.5V Symbol Parameter Test Conditions Min. Max. Min. Max. Unit VOH Output HIGH Voltage IOH = –4.0 mA (3.3V) IOH = –1.0 mA (2.5V) 2.4 — 2.0 — V VOL Output LOW Voltage IOL = 8.0 mA (3.3V) IOL = 1.0 mA (2.5V) — 0.4 — 0.4 V VIH Input HIGH Voltage 2.0 VDD + 0.3 1.7 VDD + 0.3 V VIL Input LOW Voltage –0.3 0.8 –0.3 0.7 V ILI Input Leakage Current VSS ≤ VIN ≤ VDD(1) –5 5 –5 5 µA ILO Output Leakage Current VSS ≤ VOUT ≤ VDDQ, OE = VIH –5 5 –5 5 µA POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Temp. range x18 -250 MAX x36 x72 x18 -200 MAX x36 x72 Unit Symbol Parameter Test Conditions ICC AC Operating Supply Current Device Selected, Com. OE = VIH, ZZ ≤ VIL, Ind. All Inputs ≤ 0.2V or ≥ VDD – 0.2V, Cycle Time ≥ tKC min. 450 500 450 500 600 650 425 475 425 475 550 600 mA ISB Standby Current TTL Input Device Deselected, VDD = Max., All Inputs ≤ VIL or ≥ VIH, ZZ ≤ VIL, f = Max. Com. Ind. 150 150 150 150 150 150 150 150 150 150 150 150 mA ISBI Standby Current CMOS Input Device Deselected, Com. VDD = Max., Ind. VIN ≤ VSS + 0.2V or ≥VDD – 0.2V f=0 110 125 110 125 110 125 110 125 110 125 110 125 mA ISB2 Sleep Mode ZZ>VIH 60 75 60 75 60 75 60 75 60 75 60 75 mA Com. Ind. Note: 1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits ±100µA maximum leakage current when tied to ≤ VSS + 0.2V or ≥ VDD – 0.2V. 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 3.3V I/O OUTPUT LOAD EQUIVALENT 317 Ω +3.3V Zo= 50Ω OUTPUT OUTPUT 5 pF Including jig and scope 50Ω 351 Ω 1.5V Figure 1 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 Figure 2 13 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 Ω +2.5V ZO = 50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 1,538 Ω 1.25V Figure 3 14 Figure 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -250 Min. Max. -200 Min. Max. Symbol Parameter fmax Clock Frequency — 250 — 200 MHz tKC Cycle Time 4.0 — 5 — ns tKH Clock High Time 1.7 — 2 — ns tKL Clock Low Time 1.7 — 2 — ns Clock Access Time — 2.6 — 3.1 ns Clock High to Output Invalid 0.8 — 1.5 — ns tKQLZ Clock High to Output Low-Z 0.8 — 1 — ns tKQHZ(2,3) Clock High to Output High-Z — 2.6 — 3.0 ns tOEQ tKQ tKQX (2) (2,3) Unit Output Enable to Output Valid — 2.8 — 3.1 ns (2,3) Output Enable to Output Low-Z 0 — 0 — ns (2,3) tOEHZ Output Disable to Output High-Z — 2.6 — 3.0 ns tAS Address Setup Time 1.2 — 1.4 — ns tWS Read/Write Setup Time 1.2 — 1.4 — ns tCES Chip Enable Setup Time 1.2 — 1.4 — ns tSE Clock Enable Setup Time 1.2 — 1.4 — ns tADVS Address Advance Setup Time 1.2 — 1.4 — ns tDS Data Setup Time 1.2 — 1.4 — ns tAH Address Hold Time 0.3 — 0.4 — ns tHE Clock Enable Hold Time 0.3 — 0.4 — ns tWH Write Hold Time 0.3 — 0.4 — ns tCEH Chip Enable Hold Time 0.3 — 0.4 — ns tADVH Address Advance Hold Time 0.3 — 0.4 — ns tDH Data Hold Time 0.3 — 0.4 — ns tPDS ZZ High to Power Down — 2 — 2 cyc tPUS ZZ Low to Power Down — 2 — 2 cyc tOELZ Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 15 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® SLEEP MODE ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Min. ISB2 Current during SLEEP MODE tPDS ZZ active to input ignored 2 cycle tPUS ZZ inactive to input sampled 2 cycle tZZI ZZ active to SLEEP current 2 cycle tRZZI ZZ inactive to exit SLEEP current 0 ns ZZ ≥ VIH Max. Unit 60 mA SLEEP MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care 16 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® READ CYCLE TIMING tKH tKL CLK tKC tADVS tADVH ADV tAS tAH Address A1 A3 A2 tWS tWH WRITE tSE tHE CKE tCES tCEH CE OE tOEQ tOEHZ tKQX tKQ tKQHZ tOEHZ Data Out Q1-1 Q2-1 Q2-2 Q2-3 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 Q2-4 Q3-1 Q3-2 Q3-3 Q3-4 Don't Care Undefined 17 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® WRITE CYCLE TIMING tKH tKL CLK tKC ADV Address A1 A3 A2 WRITE tSE tHE CKE CE OE tDS Data In D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 tDH D3-2 D3-3 D3-4 tOEHZ Data Out Q0-3 Q0-4 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 18 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® SINGLE READ/WRITE CYCLE TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 Q1 Q3 A5 A6 A7 A8 A9 WRITE CE ADV OE tOEQ tOELZ Data Out Q4 Q6 Q7 tDS tDH Data In D2 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 D5 Don't Care Undefined 19 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® CKE OPERATION TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 A6 WRITE CE ADV OE tKQ tKQHZ tKQLZ Data Out Q1 Q3 Q4 tDS tDH Data In D2 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 20 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® CE OPERATION TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 WRITE CE ADV OE tOEQ tKQHZ tKQ tKQLZ tOELZ Data Out Q1 Q2 Q4 tDS tDH Data In D3 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 D5 Don't Care Undefined 21 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) TEST ACCESS PORT (TAP) - TEST CLOCK The IS61NLP and IS61NVP have a serial boundary scan Test Access Port (TAP) in the PBGA package only. (Not available in TQFP package.) This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels. The test clock is only used with the TAP controller. All inputs are captured on the rising edge of TCK and outputs are driven from the falling edge of TCK. DISABLING THE JTAG FEATURE The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be disconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left disconnected. On power-up, the device will start in a reset state which will not interfere with the device operation. TEST MODE SELECT (TMS) The TMS input is used to send commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left disconnected if the TAP is not used. The pin is internally pulled up, resulting in a logic HIGH level. TEST DATA-IN (TDI) The TDI pin is used to serially input information to the registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the instruction loaded into the TAP instruction register. For information on instruction register loading, see the TAP Controller State Diagram. TDI is internally pulled up and can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. TAP CONTROLLER BLOCK DIAGRAM 0 Bypass Register 2 1 0 Instruction Register TDI Selection Circuitry Selection Circuitry 31 30 29 . . . 2 1 0 2 1 0 TDO Identification Register x . . . . . Boundary Scan Register* TCK TMS 22 TAP CONTROLLER Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® TEST DATA OUT (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register. PERFORMING A TAP RESET A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes up in a high-Z state. TAP REGISTERS Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK. is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 75-bit-long register and the x18 configuration also has a 75-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Scan Register Sizes Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins. (See TAP Controller Block Diagram) At power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as previously described. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register Register Name Bit Size (x18) Bit Size (x36) Bit Size (x72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan 75 75 TBD Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded to the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has vendor code and other information described in the Identification Register Definitions table. IDENTIFICATION REGISTER DEFINITIONS Instruction Field Description 256K x 72 512K x 36 1M x 18 Revision Number (31:28) Reserved for version number. xxxx xxxx xxxx Device Depth (27:23) Defines depth of SRAM. 512K or 1M 00110 00111 01000 Device Width (22:18) Defines width of the SRAM. x72, x36 or x18 00101 00100 00011 ISSI Device ID (17:12) Reserved for future use. xxxx xxxxx xxxxx ISSI JEDEC ID (11:1) Allows unique identification of SRAM vendor. 0011010101 00011010101 00011010101 ID Register Presence (0) Indicate the presence of an ID register. 1 1 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 1 23 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® TAP INSTRUCTION SET SAMPLE/PRELOAD Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; instead it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state. SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock runs more than an order of magnitude faster. Because of the clock frequency differences, it is possible that during the Capture-DR state, an input or output will under-go a transition. The TAP may attempt a signal capture while in transition (metastable state). The device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. To guarantee that the boundary scan register will capture the correct signal value, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (tCS and tCH). To insure that the SRAM clock input is captured correctly, designs need a way to stop (or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is not an issue, it is possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. Because EXTEST is not implemented in the TAP controller, this device is not 1149.1 standard compliant. The TAP controller recognizes an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is a difference between the instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE-Z The SAMPLE-Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. 24 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. RESERVED These instructions are not implemented but are reserved for future use. Do not use these instructions. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® INSTRUCTION CODES Code Instruction Description 000 EXTEST Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. 001 IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. 010 SAMPLE-Z Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. 011 RESERVED Do Not Use: This instruction is reserved for future use. 100 SAMPLE/PRELOAD 101 RESERVED Do Not Use: This instruction is reserved for future use. 110 RESERVED Do Not Use: This instruction is reserved for future use. 111 BYPASS Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. TAP CONTROLLER STATE DIAGRAM Test Logic Reset 1 0 Run Test/Idle 1 Select DR 0 0 1 1 1 Capture DR 0 Shift DR 1 Exit1 DR 0 Select IR 0 1 Exit1 IR 0 Pause DR 0 1 0 1 Exit2 DR 1 Update DR 0 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 Capture IR 0 Shift IR 1 0 Pause IR 1 0 1 1 0 1 0 Exit2 IR 1 Update IR 0 25 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® TAP Electrical Characteristics Over the Operating Range(1,2) Symbol Parameter Test Conditions Min. Max. Units VOH1 Output HIGH Voltage IOH = –2.0 mA 1.7 — V VOH2 Output HIGH Voltage IOH = –100 µA 2.1 — V VOL1 Output LOW Voltage IOL = 2.0 mA — 0.7 V VOL2 Output LOW Voltage IOL = 100 µA — 0.2 V VIH Input HIGH Voltage 1.7 VDD +0.3 V VIL Input LOW Voltage –0.3 0.7 V IX Input Leakage Current –10 10 µA VSS ≤ V I ≤ VDDQ Notes: 1. All Voltage referenced to Ground. 2. Overshoot: VIH (AC) ≤ VDD +1.5V for t ≤ tTCYC/2, Undershoot: VIL (AC) ≤ 0.5V for t ≤ tTCYC/2, Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms. TAP AC ELECTRICAL CHARACTERISTICS(1,2) (OVER OPERATING RANGE) Symbol Parameter Min. Max. Unit tTCYC TCK Clock cycle time 100 — ns fTF TCK Clock frequency — 10 MHz tTH TCK Clock HIGH 40 — ns tTL TCK Clock LOW 40 — ns tTMSS TMS setup to TCK Clock Rise 10 — ns tTDIS TDI setup to TCK Clock Rise 10 — ns tCS Capture setup to TCK Rise 10 — ns tTMSH TMS hold after TCK Clock Rise 10 — ns tTDIH TDI Hold after Clock Rise 10 — ns tCH Capture hold after Clock Rise 10 — ns tTDOV TCK LOW to TDO valid — 20 ns tTDOX TCK LOW to TDO invalid 0 — ns Notes: 1. Both tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. 26 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI TAP AC TEST CONDITIONS (2.5V/3.3V) Input pulse levels ® TAP Output Load Equivalent 0 to 2.5V/0 to 3.0V Input rise and fall times 1ns Input timing reference levels 1.25V/1.5V Output reference levels 1.25V/1.5V Test load termination supply voltage 1.25V/1.5V Vtrig 1.25V/1.5V 50Ω Vtrig TDO Z0 = 50Ω 20 pF GND TAP TIMING 1 2 tTHTH 3 4 5 6 tTLTH TCK tTHTL tMVTH tTHMX TMS tDVTH tTHDX TDI tTLOV TDO tTLOX DON'T CARE UNDEFINED Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 27 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® 209 BOUNDARY SCAN ORDER (256K X 72) 28 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® 165 PBGA BOUNDARY SCAN ORDER (x 36) Bit # Signal Bump Name ID Bit # Signal Name Bump ID Bit # Signal Name Bump ID Bit # Signal Name Bump ID 1 MODE 1R 21 DQb 11G 41 NC 1A 61 DQd 1J 2 NC 6N 22 DQb 11F 42 CE2 6A 62 DQd 1K 3 NC 11P 23 DQb 11E 43 BWa 5B 63 DQd 1L 4 A 8P 24 DQb 11D 44 BWb 5A 64 DQd 1M 5 A 8R 25 DQb 10G 45 BWc 4A 65 DQd 2J 6 A 9R 26 DQb 10F 46 BWd 4B 66 DQd 2K 7 A 9P 27 DQb 10E 47 CE2 3B 67 DQd 2L 8 A 10P 28 DQb 10D 48 CE 3A 68 DQd 2M 9 A 10R 29 DQb 11C 49 A 2A 69 DQd 1N 10 A 11R 30 NC 11A 50 A 2B 70 A 3P 11 ZZ 11H 31 A 10A 51 NC 1B 71 A 3R 12 DQa 11N 32 A 10B 52 DQc 1C 72 A 4R 13 DQa 11M 33 A 9A 53 DQc 1D 73 A 4P 14 DQa 11L 34 A 9B 54 DQc 1E 74 A1 6P 15 DQa 11K 35 ADV 8A 55 DQc 1F 75 A0 6R 16 DQa 11J 36 OE 8B 56 DQc 1G 17 DQa 10M 37 CKE 7A 57 DQc 2D 18 DQa 10L 38 WE 7B 58 DQc 2E 19 DQa 10K 39 CLK 6B 59 DQc 2F 20 DQa 10J 40 NC 11B 60 DQc 2G Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 29 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® 165 PBGA BOUNDARY SCAN ORDER (x 18) Bit # Signal Bump Name ID Bit # Signal Name Bump ID Bit # Signal Name Bump ID Bit # Signal Name Bump ID 1 MODE 1R 21 DQa 11G 41 NC 1A 61 DQb 1J 2 NC 6N 22 DQa 11F 42 CE2 6A 62 DQb 1K 3 NC 11P 23 DQa 11E 43 BWa 5B 63 DQb 1L 4 A 8P 24 DQa 11D 44 NC 5A 64 DQb 1M 5 A 8R 25 DQa 11C 45 BWb 4A 65 DQb 1N 6 A 9R 26 NC 10F 46 NC 4B 66 NC 2K 7 A 9P 27 NC 10E 47 CE2 3B 67 NC 2L 8 A 10P 28 NC 10D 48 CE 3A 68 NC 2M 9 A 10R 29 NC 10G 49 A 2A 69 NC 2J 10 A 11R 30 A 11A 50 A 2B 70 A 3P 11 ZZ 11H 31 A 10A 51 NC 1B 71 A 3R 12 NC 11N 32 A 10B 52 NC 1C 72 A 4R 13 NC 11M 33 A 9A 53 NC 1D 73 A 4P 14 NC 11L 34 A 9B 54 NC 1E 74 A1 6P 15 NC 11K 35 ADV 8A 55 NC 1F 75 A0 6R 16 NC 11J 36 OE 8B 56 NC 1G 17 DQa 10M 37 CKE 7A 57 DQb 2D 18 DQa 10L 38 WE 7B 58 DQb 2E 19 DQa 10K 39 CLK 6B 59 DQb 2F 20 DQa 10J 40 NC 11B 60 DQb 2G 30 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® ORDERING INFORMATION (3.3V core/2.5V- 3.3V I/O) Commercial Range: 0°C to +70°C Configuration Access Time Order Part Number Package 250 IS61NLP25672-250B1 209 PBGA 200 IS61NLP25672-200B1 209 PBGA 250 IS61NLP51236-250TQ IS61NLP51236-250B3 100 TQFP 165 PBGA 200 IS61NLP51236-200TQ 100 TQFP IS61NLP51236-200B3 165 PBGA 250 IS61NLP102418-250TQ IS61NLP102418-250B3 100 TQFP 165 PBGA 200 IS61NLP102418-200TQ IS61NLP102418-200B3 100 TQFP 165 PBGA Order Part Number Package 250 IS61NLP25672-250B1I 209 PBGA 200 IS61NLP25672-200B1I 209 PBGA 250 IS61NLP51236-250TQI IS61NLP51236-250TQLI IS61NLP51236-250B3I 100 TQFP 100 TQFP, Lead-free 165 PBGA 200 IS61NLP51236-200TQI IS61NLP51236-200TQLI IS61NLP51236-200B3I IS61NLP51236-200B3LI 100 TQFP 100 TQFP, Lead-free 165 PBGA 165 PBGA, Lead-free 250 IS61NLP102418-250TQI 100 TQFP IS61NLP102418-250B3I 165 PBGA IS61NLP102418-200TQI IS61NLP102418-200B3I 100 TQFP 165 PBGA 256Kx72 512Kx36 1Mx18 Industrial Range: -40°C to +85°C Configuration Access Time 256Kx72 512Kx36 1Mx18 200 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 31 IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® ORDERING INFORMATION (2.5V core/2.5V I/O) Commercial Range: 0°C to +70°C Configuration Access Time Order Part Number Package 250 IS61NVP25672-250B1 209 PBGA 200 IS61NVP25672-200B1 209 PBGA 250 IS61NVP51236-250TQ IS61NVP51236-250B3 100 TQFP 165 PBGA 200 IS61NVP51236-200TQ 100 TQFP IS61NVP51236-200B3 165 PBGA 250 IS61NVP102418-250TQ IS61NVP102418-250B3 100 TQFP 165 PBGA 200 IS61NVP102418-200TQ IS61NVP102418-200B3 100 TQFP 165 PBGA 256Kx72 512Kx36 1Mx18 Industrial Range: -40°C to +85°C Configuration Access Time Order Part Number Package 250 IS61NVP25672-250B1I 209 PBGA 200 IS61NVP25672-200B1I 209 PBGA 250 IS61NVP51236-250TQI IS61NVP51236-250B3I 100 TQFP 165 PBGA 200 IS61NVP51236-200TQI IS61NVP51236-200TQLI IS61NVP51236-200B3I 100 TQFP 100 TQFP, Lead-free 165 PBGA 250 IS61NVP102418-250TQI 100 TQFP IS61NVP102418-250B3I 165 PBGA IS61NVP102418-200TQI IS61NVP102418-200B3I 100 TQFP 165 PBGA 256Kx72 512Kx36 1Mx18 200 32 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 ISSI PACKAGING INFORMATION ® Mini Ball Grid Array - 209 Ball BGA Package Code: B (14 mm x 22mm Body, 1.0 mm Ball Pitch) φ b (209X) 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V Y A B C D E F G H J K L M N P R T U V Y e D D1 e E1 E A3 A2 A1 A SEATING PLANE Notes: 1. Controlling dimensions are in millimeters. MILLIMETERS INCHES Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 209 A — A1 0.40 0.50 0.60 A2 — 1.95 — — 0.016 — 0.54 — A3 0.65 0.70 0.75 0.026 0.028 0.030 D 21.90 22.00 22.10 0.862 0.866 0.870 18.00 BSC 0.709 BSC E 13.90 14.00 14.10 0.547 0.551 0.555 E1 10.00 BSC 0.394 BSC 1.00BSC 0.039BSC D1 e b 0.50 0.60 0.70 — 0.077 0.020 0.024 0.021 — 0.020 0.024 0.028 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 08/22/03 ISSI PACKAGING INFORMATION ® Ball Grid Array Package Code: B (165-pin) BOTTOM VIEW TOP VIEW A1 CORNER 1 2 3 4 A1 CORNER φ b (165X) 5 6 7 8 9 10 11 10 11 9 8 7 6 5 4 3 2 1 A A B B C C D D E E e F F G G D D1 H H J J K K L L M M N N P P R R e E1 E A2 A A1 BGA - 13mm x 15mm MILLIMETERS Sym. Min. N0. Leads Nom. Max. Notes: 1. Controlling dimensions are in millimeters. INCHES Min. 165 Nom. Max. 165 A — — 1.20 — A1 0.25 0.33 0.40 0.010 — 0.047 0.013 0.016 A2 — 0.79 — — 0.031 — D 14.90 15.00 15.10 0.587 0.591 0.594 D1 13.90 14.00 14.10 0.547 0.551 0.555 E 12.90 13.00 13.10 0.508 0.512 0.516 E1 9.90 10.00 10.10 0.390 0.394 0.398 e — 1.00 — — 0.039 — b 0.40 0.45 0.50 0.016 0.018 0.020 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 06/11/03 ISSI PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code: TQ D D1 E E1 N L1 L C 1 e SEATING PLANE A2 A b A1 Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max Millimeters Symbol Min Max Ref. Std. No. Leads (N) 100 A — 1.60 — 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. C 0o 7o 0o 7o 128 — 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o Integrated Silicon Solution, Inc. — 1-800-379-4774 PK13197LQ Rev. D 05/08/03 Inches Min Max — 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters. ®