DATASHEET Radiation Tolerant 5V 16-Channel Analog Multiplexer ISL71830SEH Features The ISL71830SEH is a radiation tolerant, 16-channel multiplexer that is fabricated using Intersil’s proprietary P6-SOI process technology to provide excellent latch-up performance. It operates with a single supply range from 3V to 5.5V and has a 4-bit address line plus an enable that can be driven with adjustable logic thresholds to conveniently select one of 16 available channels. An inactive channel is separated from the active channel by a high impedance, which inhibits any interaction between them. • DLA SMD# 5962-15247 The ISL71830SEH’s low rDS(ON) allows for improved signal integrity and reduced power losses. The ISL71830SEH is also designed for cold sparing, making it excellent for redundancy in high reliability applications. It is designed to provide a high impedance to the analog source in a powered off condition, making it easy to add additional backup devices without incurring extra power dissipation. The ISL71830SEH also has analog overvoltage protection on the input that disables the switch during an overvoltage event to protect upstream and downstream devices. • Cold sparing capable . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 7V The ISL71830SEH is available in a 28 Ld CDFP and operates across the extended temperature range of -55°C to +125°C. A 32-channel version is also available offered in a 48 Ld CQFP. Refer to the ISL71831SEH datasheet for more information. For a list of differences, refer to Table 1 on page 2. Related Literature • For a full list of related documents, visit our website - ISL71830SEH product page • Fabricated using P6 SOI process technology • Rail-to-rail operation • No latch-up • Low rDS(ON) . . . . . . . . . . . . . . . . . . . . . . . . . .<120Ω (maximum) • Single supply operation . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V - Adjustable logic threshold control • Analog overvoltage range . . . . . . . . . . . . . . . . . . . . -0.4V to 7V • Switch input off leakage . . . . . . . . . . . . . . . . . . . . . . . . . 120nA • Transition times (tAHL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70ns • Internally grounded metal lid • Break-before-make switching • ESD protection ≥5kV (HBM) • Operating temperature range. . . . . . . . . . . .-55°C to +125°C • Radiation tolerance - Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . . .75krad(Si) - SEL/SEB LETTH (V+ = 6.5V). . . . . . . . . . . . . 60MeV•cm2/mg • All lots are assurance tested to 75krad (0.01rad(Si)/s) wafer-by-wafer. Applications • Telemetry signal processing • Harsh environments • Down-hole drilling ISL71830SEH IN01 90 IN02 80 IN03 70 OUT ADC 60 rDS(ON) (Ω) . . . IN16 +125°C +25°C 50 40 30 -55°C 20 4 10 0 ADDRESS EN FIGURE 1. TYPICAL APPLICATION November 18, 2016 FN8758.3 1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 COMMON-MODE VOLTAGE (V) 4.5 5.0 FIGURE 2. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 5V) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC. 2015,2016. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL71830SEH Ordering Information SMD ORDERING NUMBER (Note 2) PART NUMBER (Note 1) PACKAGE (RoHS COMPLIANT) TEMP RANGE (°C) PKG. DWG. # 5962L1524701VXC ISL71830SEHVF -55 to +125 28 Ld CDFP K28.A N/A ISL71830SEHF/PROTO -55 to +125 28 Ld CDFP K28.A 5962L1524701V9A ISL71830SEHVX -55 to +125 DIE N/A ISL71830SEHX/SAMPLE -55 to +125 DIE N/A ISL71830SEHEV1Z Evaluation Board NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the “Ordering Information” table must be used when ordering. TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS PART NUMBER NUMBER OF CHANNELS OUTPUT LEAKAGE PACKAGE ISL71830SEH 16 60nA 28 Ld CDFP ISL71831SEH 32 120nA 48 Ld CQFP Submit Document Feedback 2 FN8758.3 November 18, 2016 ISL71830SEH Pin Configuration ISL71830SEH (28 LD CDFP) TOP VIEW V+ 1 28 OUT NC 2 27 NC NC 3 26 IN8 IN16 4 25 IN7 IN15 5 24 IN6 IN14 6 23 IN5 IN13 7 22 IN4 IN12 8 21 IN3 IN11 9 20 IN2 IN10 10 19 IN1 IN9 11 18 EN GND 12 17 A0 VREF 13 16 A1 A3 14 15 A2 Pin Descriptions PIN NAME ESD CIRCUIT PIN NUMBER OUT 2 28 Output for multiplexer. V+ 1 1 Positive power supply. NC - 2, 3, 27 INx 1 4, 5, 6, 7, 8, 9, 10, 11, 19, 20, 21, 22, 23, 24, 25, 26 Ax 1 14, 15, 16, 17 EN 1 18 Enable control for multiplexer (active low). VREF 1 13 Reference voltage used to set logic thresholds. GND - 12 Ground LID - - DESCRIPTION Not electrically connected. Input for multiplexer. Address lines for multiplexer. Package lid is internally connected to GND (Pin 12). VDD PIN # 9V CLAMP 9V CLAMP GND CIRCUIT 1 Submit Document Feedback 3 PIN # 9V CLAMP GND CIRCUIT 2 FN8758.3 November 18, 2016 ISL71830SEH Absolute Maximum Ratings Thermal Information (V+ Maximum Supply Voltage to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Maximum Supply Voltage (V+ to GND) (Note 5) . . . . . . . . . . . . . . . . . . .6.5V Analog Input Voltage Range (INx). . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 7V Digital Input Voltage Range (EN, Ax) . . . . . . . . . . . . . . . (GND - 0.4V) to VREF VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V ESD Tolerance Human Device Model (Tested per MIL-STD-883 TM 3015) . . . . . . . . 5kV Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 250V Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 250V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 28 Ld CDFP (Notes 3, 4) . . . . . . . . . . . . . . . 55 8.5 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Recommended Operating Conditions Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 5.5V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 5.5V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. For JC, the “case temp” location is the center of the package underside. 5. Tested in a heavy ion environment at LET = 60MeV•cm2/mg at +125°C. Electrical Specifications, V+ = 5V GND = 0V, VREF = 3.3V, VIH = 3.3V, VIL = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 75krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. PARAMETER SYMBOL Analog Input Signal Range TEST CONDITIONS Channel On-Resistance rDS(ON) V+ rDS(ON) Match Between Channels ΔrDS(ON) V+ = 4.5V, VIN = 0V, 2.25V, 4.5V IOUT = 1mA On-Resistance Flatness rFLAT(ON) V+ = 4.5V, VIN = 0V to V+ IIN(OFF) Switch Input Off Overvoltage Leakage Switch Input Off Leakage with Supply Voltage Grounded Switch Input Off Leakage with Supply Voltage Open Switch On Input Leakage with Overvoltage Applied to the Input Submit Document Feedback IIN(OFF-OV) IIN(POWER-OFF) IIN(POWER-OFF) IIN(ON-OV) 4 TYP 0 VIN Switch Input Off Leakage MIN (Note 6) = 4.5V, VIN = 0V to IOUT = 1mA V+ MAX (Note 6) UNIT V+ V - 40 120 Ω - - 5 Ω - - 40 Ω V+ = 5.5V, VIN = 5V, Unused inputs and VOUT = 0.5V -30 - 30 nA V+ = 5.5V, VIN = 0.5V, Unused inputs and VOUT = 5V -30 - 30 nA V+ = 5.5V, VIN = 7V, Unused inputs and VOUT = 0V, TA = +25°C, -55°C -30 - 30 nA TA = +125°C -30 - 120 nA Post radiation, +25°C -30 - 30 nA VIN = 7V, VOUT = 0V V+ = VEN = VREF = 0V, TA = +25°C, -55°C -20 - 20 nA TA = +125°C -20 - 50 nA Post radiation, +25°C -20 - 20 nA VIN = 7V, VOUT = 0V V+ = VEN = VREF = Open, TA = +25°C, -55°C -20 - 20 nA TA = +125°C -20 - 50 nA Post radiation, +25°C -20 - 20 nA 2.75 - 5.50 µA V+ = 5.5V, VIN = 7V, VOUT = OPEN FN8758.3 November 18, 2016 ISL71830SEH Electrical Specifications, V+ = 5V GND = 0V, VREF = 3.3V, VIH = 3.3V, VIL = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 75krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued) PARAMETER MIN (Note 6) TYP MAX (Note 6) UNIT -30 - 30 nA 0 - 150 nA Post radiation, +25°C -30 - 30 nA V+ = 5.5V, VOUT = 0.5V, All inputs = 5V, TA = +25°C, -55°C -30 - 30 nA TA = +125°C -60 0 nA Post radiation, +25°C -30 - 30 nA V+ = 5.5V, VIN = VOUT = 5V All unused inputs at 0.5V, TA = +25°C, -55°C -30 - 30 nA 0 - 150 nA Post radiation, +25°C -30 - 30 nA V+ = 5.5V, VIN = VOUT = 0.5V All unused inputs at 5V, TA = +25°C, -55°C -30 - 30 nA TA = +125°C -60 - 0 nA Post radiation, +25°C -30 - 30 nA VIH/L V+ = 5.5V, VREF = 3.3V 1.3 - 1.6 V = 5.5V, VEN = VA = VREF -0.1 - 0.1 µA SYMBOL Switch Output Off Leakage IOUT(OFF) TEST CONDITIONS V+ = 5.5V, VOUT = 5V, All inputs = 0.5V, TA = +25°C, -55°C TA = +125°C Switch Output Leakage with Switch Enabled IOUT(ON) TA = +125°C Logic Input Voltage High/Low IAH, IENH V+ Input Current with VAL, VENL IAL, IENL V+ = 5.5V, VEN = VA = 0V -0.1 - 0.1 µA Quiescent Supply Current ISUPPLY V+ = VREF = VEN = 5.5V VA = 0V, TA = +25°C, -55°C - - 100 nA TA = +125°C - - 300 nA Post radiation, +25°C - - 300 nA IREF V+ - - 200 nA Addressing Transition Time tAHL V+ = 4.5V; Figure 3 10 - 70 ns Break-Before-Make Delay tBBM V+ = 4.5V; Figure 5 5 18 40 ns tEN(ON) V+ = 4.5V; Figure 4 - - 40 ns tEN(OFF) V+ - - 40 ns - 1.4 5 pC Input Current with VAH, VENH Reference Quiescent Supply Current = VREF = VEN = 5.5V VA = 0V DYNAMIC Enable Turn-On Time Enable Turn-Off Time = 4.5V; Figure 4 Charge Injection VCTE CL = 100pF, VIN = 0V, Figure 6 Off Isolation VISO VEN = VREF, RL = OPEN, f = 1kHz 60 - - dB Crosstalk VCT VEN = 0V, f = 1kHz, VP-P = 1V, RL = OPEN 73 - - dB Input Capacitance Output Capacitance Submit Document Feedback 5 CIN(OFF) f = 1MHz - - 5 pF COUT(OFF) f = 1MHz - - 25 pF FN8758.3 November 18, 2016 ISL71830SEH Electrical Specifications, V+ = 3.3V VREF = 3.3V, VIH = 3.3V, VIL = 0V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C.; over a total ionizing dose of 75krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. PARAMETER SYMBOL Analog Input Signal Range CONDITIONS VIN V+ V+ MIN (Note 6) TYP MAX (Note 6) UNIT 0 - V+ V 25 70 200 Ω Channel On-Resistance rDS(ON) = 3V, VIN = 0V to IOUT = 1mA rDS(ON) Match Between Channels ΔrDS(ON) V+ = 3V, VIN = 0.5V, 2.5V IOUT = 1mA - - 5 Ω On-Resistance Flatness rFLAT(ON) V+ = 3V VIN = 0V to V+ - - 50 Ω V+ = 3.6V VIN = 3.1V, Unused inputs and VOUT = 0.5V -30 - 30 nA V+ = 3.6V VIN = 0.5V, Unused inputs and VOUT = 3.1V -30 - 30 nA V+ = 3.6V VIN = 7V, Unused inputs and VOUT = 0V, TA = +25°C, -55°C -30 - 30 nA TA = +125°C -30 - 100 nA Post radiation, +25°C -30 - 30 Switch Input Off Leakage IIN(OFF) Switch Input Off Overvoltage Leakage IIN(OFF-OV) Switch On Input Leakage with Overvoltage Applied to the Input IIN(ON-OV) V+ = 3.6V, VIN = 7V, VOUT = OPEN 1.8 - 3.6 µA Switch Output Off Leakage IOUT(OFF) V+ = 3.6V, VOUT = 3.1V, All inputs = 0.5V, TA = +25°C, -55°C -30 - 30 nA 0 - 60 nA Post radiation, +25°C -30 - 30 nA V+ = 3.6V, VOUT = 0.5V, All inputs = 3.1V, TA = +25°C, -55°C -30 - 30 nA 0 - 30 nA Post radiation, +25°C -30 - 30 nA V+ -30 - 30 nA 0 - 30 nA Post radiation, +25°C -30 - 30 nA V+ -30 - 30 nA 0 - 30 nA -30 - 30 nA V+ = VREF = VEN = 3.6V VA = 0V, TA = +25°C, -55°C - - 100 nA TA = +125°C - - 300 nA Post radiation, +25°C - - 300 nA V+ = VREF = VEN = 3.6V, VA = 0V - - 200 nA TA = +125°C TA = +125°C Switch Output Leakage with Switch Enabled IOUT(ON) = 3.6V, VIN = VOUT = 3.1V All unused inputs at 0.5V, TA = +25°C, -55°C TA = +125°C = 3.6V, VIN = VOUT = 0.5V All unused inputs at 3.1V, TA = +25°C, -55°C TA = +125°C Post radiation, +25°C Quiescent Supply Current ISUPPLY Reference Quiescent Supply Current Submit Document Feedback 6 IREF FN8758.3 November 18, 2016 ISL71830SEH Electrical Specifications, V+ = 3.3V VREF = 3.3V, VIH = 3.3V, VIL = 0V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C.; over a total ionizing dose of 75krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued) PARAMETER SYMBOL CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT DYNAMIC tAHL V+ = 3V; Figure 3 10 - 100 ns tBBM V+ = 3V; Figure 5 5 25 50 ns Enable Turn-On Time tEN(ON) V+ = 3V; Figure 4 - - 50 ns Enable Turn-Off Time tEN(OFF) V+ = 3V; Figure 4 - - 50 ns Addressing Transition Time Break-Before-Make Delay NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. TABLE 2. TRUTH A3 A2 A1 A0 EN “ON” CHANNEL X X X X 1 None 0 0 0 0 0 1 0 0 0 1 0 2 0 0 1 0 0 3 0 0 1 1 0 4 0 1 0 0 0 5 0 1 0 1 0 6 0 1 1 0 0 7 0 1 1 1 0 8 1 0 0 0 0 9 1 0 0 1 0 10 1 0 1 0 0 11 1 0 1 1 0 12 1 1 0 0 0 13 1 1 0 1 0 14 1 1 1 0 0 15 1 1 1 1 0 16 NOTE: 7. X = Don’t care, “1” = Logic High, “0” = Logic Low. Submit Document Feedback 7 FN8758.3 November 18, 2016 ISL71830SEH Timing Diagrams 95() ³´ ISL71830SEH IN01 A3 A2 A1 A0 VREF 50䃈 V+, 0V IN02-IN15 IN16 0V, V+ ³´ 9 0V 9 W$+/ EN 0V OUT W$+/ VOUT 287387 50pF 10k䃈 9 FIGURE 4. ADDRESS TIME TO OUTPUT DIAGRAM FIGURE 3. ADDRESS TIME TO OUTPUT TEST CIRCUIT ISL71830SEH VREF V+ IN01 A3 A2 A1 A0 IN02-IN16 EN 50% 50% 0V V+ VOUT OUT EN 90% tENABLE VREF 50pF 1kΩ 50Ω OUTPUT tDISABLE 0V 10% 0V FIGURE 6. TIME TO ENABLE/DISABLE OUTPUT DIAGRAM FIGURE 5. TIME TO ENABLE/DISABLE OUTPUT TEST CIRCUIT VREF ISL71830SEH A3 A2 A1 A0 VREF 50 Ω IN01 V+ ADDRESS IN02-IN15 IN16 0V 0V + 0V EN VOUT OUT 100Ω 50pF V 50% OUT 0V FIGURE 7. BREAK-BEFORE-MAKE TEST CIRCUIT tBBM FIGURE 8. BREAK-BEFORE-MAKE DIAGRAM VREF ISL71830SEH VREF 50䃈 IN01 A3 A2 A1 A0 IN02-IN15 EN OUT ADDRESS 0V IN16 0V 0V 0V Q = 100pF * ΔVOUT VOUT OUT 100pF ΔVOUT 0V FIGURE 9. CHARGE INJECTION TEST CIRCUIT Submit Document Feedback 8 FIGURE 10. CHARGE INJECTION DIAGRAM FN8758.3 November 18, 2016 ISL71830SEH Typical Performance Curves V+ = 5V, VREF = 3.3V, VIN = 0V, RL = Open, TA = +25°C, unless otherwise specified. 90 90 80 80 +125°C +25°C 70 rDS(ON) (Ω) rDS(ON) (Ω) 50 40 -55°C 30 50 40 30 20 20 10 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 COMMON-MODE VOLTAGE (V) 4.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FIGURE 12. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 5V) 140 70 +125°C 120 +125°C 60 +25°C 100 rDS(ON) (Ω) 50 rDS(ON) (Ω) 0 COMMON-MODE VOLTAGE (V) 80 40 30 80 60 -55°C +25°C 40 20 -55°C 20 10 0 1 2 3 4 COMMON-MODE VOLTAGE (V) 0 5 0 1.0 1.5 2.0 2.5 3.0 FIGURE 14. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 3V) 120 120 +125°C 100 80 80 rDS(ON) (Ω) 100 60 +25°C -55°C 40 +125°C 60 40 +25°C -55°C 20 20 0 0.5 COMMON-MODE VOLTAGE (V) FIGURE 13. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 5.5V) rDS(ON) (Ω) -55°C 0 4.5 FIGURE 11. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 4.5V) 0 +25°C 60 60 0 +125°C 70 0 0.5 1.0 1.5 2.0 2.5 3.0 COMMON-MODE VOLTAGE (V) FIGURE 15. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 3.3V) Submit Document Feedback 9 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 COMMON-MODE VOLTAGE (V) FIGURE 16. rDS(ON) vs COMMON-MODE VOLTAGE (V+ = 3.6V) FN8758.3 November 18, 2016 ISL71830SEH Typical Performance Curves V+ = 5V, VREF = 3.3V, VIN = 0V, RL = Open, TA = +25°C, 80 80 70 70 +25°C 60 ADDRESS DELAY (ns) ADDRESS DELAY (ns) unless otherwise specified. (Continued) +125°C 50 40 30 -55°C 20 +125°C 60 50 40 30 -55°C +25°C 20 10 10 0 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 0 3.0 5.5 FIGURE 17. ADDRESS PROPAGATION DELAY (HIGH TO LOW) 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 FIGURE 18. ADDRESS PROPAGATION DELAY (LOW TO HIGH) 40 35 2V/DIV +125°C tADLH = 44.087ns tADHL = 34.382ns tBMM DELAY (ns) 30 25 20 15 10 -55°C +25°C 5 1V/DIV 0 3.0 3.5 200ns/DIV FIGURE 19. ADDRESS PROPAGATION DELAY 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 FIGURE 20. BREAK-BEFORE-MAKE DELAY 60 2V/DIV 1V/DIV tBBM = 17.929ns tENABLE DELAY (ns) 50 +125°C 40 30 20 -55°C 10 0 3.0 200ns/DIV FIGURE 21. BREAK-BEFORE-MAKE DELAY Submit Document Feedback 10 +25°C 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) FIGURE 22. ENABLE TO OUTPUT PROPAGATION DELAY FN8758.3 November 18, 2016 ISL71830SEH Typical Performance Curves V+ = 5V, VREF = 3.3V, VIN = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued) 60 +125°C 2V/DIV tDISABLE DELAY (ns) 50 40 30 1V/DIV tDISABLE = 41.720ns -55°C +25°C 20 tENABLE = 22.670ns 10 0 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 200ns/DIV FIGURE 23. DISABLE TO OUTPUT PROPAGATION DELAY FIGURE 24. ENABLE/DISABLE PROPAGATION DELAY 120 90 80 OFF ISOLATION (dB) OFF ISOLATION (dB) 100 80 60 40 20 0 100 70 60 50 40 30 20 10 1k 10k 100k 1M 10M 0 100 100M 1k 10k FREQUENCY (Hz) FIGURE 25. OFF ISOLATION (V+ = 5V, +25°C, RL = 511Ω) 1M 10M 100M FIGURE 26. OFF ISOLATION (V+ = 5V, +25°C, RL= OPEN) 120 2.00 +125°C 1.80 CHARGE INJECTION (pC) 100 CROSSTALK (dB) 100k FREQUENCY (Hz) 80 60 40 20 1.60 1.40 1.20 1.00 +25°C 0.80 0.60 -55°C 0.40 0.20 0 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 27. CROSSTALK (V+ = 5V, +25°C, RL = OPEN) Submit Document Feedback 11 10M 0 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) FIGURE 28. CHARGE INJECTION FN8758.3 November 18, 2016 ISL71830SEH Post Low Dose Rate Radiation Characteristics (V+ = 5V) Unless otherwise specified, V+ = 5V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. 120 120 100 100 VIN = 0.5V 60 40 60 40 VIN = 2.25V 20 0 0 VIN = 0.5V 80 rDS(ON) (Ω) rDS(ON) (Ω) 80 10 20 30 VIN = 2.25V VIN = 4V 40 50 60 70 0 80 0 10 LOW DOSE RATE RADIATION (krad(Si)) 30 40 50 60 70 80 70 80 20 30 40 50 60 70 LOW DOSE RATE RADIATION (krad(Si)) 80 FIGURE 30. rDS(ON) (V+ = 4.5V), GROUNDED 120 120 100 100 GROUNDED 80 GROUNDED rDS(ON) (Ω) rDS(ON) (Ω) 20 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 29. rDS(ON) (V+ = 4.5V), BIASED 80 VIN = 4V 20 60 40 60 40 BIASED BIASED 20 0 0 10 20 30 40 50 20 60 70 0 80 0 10 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 31. rDS(ON) MINIMUM (V+ = 4.5V) 5.0 40 4.5 35 4.0 BIASED rDS(ON) (Ω) rDS(ON) (Ω) 40 50 60 3.5 GROUNDED 25 20 15 3.0 2.5 GROUNDED 2.0 BIASED 1.5 10 1.0 5 0.5 0 0 30 FIGURE 32. rDS(ON) MAXIMUM (V+ = 4.5V) 45 30 20 LOW DOSE RATE RADIATION (krad(Si)) 10 20 30 40 50 60 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 33. rDS(ON) FLATNESS (V+ = 4.5V) Submit Document Feedback 12 70 80 0 0 10 FIGURE 34. rDS(ON) MATCH (V+ = 4.5V, VIN = 0.5V) FN8758.3 November 18, 2016 ISL71830SEH Post Low Dose Rate Radiation Characteristics (V+ = 5V) 5.0 1.0 4.5 0.8 4.0 0.6 3.5 0.4 LEAKAGE (nA) rDS(ON) (Ω) Unless otherwise specified, V+ = 5V, VCM = 0, VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. (Continued) 3.0 2.5 GROUNDED BIASED 2.0 1.5 0 -0.2 -0.4 1.0 -0.6 0.5 -0.8 0 0 10 20 30 40 50 60 70 -1.0 80 GROUNDED 0.2 BIASED 0 10 LOW DOSE RATE RADIATION (krad(Si)) 1.0 5.5 0.8 5.0 0.6 4.5 0.4 GROUNDED 0 -0.2 -0.4 BIASED 3.5 GROUNDED 3.0 2.5 2.0 1.5 -0.6 1.0 -0.8 0.5 10 BIASED 4.0 0.2 -1.0 0 20 30 40 50 60 70 LOW DOSE RATE RADIATION (krad(Si)) 0 80 0 20 30 40 50 60 70 80 70 80 FIGURE 38. IS(ON) (V+ = 5.5V, VIN = 5V) 1.0 1.0 0.8 0.8 GROUNDED 0.6 0.6 0.4 LEAKAGE (nA) LEAKAGE (nA) 10 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 37. IS(OFF) (V+ = 5.5V, VS = 7V) 0.2 0 -0.2 BIASED -0.4 0.2 0 -0.2 -0.6 -0.8 20 30 40 50 60 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 39. ID(ON) (V+ = 5.5V, VIN = 5V) Submit Document Feedback 13 70 80 BIASED -0.4 -0.8 10 GROUNDED 0.4 -0.6 -1.0 0 80 FIGURE 36. IS(OFF) (V+ = 5.5V, VIN = 5V) LEAKAGE (nA) LEAKAGE (nA) FIGURE 35. rDS(ON) MATCH (V+ = 4.5V, VIN = 4V) 20 30 40 50 60 70 LOW DOSE RATE RADIATION (krad(Si)) -1.0 0 10 20 30 40 50 60 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 40. ID(OFF) (V+ = 3.6V, VIN = 3.1V) FN8758.3 November 18, 2016 ISL71830SEH Post Low Dose Rate Radiation Characteristics (V+ = 3.3V) 120 120 100 100 80 80 60 VIN = 2.5V 40 VIN = 1.5V rDS(ON) (Ω) rDS(ON) (Ω) Unless otherwise specified, V+ = 3.3V, VCM = 0,VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. VIN = 0.5V 60 40 20 20 0 0 10 20 30 40 50 60 70 0 80 0 10 LOW DOSE RATE RADIATION (krad(Si)) 40 50 60 70 80 120 100 GROUNDED BIASED 100 80 rDS(ON) (Ω) 80 rDS(ON) (Ω) 30 FIGURE 42. rDS(ON) (V+ = 3V), GROUNDED 120 60 40 20 20 10 20 30 40 50 60 70 0 80 0 10 LOW DOSE RATE RADIATION (krad(Si)) 20 30 40 50 60 70 80 70 80 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 44. rDS(ON) MAXIMUM (V+ = 3V) 45 5.0 40 4.5 35 GROUNDED 60 40 0 BIASED FIGURE 43. rDS(ON) MINIMUM (V+ = 3V) 4.0 GROUNDED 3.5 rDS(ON) (Ω) 30 rDS(ON) (Ω) 20 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 41. rDS(ON) (V+ = 3V), BIASED 0 VIN = 0.5V VIN = 1.5V VIN = 2.5V 25 20 BIASED 15 3.0 2.5 GROUNDED 2.0 1.5 10 1.0 5 0.5 0 0 0.0 10 20 30 40 50 60 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 45. rDS(ON) FLATNESS (V+ = 3V) Submit Document Feedback 14 70 80 BIASED 0 10 20 30 40 50 60 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 46. rDS(ON) MATCH (V+ = 3V, VIN = 0.5V) FN8758.3 November 18, 2016 ISL71830SEH Post Low Dose Rate Radiation Characteristics (V+ = 3.3V) 5.0 1.0 4.5 0.8 4.0 0.6 3.5 0.4 LEAKAGE (nA) rDS(ON) (Ω) Unless otherwise specified, V+ = 3.3V, VCM = 0,VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation. These are not limits nor are they guaranteed. (Continued) 3.0 2.5 GROUNDED BIASED 2.0 1.5 0.2 0 -0.2 -0.4 1.0 -0.6 0.5 -0.8 0 0 10 20 30 40 50 60 70 LOW DOSE RATE RADIATION (krad(Si)) -1.0 80 GROUNDED BIASED 0 FIGURE 47. rDS(ON) MATCH (V+ = 3V, VIN = 2.5V) 5.5 0.8 5.0 4.0 LEAKAGE (nA) LEAKAGE (nA) GROUNDED 0.4 0.2 0 -0.2 BIASED 3.0 2.5 2.0 1.5 1.0 -0.8 0.5 10 20 30 40 50 60 70 0 0 80 10 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 49. IS(OFF) (V+ = 3.6V, VIN = 7V) 1.0 0.8 0.8 0.6 0.6 BIASED GROUNDED LEAKAGE (nA) LEAKAGE (nA) 20 30 40 50 60 70 LOW DOSE RATE RADIATION (krad(Si)) 0.2 0 -0.2 -0.4 0 -0.2 -0.4 -0.6 -0.8 20 30 40 50 60 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 51. ID(ON) (V+ = 3.6V, VIN = 3.1V) Submit Document Feedback 15 70 80 BIASED 0.2 -0.8 10 GROUNDED 0.4 -0.6 0 80 FIGURE 50. IS(ON) (V+ = 3.6V, VIN = 7V) 1.0 -1.0 GROUNDED BIASED 3.5 -0.6 0.4 80 4.5 0.6 -1.0 0 20 30 40 50 60 70 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 48. IS(OFF) (V+ = 3.6V, VIN = 3.1V) 1.0 -0.4 10 -1.0 0 10 20 30 40 50 60 70 80 LOW DOSE RATE RADIATION (krad(Si)) FIGURE 52. ID(OFF) (V+ = 3.6V, VIN = 3.1V) FN8758.3 November 18, 2016 ISL71830SEH Applications Information ISL71830SEH vs ISL71831SEH Power-Up Considerations A 32-channel version of the ISL71830SEH is available in a 48 Ld CQFP. In terms of performance specs, the parts are very similar in behavior. Apart from the apparent increase in channel density, the ISL71831SEH does have slightly higher output leakage compared to the ISL71830SEH due to having more channels connected to the output. The supply current for the ISL71831SEH is also a bit higher compared to the ISL71830SEH. The circuit is designed to be insensitive to any given power-up sequence between V+ and VREF, however, it is recommended that all supplies power-up relatively close to each other. Overvoltage Protection The ISL71830SEH has overvoltage protection on both the input as well as the output. On the output, the voltage is limited to a diode past the rails. Each of the inputs has independent overvoltage protection that works regardless of the switch being selected. If a switch experiences an overvoltage condition, the switch is turned off. As soon as the voltage returns within the rails, the switch returns to normal operation. VREF and Logic Functionality The VREF pin sets the logic threshold for the ISL71830SEH. The range for VREF is between 3V and 5.5V. The switching point is set to around 50% of the voltage presented to VREF. This switching point allows for both 5V and 3.3V logic control. Submit Document Feedback 16 FN8758.3 November 18, 2016 ISL71830SEH Die Characteristics Assembly Related Information Die Dimensions SUBSTRATE POTENTIAL Floating 2026µm x 2240µm (79.7638 mils x 88.1890 mils) Thickness: 483µm ± 25µm (19 mils ± 1 mil) Additional Information Interface Materials WORST CASE CURRENT DENSITY GLASSIVATION Type: 12kÅ Silicon Nitride on 3kÅ Oxide 1.6 x 105 A/cm2 TRANSISTOR COUNT TOP METALLIZATION Type: 300Å TiN on 2.8µm AlCu 3875 Weight of Packaged Device In Bondpads, TiN has been removed. 2.091 grams BACKSIDE FINISH Lid Characteristics Silicon Finish: Gold Potential: Grounded, tied to package pin 12 PROCESS P6SOI Metalization Mask Layout IN16 IN8 OUT IN15 IN7 IN14 IN6 IN13 IN5 IN12 IN4 IN11 IN3 IN10 IN2 IN9 IN1 GND Submit Document Feedback V+ 17 VREF A3 A2 A1 A0 EN BAR FN8758.3 November 18, 2016 ISL71830SEH TABLE 3. ISL71830SEH DIE LAYOUT X-Y COORDINATES PAD NUMBER PAD NAME PACKAGING PIN ΔX (µm) ΔY (µm) X (µm) Y (µm) 1 IN8 P26 110 110 1693.925 1939.8 5 OUT P28 110 110 1050.875 1915.8 6 V+ P1 110 110 844.875 1915.8 10 IN16 P4 110 110 201.8 1939.8 11 IN15 P5 110 110 201.8 1693.8 12 IN14 P6 110 110 201.8 1477.8 13 IN13 P7 110 110 201.8 1271.8 14 IN12 P8 110 110 201.8 1065.8 15 IN11 P9 110 110 201.8 859.8 16 IN10 P10 110 110 201.8 653.8 17 IN9 P11 110 110 201.8 442.8 18 GND P12 110 110 206.225 201.8 19 VREF P13 110 110 440.35 201.8 20 A3 P14 110 110 676.35 201.8 21 A2 P15 110 110 912.35 201.8 22 A1 P16 110 110 1148.35 201.8 23 A0 P17 110 110 1384.35 201.8 24 EN P18 110 110 1620.35 201.8 25 IN1 P19 110 110 1693.925 442.8 26 IN2 P20 110 110 1693.925 653.8 27 IN3 P21 110 110 1693.925 859.8 28 IN4 P22 110 110 1693.925 1065.8 29 IN5 P23 110 110 1693.925 1271.8 30 IN6 P24 110 110 1693.925 1477.8 31 IN7 P25 110 110 1693.925 1693.8 NOTE: Origin of coordinates is the center of the die. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 18 FN8758.3 November 18, 2016 ISL71830SEH Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE November 18, 2016 FN8758.3 Added ESD diagrams to the “Pin Descriptions” on page 3. Updated Related Literature section. March 4, 2016 FN8758.2 Page 1 Features, changed the following: From: SEL/B immune to LET 60MeV•mg/cm2 To: SEL/B immune to LET 60MeV•cm2/mg December 10, 2015 FN8758.1 Changed rON to rDS(ON) throughout datasheet Changed in Features on page 1 last item under “Radiation tolerance” “V+ = 5V” to “V+ = 6.5V” Changed in Description and Features on page 1 supply voltage from “3.3V to 5V” to “3V to 5.5V”. Removed ADDR throughout datasheet from: Pin Configuration from pins 14 through 17 on page 3 “Pin Descriptions” on page 3, “Absolute Maximum Ratings” on page 4 and Table 3 on page 18. Abs Max Section, page 4, changed: Maximum Supply Voltage (V+ to GND) (Note 5) . . . . . . 7V TO: Maximum Supply Voltage (V+ to GND) (Note 5) . . . . . 6.5V Electrical Spec table: page 4 Changed TYP from 60 to 40 page 5 tBBM changed TYP from 15 to 18 VCTE changed TYP from 2 to 1.4 Swapped the "VEN = " statements between Off Isolation and Crosstalk. Off Isolation changed: From: 60dB (TYP) To: 60dB (MIN) and Crosstalk changed: From: 73dB (TYP) To: 73dB (MIN) page 6 Changed TYP from 60 to 70 page 7 tBBM changed TYP from 15 to 25 “Timing Diagrams” on page 8 Figures 5 and 7 changed 500 to 50Ω On page 7 added Truth table. Replaced die plot on page 17, changed VDD to V+. Page 18 X-Y Coordinates table, changed VDD to V+ Figure 7 changed 1000 on bottom right resistor to 100Ω. Y-Axis Changes: Figure 20: from ADDRESS DELAY (ns) to: tBMM DELAY (ns) Figure 22: from ADDRESS DELAY (ns) to: tENABLE DELAY (ns) Figure 23: from ADDRESS DELAY (ns) to: tDISABLE DELAY (ns) September 24, 2015 FN8758.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. Submit Document Feedback 19 FN8758.3 November 18, 2016 ISL71830SEH Ceramic Metal Seal Flatpack Packages (Flatpack) K28.A MIL-STD-1835 CDFP3-F28 (F-11A, CONFIGURATION B) A e 28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE A INCHES PIN NO. 1 ID AREA SYMBOL -A- D -B- S1 b E1 0.004 M H A-B S D S Q 0.036 M H A-B S D S C E -D- A -C- -HL E2 E3 SEATING AND BASE PLANE c1 L E3 BASE METAL (c) b1 M M MIN MAX NOTES 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - D - 0.740 - 18.80 3 E 0.460 0.520 E1 - 0.550 - E2 0.180 - 4.57 - - E3 0.030 - 0.76 - 7 11.68 2 0.050 BSC 13.21 - 13.97 3 1.27 BSC - k 0.008 0.015 0.20 0.38 L 0.250 0.370 6.35 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.00 - 0.00 - 6 M - 0.0015 - 0.04 - N (b) MILLIMETERS MAX A e LEAD FINISH MIN 28 28 Rev. 0 5/18/94 SECTION A-A NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. Submit Document Feedback 20 For the most recent package outline drawing, see K28.A. FN8758.3 November 18, 2016