LINER LTC6241HVCDD Dual/quad 18mhz, low noise, rail-to-rail, cmos op amp Datasheet

LTC6241/LTC6242
Dual/Quad 18MHz, Low
Noise, Rail-to-Rail,
CMOS Op Amps
DESCRIPTIO
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FEATURES
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The LTC®6241/LTC6242 are dual and quad low noise,
low offset, rail-to-rail output, unity gain stable CMOS op
amps that feature 1pA of input bias current. The 0.1Hz to
10Hz noise of only 550nVP-P, along with an offset of just
125µV make them uncommon among traditional CMOS
op amps. Additionally, noise is guaranteed to be less
than 10nV/√Hz at 1kHz. An 18MHz gain bandwidth, and
10V/µs slew rate, along with the wide supply range and
low input capacitance, make them perfect for use as fast
signal processing amplifiers.
0.1Hz to 10Hz Noise: 550nVP-P
Input Bias Current: 1pA (Typ at 25°C)
Low Offset Voltage: 125µV Max
Low Offset Drift: 2.5µV/°C Max
Voltage Gain: 124dB Typ
Gain Bandwidth Product: 18MHz
Output Swings Rail-to-Rail
Supply Operation:
2.8V to 6V LTC6241/LTC6242
2.8V to ±5.5V LTC6241HV/LTC6242HV
Low Input Capacitance
Dual LTC6241 in 8-Pin SO and Tiny DFN Packages
Quad LTC6242 in 16-Pin SSOP and 5mm × 3mm
DFN Packages
These op amps have an output stage that swings within
30mV of either supply rail to maximize the signal dynamic
range in low supply applications. The input common mode
range extends to the negative supply. They are fully specified on 3V and 5V, and an HV version guarantees operation
on supplies up to ±5.5V.
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APPLICATIO S
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The LTC6241 is available in the 8-pin SO, and for compact
designs it is packaged in the tiny dual fine pitch leadless
(DFN) package. The LTC6242 is available in the 16-Pin
SSOP as well as the 5mm × 3mm DFN package.
Photo Diode Amplifiers
Charge Coupled Amplifiers
Low Noise Signal Processing
Active Filters
Medical Instrumentation
High Impedance Transducer Amplifier
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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TYPICAL APPLICATIO
Low Noise Single-Ended Input to Differential Output Amplifier
Noise Voltage vs Frequency
60
C3
10pF
C1
10pF
R4
4.99k
R3
4.99k
VIN
+2.5V
–
1/2
LTC6241
+
–
40
30
20
10
–2.5V
1/2
LTC6241
+
VOUT
+
NOISE VOLTAGE (nV/√Hz)
50
C4
10pF
R1
200k
TA = 25°C
VS = ±2.5V
VCM = 0V
VOUT–
0
R2
200k
1
C2
10pF
10
100
1k
FREQUENCY (Hz)
10k
100k
6241 TA01b
6241 TA01a
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LTC6241/LTC6242
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ABSOLUTE
AXI U RATI GS
(Note 1)
Total Supply Voltage (V+ to V–)
LTC6241/LTC6242 ..................................................7V
LTC6241HV/LTC6242HV .......................................12V
Input Voltage.......................... (V+ + 0.3V) to (V– – 0.3V)
Input Current........................................................±10mA
Output Short Circuit Duration (Note 2) ............ Indefinite
Operating Temperature Range (Note 3) ... –40°C to 85°C
Specified Temperature Range (Note 4) .... –40°C to 85°C
Junction Temperature ........................................... 150°C
DHC, DD Package ............................................. 125°C
Storage Temperature Range....................–65ºC to 150°C
DHC, DD Package ...............................–65ºC to 125°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
OUT A 1
–IN A 2
8
7 OUT B
A
+IN A 3
V
–
V+
6 –IN B
B
5 +IN B
4
OUT A 1
–IN A 2
V–
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
UNDERSIDE METAL CONNECTED TO V–
(PCB CONNECTION OPTIONAL)
1
–IN A
2
+IN A
3
14 +IN D
V+
4
13 V –
+IN B
5
–IN B
6
11 –IN C
OUT B
7
10 OUT C
NC
8
9
17
B
C
V+
7
OUT B
6
–IN B
5
+IN B
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 190°C/W
TOP VIEW
16 OUT D
OUT A
D
B
4
TOP VIEW
A
A
+IN A 3
8
15 –IN D
12 +IN C
NC
DHC16 PACKAGE
16-LEAD (5mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
UNDERSIDE METAL CONNECTED TO V–
OUT A
1
16 OUT D
–IN A
2
15 –IN D
+IN A
3
14 +IN D
V+
4
13 V –
+IN B
5
–IN B
6
11 –IN C
OUT B
7
10 OUT C
NC
8
9
A
B
D
C
12 +IN C
NC
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 135°C/W
ORDER PART
NUMBER
DD PART
MARKING*
LTC6241CDD
LTC6241HVCDD
LTC6241IDD
LTC6241HVIDD
LBPD
LBRR
LBPD
LBRR
ORDER PART
NUMBER
S8 PART
MARKING
LTC6241CS8
LTC6241HVCS8
LTC6241IS8
LTC6241HVIS8
6241
6241HV
6241I
241HVI
ORDER PART
NUMBER
DHC PART
MARKING*
LTC6242CDHC
LTC6242HVCDHC
LTC6242IDHC
LTC6242HVIDHC
6242
6242HV
6242
6242HV
ORDER PART
NUMBER
GN PART
MARKING
LTC6242CGN
LTC6242HVCGN
LTC6242IGN
LTC6242HVIGN
6242
6242HV
6242I
242HVI
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
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LTC6241/LTC6242
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AVAILABLE OPTIO S
PART NUMBER
AMPS/PACKAGE
SPECIFIED TEMP RANGE
SPECIFIED SUPPLY VOLTAGE
PACKAGE
PART MARKING
LTC6241CS8
2
0°C to 70°C
3V, 5V
SO-8
6241
LTC6241CDD
2
0°C to 70°C
3V, 5V
DD
LBPD
LTC6241HVCS8
2
0°C to 70°C
3V, 5V, ±5V
SO-8
6241HV
LTC6241HVCDD
2
0°C to 70°C
3V, 5V, ±5V
DD
LBRR
LTC6241IS8
2
–40°C to 85°C
3V, 5V
SO-8
6241I
LTC6241IDD
2
–40°C to 85°C
3V, 5V
DD
LBPD
LTC6241HVIS8
2
–40°C to 85°C
3V, 5V, ±5V
SO-8
241HVI
LTC6241HVIDD
2
–40°C to 85°C
3V, 5V, ±5V
DD
LBRR
LTC6242CGN
4
0°C to 70°C
3V, 5V
GN
6242
LTC6242CDHC
4
0°C to 70°C
3V, 5V
DHC
6242
LTC6242HVCGN
4
0°C to 70°C
3V, 5V, ±5V
GN
6242HV
LTC6242HVCDHC
4
0°C to 70°C
3V, 5V, ±5V
DHC
6242HV
LTC6242IGN
4
–40°C to 85°C
3V, 5V
GN
6242I
LTC6242IDHC
4
–40°C to 85°C
3V, 5V
DHC
6242
LTC6242HVIGN
4
–40°C to 85°C
3V, 5V, ±5V
GN
242HVI
LTC6242HVIDHC
4
–40°C to 85°C
3V, 5V, ±5V
DHC
6242HV
ELECTRICAL CHARACTERISTICS
(LTC6241/LTC6241HV, LTC6242/LTC6242HV) The ● denotes the
specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C. VS = 5V, 0V, VCM = 2.5V
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
VOS
Input Offset Voltage (Note 5)
SO-Package
0°C to 70°C
–40°C to 85°C
●
●
GN Package
0°C to 70°C
–40°C to 85°C
●
●
DD, DHC Packages
0°C to 70°C
–40°C to 85°C
●
●
VOS Match Channel-to-Channel (Note 6) SO-8 Package
0°C to 70°C
–40°C to 85°C
●
●
GN Package
0°C to 70°C
–40°C to 85°C
●
●
DD, DHC Packages
0°C to 70°C
–40°C to 85°C
●
●
TC VOS
Input Offset Voltage Drift (Note 7)
IB
Input Bias Current (Notes 5, 8)
●
TYP
MAX
UNITS
40
125
250
300
µV
µV
µV
50
150
275
300
µV
µV
µV
100
550
650
725
µV
µV
µV
40
160
300
375
µV
µV
µV
50
185
325
400
µV
µV
µV
150
650
700
750
µV
µV
µV
0.7
2.5
µV/°C
75
pA
pA
1
●
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LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(LTC6241/LTC6241HV, LTC6242/LTC6242HV) The ● denotes the
specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C. VS = 5V, 0V, VCM = 2.5V
unless otherwise noted.
SYMBOL
PARAMETER
IOS
Input Offset Current (Notes 5, 8)
CONDITIONS
MIN
TYP
MAX
0.5
●
75
pA
pA
Input Noise Voltage
0.1Hz to 10Hz
en
Input Noise Voltage Density
f = 1kHz
in
Input Noise Current Density (Note 9)
RIN
Input Resistance
Common Mode
CIN
Input Capacitance
Differential Mode
Common Mode
f = 100kHz (See Typical Characteristic
Curves)
VCM
Input Voltage Range
Guaranteed by CMRR
●
0
CMRR
Common Mode Rejection
0V ≤ VCM ≤ 3.5V
●
80
105
dB
●
76
95
dB
VO = 1V to 4V
RL = 10k to VS/2
0°C to 70°C
–40°C to 85°C
425
300
200
1600
●
●
V/mV
V/mV
V/mV
VO = 1.5V to 3.5V
RL = 1k to VS/2
0°C to 70°C
–40°C to 85°C
90
60
50
215
●
●
V/mV
V/mV
V/mV
CMRR Match
Channel-to-Channel (Note 6)
AVOL
Large Signal Voltage Gain
550
UNITS
7
nVP-P
10
nV/√Hz
0.56
fA/√Hz
1012
Ω
0.5
3
pF
pF
3.5
V
VOL
Output Voltage Swing Low (Note 10)
No Load
ISINK = 1mA
ISINK = 5mA
●
●
●
7
40
190
30
75
325
mV
mV
mV
VOH
Output Voltage Swing High (Note 10)
No Load
ISOURCE = 1mA
ISOURCE = 5mA
●
●
●
11
45
190
30
75
325
mV
mV
mV
PSRR
Power Supply Rejection
VS = 2.8V to 6V, VCM = 0.2V
●
80
104
dB
PSRR Match
Channel-to-Channel (Note 6)
●
74
100
dB
Minimum Supply Voltage (Note 11)
●
2.8
ISC
Short-Circuit Current
●
15
IS
Supply Current per Amplifier
V
30
1.8
0°C to 70°C
–40°C to 85°C
●
●
mA
2.2
2.3
2.4
mA
mA
mA
GBW
Gain Bandwidth Product
Frequency = 20kHz, RL = 1kΩ
●
13
18
MHz
SR
Slew Rate (Note 12)
AV = –2, RL = 1kΩ
●
5
10
V/µs
FPBW
Full Power Bandwidth (Note 13)
VOUT = 3VP-P, RL = 1kΩ
●
0.53
1.06
MHz
ts
Settling Time
VSTEP = 2V, AV = –1, RL = 1kΩ, 0.1%
1100
ns
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LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(LTC6241/LTC6241HV, LTC6242/LTC6242HV) The ● denotes the
specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C. VS = 3V, 0V, VCM = 1.5V
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOS
Input Offset Voltage (Note 5)
SO-8 Package
0°C to 70°C
–40°C to 85°C
●
●
GN Package
0°C to 70°C
–40°C to 85°C
●
●
DD, DHC Packages
0°C to 70°C
–40°C to 85°C
●
●
IB
IOS
MIN
VOS Match Channel-to-Channel (Note 6) SO-8 Package
0°C to 70°C
–40°C to 85°C
●
●
GN Package
0°C to 70°C
–40°C to 85°C
●
●
DD, DHC Packages
0°C to 70°C
–40°C to 85°C
●
●
Input Bias Current (Notes 5, 8)
TYP
MAX
UNITS
40
175
275
325
µV
µV
µV
60
200
275
325
µV
µV
µV
100
550
650
725
µV
µV
µV
40
200
325
400
µV
µV
µV
60
225
325
400
µV
µV
µV
150
650
700
750
µV
µV
µV
75
pA
pA
75
pA
pA
1.5
V
1
●
Input Offset Current (Notes 5, 8)
0.5
●
VCM
Input Voltage Range
Guaranteed by CMRR
●
0
CMRR
Common Mode Rejection
0V ≤ VCM ≤ 1.5V
●
78
100
dB
●
76
95
dB
VO = 1V to 2V
RL = 10k to VS/2
0°C to 70°C
–40°C to 85°C
140
100
75
600
●
●
V/mV
V/mV
V/mV
CMRR Match
Channel-to-Channel (Note 6)
AVOL
Large Signal Voltage Gain
VOL
Output Voltage Swing Low (Note 10)
No Load
ISINK = 1mA
●
●
3
65
30
110
mV
mV
VOH
Output Voltage Swing High (Note 10)
No Load
ISOURCE = 1mA
●
●
4
70
30
120
mV
mV
PSRR
Power Supply Rejection
VS = 2.8V to 6V, VCM = 0.2V
●
80
104
dB
PSRR Match
Channel-to-Channel (Note 6)
●
74
100
dB
Minimum Supply Voltage (Note 11)
●
2.8
ISC
Short-Circuit Current
●
3
IS
Supply Current per Amplifier
GBW
Gain Bandwidth Product
V
6
1.4
0°C to 70°C
–40°C to 85°C
●
●
Frequency = 20kHz, RL = 1kΩ
●
12
17
mA
1.7
1.8
1.9
mA
mA
mA
MHz
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LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(LTC6241HV/LTC6242HV) The ● denotes the specifications which apply over
the specified temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, 0V, VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOS
Input Offset Voltage (Note 5)
SO-8 Package
0°C to 70°C
–40°C to 85°C
●
●
GN Package
0°C to 70°C
–40°C to 85°C
●
●
DD, DHC Packages
0°C to 70°C
–40°C to 85°C
●
●
VOS Match Channel-to-Channel (Note 6) SO-8 Package
0°C to 70°C
–40°C to 85°C
●
●
GN Package
0°C to 70°C
–40°C to 85°C
●
●
DD, DHC Packages
0°C to 70°C
–40°C to 85°C
●
●
TC VOS
Input Offset Voltage Drift (Note 7)
IB
Input Bias Current (Notes 5, 8)
IOS
MIN
●
TYP
MAX
UNITS
50
175
275
325
µV
µV
µV
60
200
275
325
µV
µV
µV
100
550
650
725
µV
µV
µV
50
200
325
400
µV
µV
µV
60
225
325
400
µV
µV
µV
150
650
700
750
µV
µV
µV
0.7
2.5
µV/°C
75
pA
pA
75
pA
pA
1
●
Input Offset Current (Notes 5, 8)
0.5
●
Input Noise Voltage
0.1Hz to 10Hz
en
Input Noise Voltage Density
f = 1kHz
in
Input Noise Current Density (Note 9)
0.56
fA/√Hz
RIN
Input Resistance
Common Mode
1012
Ω
CIN
Input Capacitance
Differential Mode
Common Mode
f = 100kHz (See Typical Characteristic
Curves)
0.5
3
pF
pF
VCM
Input Voltage Range
Guaranteed by CMRR
●
–5
CMRR
Common Mode Rejection
–5V ≤ VCM ≤ 3.5V
●
83
105
dB
●
76
95
dB
VO = –3.5V to 3.5V
RL = 10k
0°C to 70°C
–40°C to 85°C
775
600
500
2700
●
●
V/mV
V/mV
V/mV
RL = 1k
0°C to 70°C
–40°C to 85°C
150
90
75
360
●
●
V/mV
V/mV
V/mV
CMRR Match
Channel-to-Channel (Note 6)
AVOL
Large Signal Voltage Gain
550
7
nVP-P
10
3.5
nV/√Hz
V
VOL
Output Voltage Swing Low (Note 10)
No Load
ISINK = 1mA
ISINK = 10mA
●
●
●
15
45
360
30
75
550
mV
mV
mV
VOH
Output Voltage Swing High (Note 10)
No Load
ISOURCE = 1mA
ISOURCE = 10mA
●
●
●
15
45
360
30
75
550
mV
mV
mV
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LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS
(LTC6241HV/LTC6242HV) The ● denotes the specifications which apply over
the specified temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, 0V, VCM = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
PSRR
Power Supply Rejection
VS = 2.8V to 11V, VCM = 0.2V
●
MIN
TYP
85
110
dB
106
dB
PSRR Match
Channel-to-Channel (Note 6)
●
82
Minimum Supply Voltage (Note 11)
●
2.8
ISC
Short-Circuit Current
●
15
IS
Supply Current per Amplifier
●
●
UNITS
V
35
2.5
0°C to 70°C
–40°C to 85°C
MAX
mA
3.2
3.3
3.7
mA
mA
mA
GBW
Gain Bandwidth Product
Frequency = 20kHz, RL = 1kΩ
●
13
18
MHz
SR
Slew Rate (Note 12)
AV = –2, RL = 1kΩ
●
5.5
10
V/µs
FPBW
Full Power Bandwidth (Note 13)
VOUT = 3VP-P, RL = 1kΩ
●
0.58
1.06
MHz
ts
Settling Time
VSTEP = 2V, AV = –1, RL = 1kΩ, 0.1%
900
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 3: All versions of the LTC6241/LTC6242 are guaranteed functional
over the temperature range of –40°C and 85°C.
Note 4: The LTC6241C/LTC6241HVC, LTC6242C/LTC6242HVC are
guaranteed to meet specified performance from 0°C to 70°C. They are
designed, characterized and expected to meet specified performance from
–40°C to 85°C, but are not tested or QA sampled at these temperatures.
The LTC6241I/LTC6241HVI, LTC6242I/LTC6242HVI are guaranteed to meet
specified performance from –40°C to 85°C.
Note 5: ESD (Electrostatic Discharge) sensitive device. ESD protection
devices are used extensively internal to the LTC6241/LTC6242; however,
high electrostatic discharge can damage or degrade the device. Use proper
ESD handling precautions.
Note 6: Matching parameters are the difference between the two amplifiers
A and D and between B and C of the LTC6242; between the two amplifiers
of the LTC6241. CMRR and PSRR match are defined as follows: CMRR
and PSRR are measured in µV/V on the matched amplifiers. The difference
is calculated between the matching sides in µV/V. The result is converted
to dB.
Note 7: This parameter is not 100% tested.
Note 8: This specification is limited by high speed automated test
capability. See Typical Characteristics curves for actual typical
performance.
Note 9: Current noise is calculated from the formula: in = (2qIB)1/2
where q = 1.6 × 10–19 coulomb. The noise of source resistors up to
50GΩ dominates the contribution of current noise. See also Typical
Characteristics curve Noise Current vs Frequency.
Note 10: Output voltage swings are measured between the output and
power supply rails.
Note 11: Minimum supply voltage is guaranteed by the power supply
rejection ratio test.
Note 12: Slew rate is measured in a gain of –2 with RF = 1k and RG
= 500Ω. On the LTC6241/LTC6242, VIN is ±1V and VOUT slew rate is
measured between –1V and +1V. On the LTC6241HV/LTC6242HV, VIN is
±2V and VOUT slew rate is measured between –2V and +2V.
Note 13: Full-power bandwidth is calculated from the slew rate:
FPBW = SR/2πVP.
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LTC6241/LTC6242
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TYPICAL PERFOR A CE CHARACTERISTICS
VOS Distribution
VOS Temperature Coefficient
Distribution
VOS Distribution
90
120
VS = ±2.5V
80 SO-8 PACKAGE
16
VS = ±2.5V
DD PACKAGE
14
100
60
50
40
30
NUMBER OF UNITS
12
NUMBER OF UNITS
NUMBER OF UNITS
70
80
60
40
10
8
6
4
20
20
2
10
0
0
–70
–50 –30 –10 10
30
50
INPUT OFFSET VOLTAGE (µV)
70
0
–350 –250 –150 –50 50 150 250
INPUT OFFSET VOLTAGE (µV)
6241 G01
300
2.0
TA = 125°C
1.5
1.0
TA = 125°C
150
100
50
TA = 25°C
0
–50
TA = –55°C
–100
–150
1000
VS = 5V, 0V
TA = 125°C
100
TA = 85°C
10
–200
0.5
1.8
Input Bias Current vs Common
Mode Voltage
INPUT BIAS CURRENT (pA)
OFFSET VOLTAGE (µV)
200
TA = –55°C
1.4
6241 G03
VS = 5V, 0V
250
TA = 25°C
2.5
–1.0 –0.6 –0.2 0.2 0.6 1.0
DISTRIBUTION (µV/°C)
Offset Voltage vs Input Common
Mode Voltage
3.5
3.0
350
6241 G02
Supply Current vs Supply Voltage
SUPPLY CURRENT (mA)
VS = ±2.5V
2 LOTS
–55°C TO 125°C
TA = 25°C
–250
0
2
8
6
10
4
TOTAL SUPPLY VOLTAGE (V)
12
Input Bias Current vs
Common Mode Voltage
1000
VS = 5V, 0V
INPUT BIAS CURRENT (pA)
500
400
300
200
TA = 25°C
TA = 125°C
100
0
–100
–200
TA = 85°C
Output Saturation Voltage vs
Load Current (Output Low)
10
VCM = VS/2
100
VS = 10V
10
VS = 5V
–300
–400
–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
COMMON MODE VOLTAGE (V)
6241 G07
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
COMMON MODE VOLTAGE (V)
6241 G06
Input Bias Current vs Temperature
INPUT BIAS CURRENT (pA)
600
0
6241 G05
6241 G04
700
1
–300
–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
INPUT COMMON MODE VOLTAGE (V)
OUTPUT LOW SATURATION VOLTAGE (V)
0
1
25 35 45 55 65 75 85 95 105 115 125
TEMPERATURE (°C)
6241 G08
VS = 5V, 0V
TA = 25°C
1
TA = 125°C
0.1
TA = –55°C
0.01
0.001
0.1
10
1
LOAD CURRENT (mA)
100
6241 G09
62412f
8
LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Output Saturation Voltage vs
Load Current (Output High)
TA = –55°C
0.1
PHASE MARGIN
30
40
30
VS = ±5V
20
0
–55 –35 –15
100
GAIN BANDWIDTH
20
5 25 45 65 85 105 125
TEMPERATURE (°C)
14
12
8
VS = ±5V RISING
VS = ±2.5V RISING
20
–40
–50
–60
–70
–80
–90
10
–100
0
–110
–10
10k
100k
1M
10M
FREQUENCY (Hz)
100M
6241 G17
100k
1M
FREQUENCY (Hz)
10M
6241 G16
Power Supply Rejection Ratio vs
Frequency
–120
10k
90
POWER SUPPLY REJECTION RATIO (dB)
–30
30
AV = 2
AV = 1
0.01
10k
5 25 45 65 85 105 125
TEMPERATURE (°C)
TA = 25°C
VS = ±2.5V
AV = 1
–20
VOLTAGE GAIN (dB)
COMMON MODE REJECTION (dB)
0
–10
80
40
1
Channel Separation vs Frequency
TA = 25°C
VS = ±2.5V
50
AV = 10
10
6241 G15
Common Mode Rejection Ratio vs
Frequency
60
100
0.10
6241 G14
70
TA = 25°C
VS = ±2.5V
1k
VS = ±2.5V FALLING
4
–55 –35 –15
12
–80
100M
1M
10M
FREQUENCY (Hz)
Output Impedance vs Frequency
10k
6
0
90
100k
6241 G13
VS = ±5V FALLING
10
GAIN BANDWIDTH
100
–40
–60
–20
10k
OUTPUT IMPEDANCE (Ω)
30
0
–20
VS = ±1.5V
0
16
SLEW RATE (V/µs)
GAIN BANDWIDTH (MHz)
40
4
6
8
10
TOTAL SUPPLY VOLTAGE (V)
10
AV = –2
18 RF = 1k, RG = 500Ω
CONDITIONS: SEE NOTE 12
PHASE MARGIN (DEG)
50
PHASE MARGIN
20
VS = ±5V
20
Slew Rate vs Temperature
60
40
VS = ±1.5V
30
20
70
TA = 25°C
CL = 5pF
RL = 1k
2
60
VS = ±5V
GAIN
40
6241 G12
Gain Bandwidth and Phase
Margin vs Supply Voltage
0
50
–10
6241 G10
10
60
VS = ±1.5V
10
10
1
LOAD CURRENT (mA)
40
VS = ±1.5V
70
GAIN (dB)
GAIN BANDWIDTH (MHz)
TA = 125°C
50
120
CL = 5pF
100
RL = 1k
VCM = VS/2
80
PHASE
PHASE (DEG)
1
80
CL = 5pF
RL = 1k 60
VS = ±5V
TA = 25°C
0.01
0.1
Open Loop Gain vs Frequency
70
VS = 5V, 0V
PHASE MARGIN (DEG)
OUTPUT HIGH SATURATION VOLTAGE (V)
10
Gain Bandwidth and Phase
Margin vs Temperature
TA = 25°C
VS = ±2.5V
80
70
60
50
POSITIVE SUPPLY
40
30
20
NEGATIVE SUPPLY
10
0
100k
1M
10M
FREQUENCY (Hz)
100M
6241 G18
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
6241 G19
62412f
9
LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
16
CHANGE IN OFFSET VOLTAGE (µV)
CCM
10
8
CDM
6
4
2
50
VCM = VS/2
80
14
INPUT CAPACITANCE (pF)
100
VS = ±1.5V
12
Output Short Circuit Current vs
Power Supply Voltage
Minimum Supply Voltage
60
40
TA = 25°C
20
0
–20
TA = –55°C
–40
TA = 125°C
–60
–80
0
1k
10k
100k
1M
FREQUENCY (Hz)
0
1
2 3 4 5 6 7 8
TOTAL SUPPLY VOLTAGE (V)
10
20
0
80
60
RL = 10k
40
RL = 1k
20
2.5
TA = 125°C
SOURCING
–30
–40
TA = –55°C
2.0 2.5 3.0 3.5 4.0 4.5
POWER SUPPLY VOLTAGE (±V)
3.0
TA = 25°C
VS = ±5V
60
40
20
RL = 10k
0
RL = 1k
–20
–60
0
1
2
3
4
OUTPUT VOLTAGE (V)
6241 G23
–5 –4 –3 –2 –1 0 1 2 3
OUTPUT VOLTAGE (V)
5
VS = ±5V
60
TA = 25°C
TA = 25°C
VS = ±2.5V
VCM = 0V
TA = 125°C
200
100
TA = 25°C
0
–100
TA = –55°C
–200
–300
50
20
VS = ±5V
NOISE VOLTAGE (nV/√Hz)
OFFSET VOLTAGE (µV)
CHANGE IN OFFSET VOLTAGE (µV)
400
300
15
VS = ±2.5V
10
5
VS = ±1.5V
0
5
Noise Voltage vs Frequency
Warm-Up Drift vs Time
25
4
6241 G25
6241 G24
Offset Voltage vs Output Current
5.0
–40
–20
1.0
1.5
2.0
OUTPUT VOLTAGE (V)
500
–20
80
0
0.5
–10
100
INPUT VOLTAGE (µV)
INPUT VOLTAGE (µV)
RL = 10k
40
TA = 25°C
0
6241 G22
TA = 25°C
VS = 5V, 0V
100
100
0
10
Open Loop Gain
120
TA = 25°C
VS = 3V, 0V
RL = 100k
TA = 125°C
20
Open Loop Gain
80
TA = –55°C
SINKING
30
6241 G21
Open Loop Gain
120
60
9
40
–50
1.5
–100
100M
10M
6241 G20
INPUT VOLTAGE (µV)
OUTPUT SHORT-CIRCUIT CURRENT (mA)
Input Capacitance vs Frequency
40
30
20
10
–400
–500
–50 –40 –30 –20 –10 0 10 20 30 40 50
OUTPUT CURRENT (mA)
6241 G26
0
–5
0
5 10 15 20 25 30 35 40 45 50 55 60
TIME AFTER POWER UP (s)
6241 G27
1
10
100
1k
FREQUENCY (Hz)
10k
100k
6241 G28
62412f
10
LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
0.1Hz to 10Hz Voltage Noise
Series Output Resistance and
Overshoot vs Capacitive Load
Noise Current vs Frequency
1000
60
TA = 25°C
VS = ±2.5V
VCM = 0V
75pF
50
1k
10
1k
–
100
RS
+
40
OVERSHOOT (%)
NOISE CURRENT (pA/√Hz)
VOLTAGE NOISE (200nV/DIV)
VS = 5V, 0V
CL
30
RS = 10Ω
20
RS = 50Ω
1
10
0
0.1
100
10k
1k
FREQUENCY (Hz)
TIME (1s/DIV)
6241 G42
+
40
RS
SETTLING TIME (µs)
OVERSHOOT (%)
TA = 25°C
VS = ±5V
3.0 A = 1
V
1k
–
CL
30
RS = 10Ω
20
RS = 50Ω
10
0
100
CAPACITIVE LOAD (pF)
2.5
–
VIN
+
VOUT
1k
2.0
1mV
1.5
1.0
1mV
0.5
VS = ±2.5V
AV = –2
10
6241 G29
3.5
75pF
500Ω
10mV
10mV
0
1000
–4
–3
–2
–1
0
1
2
OUTPUT STEP (V)
10
TA = 25°C
VS = ±5V
2.5 AV = –1
1k
SETTLING TIME (µs)
VIN
–
+
2.0
OUTPUT VOLTAGE SWINGING (VP-P)
3.0
1k
VOUT
1k
1mV
1mV
1.0
10mV
0.5
10mV
0
–3
4
Maximum Undistorted Output
Signal vs Frequency
Settling Time vs Output Step
(Inverting)
–4
3
6241 G31
6241 G30
1.5
1000
Settling Time vs Output Step
(Non-Inverting)
Series Output Resistance and
Overshoot vs Capacitive Load
50
100
CAPACITIVE LOAD (pF)
10
100k
6241 G11
60
VS = ±2.5V
AV = –1
–2
–1
0
1
2
OUTPUT STEP (V)
3
4
6241 G32
9
8
AV = –1
7
6
AV = +2
5
4
3
TA = 25°C
2 VS = ±5V
HD2, HD3 < –40dBc
1
10k
100k
1M
FREQUENCY (Hz)
10M
6241 G33
62412f
11
LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Distortion vs Frequency
VS = ±2.5V
AV = 1
–40 V
OUT = 2VP-P
–30
–50
–50
VS = ±5V
AV = 1
–40 V
OUT = 2VP-P
DISTORTION (dBc)
DISTORTION (dBc)
Distortion vs Frequency
–30
RL = 1k, 2ND
–60
–70
RL = 1k, 3RD
–80
–90
–60
RL = 1k, 2ND
–70
RL = 1k, 3RD
–80
–90
–100
10k
100k
1M
FREQUENCY (Hz)
10M
–100
10k
100k
1M
FREQUENCY (Hz)
6241 G34
6241 G35
Distortion vs Frequency
VS = ±2.5V
AV = 2
–40 V
OUT = 2VP-P
–30
–50
–50
VS = ±5V
AV = 2
–40 V
OUT = 2VP-P
DISTORTION (dBc)
DISTORTION (dBc)
Distortion vs Frequency
–30
–60
RL = 1k, 2ND
–70
–80
RL = 1k, 3RD
–90
–100
10k
10M
–60
RL = 1k, 2ND
–70
RL = 1k, 3RD
–80
–90
100k
1M
FREQUENCY (Hz)
10M
6241 G36
–100
10k
100k
1M
FREQUENCY (Hz)
10M
6241 G37
62412f
12
LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Small Signal Response
Large Signal Response
0V
0V
VS = ±2.5V
AV = 1
RL = ∞
VS = ±5V
AV = 1
RL = ∞
6241 G38
Large Signal Response
6241 G39
Output Overdrive Recovery
0V
VIN
(1V/DIV)
0V
0V
VOUT
(2V/DIV)
VS = ±2.5V
AV = –1
RL = 1k
6241 G40
VS = ±2.5V
AV = 3
RL = ∞
500ns/DIV
6241 G41
62412f
13
LTC6241/LTC6242
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Amplifier Characteristics
Figure 1 is a simplified schematic of the LTC6241, which
has a pair of low noise input transistors M1 and M2. A
simple folded cascode Q1, Q2 and R1, R2 allow the input
stage to swing to the negative rail, while performing level
shift to the Differential Drive Generator. Low offset voltage
is accomplished by laser trimming the input stage.
Capacitor C1 reduces the unity cross frequency and improves the frequency stability without degrading the gain
bandwidth of the amplifier. Capacitor Cm sets the overall
amplifier gain bandwidth. The differential drive generator
supplies signals to transistors M3 and M4 that swing the
output from rail-to-rail.
The photo of Figure 2 shows the output response to an
input overdrive with the amplifier connected as a voltage
follower. If the negative going input signal is less than
a diode drop below V–, no phase inversion occurs. For
input signals greater than a diode drop below V–, limit the
current to 3mA with a series resistor RS to avoid phase
inversion.
ESD
The LTC6241 has reverse-biased ESD protection diodes
on all input and outputs as shown in Figure 1. If these
pins are forced beyond either supply, unlimited current
will flow through these diodes. If the current is transient
and limited to one hundred milliamps or less, no damage
to the device will occur.
The amplifier input bias current is the leakage current of
these ESD diodes. This leakage is a function of the temperature and common mode voltage of the amplifier, as
shown in the Typical Performance Curves.
Noise
The LTC6241 exhibits exceptionally low 1/f noise in the
0.1Hz to 10Hz region. This 550nVP-P noise allows these
op amps to be used in a wide variety of high impedance
low frequency applications, where Zero-Drift amplifiers
might be inappropriate due to their charge injection.
In the frequency region above 1kHz the LTC6241 also
show good noise voltage performance. In this frequency
region, noise can easily be dominated by the total source
resistance of the particular application. Specifically, these
amplifiers exhibit the noise of a 3.1kΩ resistor, meaning it
is desirable to keep the source and feedback resistance at
or below this value, i.e. RS + RG||RFB ≤ 3.1kΩ. Above this
total source impedance, the noise voltage is not dominated
by the amplifier.
Noise current can be estimated from the expression in =
√2qIB, where q = 1.6 • 10–19 coulombs. Equating √4kTRΔf
and R√2qIBΔf shows that for source resistors below 50GΩ
the amplifier noise is dominated by the source resistance.
See the Typical Characteristics curve Noise Current vs
Frequency.
VDD =
+2.5V
V+
ITAIL
M3
CM
V–
V+
DESD1
V+
DESD2
VIN+
DESD5
M1
VIN–
DIFFERENTIAL
DRIVE
GENERATOR
M2
VO
DESD4
V–
V+
VOUT AND VIN OF FOLLOWER WITH LARGE INPUT OVERDRIVE
DESD6
C1
DESD3
VSS =
–2.5V
V–
+2.5V
V–
Q1
Q2
RS
M4
BIAS
VIN
+
1/2
LTC6241
VOUT
–
R1
R2
–2.5V
V–
6241 F01
Figure 1. Simplified Schematic
6241 F02
Figure 2. Unity Gain Follower Test Circuit
62412f
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Proprietary design techniques are used to obtain simultaneous low 1/f noise and low input capacitance. Low
input capacitance is important when the amplifier is used
with high source and feedback resistors. High frequency
noise from the amplifier tail current source, ITAIL in Figure 1, couples through the input capacitance and appears
across these large source and feedback resistors. As an
example, the photodiode amplifier of Figure 11 on the last
page of this data sheet shows the noise results from the
LTC6241 and the results of a competitive CMOS amplifier.
The LTC6241 output is the ideal noise of a 1MΩ resistor
at room temperature, 130nV√Hz.
+2.5
+
1/4
LTC6242
1k
–
–2.5
1k
10Ω
+
1/4
LTC6242
1k
–
VIN
The circuit shown in Figure 3 can be used to achieve even
lower noise voltage. By paralleling 4 amplifiers the noise
voltage can be lowered by √4, or half as much noise. The
√ comes about from an RMS summing of uncorrelated
noise sources. This circuit maintains extremely high input
resistance, and has a 250Ω output resistance. For lower
output resistance, a buffer amplifier can be added without
influencing the noise.
Stability
The good noise performance of these op amps can be attributed to large input devices in the differential pair. Above
several hundred kilohertz, the input capacitance rises and
can cause amplifier stability problems if left unchecked.
When the feedback around the op amp is resistive (RF), a
pole will be created with RF , the source resistance, source
capacitance (RS, CS), and the amplifier input capacitance.
In low gain configurations and with RF and RS in even
the kilohm range (Figure 4), this pole can create excess
phase shift and possibly oscillation. A small capacitor CF
in parallel with RF eliminates this problem.
Low Noise Single-Ended Input to Differential Output
Amplifier
VO
1k
10Ω
Half the Noise
+
1/4
LTC6242
1k
–
The circuit on the first page of the data sheet is a low noise
single-ended input to differential output amplifier, with a
200k input impedance. The very low input bias current
of the LTC6241 allows for these large input and feedback
resistors. The 200k resistors, R1 and R2, along with C1
and C2 set the –3dB bandwidth to 80kHz. Capacitor C3 is
used to cancel effects of input capacitance, while C4 adds
1k
10Ω
CF
RF
+
1/4
LTC6242
1k
–
–
RS
CIN
CS
OUTPUT
+
6241 F04
10Ω
1k
Figure 4. Compensating Input Capacitance
6241 F03
Figure 3. Parallel Amplifier Lowers Noise by 2x
62412f
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DIFFERENTIAL OUTPUT VOLTAGE DENSITY (nV/√Hz)
phase lead to compensate the phase lag of the second
amplifier. The op amp’s good input offset voltage match
and low input bias current means that the typical differential
output voltage is less than 40µV. A noise spectrum plot of
the differential output is shown in Figure 5.
140
VS = ±2.5V
TA = 25°C
120 –3dB BW = 80kHz
100
80
60
40
20
gain of the difference amplifier is one. An LTC6910-2 PGA
amplifies the difference amplifier output with inverting
gains of –1, –2, –4, –8, –16, –32 and –64. The second
LTC6241 op amp is used as an integrator to set the DC
output voltage equal to the LT6650 reference voltage VREF.
The integrator drives the PGA analog ground to provide
a feedback loop, in addition to blocking any DC voltage
through the PGA. The reference voltage of the LT6650
can be set to a voltage from 400mV to V+ – 350mV with
resistors R5 and R6. If R6 is 20k or less, the error due
to the LT6650 op amp bias current is negligible. The low
voltage offset and drift of the LTC6241 integrator will not
contribute any significant error to the LT6650 reference
voltage. The LT6650 VREF voltage has a maximum error
V+
R3
0
0
10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)
R1
6241 F05
8
V1
G1
G0
7
6
5
LTC6910-2
Figure 5. Differential Output Noise
OUT AGND IN V–
1
2
3
4
+
1/2
LTC6241
Achieving Low Input Bias Current
–
VOUT
R2
100Ω
R4
R7
C3
V2
C2
V+
R1 = R2 = R3 = R4
0.1µF
R5
–
1/2
LTC6241
1000pF
+
The DD package is leadless and makes contact to the PCB
beneath the package. Solder flux used during the attachment of the part to the PCB can create leakage current
paths and can degrade the input bias current performance
of the part. All inputs are susceptible because the backside
paddle is connected to V– internally. As the input voltage
changes or if V– changes, a leakage path can be formed
and alter the observed input bias current. For lowest bias
current, use the LTC6241 in the SO-8 and provide a guard
ring around the inputs that are tied to a potential near the
input voltage.
G2
0.1µF
C1
R6
20k
1
LT6650
2
5
VREF
1µF
3
1k
4
V+
1µF
A Digitally Programmable AC Difference Amplifier
The LTC6241 configured as a difference amplifier, can
be combined with a programmable gain amplifier (PGA)
to obtain a low noise high speed programmable difference amplifier. Figure 6 shows the LTC6241 based as a
single-supply AC amplifier. One LTC6241 op amp is used
at the circuit’s input as a standard four resistor difference
amplifier. The low bias current and current noise of the
LTC6241 allow the use of high valued input resistors, 100k
or greater. Resistors R1, R2, R3 and R4 are equal and the
DIGITAL INPUTS
G2 G1 GO
GAIN
0
0
1
1
0
0
1
1
0
–1
–2
–4
–8
–16
–32
–64
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
VOUT = (V1 – V2) GAIN + VREF
⎛ R5 ⎞
VREF = 0.4 • ⎜
+1
⎝ R6 ⎟⎠
R5 = 10k • ( 5 • VREF – 2) R6 = 20k
–3d BANDWIDTH = ( fHIGH – fLOW )
fHIGH =
1
GAIN
=
f
2 • π • R3 • C1 LOW 2 • π • R7 • C3
6241 F06
Figure 6. Wideband Difference Amplifier with High
Input Impedance and Digitally Programmable Gain
62412f
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of ±2% with 1% resistors. The upper –3dB frequency of
the amplifier is set by resistor R3 and capacitor C1 and
is limited by the bandwidth of the PGA when operated at
a gain of 64. Capacitor C2 is equal to C1 and is added to
maintain good common mode rejection at high frequency.
The lower –3dB frequency is set by the integrator resistor
R7, capacitor C3, and the gain setting of the LTC6910-2
PGA. This lower –3dB zero frequency is multiplied by the
PGA gain. The rail-to-rail output of the LTC6910-2 PGA
allows for a maximum output peak-to-peak voltage equal
to twice the VREF voltage. At the maximum gain setting of
64, the maximum peak-to-peak difference between inputs
V1 and V2 is equal to twice VREF divided by 64.
Example Design: Design a programmable gain AC difference amplifier, with a bandwidth 10Hz to 100kHz, an input
impedance equal or greater than 100kΩ, and an output
DC reference equal to 1V.
a. Select input resistors R1, R2, R3 and R4 equal to
100k.
b. If the upper –3dB frequency is 100kHz then C1 = 1/(2π
• R2 • f3dB) = 1/(6.28 • 100kΩ • 100kHz) = 15pF (to
the nearest 5% value) and C2 = C1 = 15pF.
c. Select R7 equal to one 1M and set the lower –3dB
frequency to 10Hz at the highest PGA gain of 64, then
C3 = Gain/(2π • R7 • f3dB) = 64/(6.28 • 100kΩ • 10Hz)
= 1uF. Lower gains settings will give a lower f3dB.
d. Calculate the value of R5 to set the LT6650 reference
equal to 1V;
VREF = 0.4(R5/R6 + 1), so R5 = R6(2.5VREF – 1). For
R6 = 20kΩ, R5 = 30kΩ
With VREF = 1V the maximum input difference voltage
is equal to 2V/64 = 31.2mV.
40nVpp Noise, 0.05µV/°C Drift, Chopped FET
Amplifier
Figure 7’s circuit combines the 5V rail-to-rail performance
of the LTC6241 with a pair of extremely low noise JFETs
configured in a chopper based carrier modulation scheme
to achieve an extraordinarily low noise and low DC drift.
The performance of this circuit is suited for the demanding transducer signal conditioning situations such as high
resolution scales and magnetic search coils.
The LTC1799’s output is divided down to form a 2-phase
925Hz square wave clock. This frequency, harmonically
unrelated to 60Hz, provides excellent immunity to harmonic
beating or mixing effects which could cause instabilities.
S1 and S2 receive complementary drive, causing A1 to
see a chopped version of the input voltage. A1’s square
wave output is synchronously demodulated by S3 and
S4. Because these switches are synchronously driven
with the input chopper, proper amplitude and polarity
information is presented to A2, the DC output amplifier.
This stage integrates the square wave into a DC voltage,
providing the output. The output is divided down (R2 and
R1) and fed back to the input chopper where it serves as
a zero signal reference. Gain, in this case 1000, is set by
the R1-R2 ratio. Because A1 is AC coupled, its DC offset
and drift do not affect the overall circuit offset, resulting
in the extremely low offset and drift noted. The JFETs
have an input RC damper that minimizes offset voltage
contribution due to parasitic switch behavior, resulting in
the 1µV offset specification.
The noise measured over a 50 second interval, in Figure 8,
is 40nV in a 0.1Hz to 10Hz bandwidth.This low noise is attributed to the input JFET’s die size and current density.
62412f
17
LTC6241/LTC6242
U
U
W
U
APPLICATIO S I FOR ATIO
5V
TO LTC201 V + PIN
–5V
TO LTC201 V – PIN
1µF
5V
18.5kHz
V+
74C90 ÷ 10
DIV LTC1799 OUT
RSET
5V
+
+
1µF
5V
74C74 ÷ 2
Q
Q
925Hz
54.2k*
TO
Ø1
POINTS
5V
Ø1
TO
Ø2
POINTS
8
898Ω**
3k
INPUT
898Ω**
6
7
Ø2
S1
S2
0.01µF
11
10
9
Ø2
1µF
1
–
LSK389
499Ω**
1µF
A1
LTC6241HV
+
3
2
S3
S4
10M
–5V
240k
14
15
16
10k
Ø1
1µF
* = 0.1% METAL FILM RESISTOR
** = 1% METAL FILM RESISTOR
= LTC201 QUAD
= LSK389
= LINEAR INTEGRATED SYSTEMS
FREMONT, CA
NOISE = 40nVP-P 0.1Hz TO 10Hz
OFFSET = 1µV
DRIFT = 0.05µV/°C
R2 +1
GAIN =
10
OPEN-LOOP GAIN = 10 9
I BIAS = 500pA
–
A2
LTC6241HV
OUTPUT
+
R2
10k
R1
10Ω
6241 F07
Figure 7. Ultra Low Noise Chopper Amplifier
VERT = 20nV/DIV
HORIZ = 5s/DIV
6241 F08
Figure 8. Noise in a 0.1Hz to 10Hz Bandwidth
62412f
18
LTC6241/LTC6242
U
U
W
U
APPLICATIO S I FOR ATIO
Low Noise Shock Sensor Amplifiers
Figures 9 and 10 show the LTC6241 realizing two different
approaches to amplifying signals from a capacitive sensor.
The sensor in both cases is a 770pF piezoelectric shock
sensor accelerometer, which generates charge under
physical acceleration.
Figure 9 shows the classical “charge amplifier” approach.
The LTC6241 is in the inverting configuration so the sensor
looks into a virtual ground. All of the charge generated
by the sensor is forced across the feedback capacitor
by the op amp action. Because the feedback capacitor
is 100 times smaller than the sensor, it will be forced to
100 times what would have been the sensor’s open circuit
voltage. So the circuit gain is 100. The benefit of this approach is that the signal gain of the circuit is independent
of any cable capacitance introduced between the sensor
and the amplifier. Hence this circuit is favored for remote
accelerometers where the cable length may vary. Difficulties
with the circuit are inaccuracy of the gain setting with the
small capacitor, and low frequency cutoff due to the bias
resistor working into the small feedback capacitor.
Figure 10 shows a non-inverting amplifier approach. This
approach has many advantages. First of all, the gain is set
accurately with resistors rather than with a small capacitor. Second, the low frequency cutoff is dictated by the
bias resistor working into the large 770pF sensor, rather
than into a small feedback capacitor, for lower frequency
response. Third, the non-inverting topology can be paralleled and summed (as shown) for scalable reductions in
voltage noise. The only drawback to this circuit is that the
parasitic capacitance at the input reduces the gain slightly.
This circuit is favored in cases where parasitic input
capacitances such as traces and cables will be relatively
small and invariant.
VS+
+
+
SHOCK SENSOR
MURATA-ERIE
PKGS-00LD
770pF
CABLE HAS
UNKNOWN C
1/2
LTC6241
–
Cf
7.7pF
Rf
1G
BIAS RESISTOR
VISHAY-TECHNO
CRHV2512AF1007G
(OR EQUIVALENT)
1/2
LTC6241HV
SHOCK SENSOR
MURATA-ERIE
PKGS-00LD
770pF
–
100Ω
VOUT = 110mV/g
MAIN
GAIN-SETTING
ELEMENT IS A
CAPACITOR
1G
Figure 9. Classical Inverting Charge Amplifier
10k
VOUT
1k
+
1/2
LTC6241HV
BIAS RESISTOR
VISHAY-TECHNO
CRHV2512AF1007G
(OR EQUIVALENT)
–
100Ω
6241 F09
1k
VOUT = 110mV/g
VS = ±1.4V to ±5.5V
BW = 0.2Hz to 10kHz
VS–
10k
6241 F10
Figure 10. Low Noise Non-Inverting Shock Sensor Amplifier
62412f
19
LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
0.65 ±0.05
3.50 ±0.05
1.65 ±0.05
2.20 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
4.40 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
5.00 ±0.10
(2 SIDES)
R = 0.20
TYP
3.00 ±0.10
(2 SIDES)
9
0.40 ± 0.10
16
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PIN 1
NOTCH
(DHC16) DFN 1103
8
0.200 REF
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
4.40 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
62412f
20
LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ± .0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
2 3
4
5 6
7
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN16 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
62412f
21
LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
TYP
5
0.38 ± 0.10
8
0.675 ±0.05
3.5 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
3.00 ±0.10
(4 SIDES)
PACKAGE
OUTLINE
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD8) DFN 1203
0.25 ± 0.05
0.200 REF
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.75 ±0.05
0.00 – 0.05
4
0.25 ± 0.05
1
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
62412f
22
LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
.050 BSC
8
.245
MIN
7
6
5
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
× 45°
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
3
4
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
2
.014 – .019
(0.355 – 0.483)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
.050
(1.270)
BSC
SO8 0303
62412f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC6241/LTC6242
U
TYPICAL APPLICATIO
150kHz 3RD ORDER BUTTERWORTH FILTER
1MΩ TIA
R1
866Ω
+
1/2
LTC6241
–
RF
1MΩ
C1
1500pF
R2
1.69k
R3
2k
C2
1500pF
+1.5V
+
1/2
LTC6241
C3
180pF
–
SFH213FA
OR EQUIVALENT
(≤4pF)
–1.5V
6241 TA02a
CF
1pF
–1.5V
Figure 11. Ultralow Noise 1MΩ 150kHz Photodiode Amplifier
Competition Output Noise Spectrum. Op Amp Noise Dominates;
Performance Compromised
30nV/√Hz PER DIV
30nV/√Hz PER DIV
LTC6241 Output Noise Spectrum. 1MΩ Resistor Noise
Dominates; Ideal Performance
0V
0V
1kHz
10kHz/DIV
101kHz
1kHz
10kHz/DIV
101kHz
6241 TA02b
6241 TA02c
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1151
±15V Zero-Drift Op Amp
Dual High Voltage Operation ±18V
LT1792
Low Noise Precision JFET Op Amp
6nV/√Hz Noise, ±15V Operation
LTC2050
Zero-Drift Op Amp
2.7 Volt Operation, SOT-23
LTC2051/LTC2052
Dual/Quad Zero-Drift Op Amp
Dual/Quad Version of LTC2050 in MS8/GN16 Packages
LTC2054/LTC2055
Single/Dual Zero-Drift Op Amp
Micropower Version of the LTC2050/LTC2051 in SOT-23 and DD Packages
62412f
24 Linear Technology Corporation
LT/TP 0605 500 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005