NSC DS90CF583 Lvds 24-bit color flat panel display (fpd) linkâ 65 mhz Datasheet

DS90CF583/DS90CF584
LVDS 24-Bit Color Flat Panel Display (FPD) Link—
65 MHz
General Description
Features
The DS90CF583 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. The DS90CF584 receiver converts the LVDS
data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 4
bits of LCD timing and control data (FPLINE, FPFRAME,
DRDY, CONTROL) are transmitted at a rate of 455 Mbps per
LVDS data channel. Using a 65 MHz clock, the data throughput is 227 Mbytes per second. These devices are offered
with falling edge data strobes for convenient interface with a
variety of graphics and LCD panel controllers.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
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20 to 65 MHz shift clk support
Up to 227 Mbytes/s bandwidth
Cable size is reduced to save cost
290 mV swing LVDS devices for low EMI
Low power CMOS design ( < 550 mW typ)
Power-down mode saves power ( < 0.25 mW)
PLL requires no external components
Low profile 56-lead TSSOP package
Falling edge data strobe
Compatible with TIA/EIA-644 LVDS standard
Single pixel per clock XGA (1024 x 768)
Supports VGA, SVGA, XGA and higher
1.8 Gbps throughput
Block Diagrams
DS012616-24
Order Number DS90CF583MTD
See NS Package Number MTD56
DS012616-1
Order Number DS90CF584MTD
See NS Package Number MTD56
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS012616
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DS90CF583/DS90CF584 LVDS 24-Bit Color Flat Panel Display (FPD) Link— 65 MHz
November 1996
Block Diagrams
(Continued)
DS012616-2
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2
Absolute Maximum Ratings (Note 1)
DS90CF584
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Duration
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 4 sec)
Maximum Power Dissipation @ 25˚C
MTD56 (TSSOP) Package:
DS90CF583
−0.3V to +6V
(VCC + 0.3V)
(VCC + 0.3V)
(VCC + 0.3V)
(VCC + 0.3V)
Continuous
+150˚C
−65˚C to +150˚C
+260˚C
−0.3V
−0.3V
−0.3V
−0.3V
1.61W
Package Derating:
DS90CF583
12.5 mW/˚C above +25˚C
DS90CF584
12.4 mW/˚C above +25˚C
This device does not meet 2000V ESD rating (Note 4) .
to
to
to
to
Recommended Operating
Conditions
Supply Voltage (VCC)
Operating Free Air
Temperature (TA)
Receiver Input Range
Supply Noise Voltage (VCC)
Min
4.75
−10
Nom
5.0
+25
0
Max
5.25
+70
Units
V
˚C
2.4
100
V
mVP-P
1.63W
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
CMOS/TTL DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VCC
VIL
Low Level Input Voltage
GND
0.8
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VCL
Input Clamp Voltage
IIN
Input Current
IOS
Output Short Circuit Current
IOH = −0.4 mA
IOL = 2 mA
3.8
ICL = −18 mA
VIN = VCC, GND, 2.5V or 0.4V
VOUT = 0V
4.9
V
V
0.1
0.3
V
−0.79
−1.5
V
± 5.1
± 10
µA
−120
mA
LVDS DRIVER DC SPECIFICATIONS
VOD
Differential Output Voltage
∆VOD
Change in VOD between
RL = 100Ω
250
290
450
mV
35
mV
Complementary Output States
VCM
Common Mode Voltage
∆VCM
Change in VCM between
1.1
1.25 1.375
35
V
mV
Complementary Output States
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
IOS
Output Short Circuit Current
IOZ
Output TRI-STATE ® Current
1.3
0.9
VOUT = 0V, RL = 100Ω
Power Down = 0V, VOUT = 0V or VCC
1.6
1.01
V
V
−2.9
−5
mA
±1
± 10
µA
+100
mV
LVDS RECEIVER DC SPECIFICATIONS
VTH
Differential Input High
Threshold
VTL
Differential Input Low Threshold
IIN
Input Current
VCM = +1.2V
−100
VIN = +2.4V
VIN = 0V
VCC = 5.5V
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
f = 32.5 MHz
mV
± 10
± 10
µA
µA
TRANSMITTER SUPPLY CURRENT
ICCTW
ICCTG
Transmitter Supply Current,
RL = 100Ω, CL = 5 pF,
Worst Case
Worst Case Pattern
Transmitter Supply Current,
(Figure 1, Figure 3)
RL = 100Ω, CL = 5 pF,
16 Grayscale
16 Grayscale Pattern
(Figure 2, Figure 3)
3
f = 37.5 MHz
f = 65 MHz
49
63
mA
51
64
mA
70
84
mA
40
55
mA
41
55
mA
55
67
mA
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Electrical Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1
25
µA
TRANSMITTER SUPPLY CURRENT
ICCTZ
Power Down = Low
Transmitter Supply Current,
Power Down
RECEIVER SUPPLY CURRENT
ICCRW
ICCRG
ICCRZ
Receiver Supply Current,
CL = 8 pF,
Worst Case
Worst Case Pattern
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
f = 32.5 MHz
Receiver Supply Current,
(Figure 1, Figure 4)
CL = 8 pF,
16 Grayscale
16 Grayscale Pattern
Receiver Supply Current,
(Figure 2, Figure 4)
Power Down = Low
f = 37.5 MHz
f = 65 MHz
64
77
mA
70
85
mA
110
140
mA
35
55
mA
37
55
mA
55
67
mA
1
10
µA
Power Down
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VCC = 5.0V and TA = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ∆VOD).
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF)
PLL VCC ≥ 1000V
All other pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Typ
Max
Units
LLHT
LVDS Low-to-High Transition Time (Figure 3)
0.75
1.5
ns
LHLT
LVDS High-to-Low Transition Time (Figure 3)
0.75
1.5
ns
TCIT
TxCLK IN Transition Time (Figure 5)
TCCS
TxOUT Channel-to-Channel Skew (Note 5) (Figure 6)
TxCLK IN to TxCLK OUT Delay @ 25˚C, VCC = 5.0V
TCCD
Parameter
Min
3.5
8
ns
350
ps
8.5
ns
(Figure 9)
TCIP
TxCLK IN Period (Figure 7)
TCIH
TxCLK IN High Time (Figure 7)
TCIL
TxCLK IN Low Time (Figure 7)
TSTC
TxIN Setup to TxCLK IN (Figure 7 )
THTC
TxIN Hold to TxCLK IN (Figure 7)
f = 65 MHz
15
T
50
ns
0.35T
0.5T
0.65T
ns
0.35T
0.5T
0.65T
ns
5
3.5
ns
2.5
1.5
ns
TPDD
Transmitter Powerdown Delay (Figure 18)
100
ns
TPLLS
Transmitter Phase Lock Loop Set (Figure 11)
10
ms
TPPos0
Transmitter Output Pulse Position 0 (Figure 13)
−0.30
0
0.30
ns
TPPos1
Transmitter Output Pulse Position 1
1.70
1/7 Tclk
2.50
ns
TPPos2
Transmitter Output Pulse Position 2
3.60
2/7 Tclk
4.50
ns
TPPos3
Transmitter Output Pulse Position 3
5.90
3/7 Tclk
6.75
ns
TPPos4
Transmitter Output Pulse Position 4
8.30
4/7 Tclk
9.00
ns
TPPos5
Transmitter Output Pulse Position 5
10.40
5/7 Tclk
11.10
ns
TPPos6
Transmitter Output Pulse Position 6
12.70
6/7 Tclk
13.40
ns
Note 5: This limit based on bench characterization.
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4
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Typ
Max
Units
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 4)
Parameter
Min
2.5
4.0
ns
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 4)
2.0
3.5
ns
RCOP
RxCLK OUT Period
15
T
50
ns
RCOH
RxCLK OUT High Time
9
ns
RxCLK OUT Low Time
3.8
5
ns
RSRC
RxOUT Setup to RxCLK OUT
f = 65 MHz
f = 65 MHz
f = 65 MHz
7.8
RCOL
2.5
4.2
ns
RHRC
RxOUT Hold to RxCLK OUT
f = 65 MHz
4.0
5.2
RCCD
RxCLK IN to RxCLK OUT Delay @ 25˚C, VCC = 5.0V
6.4
ns
10.7
ns
10
ms
(Figure 10)
RPLLS
Receiver Phase Lock Loop Set (Figure 12)
RSKM
RxIN Skew Margin (Note 6) (Figure 14)
RPDD
Receiver Powerdown (Figure 17)
VCC = 5V, TA = 25˚C
600
ps
1
µs
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
DS012616-3
FIGURE 1. “Worst Case” Test Pattern
5
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AC Timing Diagrams
(Continued)
DS012616-4
FIGURE 2. “16 Grayscale” Test Pattern
Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 9: Figure 1 and Figure 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 10: Recommended pin to signal mapping. Customer may choose to define differently.
DS012616-5
FIGURE 3. DS90CF583 (Transmitter) LVDS Output Load and Transition Times
DS012616-6
FIGURE 4. DS90CF584 (Receiver) CMOS/TTL Output Load and Transition Times
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AC Timing Diagrams
(Continued)
DS012616-7
FIGURE 5. DS90CF583 (Transmitter) Input Clock Transition Time
DS012616-8
Note:Measurements at Vdiff = 0V
Note: TCSS measured between earliest and latest LVDS edges.
Note: TxCLK Differential High→Low Edge
FIGURE 6. DS90CF583 (Transmitter) Channel-to-Channel Skew and Pulse Width
DS012616-9
FIGURE 7. DS90CF583 (Transmitter) Setup/Hold and High/Low Times
DS012616-10
FIGURE 8. DS90CF584 (Receiver) Clock In to Clock Out Delay
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AC Timing Diagrams
(Continued)
DS012616-11
FIGURE 9. DS90CF583 (Transmitter) Clock In to Clock Out Delay
DS012616-23
FIGURE 10. DS90CF584 (Receiver) Clock In to Clock Out Delay
DS012616-13
FIGURE 11. DS90CF583 (Transmitter) Phase Lock Loop Set Time
DS012616-14
FIGURE 12. DS90CF584 (Receiver) Phase Lock Loop Set Time
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AC Timing Diagrams
(Continued)
DS012616-19
FIGURE 13. Receiver LVDS Input Pulse Position Measurement
DS012616-20
SW — Setup and Hold Time (Internal Data Sampling Window)
TCCS — Transmitter Output Skew
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)
Cable Skew — typically 10 ps–40 ps per foot
FIGURE 14. Receiver LVDS Input Skew Margin
DS012616-17
FIGURE 15. Seven Bits of LVDS in One Clock Cycle
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AC Timing Diagrams
(Continued)
DS012616-18
FIGURE 16. Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF583)
DS012616-21
FIGURE 17. Receiver Powerdown Delay
DS012616-22
FIGURE 18. Transmitter Powerdown Delay
DS90CF583 Pin Descriptions — FPD Link Transmitter
I/O
No.
TxIN
Pin Name
I
28
TxOUT+
O
4
Positive LVDS differential data output
TxOUT−
O
4
Negative LVDS differential data output
FPSHIFT IN
I
1
TTL level clock input. The falling edge acts as data strobe
TxCLK OUT+
O
1
Positive LVDS differential clock output
TxCLK OUT−
O
1
Negative LVDS differential clock output
PWR DOWN
I
1
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down
VCC
I
4
Power supply pins for TTL inputs
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Description
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME, DRDY and CNTL (also referred to as HSYNC, VSYNC, Data Enable, CNTL)
10
DS90CF583 Pin Descriptions — FPD Link Transmitter
I/O
No.
GND
Pin Name
I
5
Ground pins for TTL inputs
Power supply pin for PLL
(Continued)
Description
PLL VCC
I
1
PLL GND
I
2
Ground pins for PLL
LVDS VCC
I
1
Power supply pin for LVDS outputs
LVDS GND
I
3
Ground pins for LVDS outputs
DS90CF584 Pin Descriptions — FPD Link Receiver
Pin Name
RxIN+
I/O
No.
I
4
Positive LVDS differential data inputs
Description
Negative LVDS differential data inputs
RxIN−
I
4
RxOUT
O
28
RxCLK IN+
I
1
RxCLK IN−
I
1
Negative LVDS differential clock input
FPSHIFT
OUT
O
1
TTL level clock output. The falling edge acts as data strobe
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME, DRDY and CNTL (also referred to as HSYNC, VSYNC, Data Enable, CNTL)
Positive LVDS differential clock input
PWR DOWN
I
1
TTL level input. Assertion (low input) maintains the receiver outputs in the previous state
VCC
I
4
Power supply pins for TTL outputs
GND
I
5
Ground pins for TTL outputs
PLL VCC
I
1
Power supply for PLL
PLL GND
I
2
Ground pin for PLL
LVDS VCC
I
1
Power supply pin for LVDS inputs
LVDS GND
I
3
Ground pins for LVDS inputs
Connection Diagrams
DS012616-16
DS012616-15
11
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DS90CF583/DS90CF584 LVDS 24-Bit Color Flat Panel Display (FPD) Link— 65 MHz
Physical Dimensions
inches (millimeters) unless otherwise noted
56-Lead Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90CF583MTD or DS90CF584MTD
NS Package Number MTD56
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