ICS852911I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS852911I is a low skew, 1-to-9 DifferenICS tial-to-HSTL Fanout Buffer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS852911I has two selectable clock inputs which can accept most differential input levels. • 9 HSTL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • HSTL_CLK, nHSTL_CLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL • PECL_CLK, nPECL_CLK supports the following input types: LVPECL, CML, SSTL Guaranteed output skew, part-to-part skew and crossover voltage characteristics make the ICS852911I ideal for today’s most advanced applications, such as IA64 and static RAMs. • Maximum output frequency: 500MHz • Output skew: 100ps (maximum) • Part-to-part skew: 300ps (maximum) • Propagation delay: 1.7ns (maximum) • VOH = 1.4V (maximum) • 3.3V core, 1.6V to 3.6V output supply range • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM 23 22 nQ2 24 Q2 25 nQ1 CLK_SEL VDDO 1 Q1 PECL_CLK nPECL_CLK nQ0 0 Q0 HSTL_CLK nHSTL_CLK PIN ASSIGNMENT 21 20 19 Q0 nQ0 Q1 nQ1 Q2 GND 26 18 Q3 CLK_SEL 27 17 nQ3 HSTL_CLK 28 16 Q4 15 VDDO nQ2 ICS852911I VDD 1 nHSTL_CLK 2 14 nQ4 PECL_CLK 3 13 Q5 nPECL_CLK 4 Q6 nQ6 7 8 9 10 12 11 nQ5 Q6 6 Q7 nQ5 5 nQ6 Q5 nQ7 nQ4 VDDO Q4 Q8 nQ3 nQ8 Q3 28-Lead PLCC 11.6mm x 11.4mm x 4.1mm package body V Package Top View Q7 nQ7 Q8 nQ8 852911AVI www.icst.com/products/hiperclocks.html 1 REV. A MAY 23, 2005 ICS852911I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 VDD Power 2 nHSTL_CLK Input 3 PECL_CLK Input 4 nPECL_CLK Input 5, 6 nQ8, Q8 Output 7, 9 8, 15, 22 nQ7, Q7 VDDO Output Power Differential output pair. HSTL interface level. Output supply pins. Core supply pin. Pullup/ Inver ting differential clock input. VCC/2 default when left floating. Pulldown Pulldown Non-inver ting differential LVPECL clock input. Pullup/ Inver ting differential clock input. VCC/2 default when left floating. Pulldown Differential output pair. HSTL interface level. 10, 11 nQ6, Q6 Output Differential output pair. HSTL interface level. 12, 13 nQ5, Q5 Output Differential output pair. HSTL interface level. 14, 16 nQ4, Q4 Output Differential output pair. HSTL interface level. 17, 18 nQ3 Q3 Output Differential output pair. HSTL interface level. 19, 20 nQ2, Q2 Output Differential output pair. HSTL interface level. 21, 23 nQ1, Q1 Output Differential output pair. HSTL interface level. 24, 25 nQ0, Q0 Output Differential output pair. HSTL interface level. 26 GND Power 27 CLK_SEL Input 28 HSTL_CLK Input Power supply ground. Clock select input. When HIGH, selects PECL_CLK, nPECL_CLK inputs. Pulldown When LOW, selects HSTL_CLK, nHSTL_CLK. LVTTL / LVCMOS interface levels. Pulldown Non-inver ting differential clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ TABLE 3. CONTROL INPUT FUNCTION TABLE Inputs CLK_SEL 852911AVI Selected Sourced 0 HSTL_CLK, nHSTL_CLK 1 PECL_CLK, nPECL_CLK www.icst.com/products/hiperclocks.html 2 REV. A MAY 23, 2005 ICS852911I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 37.8°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±0.3V, VDDO = 1.6V TO 3.6V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.0 3.3 3.6 V VDDO Output Supply Voltage 1.6 3.3 3.6 V IDD Power Supply Current 95 mA Maximum Units VDD + 0.3 V TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±0.3V, VDDO = 1.6V TO 3.6V, TA = -40°C TO 85°C Symbol Parameter VIH CLK_SEL Test Conditions Minimum Typical 2 VIL CLK_SEL IIH Input High Current CLK_SEL VIN = VDD = 3.6V IIL Input Low Current CLK_SEL VIN = 0V, VDD = 3.6V -0.3 0.8 V 150 µA -5 µA TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = 3.3V±0.3V, VDDO = 1.6V TO 3.6V, TA = -40°C TO 85°C Symbol IIH Parameter Input High Current Test Conditions PECL_CLK Minimum VDD = VIN = 3.6V Typical Maximum Units 150 µA nPECL_CLK VDD = VIN = 3.6V PECL_CLK VDD = 3.6V, VIN = 0V -5 µA nPECL_CLK VDD = 3.6V, VIN = 0V -150 µA IIL Input Low Current VPP Peak-to-Peak Input Voltage 150 0.3 1 VCMR Common Mode Input Voltage; NOTE 1, 2 1.5 VDD NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PECL_CLK and nPECL_CLK is VDD + 0.3V. 852911AVI www.icst.com/products/hiperclocks.html 3 µA V V REV. A MAY 23, 2005 ICS852911I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 4D. HSTL DC CHARACTERISTICS, VDD = 3.3V±0.3V, VDDO = 1.6V TO 3.6V, TA = -40°C TO 85°C Symbol Parameter Maximum Units HSTL_CLK Test Conditions VIN = VDD = 3.6V Minimum Typical 150 µA nHSTL_CLK VIN = VDD = 3.6V 150 µA IIH Input High Current IIL Input Low Current VPP 0.15 1.3 V 0.5 VDD - 0.85 V VOH Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage; NOTE 3 1.0 1.4 V VOL Output Low Voltage; NOTE 3 0 0.4 V VOX Output Crossover Voltage; NOTE 4 40 60 % VCMR HSTL_CLK VIN = 0V, VDD = 3.6V -5 µA nHSTL_CLK VIN = 0V, VDD = 3.6V -150 µA Peak-to-Peak Output Voltage Swing 0.6 1.1 VSWING NOTE 1: For single ended applications, the maximum input voltage for HSTL_CLK and nHSTL_CLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: Outputs terminated with 50Ω to ground. NOTE 4: Defined with respect to output voltage swing at a given condition. V TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±0.3V, VDDO = 1.6V TO 3.6V, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 tR / tF Output Rise/Fall Time Test Conditions Minimum 1.3 20% to 80% Typical 1.5 200 odc Output Duty Cycle 47 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. Measured from VDD/2 to the output differential crossing point for single ended input levels. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 852911AVI www.icst.com/products/hiperclocks.html 4 Maximum Units 500 MHz 1. 7 ns 100 ps 300 ps 600 ps 53 % REV. A MAY 23, 2005 ICS852911I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 3.3V±0.3V 1.6V to 3.6V VDD VDD Qx SCOPE nHSTL_CLK, nPECL_CLK VDDO V HSTL GND V Cross Points PP CMR HSTL_CLK, PECL_CLK nQx GND 0V 3.3V CORE/1.6V TO 3.6V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART 1 nQx nQx Qx Qx PART 2 nQy nQy Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nHSTL_CLK, nPECL_CLK 80% 80% HSTL_CLK, PECL_CLK VOD Clock Outputs nQ0:nQ8 20% 20% tR tF Q0:Q8 tPD OUTPUT RISE/FALL TIME PROPAGATION DELAY nQ0:nQ8 Q0:Q8 t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 852911AVI www.icst.com/products/hiperclocks.html 5 REV. A MAY 23, 2005 ICS852911I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K CLK_IN + V_REF C1 0.1uF R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 852911AVI www.icst.com/products/hiperclocks.html 6 REV. A MAY 23, 2005 ICS852911I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The HSTL_CLK/nHSTL_CLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS HSTL_CLK/nHSTL_CLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS HSTL drivers. If you are using an HSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 2A. HIPERCLOCKS HSTL_CLK/nHSTL_CLK INPUT DRIVEN BY ICS HIPERCLOCKS HSTL DRIVER FIGURE 2B. HIPERCLOCKS HSTL_CLK/nHSTL_CLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 2C. HIPERCLOCKS HSTL_CLK/nHSTL_CLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 2D. HIPERCLOCKS HSTL_CLK/nHSTL_CLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 2E. HIPERCLOCKS HSTL_CLK/nHSTL_CLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE 852911AVI www.icst.com/products/hiperclocks.html 7 REV. A MAY 23, 2005 ICS852911I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE The PECL_CLK/nPECL_CLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS PECL_CLK/ nPECL_CLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 3.3V 3.3V 3.3V 2.5V 3.3V R1 50 CML R3 120 R2 50 SSTL Zo = 50 Ohm R4 120 Zo = 60 Ohm PCLK PCLK Zo = 60 Ohm Zo = 50 Ohm nPCLK nPCLK HiPerClockS PCLK/nPCLK R1 120 FIGURE 3A. HIPERCLOCKS PECL_CLK/nPECL_CLK INPUT DRIVEN BY A CML DRIVER HiPerClockS PCLK/nPCLK R2 120 FIGURE 3B. HIPERCLOCKS PECL_CLK/nPECL_CLK INPUT DRIVEN BY AN SSTL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm C1 LVDS Zo = 50 Ohm R3 1K R4 1K PCLK PCLK R5 100 Zo = 50 Ohm nPCLK LVPECL R1 84 C2 nPCLK Zo = 50 Ohm HiPerClockS Input R1 1K R2 84 FIGURE 3C. HIPERCLOCKS PECL_CLK/nPECL_CLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER HiPerClockS PC L K/n PCL K R2 1K FIGURE 3D. HIPERCLOCKS PECL_CLK/nPECL_CLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK nPCLK R5 100 - 200 R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 FIGURE 3E. HIPERCLOCKS PECL_CLK/nPECL_CLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC C OUPLE 852911AVI www.icst.com/products/hiperclocks.html 8 REV. A MAY 23, 2005 ICS852911I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER SCHEMATIC EXAMPLE Figure 4 shows a schematic example of ICS852911I. In this example, the input is driven by an ICS HiPerClockS HSTL driver. The decoupling capacitors should be physically located near the power pin. Zo = 50 + Zo = 50 VCCO 26 27 28 1 2 3 4 VCC R9 R10 C9 50 50 0.1u Q3 nQ3 Q4 VCCO nQ4 Q5 nQ5 18 17 16 15 14 13 12 ICS852911I 5 6 7 8 9 10 11 HSTL Driv er VEE CLK_SEL HSTL_CLK VCC nHSTL_CLK PECL_CLK nPECL_CLK nQ8 Q8 nQ7 VCCO Q7 nQ6 Q6 Zo = 50 Ohm Q0 nQ0 Q1 VCCO nQ1 Q2 nQ2 U1 Zo = 50 Ohm R1 50 25 24 23 22 21 20 19 VCCO R2 50 R12 1K (U1-8) VCCO C1 0.1uF (U1-15) Zo = 50 (U1-22) + C2 0.1uF C3 0.1uF Zo = 50 VCC=3.3V - VCCO=1.6V to 3.6V R8 50 R7 50 FIGURE 4. ICS852911I HSTL BUFFER SCHEMATIC EXAMPLE 852911AVI www.icst.com/products/hiperclocks.html 9 REV. A MAY 23, 2005 ICS852911I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS852911I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS852911I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * IDD_MAX = 3.6V * 95mA = 342mW Power (outputs)MAX = 87.2mW/Loaded Output pair If all outputs are loaded, the total power is 9 * 87.2mW = 784.8mW Total Power_MAX (3.6V, with all outputs switching) = 342mW + 784.8mW = 1126.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 1.127W * 31.1°C/W = 120°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 28-pin PLCC, Forced Convection θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 37.8°C/W 31.1°C/W 28.3°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 852911AVI www.icst.com/products/hiperclocks.html 10 REV. A MAY 23, 2005 ICS852911I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 5. VDDO Q1 VOUT RL 50Ω FIGURE 5. HSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V /R ) * (V OH_MAX Pd_L = (V OL_MAX L -V DDO_MAX /R ) * (V L -V DDO_MAX ) OH_MAX ) OL_MAX Pd_H = (1.4V/50Ω) * (3.6V - 1.4V) = 61.6mW Pd_L = (0.4V/50Ω) * (3.6V - 0.4V) = 25.6mW Total Power Dissipation per output pair = Pd_H + Pd_L = 87.2mW 852911AVI www.icst.com/products/hiperclocks.html 11 REV. A MAY 23, 2005 ICS852911I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 28 LEAD PLCC θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 37.8°C/W 31.1°C/W 28.3°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS852911I is: 726 Pin compatible with MPC911 852911AVI www.icst.com/products/hiperclocks.html 12 REV. A MAY 23, 2005 ICS852911I Integrated Circuit Systems, Inc. PACKAGE OUTLINE - V SUFFIX FOR LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER 28 LEAD PLCC TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM MAXIMUM 28 N A 4.19 4.57 A1 2.29 3.05 A2 1.57 2.11 b 0.33 0.53 c 0.19 0.32 D 12.32 12.57 D1 11.43 11.58 D2 4.85 5.56 E 12.32 12.57 E1 11.43 11.58 E2 4.85 5.56 Reference Document: JEDEC Publication 95, MS-018 852911AVI www.icst.com/products/hiperclocks.html 13 REV. A MAY 23, 2005 ICS852911I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS852911AVI ICS852911AVI 28 Lead PLCC Tube -40°C to 85°C ICS852911AVIT ICS852911AVI 28 Lead PLCC 500 Tape & Reel -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 852911AVI www.icst.com/products/hiperclocks.html 14 REV. A MAY 23, 2005 ICS852911I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER REVISION HISTORY SHEET Rev A 852911AVI Table Page 1 Description of Change Block Diagram - corrected drawing. www.icst.com/products/hiperclocks.html 15 Date 5/23/05 REV. A MAY 23, 2005