CDB5560-2
50 kSps, 24-bit ∆Σ ADC
Evaluation Board
Features
General Description
Single Analog Input Channel to the CS5560 ADC
Pre-configured to require a minimum number of external
connections to your data acquisition system.
All functionality accessible through the connector interface
and board-level options.
The CDB5560-2 is a versatile tool designed for evaluating the functionality and performance of the CS5560 ADC (Analog-to-Digital
Converter). The SPI serial port on the CDB5560-2 evaluation
board is configured in Master mode and will start transmitting data
after power-up upon reset. This evaluation board is designed to
connect to your data capture system or will interface to the
CapturePlus II data acquisition system available from Cirrus Logic.
On-board 4.096 V Reference
The CS5560 delta-sigma ADC produces fully settled conversions to
full specified accuracy at 50 kSps. .
Pre-configured for Master mode SPI™ communication to a
All evaluation board functionality for evaluating the CS5560 ADC is
accessed through the connector interface and board-level options.
data capture system.
Schematics in PADS™ PowerLogic™ format are available for
download at:
http://www.cirrus.com/en/products/pro/detail/P1120.html.
ORDERING INFORMATION
CDB5560-2
www.cirrus.com
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
Evaluation Board
SEP ‘07
DS790DB2
CDB5560-2
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you
go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives
consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR
USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY
DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT
IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND
OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.
PADS and PowerLogic are trademarks of Mentor Graphics.
2
DS790DB2
CDB5560-2
TABLE OF CONTENTS
1. INTRODUCTION ....................................................................................................................... 4
1.1 Overview ............................................................................................................................ 5
2. QUICK START
............................................................................................................ 6
3. HARDWARE DESCRIPTION ................................................................................................... 7
3.1 Absolute Maximum Ratings ............................................................................................... 7
3.2 Power Supply .................................................................................................................... 7
3.3 Analog Section .................................................................................................................. 7
3.3.1 Analog Input Buffers ............................................................................................. 7
3.3.2 Multiplexer ............................................................................................................. 8
3.3.3 ADC Reset ............................................................................................................ 8
3.3.4 Voltage Reference ................................................................................................ 8
3.3.5 ADC Reference Frequency ................................................................................... 8
3.4 Digital Section .................................................................................................................... 9
3.4.1 Hardware Configuration ........................................................................................ 9
3.4.2 SPI™ Serial Port Communications ....................................................................... 9
Appendix A. Maximizing the Performance of the CS5560...................................................... 10
A.1 PCB Layout Considerations ............................................................................................ 10
A.2 Hardware Considerations................................................................................................ 10
Appendix B. Bill Of Materials .................................................................................................... 11
Appendix C. Schematics .......................................................................................................... 12
Appendix D. Layer Plots ........................................................................................................... 17
LIST OF FIGURES
Figure 1. CDB5560-2 Block Diagram.............................................................................................. 5
Figure 2. CDB5560-2 Board Layout................................................................................................ 6
Figure 3. Schematic - Block Diagram............................................................................................ 12
Figure 4. Schematic - Power Supplies .......................................................................................... 13
Figure 5. Schematic - Input Buffers and Multiplexer ..................................................................... 14
Figure 6. Schematic - CS5560 ...................................................................................................... 15
Figure 7. Schematic - Configuration & Misc.................................................................................. 16
Figure 8. Top Silkscreen ............................................................................................................... 17
Figure 9. Top Solder Mask............................................................................................................ 18
Figure 10. Top Routing ................................................................................................................. 19
Figure 11. Ground Plane............................................................................................................... 20
Figure 12. Power Plane................................................................................................................. 21
Figure 13. Bottom Solder Mask..................................................................................................... 22
Figure 14. Bottom Silkscreen ........................................................................................................ 23
Figure 15. Top Solder Paste Mask................................................................................................ 24
Figure 16. Bottom Routing ............................................................................................................ 25
LIST OF TABLES
Table 1. Power Supply Connections ............................................................................................... 7
Table 2. Analog Input Connections ................................................................................................. 7
Table 3. Analog Input Channel Selection........................................................................................ 8
Table 4. Hardware Configuration Signals ....................................................................................... 9
Table 5. Serial Interface Connections ............................................................................................. 9
DS790DB2
3
CDB5560-2
1. INTRODUCTION
The CDB5560-2 evaluation board is a platform for evaluating the CS5560 ADC performance. The evaluation board is designed to connect to the SPI serial port of a processor or data capture system or will
interface directly to the CapturePlus II data acquisition system available from Cirrus Logic. The
CapturePlus II data acquisition system is a powerful integrated hardware/software tool designed to fully
exercise the CDB5560-2 and other Cirrus Logic evaluation boards.
The CDB5560-2 evaluation board is designed to simplify the hardware setup required to evaluate the
CS5560. Interfacing the CDB5560-2 evaluation board to a user-supplied data capture system can be as
simple as connecting the SPI port and using the CDB5560-2 default hardware configuration. In this configuration simply press the Reset switch on the CDB5560-2 and it will automatically begin transmitting
data to the data capture system.
All evaluation board functionality for evaluating the CS5560 ADC is accessed through the connector interface and board-level options.
The CS5560 delta-sigma ADC produces fully settled conversions to full specified accuracy at 50 kSps.
For detailed information on the CS5560 ADC, please reference data sheet DS713 at www.cirrus.com.
4
DS790DB2
CDB5560-2
1.1
Overview
The CDB5560-2 evaluation board has both analog and digital circuit sections. The analog section consists
of the CS5560 ADC, an analog input signal buffer that conditions the signal into the ADC, and a precision
4.096 V reference. The digital section consists of board operation configuration control signals, reset circuitry, an SPI™ serial port, a jumper connection for initiating ADC calibration, and an EEPROM for evaluation board identification.
The evaluation board operates from +2.5V, -2.5V, +3.3V and communicates through an SPI™ serial port.
Figure 1 illustrates the CDB5560-2 block diagram.
Differential
Analog Input
VREF
4.096 V
J8
Master/Slave
Serial Port
J6
Digital Inputs
to ADC
J7
Digital Outputs
from ADC
CS3004
INPUT A
CS5560
XTAL
16 MHz
Communication/Control
Interface
+2.5V GND -2.5V GND +3.3V GND
Figure 1. CDB5560-2 Block Diagram
DS790DB2
5
CDB5560-2
2. QUICK START
Buffer Enable
DC Supply
Calibrate
Digital Control Signals to ADC
4.096 V Reference
ADC Reset
Master/Slave SPI
ADC MCLK Out
Analog Inputs
NOTE: Shaded boxes marked with "OPT. CONFIG." are not necessary for operation in an end user product.
Figure 2. CDB5560-2 Board Layout
The CDB5560-2 evaluation board is designed to interface with a data acquisition system. To connect and
configure the CDB5560-2 perform the following initialization procedure:
1. Verify that the power supplies are off.
2. Connect the power supplies to the CDB5560-2 as shown in Table 1 on page 7.
3. Verify that the power is off to the analog input signal & control signal sources.
4. Connect the analog input signal source to the evaluation board per Table 2 on page 7. .
5. Configure the CDB5560-2 by connecting the control signal sources to the evaluation board as shown in
Table 3 on page 9. Apply logic-level inputs as required to override the resistor pull-ups/pull-downs.
6. Make connections to the SPI™ serial port connector as shown in Table 4 on page 9. The CS5560 ADC
serial port is configured by default to operate in the SSC (Synchronous Self Clocking) mode. Refer to the
CS5560 data sheet for more information on serial communication modes and signal timing.
7. Turn on the power supplies to the evaluation board.
8. Apply power to the signal source.
9. Press the Reset switch on the evaluation board.
10. The CS5560 ADC's SPI™ serial port should now be communicating data.
6
DS790DB2
CDB5560-2
3. HARDWARE DESCRIPTION
3.1
Absolute Maximum Ratings
Observe the following limits to ensure the CDB5560-2 component ratings are not exceeded.
• CS5560
– The absolute maximum supply voltage that can be applied to the +3.3V power supply
connection is +3.6V.
– The absolute maximum power supply voltage that can be applied between pins VL and V1is 6.1 V.
• CS3004
– The absolute maximum power supply voltage that can be applied between the +2.5V and
-2.5V power supply connections is +5.5V.
3.2
Power Supply
Power supply connections and requirements are specified in Table 1. below.
Table 1. Power Supply Connections
Power Supply
Requirement
Power Supply
Connection
Associated
Ground Return
Associated
Test Points
+2.5 V DC, ±5%, <50 mA
E5
E3
TP2, TP1 (GND)
-2.5 V DC, ±5%, <50 mA
E9
E7
TP4, TP3 (GND)
+3.3 V DC, ±5%, <50 mA
E16
E13
TP6, TP5 (GND)
Important: It is recommended that all power supplies be isolated from utility ground to prevent the introduction of a ground loop. One ground connection may already exist through the serial port connection to
utility ground. Using the Cirrus Logic CapturePlus II system simplifies making connections to the
CDB5560-2 by providing electrical isolation between the two.
Using twisted/shielded wire will reduce electrical noise induced onto the power supply cables.
Power supplies are to be adequately regulated and sufficiently low noise to meet the application requirements.
3.3
3.3.1
Analog Section
Analog Input Buffers
The analog input signal connections to the input buffers are made at the INPUT A connector, as specified
in Table 2.
Table 2. Analog Input Connection
Channel
Analog Input
Connection
Differential Input Signal
Voltage Range
Impedance
INPUT A
J4
-4.096 V to +4.096 V
50 Ohms
There is one analog input channel on the evaluation board. The analog input channel consists of two lownoise amplifiers configured as unity gain non-inverting buffers. The buffers utilize a Cirrus Logic CS3004
precision, low-noise, low-voltage, dual op-amp These op-amps enable both the inputs and outputs of the
analog input buffer to operate virtually rail to rail. The channel input impedance is 50 Ohms.
For detailed information on the CS3004 precision industrial op-amps, please reference data sheet DS719
at www.cirrus.com.
DS790DB2
7
CDB5560-2
The theoretical input frequency range of the CS5560 is from DC to the Nyquist frequency of 25 kHz. The
analog input buffer amplifiers are configured for a cutoff frequency of 16.8 kHz to band-limit noise into the
ADC. Changing the cutoff frequency will change the noise bandwidth accordingly.
3.3.2
ADC Reset
The CS5560 ADC makes use of an externally generated power-on reset. Therefore, after power is applied to the ADC, the reset pin must be driven low then released. Pressing the Reset button generates a
reset cycle. A reset cycle can be generated at any time during ADC operation. The ADC RST pin (active
low) is held inactive through a pull-up resistor.
3.3.3
Voltage Reference
The voltage reference IC provided generates a 4.096 V precision reference.
3.3.4
ADC Reference Frequency
The reference frequency for the CS5560 ADC is provided by a 16.000 MHz oscillator.
8
DS790DB2
CDB5560-2
3.4
Digital Section
3.4.1
Hardware Configuration
The CDB5560-2 evaluation board hardware comes pre-configured so the only connection required
between it and a data acquisition system is the serial port connection.
The hardware setup is reconfigurable through the hardware control interface connectors. Configure the
evaluation board by setting the appropriate control line to the appropriate logic level.
Table 3. Hardware Configuration Signals
Function
Default Level
Label
Connector
Test Point
Analog Input Buffers
Buffers = Enabled (High)
BUFEN
J1
J3, Pin1
Serial Port Mode
Sync. Self Clock = Enabled (High)
SMODE
J6, Pin 12
J3, Pin 3
Data Ready Flag
Data Ready When Set (Low)
RDY
J8, Pin 10
J3, Pin 4
Reset
Reset = Inactive (High)
RST
J6, Pin 6; S1
J3, Pin 6
Self Calibration Mode
Calibration = Inactive (Low)
CAL
J6, Pin 8; J2
J3, Pin 7
Bipolar / Unipolar Mode
Bipolar = Enabled (High)
BP / UP
J6, Pin 2
J3, Pin 8
Sleep Mode
Sleep = Inactive (High)
SLEEP
J6, Pin 4
J3, Pin 9
Serial Port Communication
Chip Select = Enabled (Low)
CS
J8, Pin 2
E23
Data Conversion Mode
Continuous Conversion = Active (Low)
CONV
J8, Pin 12
E21
3.4.2
SPI™ Serial Port Communications
The CS5560 ADC communications port features an SPI™ serial port. It can be configured for SSC mode
(Master) or SEC mode (Slave) mode as shown in Table 4. Test points are provided to monitor serial communications.
Connections to the serial interface are made according to the following table.
Table 4. Serial Interface Connections
DS790DB2
Function
Label
Connector
Test Point
Chip Select
CS
J8, Pin 2
E23
Serial Data Input
SDI
J8, Pin 4
E24
Serial Data Output
SDO
J8, Pin 6
E25
Serial Clock
SCLK
J8, Pin 8
E26
9
CDB5560-2
APPENDIX A. MAXIMIZING THE PERFORMANCE OF THE CS5560
A.1
PCB Layout Considerations
• Keep the signal path short between the CS5560 ADC input capacitors C20, C28 and the ADC
input pins to minimize trace inductance.
• Power supply noise is a major design consideration and the power supplies need adequate
bypassing and bulk capacitance.
• When operating the ADC from +2.5 V and -2.5 V split supplies, place the power supply & buffer
amplifier bypass capacitor ground connections close together.
• Keep all ground connections on each differential buffer amplifier as close to the device as possible to avoid introducing differential noise through high-impedance connections.
• Keep trace lengths short between the ADC and the voltage reference IC negative supply pins.
• Route the oscillator output away from analog circuitry.
• Use a solid ground plane in the PCB layout.
• Provide adequate separation between analog and digital signals.
• To minimize distortion within the analog signal path, consider using components with smaller
voltage dependencies.
• Minimize ADC digital output edge transition current loading.
A.2
Hardware Considerations
At a system level, use shielded cable for interconnects. Keep interconnect cable lengths as short as possible. Route analog and digital signals connecting to the PCB away from each other.
10
DS790DB2
DS790DB2
Cirrus P/N
001-03713-Z1
001-04345-Z1
012-00012-Z1
001-03987-Z1
001-02976-Z1
001-06472-Z1
001-03710-Z1
001-10036-Z1
070-00111-Z1
070-00010-Z1
000-00025-Z1
115-00052-Z1
115-00217-Z1
115-00202-Z1
115-00239-Z1
115-00238-Z1
115-00241-Z1
304-00012-Z1
021-00435-Z1
021-00363-Z1
020-02044-Z1
020-01895-Z1
021-00387-Z1
021-00423-Z1
023-00002-Z1
020-01667-Z1
120-00057-Z1
110-00045-Z1
110-00024-Z1
110-00025-Z1
060-00351-Z1
065-00212-Z1
065-00219-Z1
062-00064-Z1
102-00097-Z1
603-00278-Z1
240-00278-Z1
600-00278-Z1
300-00002-Z1
Item
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
C
C
C
A
A
A
A
A
A0
A0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Rev
A
A
ASSY DWG PWA CDB5560-2-Z NPb
PCB CDB5560-2-Z NPb
SCHEM CDB5560-2-Z NPb
SCREW 4-40X1/4" PH NYLON NPb
CON TEST PT .1"CTR TIN PLAT NPb BLK
CON TEST PT .1" TIN PLT RED NPb TH
CON TEST PT .1" TIN PLATE WHT NPb
IC LNR PREC VREF 4.096Vout NPb SO8
IC CRUS ADC 1CH 24BIT NPb SSOP24
IC CRUS PREC DL LO-V AMP NPb SOIC8
IC PGM SPI EEPROM 8kX8 2MHz NPb SO8
OSC 16MHz 50ppm 3.3V NPb SMD 3x5
RES 49.9 OHM 1/10W ±.5% NPb 0805 TN
RES 49.9 OHM 1/8W ±1% NPb 0805 FILM
SWT SPST 130G 0/1 7mm TACT ESD NPb
RES 10k OHM 1/8W ±5% NPb 0805 FILM
RES 10 OHM 1/8W ±5% NPb 0805 FILM
RES 100k OHM 1/8W ±1% NPb 0805 FILM
RES 4.99k OHM 1/8W ±1% NPb 0805 FLM
RES 100 OHM 1/8W ±5% NPb 0805 FILM
RES 3.3k OHM 1/8W ±5% NPb 0805 FIL
HDR 2x1 ML .1"CTR 093 GLD NPb
HDR 10X1 FML .1" 093 GLD NPb TH
HDR 3X1 ML .1" PCH .062BD NPb TH
HDR 8X2 093BD FML .1" .331" NPb TH
HDR 5X2 093BD FML .1" .331" NPb TH
HDR 6X2 093BD FML .1" .331" NPb TH
SPCR STANDOFF NYL HEX750/4-40TH NPb
CAP 10uF ±20% 16V ELEC NPb CASE A
CAP 4700pF ±10% 50V X7R NPb 0805
CAP 47pF ±10% 50V C0G NPb 0805
CAP 4700pF ±5% 50V C0G NPb 1206
CAP 1000pF ±5% 50V C0G NPb 0805
CAP 2200pF ±5% 50V C0G NPb 0805
DIODE TR 6.8V 600W NPb DO-214AA
DIODE SCHTKY BAR 30V 0.2A NPb SOT23
NO POP 040 PAD 064 NPb TH
Description
CAP 1000pF ±10% 50V X7R NPb 0805
CAP 0.1uF ±10% 50V X7R NPb 0805
REF
1
REF
4
3
2
1
1
1
1
1
1
2
2
1
6
4
5
8
1
1
0
0
1
1
1
1
4
3
1
2
2
0
0
3
1
0
Qty
2
22
XMH1 XMH2 XMH3 XMH4
TP1 TP3 TP5
TP2 TP6
TP4
U1
U2
U3
U4
Y1
R18 R26
R20 R29
S1
R1 R2 R7 R8 R31 R32
R3 R21 R22 R25
R4 R5 R6 R10 R30
R12 R15 R16 R19 R23 R24 R27 R28
R13
R17
Reference Designator
C1 C2
C3 C4 C5 C9 C10 C11 C12 C15 C16 C17 C18
C19 C21 C22 C23 C25 C26 C27 C29 C32 C35
C38
C6 C7 C13
C8
C14 C31
C20 C28
C24
C34 C36
D1 D2 D3
D4
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13
E14 E15 E16 E17 E18 E19 E20 E21 E22 E23
E24
J1 J2
J3
J4
J6
J7
J8
MH1 MH2 MH3 MH4
RR1220Q-49R9-D-M
CRCW080549R9FKEA
PTS645TL70
CRCW080510K0JNEA
CRCW080510R0JNEA
CRCW0805100KFKEA
CRCW08054K99FKEA
CRCW0805100RJNEA
CRCW08053K300JNEA
TSW-102-26-G-S
SSW-110-01-G-S
22-66-2030
SSW-108-01-G-D
SSW-105-01-G-D
SSW-106-01-G-D
1902D
EEE1CS100SR
C0805C472K5RAC
C0805C470K5GAC
C1206C472J5GAC
C0805C102J5GAC
C0805C222J5GAC
P6SMBJ6.8A
BAT54
NP-PAD-040
MFG P/N
C0805C102K5RAC
C0805C104K5RAC
5001
5000
5002
MAX6126AASA41+
CS5560-ISZ/A0
CS3004-FSZ/A0
25LC640-I/SN
ASFL1-16.000MHZ-ECT
CIRRUS LOGIC
603-00278-Z1
CIRRUS LOGIC
240-00278-Z1
CIRRUS LOGIC
600-00278-Z1
BUILDING FASTENERS NY PMS 440 0025 PH
KEYSTONE
KEYSTONE
KEYSTONE
MAXIM
CIRRUS LOGIC
CIRRUS LOGIC
MICROCHIP
ABRACON
SUSUMU
DALE
ITT INDUSTRIES
DALE
DALE
DALE
DALE
DALE
DALE
SAMTEC
SAMTEC
MOLEX
SAMTEC
SAMTEC
SAMTEC
KEYSTONE
PANASONIC
KEMET
KEMET
KEMET
KEMET
KEMET
LITTELFUSE
PHILIPS
NO POP
MFG
KEMET
KEMET
INSTALL AFTER WASH PROCESS
REQUIRES SCREW 4-40X1X4" PH
NYLON, 300-00002-Z1
NO POP
NO POP
NO POP
NO POP
NO POP
Notes
CDB5560-2
APPENDIX B. BILL OF MATERIALS
11
CDB5560-2
Figure 3. Schematic - Block Diagram
APPENDIX C. SCHEMATICS
12
DS790DB2
Figure 4. Schematic - Power Supplies
CDB5560-2
DS790DB2
13
Figure 5. Schematic - Input Buffers and Multiplexer
CDB5560-2
14
DS790DB2
Figure 6. Schematic - CS5560
CDB5560-2
DS790DB2
15
Figure 7. Schematic - Configuration & Misc.
CDB5560-2
16
DS790DB2
CDB5560-2
Figure 8. Top Silkscreen
APPENDIX D. LAYER PLOTS
DS790DB2
17
Figure 9. Top Solder Mask
CDB5560-2
18
DS790DB2
Figure 10. Top Routing
CDB5560-2
DS790DB2
19
Figure 11. Ground Plane
CDB5560-2
20
DS790DB2
Figure 12. Power Plane
CDB5560-2
DS790DB2
21
Figure 13. Bottom Solder Mask
CDB5560-2
22
DS790DB2
Figure 14. Bottom Silkscreen
CDB5560-2
DS790DB2
23
Figure 15. Top Solder Paste Mask
CDB5560-2
24
DS790DB2
Figure 16. Bottom Routing
CDB5560-2
DS790DB2
25
CDB5560-2
REVISION HISTORY
Revision
Date
DB1
APR 2007
Initial Release.
DB2
SEP 2007
Updated schematics, gerber plots to reflect rev C assembly, non-inverting
buffers. Added photo of board.
26
Changes
DS790DB2