Qimonda HYB18T512161BF 512-mbit x16 ddr2 sdram Datasheet

December 2006
HYB18T 512161 B F
512-Mbit x16 DDR2 SDRAM
DDR2 SDRAM
RoHS compliant
Internet Data Sheet
Rev. 1.43
Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512161BF
Revision History: 2006-11, Rev. 1.43
Page
Subjects (major changes since last revision)
All
Adapted internet edtion
94-101
added chapter 7 explaining AC timing measurement condition (reference load ; slew rate ; set up & hold timing
references ; derating values for input /command ,data )
82-86
setup & hold timings are changed with reference to Industrial standard definition
All
removed all the occurances of RDQS as it in not used in graphics (x16)
Previous Revision: 2006-09, Rev. 1.32
All
Qimonda Update
Previous Revision: 2006-03, Rev. 1.31
9
added power supply info for [-20 and -22]
86
table 41: change IDD max to IDD typ
77 - 80
Corrected AC Timing values for -20 speedsort in table 35 and table 36
Previous Revision: 2006-02, Rev. 1.21
67
table 18: added speed sort -20
71
table 24: added speed sort -20
76
table 33 and table 34: added speed sort -20
77
table 35: change CL=7 2.0 tCK (speed sort -20)
78
table 36: added all values for speed sort -20
86
table 41: added all IDD values (all speed sorts)
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-01
03292006-L40N-L04G
2
Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family for graphics application and
describes its main characteristics.
1.1
Features
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
• Commands entered on each positive clock edge, data and
• 1.8 V ± 0.1V VDD for [–25/–28/–33]
• 2.0 V ± 0.1V VDD for [–20/–22]
data mask are referenced to both edges of DQS
• 1.8 V ± 0.1V VDDQ for [–25/–28/–33]
• Data masks (DM) for write data
• 2.0 V ± 0.1V VDDQ for [–20/–22]
• Posted CAS by programmable additive latency for better
• DRAM organizations with 16 data in/outputs
command and data bus efficiency
• Double Data Rate architecture:
• Off-Chip-Driver impedance adjustment (OCD) and On– two data transfers per clock cycle
Die-Termination (ODT) for better signal quality.
– four internal banks for concurrent operation
• Auto-Precharge operation for read and write bursts
• Programmable CAS Latency: 3, 4, 5, 6, 7
• Auto-Refresh, Self-Refresh and power saving Power• Programmable Burst Length: 4 and 8
Down modes
• Differential clock inputs (CK and CK)
• Average Refresh Period 7.8 µs at a TCASE lower than
• Bi-directional, differential data strobes (DQS and DQS) are
85 °C, 3.9 µs between 85 °C and 95 °C
transmitted / received with data. Edge aligned with read
• Full Strength and reduced Strength (60%) Data-Output
data and center-aligned with write data.
Drivers
• DLL aligns DQ and DQS transitions with clock
• 2kB page size
• DQS can be disabled for single-ended data strobe
• Packages: P-TFBGA-84 for ×16 components
operation
• RoHS Compliant Products1)
TABLE 1
Ordering Information for RoHS compliant products
Product Number
Org.
Clock (MHz)
Package
HYB18T512161BF–20/22/25/28/33
×16
500/450/400/350/300
P-TFBGA-84
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
1.2
Description
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 15-bit address bus for ×16 components is used to convey
row, column and bank address information in a RAS-CAS
multiplexing style.
An Auto-Refresh and Self-Refresh mode is provided along
with various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in P-TFBGA package.
The 512-Mb DDR2 DRAM is a high-speed Double-DataRate-Two CMOS DRAM device containing 536,870,912 bits
and internally configured as a quad-bank DRAM. The 512-Mb
device is organized as 8 Mbit × 16 I/O × 4 banks chip. These
devices achieve high speed transfer rates starting at
400 Mb/sec/pin for general applications.
The device is designed to comply with all DDR2 DRAM key
features:
1. posted CAS with additive latency,
2. write latency = read latency - 1,
3. normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
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HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
2
Pin Configuration
2.1
Pin Configuration
The pin configuration of a DDR2 SDRAM is listed by function in Table 2. The abbreviations used in the Pin#/Buffer Type
columns are explained in Table 3 and Table 4 respectively. The pin numbering for the FBGA package is depicted in Figure 1
for ×16.
TABLE 2
Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signal CK, Complementary Clock Signal CK
Clock Signals ×16 organization
J8
CK
I
SSTL
K8
CK
I
SSTL
K2
CKE
I
SSTL
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Control Signals ×16 organization
K7
RAS
I
SSTL
L7
CAS
I
SSTL
K3
WE
I
SSTL
L8
CS
I
SSTL
Chip Select
Bank Address Bus 1:0
Address Signals ×16 organization
L2
BA0
I
SSTL
L3
BA1
I
SSTL
L1
NC
–
–
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512-Mbit Double-Data-Rate-Two SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
M8
A0
I
SSTL
Address Signal 12:0,Address Signal 10/Autoprecharge
M3
A1
I
SSTL
M7
A2
I
SSTL
N2
A3
I
SSTL
N8
A4
I
SSTL
N3
A5
I
SSTL
N7
A6
I
SSTL
P2
A7
I
SSTL
P8
A8
I
SSTL
P3
A9
I
SSTL
M2
A10
I
SSTL
AP
I
SSTL
P7
A11
I
SSTL
R2
A12
I
SSTL
Data Signals ×16 organization
G8
DQ0
I/O
SSTL
G2
DQ1
I/O
SSTL
H7
DQ2
I/O
SSTL
H3
DQ3
I/O
SSTL
H1
DQ4
I/O
SSTL
H9
DQ5
I/O
SSTL
F1
DQ6
I/O
SSTL
F9
DQ7
I/O
SSTL
C8
DQ8
I/O
SSTL
C2
DQ9
I/O
SSTL
D7
DQ10
I/O
SSTL
D3
DQ11
I/O
SSTL
D1
DQ12
I/O
SSTL
D9
DQ13
I/O
SSTL
B1
DQ14
I/O
SSTL
B9
DQ15
I/O
SSTL
Data Signal 15:0
Note: Bi-directional data bus. DQ[15:0] for ×16 components
Data Strobe ×16 organization
B7
UDQS
I/O
SSTL
A8
UDQS
I/O
SSTL
F7
LDQS
I/O
SSTL
E8
LDQS
I/O
SSTL
Rev. 1.43, 2006-11
03292006-L40N-L04G
Data Strobe Upper Byte
Data Strobe Lower Byte
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512-Mbit Double-Data-Rate-Two SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Data Mask ×16 organization
B3
UDM
I
SSTL
Data Mask Upper Byte
F3
LDM
I
SSTL
Data Mask Lower Byte
Power Supplies ×16 organizations
A9,C1,C3,C7,C VDDQ
9
PWR
–
I/O Driver Power Supply
VDD
A7,B2,B8,D2,D VSSQ
PWR
–
Power Supply
PWR
–
Power Supply
PWR
–
Power Supply
A1
8
A3,E3
VSS
Power Supplies ×16 organization
VREF
E9, G1, G3, G7, VDDQ
AI
–
I/O Reference Voltage
PWR
–
I/O Driver Power Supply
J1
VDDL
VDD
E7, F2, F8, H2, VSSQ
PWR
–
Power Supply
E1, J9, M9, R1
PWR
–
Power Supply
PWR
–
Power Supply
PWR
–
Power Supply
PWR
–
Power Supply
–
Not Connected
SSTL
On-Die Termination Control
J2
G9
H8
J7
J3,N1,P9
VSSDL
VSS
Not Connected ×16 organization
A2, E2, L1, R3, NC
R7, R8
NC
Other Pins ×16 organization
K9
ODT
I
TABLE 3
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
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512-Mbit Double-Data-Rate-Two SDRAM
TABLE 4
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
FIGURE 1
Pin Configuration for ×16 components, P-TFBGA-84 (top view)
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5
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6''
.#
666
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0337
Note:
1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is
data strobe for DQ[7:0]
2. LDM is the data mask signal for DQ[7:0], UDM is the data
mask signal for DQ[15:8]
Rev. 1.43, 2006-11
03292006-L40N-L04G
3. VDDL and VDDSL are power and ground for the DLL. They
are isolated on the device from VDD, VDDQ, VSS and VSSQ.
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512-Mbit Double-Data-Rate-Two SDRAM
2.2
512 Mbit DDR2 Addressing
TABLE 5
512-Mbit DDR2 Addressing
Configuration
32-Mbit x 16
Bank Address
BA[1:0]
Number of Banks
4
Auto-Precharge
A10 / AP
Note
Row Address
A[12:0]
Column Address
A[9:0]
Number of Column Address Bits
10
1)
Number of I/Os
16
2)
Page Size [Bytes]
2048 (2K)
3)
1) Referred to as ’colbits’
2) Referred to as ’org’
3) PageSize = 2colbits× org/8 [Bytes
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512-Mbit Double-Data-Rate-Two SDRAM
3
Functional Description
%
$
%
$
$
$
$
$
$
$
$
$
$
$
$
$
$
3
'
:
5
'
/
/
7
0
&
/
%
7
%
/
Z
Z
ZZ
Z
Z
Z
U
H
J
D
G
G
U
TABLE 6
Mode Register Definition (BA[1:0] = 00B)
Field
Bits
Type1)
Description
BA1
14
reg. addr.
Bank Address [1]
BA1 Bank Address
0B
BA0
13
PD
12
w
Active Power-Down Mode Select
PD Fast exit
0B
1B
PD Slow exit
WR
[11:9]
w
Write Recovery2)
Note: All other bit combinations are illegal.
Bank Address [0]
0B
BA0 Bank Address
001B
010B
011B
100B
101B
WR 2
WR 3
WR 4
WR 5
WR 6
DLL
8
w
DLL Reset
DLL No
0B
1B
DLL Yes
TM
7
w
Test Mode
0B
TM Normal Mode
1B
TM Vendor specific test mode
CL
[6:4]
w
CAS Latency
Note: All other bit combinations are illegal.
010B
011B
100B
101B
110B
111B
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CL reserved
CL 3
CL 4
CL 5
CL 6
CL 7
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512-Mbit Double-Data-Rate-Two SDRAM
Field
Bits
Type1)
Description
BT
3
w
Burst Type
0B
BT Sequential
BT Interleaved
1B
BL
[2:0]
w
Burst Length
Note: All other bit combinations are illegal.
010B BL 4
011B BL 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and
rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement
for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN.
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512-Mbit Double-Data-Rate-Two SDRAM
%
$
$
$
$
$
$
$
$
$
$
$
$
%
$
$
$
4
R
I
I
2
&
'
3
U
R
J
U
D
P
'
4
6
5
W
W
U
H
J
D
G
G
U
$
/ 5
'
,
&
'
/
/
W
W
Z Z Z Z Z
Z
Z
TABLE 7
Extended Mode Register Definition (BA[1:0] = 01B)
1)
Field
Bits
Type
Description
BA1
14
reg. addr.
Bank Address [1]
BA1 Bank Address
0B
BA0
13
Qoff
12
DQS
10
Bank Address [0]
0B
BA0 Bank Address
w
Output Disable
QOff Output buffers enabled
0B
1B
QOff Output buffers disabled
Complement Data Strobe (DQS Output)
0B
DQS Enable
1B
DQS Disable
OCD
[9:7]
Program
Off-Chip Driver Calibration Program
000B OCD OCD calibration mode exit, maintain setting
001B OCD Drive (1)
010B OCD Drive (0)
100B OCD Adjust mode
111B OCD OCD calibration default
AL
Additive Latency
Note: All other bit combinations are illegal.
[5:3]
000B
001B
010B
011B
100B
101B
110B
AL 0
AL 1
AL 2
AL 3
AL 4
AL 5
AL 6
RTT
2,6
Nominal Termination Resistance of ODT
00B RTT ∞ (ODT disabled)
01B RTT 75 Ohm
10B RTT 150 Ohm
11B RTT 50 Ohm
DIC
1
Off-chip Driver Impedance Control
0B
DIC Full (Driver Size = 100%)
1B
DIC Reduced
DLL
0
DLL Enable
0B
DLL Enable
1B
DLL Disable
1) w = write only register bits
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512-Mbit Double-Data-Rate-Two SDRAM
%$
%$
$
$
$
$
$
$
65)
$
$
$
$
$
$
$
3$65
UHJDGGU
TABLE 8
EMRS(2) Programming Extended Mode register Definition (BA[1:0]=10B)
Field
Bits
Type1)
Description
BA
[14:13]
w
Bank Adress[14:13]
00B BA MRS
01B BA EMRS(1)
10B BA EMRS(2)
11B BA EMRS(3): Reserved
A
[12:8]
w
Address Bus[12:8]
A[12:8] Address bits
0B
A
7
w
Address Bus[7]
Note: adapted self refresh rate for Tcase > 85°C
0B
1B
A
[6:3]
w
A7 disable
A7 enable 2)3)
Address Bus[6:3]
0B
A[6:3] Address bits
Partial Self Refresh for 4 banks
A
[2:0]
w
Address Bus[2:0], Partial Array Self Refresh for 4 Banks
000B PASR0 Full Array
001B PASR1 Half Array (BA[1:0]=00, 01)
010B PASR2 Quarter Array (BA[1:0]=00)
011B PASR3 Not defined
100B PASR4 3/4 array (BA[1:0]=01, 10, 11)
101B PASR5 Half array (BA[1:0]=10, 11)
110B PASR6 Quarter array (BA[1:0]=11)
111B PASR7 Not defined
1) w = write only
2) When DRAM is operated at 85C ≤ TCase ≤ 95C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self refresh
mode can be entered.
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh
is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued
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512-Mbit Double-Data-Rate-Two SDRAM
%
$
%
$
$
$
$
$
$
$
$
$
$
$
$
$
$
U
H
J
D
G
G
U
0
3
%
7
TABLE 9
EMR(3) Programming Extended Mode Register Definition (BA[1:0]=10B)
Type
1)
Description
Field
Bits
BA1
14
Bank Adress[1]
BA1 Bank Address
1B
BA0
13
Bank Adress[0]
1B
BA0 Bank Address
A
[12:0]
w
Address Bus[12:0]
0B
A[12:0] Address bits
1) w = write only
TABLE 10
ODT Truth Table
Input Pin
EMRS(1) Address Bit A10
EMRS(1) Address Bit A11
x16 components
DQ[7:0]
X
DQ[15:8]
X
LDQS
X
LDQS
0
UDQS
X
UDQS
0
LDM
X
UDM
X
X
X
Note: X = don’t care; 0 = bit set to low; 1 = bit set to high
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512-Mbit Double-Data-Rate-Two SDRAM
TABLE 11
Burst Length and Sequence
Burst Length
Starting Address
(A2 A1 A0)
Sequential Addressing
(decimal)
Interleave Addressing
(decimal)
4
x00
0, 1, 2, 3
0, 1, 2, 3
x01
1, 2, 3, 0
1, 0, 3, 2
x10
2, 3, 0, 1
2, 3, 0, 1
x11
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
8
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
Notes
2. Order of burst access for sequential addressing is “nibblebased” and therefore different from SDR or DDR
components
1. PageSize and Length is a function of I/O
organization:32Mb x 16 organization (CA[9:0]); Page Size
= 2 kByte; Page Length = 1024
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512-Mbit Double-Data-Rate-Two SDRAM
4
Truth Tables
TABLE 12
Command Truth Table
Function
CKE
CS RAS
CAS
WE BA0
BA1
A[13:11]
A10 A[9:0]
Note1)2)3)
Previous
Cycle
Current
Cycle
(Extended) Mode
Register Set
H
H
L
L
L
L
BA
OP Code
Auto-Refresh
H
H
L
L
L
H
X
X
X
X
4)
Self-Refresh Entry
H
L
L
L
L
H
X
X
X
X
4)6)
Self-Refresh Exit
L
H
H
X
X
X
X
X
X
X
4)6)7)
L
H
H
H
4)5)
Single Bank Precharge
H
H
L
L
H
L
BA
X
L
X
4)5)
Precharge all Banks
H
H
L
L
H
L
X
X
H
X
4)
Bank Activate
H
H
L
L
H
H
BA
Row Address
Write
H
H
L
H
L
L
BA
Column
L
Column
4)5)8)
Write with AutoPrecharge
H
H
L
H
L
L
BA
Column
H
Column
4)5)8)
Read
H
H
L
H
L
H
BA
Column
L
Column
4)5)8)
Read with AutoPrecharge
H
H
L
H
L
H
BA
Column
H
Column
4)5)8)
No Operation
H
X
L
H
H
H
X
X
X
X
4)
Device Deselect
H
X
H
X
X
X
X
X
X
X
4)
Power Down Entry
H
L
H
X
X
X
X
X
X
X
4)9)
L
H
H
H
H
X
X
X
X
X
X
X
4)9)
L
H
H
H
Power Down Exit
L
H
4)5)
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means “H or L (but a defined logic level)”.
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
5) Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode Register.
6) VREF must be maintained during Self Refresh operation.
7) Self Refresh Exit is asynchronous.
8) Burst reads or writes at BL = 4 cannot be terminated.
9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
requirements.
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TABLE 13
Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State1)
CKE
Command
Action (N)2)
(N)2)3)RAS, CAS, WE,
CS
Note4)5)
Previous Cycle6)
(N-1)
Current Cycle6)
(N)
L
L
X
Maintain Power-Down
7)8)11)
L
H
DESELECT or NOP
Power-Down Exit
7)9)10)11)
L
L
X
Maintain Self Refresh
8)11)12)
L
H
DESELECT or NOP
Self Refresh Exit
9)12)13)14)
Bank(s)Active
H
L
DESELECT or NOP
Active Power-Down Entry
7)9)10)11)15)
All Banks Idle
H
L
DESELECT or NOP
Precharge Power-Down
Entry
9)10)11)15)
H
L
AUTOREFRESH
Self Refresh Entry
7)11)14)16)
H
H
Refer to the Command Truth Table
Power-Down
Self Refresh
Any State other
than
listed above
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
11)
12)
13)
14)
15)
16)
17)
17)
Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)
The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
CKE must be maintained HIGH while the device is in OCD calibration mode.
Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh
requirements
“X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in
Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).
All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2×tCKE + tIH.
VREF must be maintained during Self Refresh operation.
On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read
commands may be issued only after tXSRD (200 clocks) is satisfied.
Valid commands for Self Refresh Exit are NOP and DESELCT only.
Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or
Refresh operations are in progress.
Self Refresh mode can only be entered from the All Banks Idle state.
Must be a legal command as defined in the Command Truth Table.
TABLE 14
Data Mask (DM) Truth Table
Name (Function)
DM
DQs
Note
Write Enable
L
Valid
1)
Write Inhibit
H
X
1)
1) Used to mask write data; provided coincident with the corresponding data.
Rev. 1.43, 2006-11
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512-Mbit Double-Data-Rate-Two SDRAM
5
Electrical Characteristics
TABLE 15
DRAM Component Operating Temperature Range
Symbol
Parameter
Rating
Unit
Note
TCASE
Operating Temperature
0 to 95
°C
1)2)3)4)
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1“. Note, when the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
5.1
Absolute Maximum Ratings
TABLE 16
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VDDL
VIN, VOUT
TJ
TSTG
Parameter
Rating
Unit
Note
min.
max.
Voltage on VDD pin relative to VSS
–1.0
2.3
V
1)
Voltage on VDDQ pin relative to VSS
–0.5
2.3
V
1)
Voltage on VDDL pin relative to VSS
–0.5
2.3
V
1)
Voltage on any pin relative to VSS
–0.5
2.3
V
1)
Junction Temperature
—
125
°C
1)
Storage Temperature
–55
150
°C
1)2)
1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Rev. 1.43, 2006-11
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512-Mbit Double-Data-Rate-Two SDRAM
5.2
DC Characteristics
TABLE 17
Recommended DC Operating Conditions (SSTL_18)
Symbol
VDD
VDDDL
VDDQ
VDD
VDDDL
VDDQ
VREF
VTT
Parameter
Rating
Unit
Note
Min.
Typ.
Max.
Supply Voltage
1.7
1.8
1.9
V
1)2)
Supply Voltage for DLL
1.7
1.8
1.9
V
1)2)
Supply Voltage for Output
1.7
1.8
1.9
V
1)2)
Supply Voltage
1.9
2.0
2.1
V
2)3)
Supply Voltage for DLL
1.9
2.0
2.1
V
2)3)
Supply Voltage for Output
1.9
2.0
2.1
V
2)3)
Input Reference Voltage
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
4)5)
Termination Voltage
VREF – 0.04
VREF
VREF + 0.04
V
6)
1)
2)
3)
4)
HYB18T512161BF–[25/28/33]
VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
HYB18T512161BF–[20/22]
The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to
be about 0.5 × VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
5) Peak to peak ac noise on VREF may not exceed ± 2% VREF (dc)
6) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in die dc level of VREF.
TABLE 18
ODT DC Electrical Characteristics
Parameter / Condition
Symbol
Min.
Nom.
Max.
Unit
Note
Termination resistor impedance value for
EMRS(1)[A6,A2] = [0,1]; 75 Ohm
Rtt1(eff)
60
75
90
Ω
1)
Termination resistor impedance value for
EMRS(1)[A6,A2] =[1,0]; 150 Ohm
Rtt2(eff)
120
150
180
Ω
1)
Termination resistor impedance value for
EMRS(1)(A6,A2)=[1,1]; 50 Ohm
Rtt3(eff)
40
50
60
Ω
1)
Deviation of VM with respect to VDDQ / 2
delta VM
–6.00
—
+ 6.00
%
2)
1)
Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively.
Rtt(eff) = (VIH(ac) – VIL(ac)) /(I(VIHac) – I(VILac)).
2) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load: delta VM = ((2 x VM / VDDQ) –
1) x 100%
Rev. 1.43, 2006-11
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512-Mbit Double-Data-Rate-Two SDRAM
TABLE 19
Input and Output Leakage Currents
Symbol
Parameter / Condition
Min.
Max.
Unit
Note
IIL
Input Leakage Current; any input 0 V < VIN < VDD
–2
+2
µA
1)
IOL
Output Leakage Current; 0 V < VOUT < VDDQ
–5
+5
µA
2)
1) all other pins not under test = 0 V
2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS are disabled and ODT is turned off
5.3
DC & AC Characteristics
DDR2 SDRAM pin timing are specified for either single ended
or differential mode depending on the setting of the EMRS(1)
“Enable DQS” mode bit; timing advantages of differential
mode are realized in system design. The method by which the
DDR2 SDRAM pin timing are measured is mode dependent.
In single ended mode, timing relationships are measured
relative to the rising or falling edges of DQS crossing at VREF.
In differential mode, these timing relationships are measured
relative to the crosspoint of DQS and its complement, DQS.
This distinction in timing methods is verified by design and
characterization but not subject to production test. In single
ended mode, the DQS signals are internally disabled and
don’t care.
TABLE 20
DC & AC Logic Input Levels
Symbol
Parameter
Min.
Max.
Units
VIH(dc)
VIL(dc)
VIH(ac)
VIL(ac)
DC input logic high
VREF + 0.125
V
DC input low
–0.3
VDDQ + 0.3
VREF – 0.125
AC input logic high
VREF + 0.250
—
V
AC input low
—
VREF – 0.250
V
V
TABLE 21
Single-ended AC Input Test Conditions
Symbol
Condition
Value
Unit
Note
VREF
VSWING.MAX
Input reference voltage
0.5 × VDDQ
V
1)
Input signal maximum peak to peak swing
1.0
V
1)
SLEW
Input signal minimum Slew Rate
1.0
V / ns
2)3)
1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the range from VREF to
VIL(ac).MAX for falling edges as shown in Figure 2
3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative
transitions.
Rev. 1.43, 2006-11
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512-Mbit Double-Data-Rate-Two SDRAM
FIGURE 2
Single-ended AC Input Test Conditions Diagram
9''4
9,+ DF PLQ 9,+ GF PLQ 96:,1* 0$
;
95() 9,/ GF PD[ 9,/ DF PD[ 966
GHOWD7)
GHOWD75
PLQ 95(
9
)
5LV LQ
J6OH
Z ,+ D F GHOWD75
95(
)
9,/ D FPD[
)DOOLQ
J6OHZ GHOWD7)
TABLE 22
Differential DC and AC Input and Output Logic Levels
Symbol
VIN(dc)
VID(dc)
VID(ac)
VIX(ac)
VOX(ac)
1)
2)
3)
4)
Parameter
Min.
Max.
DC input signal voltage
–0.3
DC differential input voltage
0.25
AC differential input voltage
0.5
AC differential cross point input voltage
0.5 × VDDQ – 0.175
AC differential cross point output voltage
0.5 × VDDQ – 0.125
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
0.5 × VDDQ + 0.175
0.5 × VDDQ + 0.125
Unit
Note
—
1)
—
2)
V
3)
V
4)
V
5)
VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
VID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc).
VID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac).
The value of VIX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac)
indicates the voltage at which differential input signals must cross.
5) The value of VOX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac)
indicates the voltage at which differential input signals must cross.
FIGURE 3
Differential DC and AC Input and Output Logic Levels Diagram
9''
4
975
&URVVLQJ3RLQW
9,'
9,;RU9
2;
9&3
9664
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512-Mbit Double-Data-Rate-Two SDRAM
5.4
Output Buffer Characteristics
TABLE 23
Full Strength Calibrated Pull-up Driver Characteristics
Voltage (V)
Calibrated Pull-up Driver Current [mA]
Nominal(18
Nominal Minimum1) Nominal
Low2)(18.75 Ohms) ohms)3)
(21 Ohms)
Nominal
High2)(17.25
Ohms)
Nominal
Maximum4) (15
Ohms)
0.2
–9.5
–10.7
–11.4
–11.8
–13.3
0.3
–14.3
–16.0
–16.5
–17.4
–20.0
0.4
–18.3
–21.0
–21.2
–23.0
–27.0
1)
2)
3)
4)
The driver characteristics evaluation conditions are Nominal Minimum 95 °C (TCASE). VDDQ = 1.7 V, any process
The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 °C (TCASE), VDDQ = 1.8 V, any process
The driver characteristics evaluation conditions are Nominal 25 °C (TCASE), VDDQ = 1.8 V, typical process
The driver characteristics evaluation conditions are Nominal Maximum 0 °C (TCASE), VDDQ = 1.9 V, any process
TABLE 24
Full Strength Calibrated Pull-down Driver Characteristics
Voltage (V)
Calibrated Pull-down Driver Current [mA]
Nominal Minimum1)
(21 Ohms)
Nominal
Low2)(18.75
Ohms)
Nominal3)(18
ohms)
Nominal
High2)(17.25
Ohms)
Nominal
Maximum4) (15
Ohms)
0.2
9.5
10.7
11.5
11.8
13.3
0.3
14.3
16.0
16.6
17.4
20.0
0.4
18.7
21.0
21.6
23.0
27.0
1)
2)
3)
4)
The driver characteristics evaluation conditions are Nominal Minimum 95 °C (TCASE). VDDQ = 1.7 V, any process
The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 °C (TCASE), VDDQ = 1.8V, any process
The driver characteristics evaluation conditions are Nominal 25 °C (TCASE), VDDQ = 1.8 V, typical process
The driver characteristics evaluation conditions are Nominal Maximum 0 °C (TCASE), VDDQ = 1.9 V, any process
Rev. 1.43, 2006-11
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512-Mbit Double-Data-Rate-Two SDRAM
5.5
Input / Output Capacitance
TABLE 25
Input / Output Capacitance
Symbol
Parameter
Min.
Max.
Unit
CCK
Input capacitance, CK and CK
1.0
2.0
pF
CDCK
Input capacitance delta, CK and CK
—
0.25
pF
CI
Input capacitance, all other input-only pins
1.0
1.75
pF
CDI
Input capacitance delta, all other input-only pins
—
0.25
pF
CIO
Input/output capacitance,
DQ, DM, DQS, DQS
2.5
3.5
pF
CDIO
Input/output capacitance delta,
DQ, DM, DQS, DQS
—
0.5
pF
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512-Mbit Double-Data-Rate-Two SDRAM
5.6
Overshoot and Undershoot Specification
TABLE 26
AC Overshoot / Undershoot Specification for Address and Control Pins
Parameter
–20
–22
–25
–28
–33
Unit
Maximum peak amplitude allowed for overshoot area
0.5
0.5
0.5
0.5
0.5
V
Maximum peak amplitude allowed for undershoot area
0.5
0.5
0.5
0.5
0.5
V
Maximum overshoot area above VDD
0.80
0.80
0.80
0.80
0.80
V.ns
Maximum undershoot area below VSS
0.80
0.80
0.80
0.80
0.80
V.ns
FIGURE 4
AC Overshoot / Undershoot Diagram for Address and Control Pins
9ROWV 9
0D[LP
XP$PSOLWXGH
2YH
UVK
RRW$UH
D
9''
966
0D[LP
XP$PSOLWXGH
7LP
H QV Rev. 1.43, 2006-11
03292006-L40N-L04G
24
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512-Mbit Double-Data-Rate-Two SDRAM
TABLE 27
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins
Parameter
–20
–22
–25
–28
–33
Unit
Maximum peak amplitude allowed for overshoot area
0.9
0.9
0.9
0.9
0.9
V
Maximum peak amplitude allowed for undershoot area
0.9
0.9
0.9
0.9
0.9
V
Maximum overshoot area above VDDQ
0.23
0.23
0.23
0.23
0.23
V.ns
Maximum undershoot area below VSSQ
0.23
0.23
0.23
0.23
0.23
V.ns
FIGURE 5
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins
9ROWV 9 0D[LP
XP$PSOLWXGH
2YH
UVK
RRW$UH
D
9''
4
966
4
0D[LP
XP$PSOLWXGH
7LP
H QV Rev. 1.43, 2006-11
03292006-L40N-L04G
25
8QGHUV KRRW$
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D
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HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
5.7
AC Characteristics
5.7.1
Speed Grade Definitions
TABLE 28
Speed Grade Definition
Speed Grade
–20
Parameter
Clock
Frequency
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
@ CL = 7
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
–22
–25
–28
–33
Unit
Note
Symbol
Min. Max. Min. Max. Min. Max. Min. Max.
Min. Max.
tCK
tCK
tCK
tCK
tCK
tRAS
3.75 8
3.75 8
3.75 8
3.75 8
3.75 8
ns
1)2)3)4)
3.75 8
3.75 8
3.75 8
3.75 8
3.75 8
ns
1)2)3)4)
3
8
3
8
3
8
3
8
3.33 8
ns
1)2)3)4)
2.5
8
2.5
8
2.5
8
2.8
8
3.33 8
ns
1)2)3)4)
2.0
8
2.2
8
—
—
—
—
—
—
ns
1)2)3)4)
45
70k
45
70k
45
70k
45
70k
45
70k
ns
1)2)3)4)
tRC
tRCD
tRP
5)
60
—
60
—
60
—
60
—
60
—
ns
1)2)3)4)
15
—
15
—
15
—
15
—
15
—
ns
1)2)3)4)
15
—
15
—
15
—
15
—
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 7.Timings
are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0).
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, input reference
level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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512-Mbit Double-Data-Rate-Two SDRAM
5.7.2
AC Timing Parameters
List of Timing Parameters
TABLE 29
Timing Parameter by Speed Grade
Parameter
Symbol
–20
–22
–25
Unit
Note1)
2)3)4)5)6)
Min.
Max.
Min.
Max.
Min.
Max.
DQ output access time from CK /
CK
tAC
–450
+450
–450
+450
–500
+500
ps
CAS A to CAS B command period
tCCD
tCH
tCKE
2
—
2
—
2
—
0.45
0.55
0.45
0.55
0.45
0.55
3
—
3
—
3
—
tCK
tCK
tCK
tCL
tDAL
0.45
0.55
0.45
0.55
0.45
0.55
WR + tRP —
WR + tRP —
WR + tRP —
Minimum time clocks remain ON
after CKE asynchronously drops
LOW
tDELAY
tIS + tCK + ––
tIH
tIS + tCK + ––
tIH
tIS + tCK + ––
tIH
ns
8)
DQ and DM input hold time
(differential data strobe)
tDH
145
––
220
––
250
––
ps
9)
DQ and DM input hold time (single tDH1
ended data strobe)
-105
––
-30
––
0
––
ps
9)
DQ and DM input pulse width (each tDIPW
input)
0.35
—
0.35
—
0.35
—
tCK
DQS output access time from CK / tDQSCK
CK
–450
+450
–450
+450
–500
+500
ps
DQS input low (high) pulse width
(write cycle)
tDQSL,H
0.35
—
0.35
—
0.35
—
tCK
DQS-DQ skew (for DQS &
associated DQ signals)
tDQSQ
—
450
—
450
—
450
ps
WL –
0.25
WL +
0.25
WL –
0.25
WL +
0.25
WL –
0.25
WL +
0.25
tCK
20
—
95
––
125
––
ps
9)
DQ and DM input setup time (single tDS1
ended data strobe)
-105
—
-30
––
0
––
ps
9)
DQS falling edge hold time from CK tDSH
(write cycle)
0.2
—
0.2
—
0.2
—
tCK
tDSS
0.2
—
0.2
—
0.2
—
tCK
MIN. (tCL, tCH)
—
11)
ps
12)
CK, CK high-level width
CKE minimum high and low pulse
width
CK, CK low-level width
Auto-Precharge write recovery +
precharge time
Write command to 1st DQS latching tDQSS
transition
DQ and DM input setup time
(differential data strobe)
DQS falling edge to CK setup time
(write cycle)
tDS
tHP
Data-out high-impedance time from tHZ
Clock half period
CK / CK
Rev. 1.43, 2006-11
03292006-L40N-L04G
MIN. (tCL, tCH)
—
MIN. (tCL, tCH)
tAC.MAX —
27
tAC.MAX
—
tAC.MAX
tCK
tCK
7)18)
9)
10)
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512-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
–20
–22
–25
Unit
Note1)
2)3)4)5)6)
Min.
Address and control input hold time tIH
Max.
525
Min.
Max.
Min.
Max.
525
—
575
—
ps
Address and control input pulse
width
(each input)
tIPW
0.6
—
0.6
—
0.6
—
tCK
Address and control input setup
time
tIS
400
—
400
—
450
—
ps
DQ low-impedance time from CK /
CK
tLZ(DQ)
2×
tAC.MAX 2 ×
tAC.MIN
tAC.MAX tAC.MIN
tAC.MAX
2×
12)
tAC.MAX
tAC.MIN
tAC.MIN
tAC.MAX
ps
tAC.MIN
tAC.MIN
tAC.MAX
ps
12)
DQS low-impedance from CK / CK tLZ(DQS)
Mode register set command cycle
time
tMRD
2
—
2
—
2
—
tCK
OCD drive mode output delay
tOIT
tQH
tQHS
tREFI
0
12
0
12
0
12
ns
tHP–tQHS
—
tHP–tQHS
—
tHP–tQHS
—
—
—
600
—
600
—
600
ps
—
7.8
—
7.8
—
7.8
µs
13)14)
—
3.9
—
3.9
—
3.9
µs
13)15)
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
Auto-Refresh to Active/AutoRefresh command period
tRFC
105
—
105
—
105
—
ns
16)
Read preamble
tRPRE
tRPST
tRRD
0.9
1.1
0.9
1.1
0.9
1.1
12)
0.40
0.60
0.40
0.60
0.40
0.60
tCK
tCK
10
—
10
—
10
—
ns
14)17)
tRTP
7.5
—
7.5
—
7.5
—
ns
Read postamble
Active bank A to Active bank B
command period
Internal Read to Precharge
command delay
12)
Write preamble
tWPRE
tWPST
Write recovery time for write without tWR
0.35 x tCK —
0.35 x tCK —
0.35 x tCK —
Write postamble
0.40
0.60
0.40
0.60
0.40
0.60
tCK
tCK
13
—
13
—
15
—
ns
Write recovery time for write with
Auto-Precharge
WR
tWR/tCK
—
tWR/tCK
—
tWR/tCK
—
tCK
18)
Internal Write to Read command
delay
tWTR
7.5
—
7.5
—
7.5
—
ns
19)
Exit power down to any valid
command
(other than NOP or Deselect)
tXARD
2
—
2
—
2
—
tCK
20)
Exit active power-down mode to
Read command (slow exit, lower
power)
tXARDS
10 – AL
—
9 – AL
—
8 – AL
—
tCK
20)
2
—
2
—
2
—
tCK
17)
Auto-Precharge
Exit precharge power-down to any tXP
valid command (other than NOP or
Deselect)
Rev. 1.43, 2006-11
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512-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
–20
–22
–25
Unit
Note1)
2)3)4)5)6)
Exit Self-Refresh to non-Read
command
Exit Self-Refresh to Read
command
1) VDDQ, VDD refer to Chapter 1.
Min.
Max.
Min.
Max.
Min.
Max.
tXSNR
tRFC +10
—
tRFC +10
—
tRFC +10
—
ns
tXSRD
200
—
200
—
200
—
tCK
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 5 of this
data sheet.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.The DQS / DQS, input reference
level is the crosspoint when in differential strobe mode;The input reference level for signals other than CK/CK, DQS / DQS is defined in
Chapter 5.3 of this data sheet.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT. See Chapter 5 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change
during power-down, a specific procedure is required.
9) timing is referenced to Industrial standard definition
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
14) 0 °C ≤ TCASE ≤ 85 °C
15) 85 °C < TCASE ≤ 95 °C
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
17) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
18) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
Rev. 1.43, 2006-11
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512-Mbit Double-Data-Rate-Two SDRAM
TABLE 30
Timing Parameter by Speed Grade
Parameter
Symbol
–28
–33
Unit
Note1)
2)3)4)5)6)
Min.
Max.
Min.
Max.
DQ output access time from CK / CK
–550
+550
–600
+600
ps
CAS A to CAS B command period
2
—
2
—
0.45
0.55
0.45
0.55
3
—
3
—
0.45
0.55
0.45
0.55
WR + tRP
—
WR + tRP
—
tCK
tCK
tCK
tCK
tCK
tAC
tCCD
CK, CK high-level width
tCH
CKE minimum high and low pulse width
tCKE
CK, CK low-level width
tCL
Auto-Precharge write recovery + precharge time tDAL
Minimum time clocks remain ON after CKE
tDELAY
asynchronously drops LOW
7)18)
tIS + tCK +
tIH
––
tIS + tCK +
tIH
––
ns
8)
DQ and DM input hold time (differential data
strobe)
tDH
275
––
295
––
ps
9)
DQ and DM input hold time (single ended data
strobe)
tDH1
25
––
45
––
ps
9)
DQ and DM input pulse width (each input)
tDIPW
tDQSCK
tDQSL,H
tDQSQ
0.35
—
0.35
—
tCK
–550
+550
–600
+600
ps
0.35
—
0.35
—
tCK
—
450
—
450
ps
tDQSS
tDS
WL – 0.25 WL + 0.25 WL – 0.25 WL + 0.25 tCK
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
Write command to 1st DQS latching transition
9)
10)
150
––
170
––
ps
9)
DQ and DM input setup time (single ended data tDS1
strobe)
25
––
45
––
ps
9)
DQS falling edge hold time from CK (write cycle) tDSH
0.2
—
0.2
—
tDSS
tHP
tHZ
tIH
tIPW
0.2
—
0.2
—
tCK
tCK
tIS
tLZ(DQ)
DQ and DM input setup time (differential data
strobe)
DQS falling edge to CK setup time (write cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
Rev. 1.43, 2006-11
03292006-L40N-L04G
tLZ(DQS)
tMRD
tOIT
tQH
tQHS
tREFI
MIN. (tCL, tCH)
MIN. (tCL, tCH)
—
11)
12)
—
tAC.MAX
—
tAC.MAX
ps
625
—
675
—
ps
0.6
—
0.6
—
tCK
500
—
550
—
ps
2×
tAC.MAX
2×
tAC.MAX
ps
12)
tAC.MAX
ps
12)
tAC.MIN
tAC.MIN
tAC.MAX
tAC.MIN
tAC.MIN
2
—
2
—
tCK
0
12
0
12
ns
tHP–tQHS
—
tHP–tQHS
—
—
—
600
—
600
ps
—
7.8
—
7.8
µs
13)14)
—
3.9
—
3.9
µs
13)15)
30
Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
–28
–33
Unit
Note1)
2)3)4)5)6)
Min.
Max.
Min.
Max.
105
—
105
—
ns
16)
tRPRE
Read postamble
tRPST
Active bank A to Active bank B command period tRRD
Internal Read to Precharge command delay
tRTP
Write preamble
tWPRE
Write postamble
tWPST
Write recovery time for write without AutotWR
0.9
1.1
0.9
1.1
12)
0.40
0.60
0.40
0.60
tCK
tCK
10
—
10
—
ns
14)17)
7.5
—
7.5
—
ns
0.35 x tCK
—
0.35 x tCK
—
0.40
0.60
0.40
0.60
tCK
tCK
15
—
15
—
ns
Write recovery time for write with Auto-Precharge WR
tWR/tCK
—
tWR/tCK
—
tCK
18)
7.5
—
7.5
—
ns
19)
2
—
2
—
tCK
20)
7 – AL
—
6 – AL
—
tCK
20)
Auto-Refresh to Active/Auto-Refresh command
period
tRFC
Read preamble
12)
17)
Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
tWTR
tXARD
Exit active power-down mode to Read command tXARDS
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
2
—
tCK
Exit Self-Refresh to non-Read command
tXSNR
tXSRD
tRFC +10
—
tRFC +10
—
ns
200
—
200
—
tCK
Exit Self-Refresh to Read command
1) VDDQ, VDD refer to Chapter 1.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 5 of this
data sheet.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.The DQS / DQS input reference
level is the crosspoint when in differential strobe mode;The input reference level for signals other than CK/CK, DQS / DQS is defined in
Chapter 5.3 of this data sheet.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT. See Chapter 5 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change
during power-down, a specific procedure is required.
9) timing is referenced to Industrial standard definition
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
14) 0 °C ≤ TCASE ≤ 85 °C
15) 85 °C < TCASE ≤ 95 °C
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
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512-Mbit Double-Data-Rate-Two SDRAM
17) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
18) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 MHz.
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
5.7.3
ODT AC Electrical Characteristics
TABLE 31
ODT AC Electrical Characteristics and Operating Conditions for all bins
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
Parameter / Condition
Unit Note
Min.
Max.
ODT turn-on delay
2
2
tCK
ODT turn-on
tAC.MAX + 0.7 ns
2 tCK + tAC.MAX + 1 ns
ns
ODT turn-on (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ODT turn-off delay
2.5
2.5
tCK
ODT turn-off
tAC.MAX + 0.6 ns
2.5 tCK + tAC.MAX + 1 ns
ns
ODT turn-off (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ODT to Power Down Mode Entry Latency
3
—
ODT Power Down Exit Latency
8
—
tCK
tCK
1)
ns
2)
ns
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measure from tAOND.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD.
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32
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512-Mbit Double-Data-Rate-Two SDRAM
6
Specifications and Conditions
TABLE 32
IDD Measurement Conditions
Parameter
Symbol
Note
Operating Current - One bank Active - Precharge
IDD0
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands. Address
and control inputs are switching; Databus inputs are switching.
1)2)3)4)
Operating Current - One bank Active - Read - Precharge
IDD1
IOUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL = CL(IDD);
CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus
inputs are switching.
1)2)3)4)
Precharge Power-Down Current
IDD2P
All banks idle; CKE is LOW; tCK = tCK(IDD);Other control and address inputs are stable; Data bus inputs are
floating.
1)2)3)4)
IDD2N
1)2)3)4)
Precharge Quiet Standby Current
IDD2Q
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are stable, Data
bus inputs are floating.
1)2)3)4)
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are switching,
Data bus inputs are switching.
5)6)
5)6)
5)6)
5)6)
5)6)
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus inputs
are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
IDD3P(0)
1)2)3)4)
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus inputs
are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
IDD3P(1)
1)2)3)4)
Active Standby Current
All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching;
IDD3N
1)2)3)4)
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS =
tRAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are
switching; Data Bus inputs are switching; IOUT = 0 mA.
IDD4R
1)2)3)4)
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS =
tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are
switching; Data Bus inputs are switching;
IDD4W
1)2)3)4)
Burst Refresh Current
tCK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are switching, Data bus inputs are switching.
IDD5B
1)2)3)4)
Distributed Refresh Current
IDD5D
tCK = tCK(IDD), Refresh command every tREFI = 7.8 µs interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are switching, Data bus inputs are switching.
1)2)3)4)
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33
5)6)
5)6)
5)6)
5)6)
5)6)
5)6)
5)6)
Internet Data Sheet
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512-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
Note
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data bus
inputs are floating.
1)2)3)4)
Operating Bank Interleave Read Current
IDD7
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK = tCK(IDD),
tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid commands. Address bus inputs
are stable during deselects; Data bus is switching.
1) VDDQ = 2.0 V ± 0.1 V; VDD = 2.0 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized.
3) IDD parameter are specified with ODT disabled.
1)2)3)4)
4)
5)
6)
7)
5)6)
5)6)7)
Data Bus consists of DQ, DM, DQS, DQS, LDQS, LDQS, UDQS and UDQS.
Definitions for IDD: see Table 33
Timing parameter minimum and maximum values for IDD current measurements are defined in chapter 7..
A = Activate, RA = Read with Auto-Precharge, D=DESELECT
TABLE 33
Definition for IDD
Parameter
Description
LOW
defined as VIN ≤ VIL(ac).MAX
HIGH
defined as VIN ≥ VIH(ac).MIN
STABLE
defined as inputs are stable at a HIGH or LOW level
FLOATING
defined as inputs are VREF = VDDQ / 2
SWITCHING
defined as: Inputs are changing between high and low every other clock (once per two clocks) for address
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ
signals not including mask or strobes
Rev. 1.43, 2006-11
03292006-L40N-L04G
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512-Mbit Double-Data-Rate-Two SDRAM
TABLE 34
IDD Specification
Speed Grade
–20
–22
–25
-28
-33
Symbol
typ.
typ.
typ.
typ.
typ.
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P(0)
IDD3P(1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
92
87
81
77
70
99
94
89
85
78
mA
4
4
4
4
4
mA
46
43
41
38
33
mA
40
38
38
35
31
mA
30
29
28
27
23
mA
1)
5
5
5
5
4
mA
2)
52
48
47
43
37
mA
166
158
153
145
127
mA
189
173
163
149
129
mA
127
122
119
115
109
mA
5
5
5
5
4
mA
3)
4
4
4
4
3
mA
3)
204
204
193
193
179
mA
1) MRS(12)=0
2) MRS(12)=1
3) 0 ≤ TCASE ≤ 85°C
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Unit
Note
mA
Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
7
Package
7.1
Package Dimension
FIGURE 6
Package Outline P-TFBGA-84 (top view)
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Internet Data Sheet
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512-Mbit Double-Data-Rate-Two SDRAM
7.2
Package Thermal Characteristics
TABLE 35
Package thermal characteristics
1)
Theta_jC2)
JESD51
Theta_jA
Industrial standard
Board
1s0p
Air Flow
0 m/s
1 m/s
3 m/s
0 m/s
1 m/s
3 m/s
—
Rth[K/W]
69
53
47
41
35
33
5
2s0p
1) Junction to Ambient thermal resistance. The value has been obtained by simulation using the conditions stated in the Industrial standard
JESD-51 standard.
2) Junction to Case thermal resistance. The value has been obtained by simulation.
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HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Pin Configuration for ×16 components, P-TFBGA-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package Outline P-TFBGA-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Ordering Information for RoHS compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration of DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
512-Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Mode Register Definition (BA[1:0] = 00B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Extended Mode Register Definition (BA[1:0] = 01B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
EMRS(2) Programming Extended Mode register Definition (BA[1:0]=10B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
EMR(3) Programming Extended Mode Register Definition (BA[1:0]=10B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ODT Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock Enable (CKE) Truth Table for Synchronous Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Differential DC and AC Input and Output Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Full Strength Calibrated Pull-up Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Full Strength Calibrated Pull-down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC Overshoot / Undershoot Specification for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . 25
Speed Grade Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Timing Parameter by Speed Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Timing Parameter by Speed Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ODT AC Electrical Characteristics and Operating Conditions for all bins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
IDD Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Definition for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
2.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
512 Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.7.1
5.7.2
5.7.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overshoot and Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7
7.1
7.2
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Package Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
18
18
19
20
22
23
24
26
26
27
32
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Rev. 1.43, 2006-11
03292006-L40N-L04G
40
Internet Data Sheet
Edition 2006-11
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2006.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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