Anpec APL5605KI-TRG 600ma linear regulator for dc fan speed control Datasheet

APL5605
600mA Linear Regulator for DC Fan Speed Control
Features
General Description
•
Low Dropout Voltage: 220mV (Typical) @ 600mA
•
Low Quiescent Current: 140µA
•
Enable/Shutdown Function
•
Output Voltage / VSET Voltage: 1.6 times
•
Stable with Low ESR Ceramic Capacitors
•
Over-Temperature Protection
•
Current-Limit Protection with Foldback Current
•
Internal Soft-Start
•
SOP-8 Package
•
Lead Free and Green Devices Available
The APL5605 is a low quiescent current and low dropout
linear regulator which is designed to power a DC fan
and delivers up to 600mA output current. The output
voltage follows the 1.6 times of VSET voltage and typical dropout voltage is only 220mV (typical) at 600mA
output current. The APL5605 with low 140µA quiescent
current is ideal for battery-powered system appliances
and stable with a 2.2µF ceramic output capacitor. The
features of current-limit (with foldback current) and overtemperature protection protect the device against current over-loads and over temperature. The APL5605 is
available in a SOP-8 package.
(RoHS Compliant)
Simplified Application Circuit
Applications
•
Notebook Fan Driver
•
Motherboards
•
PC Peripherals
•
Battery-Powered System
VOUT
VIN
VOUT
VIN
C2
C1
2.2µF
APL5605
1µF
ON
EN
VSET
GND
VSET
OFF
Ordering and Marking Information
APL5605
Package Code
K : SOP-8
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Assembly Material
Handling Code
Temperature Range
Package Code
APL5605 K :
APL5605
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
1
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APL5605
Pin Configuration
SOP-8 Top View
EN 1
8 GND
VIN 2
7 GND
VOUT 3
6 GND
VSET 4
5 GND
APL5605
Absolute Maximum Ratings (Note 1)
Symbol
Rating
Unit
VIN
VIN to GND
Parameter
-0.3 ~ 6.5
V
VEN
EN to GND
-0.3 ~ VIN+0.3
V
VOUT
VOUT to GND
-0.3 ~ VIN+0.3
TJ
Maximum Junction Temperature
PD
Power Dissipation
V
o
150
C
Internally Limited
TSTG
Storage Temperature Range
TSDR
Maximum Lead Temperature, 10 Seconds
-65 ~ 150
o
260
o
C
C
Note 1: Stresses beyond the absolute maximum rating may damage the device and exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
θJA
Parameter
Junction to Ambient Thermal Resistance (Note 2)
SOP-8
Typical Value
Unit
80
°C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in Free Air.
Recommended Operating Conditions
Symbol
Range
Unit
VIN
VIN to GND
3~6
V
VEN
EN to GND
0 ~ VIN
V
VOUT
VOUT to GND
0 ~ VIN-VDROP
V
VSET
VSET to GND
0 ~ 3.3
V
IOUT
Output Current
0 ~ 0.6
A
CIN
Input Capacitor
0.82 ~ 470
COUT
Parameter
Output Capacitor
1 ~ 330
µF
TJ
Junction Temperature
-40 ~ 125
°C
TA
Ambient Temperature
-40 ~ 85
°C
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
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APL5605
Electrical Characteristics
Refer to the typical application circuit. VIN = 5V, VEN = VIN, IOUT = 1mA~600mA, TJ = -40 to 125 °C, TA = -40 to 85°C,
unless otherwise specified. Typical values are at TA = 25 °C.
Symbol
Parameter
Test Conditions
APL5605
Unit
Min.
Typ.
Max.
3
-
6
V
VEN = 0V
-
-
1
µA
VEN = 5V, IOUT = 0A
-
140
200
µA
2.1
2.5
2.9
V
-
0.15
-
V
SUPPLY VOLTAGE
VIN
Input Voltage
SUPPLY CURRENT
IQ
Quiescent Current
UNDER-VOLTAGE-LOCKOUT (UVLO)
VIN UVLO Threshold
VIN rising
VIN UVLO Hysteresis
OUTPUT VOLTAGE
VDROP
VOUT Voltage / VSET Voltage
TJ = 25°C, VIN=5.5V, IOUT=1mA,
VSET=3.3V
1.552
1.6
1.648
V/V
VOUT Voltage / VSET Voltage
TJ = 40 ~ 125°C, VIN=5.5V, IOUT=1mA,
VSET=1 ~ 3.3V
1.504
1.6
1.696
V/V
VSET Pin Current
VSET=5V
-
0.05
1
µA
Load Regulation
IOUT = 1mA to 600mA
-
60
100
mV
Dropout Voltage
IOUT=600mA, VOUT=5V
-
200
320
mV
PROTECTION AND SOFT-START
Output Current Limit
700
-
-
mA
Thermal Shutdown Temperature
-
150
-
°C
Thermal Shutdown Hysteresis
-
40
-
°C
-
250
-
mA
-
130
300
µs
-
60
-
Ω
Foldback Current Limit
TSS
VOUT < 0.6V
Soft-Start Time
VOUT Pull Low Resistance
VEN=0V, VOUT=0.5V
LOGIC INPUT
EN Logic Input-High Level
1.6
-
-
V
EN Logic Input-Low Level
-
-
0.4
V
-
2
-
MΩ
EN Pull-Low Resistance
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
VEN<3V
3
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APL5605
Typical Operating Characteristics
VIN=5V, VSET=2V, VOUT=3.2V, CIN=1µF, COUT=2.2µF, unless otherwise specified.
EN Voltage threshold vs.
Input Voltage
Quiescent Current vs. VSET Voltage
180
160
1.5
Quiescent Current, IQ (μA)
EN Voltage Threshold (V)
1.6
1.4
1.3
1.2
1.1
1
0.9
IOUT=0mA
140
120
100
80
60
40
20
0
0.8
3
3.5
4
4.5
5
5.5
6
0
6.5
0.5
1
Input Voltage (V)
1.5
2
2.5
3
VSET Voltage (V)
Dropout vs. Junction Temperature
VSET Voltage vs. Output Voltage
6
300
VOUT=5V
IOUT=10mA
250
Dropout Voltage (mV)
Output Voltage (V)
5
4
3
2
1
IOUT=600mA
200
IOUT=400mA
150
IOUT=200mA
100
50
0
0
0.5
1
1.5
2
2.5
3
0
-50
3.5
0
Power Supply Rejection Ratio
(PSRR)
0
-10
PSRR (dB)
-15
IOUT=500mA
-25
-30
IOUT=400mA
-35
150
200
VIN=5, CIN=1µF, COUT=2.2µF,
VSET=2V, VOUT=3.2V
-20
100
Quiescent Current vs. Input Voltage
Quiescent Current (µA)
-5
50
Junction Temperature, TJ (°
C)
VSET Voltage (V)
160
IOUT=0mA
120
80
40
-40
-45
-50
1000
0
10000
100000
1000000
0
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
1
2
3
4
5
6
Input Voltage, VIN (V)
Frequency (Hz)
4
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APL5605
Operating Waveforms
VIN=5V, VSET=2V, VOUT=3.2V, CIN=1µF, COUT=2.2µF, unless otherwise specified.
Power On
Power Off
V SET
V IN
V IN
1
1
V SET
2
2
V OUT
I OUT
V OUT
3
3
4
V OUT
I OUT
I OUT
4
CH1 : VIN , 2V/div
CH2 : VSET , 1V/div
CH3 : VOUT , 1V/div
CH4 : IOUT , 500mA/div
Time : 200ms/div
CH1 : VIN , 2V/div
CH2 : VSET , 1V/div
CH3 : VOUT , 1V/div
CH4 : IOUT , 500mA/div
Time : 1ms/div
Line transient
Load transient
VIN=5V, VSET=2V , VOUT=3.2V
CIN=1µF, COUT=2.2µF
VIN=5V, VSET=2V , VOUT=3.2V
CIN=1µF, COUT=2.2µF
1
VIN
V OUT
VOUT
I OUT
2
1
2
CH1 : VIN , 1V/div
CH2 : VOUT , 100mV/div
Time : 1ms/div
CH1 : VOUT , 100mV/div
CH2 : IOUT , 200mV/div
Time : 200µs/div
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
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APL5605
Operating Waveforms (Cont.)
VIN=5V, VSET=2V, VOUT=3.2V, CIN=1µF, COUT=2.2µF, unless otherwise specified.
Shutdown
Enable
VSET
VSET
VEN
VEN
1
1
2
2
VOUT
VOUT
3
3
IOUT
IOUT
4
4
CH1 : VEN , 2V/div
CH2 : VSET , 1V/div
CH3 : VOUT , 1V/div
CH4 : IOUT , 500mA/div
Time : 10µs/div
CH1 : VEN , 2V/div
CH2 : VSET , 1V/div
CH3 : VOUT , 1V/div
CH4 : IOUT , 500mA/div
Time : 200µs/div
Current Limit and Foldback
Current Limit
Thermal Shutdown
VIN
1
VIN
VOUT
1
VOUT
2
2
IOUT
IOUT
3
3
CH1 : VIN , 5V/div
CH2 : VOUT , 2V/div
CH3 : IOUT , 1A/div
Time : 2ms/div
CH1 : VIN , 5V/div
CH2 : VOUT , 2V/div
CH3 : IOUT , 500mA/div
Time : 500ms/div
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
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APL5605
Pin Description
PIN
FUNCTION
NO.
NAME
1
EN
2
VIN
3
VOUT
4
VSET
Output Voltage-Set Input. The output voltage follows the 1.6 times of the VSET voltage.
5,6,7,8
GND
Ground. These pins are internally connected with the internal leadframe. Connect these pins to a
wide ground plane for good heat dissipation.
Enable Control Input. Driving the EN high turns on the regulator. Pulling the EN low turns the
regulator into shutdown mode. The EN is pulled low by an internal resistor.
Supply Voltage Input Pin. Supply voltage can range from 4.5V to 6V. Bypass with a 1µF (typical)
capacitor to GND
Regulator Output. Sources up to 600mA. A small capacitor is needed from this pin to the ground to
assure stability.
Block Diagram
VIN
VOUT = VSET x 1.6
Current Limit
and Foldback
UVLO and
Soft-Start
EN
VSET
VOUT
Thermal
Shutdown
0.6R
R
GND
Typical Application Circuit
APL5605
VIN
CIN
1µF
VIN
VSET
EN
VOUT
VOUT
GND
ON
VSET
COUT
2.2µF
VEN
OFF
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
VOUT = 1.6 ⋅ VSET
7
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APL5605
Function Description
Under-Voltage Lock-Out (UVLO)
Thermal Shutdown
The APL5605 has a built-in under-voltage lock-out circuit
to keep the output off until the internal circuitry is operat-
A thermal shutdown circuit limits the junction temperature
of APL5605. When the junction temperature exceeds
ing properly. The UVLO function initiates a soft-start process after input voltage exceeds its rising UVLO thresh-
+150 ο C, the thermal shutdown circuitry disables the
output, allowing the device to cool down. The output
old during power-on. Typical UVLO threshold is 2.5V with
0.15V hysteresis.
circuitry is enabled again after the junction temperature cools down by 40 ο C, resulting in a pulsed output
during continuous thermal overload conditions.
Soft-Start
The APL5605 provides an internal soft-start circuitry to
control rise rate of the output voltage and limit the current surge during start-up. Approximate 20µs delay time
after the VIN is over the UVLO threshold, the IC starts a
soft-start. The typical soft-start interval is about 130µs.
Enable/Shutdown
Driving the EN high turns on the regulator, driving the EN
low puts the regulator into shutdown mode. A logic low
also causes the output voltage to discharge to the GND.
The EN is pulled low by an internal resistor.
Current Limit
The APL5605 provides a current limit circuitry, which
monitors the output current and controls P-MOS’s gate
voltage to limit the output current at 700mA.
Foldback Current Limit
When the output voltage drops below 0.6V (typical), which
is caused by over load or short circuit, the foldback current limit circuitry limits the output current to 250mA. The
foldback current limit is used to ruduce the power dissipation during short circuit condition. The foldback current
limits is disabled for 0.8ms (typical) after UVLO threshold is reached, so that the IC has normal 700mA (typical)
current limit level during start-up.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
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APL5605
Application Information
Input Capacitor
PCB Layout Consideration
The APL5605 requires proper input capacitors to supply
surge current during stepping load transients to prevent
Figure 1 illustrates the layout. Below is a checklist for
your layout:
the input rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to
1. Please place the input capacitors close to the VIN
2. Ceramic capacitors for load must be placed near the
the VIN limits the slew rate of the surge current, place the
Input capacitors near VIN as close as possible. Input
load as close as possible
3. To place APL5605 and output capacitors near the load
capacitors should be larger than 0.82µF.
is good for performance.
4. Large current paths, the bold lines in figure 1, must
Output Capacitor
have wide tracks.
The APL5605 needs a proper output capacitor to maintain circuit stability and to improve transient response
APL5605
VIN
over temperature and current. In order to insure the circuit stability, the proper output capacitor value should be
VIN
VSET
VSET
EN
VOUT
VOUT
CIN
larger than 1µF. With X5R and X7R dielectrics, 2.2µF is
sufficient at all operating temperatures. Maximum output
VEN
GND
COUT
capacitor should be less than 330µF to insure the system can be powered on effectively.
Figure 1
Operation Region and Power Dissipation
The APL5605 maximum power dissipation depends on
Optimum performance can only be achieved when the
device is mounted on a PC board according to the SOP-8
the thermal resistance and temperature difference between the die junction and ambient air. The power dissi-
Board Layout diagram.
For dissipating heat
pation PD across the device is:
PD =
GND
( TJ − TA )
θJA
COUT
SOP-8
where (TJ-TA) is the temperature difference between the
junction and ambient air. θ JA is the thermal resistance
between Junction and ambient air. Assuming the TA=25οC
and maximum TJ=150ο C (typical thermal limit threshold),
VIN
VOUT
CIN
GND
the maximum power dissipation is calculated as below:
Figure 2
PD(max)=(150-25)/80
= 1.56(W)
Recommended Minimum Footprint
For normal operation, do not exceed the maximum junc8
7
6
5
1
2
3
4
0.072
0.024
tion temperature rating of TJ = 125 ο C. The calculated
power dissipation should less than:
0.212
PD =(125-25)/80
= 1.25(W)
The GND provides an electrical connection to the ground
and channels heat away. Connect the GND to the ground
by using a large pad or a ground plane.
0.050
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
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Unit : Inch
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APL5605
Package Information
SOP-8
D
E
E1
SEE VIEW A
h X 45
°
c
A
0.25
b
GAUGE PLANE
SEATING PLANE
A1
A2
e
L
VIEW A
S
Y
M
B
O
L
SOP-8
INCHES
MILLIMETERS
MIN.
MAX.
A
MIN.
MAX.
1.75
0.069
0.004
0.25
0.010
A1
0.10
A2
1.25
b
0.31
0.51
0.012
0.020
c
0.17
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
5.80
6.20
0.228
0.244
E1
3.80
4.00
0.150
0.157
e
0.049
1.27 BSC
0.050 BSC
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
0
0°
8°
0°
8°
Note: 1. Follow JEDEC MS-012 AA.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
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APL5605
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
OD1
B
A
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
SOP-8
A
H
T1
C
d
D
W
E1
F
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN.
1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
-0.00
-0.20
P0
P1
P2
D0
D1
T
A0
B0
K0
1.5+0.10
0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05
6.40±0.20 5.20±0.20 2.10±0.20
1.5 MIN.
-0.00
-0.40
(mm)
Devices Per Unit
Package Type
Unit
Quantity
SOP-8
Tape & Reel
2500
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Rev. A.4 - Mar., 2009
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APL5605
Taping Direction Information
SOP-8
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
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APL5605
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
ESD
Latch-Up
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD 78
13
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV, VMM≧200V
10ms, 1tr≧100mA
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APL5605
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
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