Fairchild FIN224AC 22-bit bi-directional serializer/deserializer Datasheet

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FIN224AC
22-Bit Bi-Directional Serializer/Deserializer
Features
Description
• Industry smallest 22-bit Serializer/Deserializer pair
The FIN224AC µSerDes™ is a low-power serializer/
deserializer (SerDes) that can help minimize the cost
and power of transferring wide signal paths. Through the
use of serialization, the number of signals transferred
from one point to another can be significantly reduced.
Typical reduction is 4:1 to 6:1 for unidirectional paths.
For bidirectional operation, using half duplex for multiple
sources, it is possible to reach signal reduction close to
10:1. Through the use of differential signaling, shielding
and EMI filters can also be minimized, further reducing
the cost of serialization. The differential signaling is also
important for providing a noise-insensitive signal that can
withstand radio and electrical noise sources. Major
reduction in power consumption allows minimal impact
on battery life in ultra-portable applications. It is possible
to use a single PLL for most applications including bidirectional operation.
• Low power for minimum impact on battery life
– Multiple power-down modes
• 100nA in standby mode, 5mA typical operating
conditions
• Highly rolled LVCMOS edge rate option to meet
regulatory requirements
• Cable reduction: 25:4 or greater
• Differential signaling:
––90dBm EMI when using CTL in lab conditions
–Minimized shielding
–Minimized EMI filter
–Minimum susceptibility to external interference
• Up to 22 bits in either direction
• Voltage translation from 1.65V to 3.6V
• High ESD protection: > 15kV HBM
• Parallel I/O power supply (VDDP) range, 1.65V - 3.6V
FIN224AC to FIN24AC Comparison
• Can support Microcontroller or RGB pixel interface
• Up to 20% power reduction
Applications
• Double wide CKP pulse on FIN224AC, Mode 3
• Image sensors
• Rolled edge rate for deserializer outputs on
FIN224AC, for single display applications
• Small displays
– LCD, cell phone, digital camera, portable gaming,
printer, PDA, video camera, automotive
• Same voltage range
• Same pinout and package
Ordering Information
Order
Number
Operating
Temperature
Range
FIN224ACGFX
-30 to +70°C
42-Ball, Ultra-Small Scale Ball Grid Array (USS-BGA),
Tape and Reel
JEDEC MO-195, 3.5mm Wide (Slow LVCMOS Edge Rate)
FIN224ACMLX
-30 to +70°C
40-Terminal, Molded Leadless Package (MLP), Quad,
JEDEC MO-220, 6mm Square (Slow LVCMOS Edge Rate)
Package Description
Packing
Method
Tape and Reel
µSerDesTM is a trademark of Fairchild Semiconductor Corporation.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
April 2011
LVCMOS
LVCMOS
CTL
FIN224AC
Serializer
FIN224AC
Deserializer
4
22
22
Figure 1. Conceptual Diagram
Functional Block Diagram
PLL
CKREF
STROBE
CKS0+
CKS0-
I
cksint
Register
DP[21:22]
+
-
0
Serializer
Control
DSO+/DSI-
+
-
Serializer
DP[1:20]
DSO-/DSI+
DP[23:24]
Register
Register
oe
+
-
Deserializer
Deserializer
Control
cksint
CKSI+
CKSI100
Termination
WORD CK
Generator
CKP
+
-
100 Gated
Termination
Control Logic
S1
S2
DIRO
Freq
Control
Direction
Control
DIRI
oe
Power Down
Control
Figure 2. Block Diagram
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
2
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
Basic Concept
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
Terminal Description
Terminal
Name
I/O Type
Number of
Terminals
DP[1:20]
I/O
20
LVCMOS parallel I/O, Direction controlled by DIRI pin
DP[21:22]
I
2
LVCMOS parallel unidirectional inputs
Description of Signals
DP[23:24]
O
2
LVCMOS unidirectional parallel outputs
CKREF
IN
1
LVCMOS clock input and PLL reference
STROBE
IN
1
LVCMOS strobe signal for latching data into the serializer
CKP
OUT
1
LVCMOS word clock output
2
CTL differential serial I/O data signals(1.)
DSO: Refers to output signal pair
DSI: Refers to input signal pair
DSO(I)+: Positive signal of DSO(I) pair
DSO(I)-: Negative signal of DSO(I) pair
2
CTL differential deserializer input bit clock
CKSI: Refers to signal pair
CKSI+: Positive signal of CKSI pair
CKSI-: Negative signal of CKSI pair
CTL differential serializer output bit clock
CKSO: Refers to signal pair
CKSO+: Positive signal of CKSO pair
CKSO-: Negative signal of CKSO pair
DSO+ / DSIDSO- / DSI+
CKSI+
CKSI-
DIFF-I/O
DIFF-IN
CKSO+
CKSO-
DIFF-OUT
2
S1
IN
1
S2
IN
1
DIRI
IN
1
LVCMOS control input used to control direction of data flow:
DIRI = “1” Serializer
DIRI = “0” Deserializer
DIRO
OUT
1
LVCMOS control output inversion of DIRI
VDDP
Supply
1
Power supply for parallel I/O and translation circuitry
LVCMOS mode selection terminals used to select frequency range for
the reflect, CKREF
VDDS
Supply
1
Power supply for core and serial I/O
VDDA
Supply
1
Power supply for analog PLL circuitry
GND
Supply
2
For ground signals (2 for µBGA, 1 for MLP)
Note:
1. The DSO/DSI serial port pins have been arranged such that if one device is rotated 180 degrees with respect to the
other device, the serial connections properly align without the need for any traces or cable signals to cross. Other
layout orientation may require that traces or cables cross.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
3
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
31 CKREF
32 STROBE
33 DP[1]
34 DP[2]
35 DP[3]
36 DP[4]
37 DP[5]
38 DP[6]
22 S2
10
21 VDDS
DP[17]
DP[18]
DP[19]
DP[20]
DP[21]
DP[22]
DP[23]
DP[24]
S1
VDDA
20
23 DIRI
9
19
24 CKSI+
8
18
25 CKSI-
7
17
26 DSO-
6
16
27 DSO+
5
15
28 CKSO-
4
14
29 CKSO+
3
13
30 DIRO
2
12
1
11
DP[9]
DP[10]
DP[11]
DP[12]
VDDP
CKP
DP[13]
DP[14]
DP[15]
DP[16]
39 DP[7]
40 DP[8]
Connection Diagrams
Figure 3. Terminal Assignments for MLP (Top View)
42 MBGA Package
3.5mm x 4.5mm
(.5mm Pitcth)
(Top View)
1
2
3
4
5
6
A
B
C
D
E
F
Pin Assignments
1
2
3
4
5
6
A
DP[9]
DP[7]
DP[5]
DP[3]
DP[1]
CKREF
B
DP[11]
DP[10]
DP[6]
DP[2]
STROBE
DIRO
C
CKP
DP[12]
DP[8]
DP[4]
CKSO+
CKSO-
D
DP[13]
DP[14]
VDDP
GND
E
DP[15]
DP[16]
GND
VDDS
CKSI+
CKSI-
F
DP[17]
DP[18]
DP[21]
VDDA
S2
DIRI
G
DP[19]
DP[20]
DP[22]
DP[23]
DP[24]
S1
DSO-/DSI+ DSO+/DSI-
G
Figure 4. Terminal Assignments for µBGA (Top View)
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
4
Turn-Around Functionality
The FIN224AC has the ability to be used as a 22-bit serializer or a 22-bit deserializer. Pins S1 and S2 must be
set to accommodate the clock reference input frequency
range of the serializer. Table 1 shows the pin programming of these options based on the S1 and S2 control
pins. The DIRI pin controls whether the device is a serializer or a deserializer. When DIRI is asserted LOW, the
device is configured as a deserializer. When the DIRI pin
is asserted HIGH, the device is configured as a serializer. Changing the state on the DIRI signal reverses the
direction of the I/O signals and generate the opposite
state signal on DIRO. For unidirectional operation the
DIRI pin should be hardwired to the HIGH or LOW state
and the DIRO pin should be left floating. For bi-directional operation, the DIRI of the master device is driven
by the system and the DIRO signal of the master is used
to drive the DIRI of the slave device.
The device passes and inverts the DIRI signal through
the device asynchronously to the DIRO signal. Care
must be taken by the system designer to ensure that no
contention occurs between the deserializer outputs and
the other devices on this port. Optimally the peripheral
device driving the serializer should be put into a HIGHimpedance state prior to the DIRI signal being asserted.
When a device with dedicated data outputs turns from a
deserializer to a serializer, the dedicated outputs remain
at the last logical value asserted. This value only
changes if the device is once again turned around into a
deserializer and the values are overwritten.
Power-Down Mode: (Mode 0)
Mode 0 is used for powering down and resetting the
device. When both of the mode signals are driven to a
LOW state, the PLL and references are disabled, differential input buffers are shut off, differential output buffers
are placed into a HIGH-impedance state, LVCMOS outputs are placed into a HIGH-impedance state, and LVCMOS inputs are driven to a valid level internally.
Additionally all internal circuitry is reset. The loss of
CKREF state is also enabled to ensure that the PLL only
powers-up if there is a valid CKREF signal.
Serializer/Deserializer with Dedicated I/O Variation
The serialization and deserialization circuitry is set up for
24 bits. Because of the dedicated inputs and outputs,
only 22 bits of data are serialized or deserialized.
DP[21:22] inputs to the serializer are transmitted to
DP[23:24] outputs on the deserializer.
In a typical application mode, signals of the device do not
change states other than between the desired frequency
range and the power-down mode. This allows for system-level power-down functionality to be implemented
via a single wire for a SerDes pair. The S1 and S2 selection signals that have their operating mode driven to a
“logic 0” should be hardwired to GND. The S1 and S2
signals that have their operating mode driven to a “logic
1” should be connected to a system-level power-down or
reset signal.
Table 1. Control Logic Circuitry
Mode
Number
S2
S1
DIRI
0
0
0
x
Power-Down Mode
0
1
1
22-Bit Serializer 2MHz to 5MHz CKREF
0
1
0
22-Bit Deserializer
1
0
1
22-Bit Serializer 5MHz to 15MHz CKREF
1
0
0
22-Bit Deserializer
1
1
1
22-Bit Serializer 10MHz to 26MHz CKREF (Divide by 2 Serial Data)
1
1
0
22-Bit Deserializer
Description
1
2
3
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
5
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
Control Logic Circuitry
The serializer configurations are described in the following sections. The basic serialization circuitry works
essentially identically in these modes, but the actual data
and clock streams differ depending on if CKREF is the
same as the STROBE signal or not. When it is stated
that CKREF does not equal STROBE, each signal is distinct and CKREF must be running at a frequency high
enough to avoid any loss of data condition. CKREF must
never be a lower frequency than STROBE.
The exact frequency that the reference clock needs to
run at depends upon the stability of the CKREF and
STROBE signal. If the source of the CKREF signal
implements spread spectrum technology, the minimun
frequency of the spread spectrum clock should be used
in calculating the ratio of STROBE frequency to the
CKREF frequency. Similarly, if the STROBE signal has
significant cycle-to-cycle variation, the maximum cycleto-cycle time needs to be factored into the selection of
the CKREF frequency.
Serializer Operation: MODE 1 or MODE 2,
DIRI = 1, CKREF = STROBE
Serializer Operation: MODE 3 (S1 = S2 =1),
DIRI =1. CKREF Divide by 2 Mode.
The PLL must receive a stable CKREF signal to achieve
lock prior to any valid data being sent. The CKREF signal can be used as the data STROBE signal provided
that data can be ignored during the PLL lock phase.
When operating in mode 3, the effective serial speed is
divided by two. This mode has been implemented to
accommodate cases where the reference clock frequency is high compared to the actual strobe frequency.
The actual strobe frequency must be less than or equal
to 50% of the CKREF frequency for this mode to work
properly. This mode, in all other ways, operates the
same as described in the section where CKREF does
not equal STROBE.
Once the PLL is stable and locked, the device can begin
to capture and serialize data. Data is captured on the rising edge of the STROBE signal and serialized. When
operating in serializer mode, the internal deserializer circuitry is disabled; including the serial clock, serial data
input buffers, bi-directional parallel outputs, and CKP
word clock. The CKP word clock is driven HIGH.
Serializer Operation: DIRI = 1, No CKREF
A third method of serialization can be acheived by providing a free-running bit clock on the CKSI signal. This
mode is enabled by grounding the CKREF signal and
driving the DIRI signal HIGH. At power-up, the device is
configured to accept a serialization clock from CKSI. If a
CKREF is received, this device enables the CKREF serialization mode. The device remains in this mode even if
CKREF is stopped. To re-enable this mode, the device
must be powered down and then powered back up with a
“logic 0” on CKREF.
Serializer Operation: DIRI = 1, CKREF Does Not
= STROBE
If the same signal is not used for CKREF and STROBE,
the CKREF signal must be run at a higher frequency
than the STROBE rate to serialize the data correctly. The
actual serial transfer rate remains at 13 times the
CKREF frequency. A data bit value of zero is sent when
no valid data is present in the serial bit stream. The operation of the serializer otherwise remains the same.
Deserializer Operation Mode
serial port and deserialized through use of the bit clock
sent with the data.
The operation of the deserializer is dependent on the
data received on the DSI data signal pair and the CKSI
clock signal pair. The following sections describe the
operation of the deserializer under distinct serializer
source conditions. References to the CKREF and
STROBE signals refer to the signals associated with the
serializer device generating the serial data and clock signals that are inputs to the deserializer. When operating in
deserializer mode, the internal serializer circuitry is disabled, including the parallel data input buffers. If there is
a CKREF signal provided, the CKSO serial clock continues to transmit bit clocks. Upon power-up (S1 or S2 = 1),
deserializer output data pins are driven LOW until valid
data is passed through the deserializer.
Deserializer Operation: DIRI = 0 (Serializer
Source: CKREF Does Not = STROBE)
The logical operation of the deserializer remains the
same if the CKREF is equal in frequency to the STROBE
or at a higher frequency than the STROBE. The actual
serial data stream presented to the deserializer is different because it has non-valid data bits sent between
words. The duty cycle of CKP varies based on the ratio
of the frequency of the CKREF signal to the STROBE
signal. The frequency of the CKP signal is equal to the
STROBE frequency. In modes 1 and 2, the CKP LOW
time equals half of the CKREF period of the serializer. In
mode 3, the CKP LOW is equal to the CKREF period.
The CKP HIGH time is approximately equal to the
STROBE period, minus the CKP LOW time.
Deserializer Operation: DIRI = 0 (Serializer
Source: CKREF = STROBE)
When the DIRI signal is asserted LOW, the device is
configured as a deserializer. Data is captured on the
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
6
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
Serializer Operation Mode
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
LVCMOS Data I/O
The LVCMOS input buffers have a nominal threshold
value equal to half VDD. The input buffers are only operational when the device is operating as a serializer.
When the device is operating as a deserializer, the inputs
are gated off to conserve power.
The LVCMOS 3-STATE output buffers are rated for a
source / sink current of approximately 0.5mA at 1.8V.
The outputs are active when the DIRI signal and either
S1 or S2 is asserted HIGH. When the DIRI signal and
either S1 or S2 is asserted LOW, the bi-directional LVCMOS I/Os is in a HIGH-Z state. Under purely capacitive
load conditions, the output swings between GND and
VDDP. When S1 or S2 initially transitions HIGH, the initial
state of the deserializer LVCMOS outputs is zero.
Unused LVCMOS input buffers must be either tied off to
a valid logic LOW or a valid logic HIGH level to prevent
static current draw due to a floating input. Unused LVCMOS output should be left floating. Unused bi-directional
pins should be connected to GND through a high-value
resistor. If a FIN224AC device is configured as an unidirectional serializer, unused data I/O can be treated as
unused inputs. If the FIN224AC is hardwired as a deserializer, unused data I/O can be treated as unused outputs.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
7
SerDes Serializer
PIXCLK_M
A6
B5
CKREF
STROBE
GPIO_MODE
F6
F5
J6
DIRI
S2
S1
J5
J4
J3
F3
J2
J1
F2
F1
E2
E1
D2
D1
C2
B1
B2
A1
C3
A2
B3
A3
C4
A4
B4
A5
DP24
DP23
DP22
DP21
DP20
DP19
DP18
DP17
DP16
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
U22
J6
F5
F6
B5
A6
STROBE
CKREF
B6
DIRO
DIRO
CKP
C1
DSO+/DSIDSO-/DSI+
D6
D5
D5
D6
DSO-/DSI+
DSO+/DSI-
CKSOCKSO+
C6
C5
E6
E5
CKSICKSI+
CKSICKSI+
E6
E5
C6
C5
CKSOCKSO+
F4
E4
D3
VDDA
VDDS
VDDP
2.8V
VDDA
VDDS
VDDP
C6
1nF
TP5
2.8V
1.8V
F4
E4
D3
FIN224AC
S1
S2
DIRI
B6
D4
E3
LCD_ENABLE_M
LCD_VSYNC_M
LCD_HSYNC_M
LCD17_M
LCD16_M
LCD15_M
LCD14_M
LCD13_M
LCD12_M
LCD
LCD11_M
Controller
LCD10_M
Out
LCD9_M
LCD8_M
LCD7_M
LCD6_M
LCD5_M
LCD4_M
LCD3_M
LCD2_M
LCD1_M
LCD0_M
SerDes Deserializer
FIN224AC
C3
.01uF
.01µF
2.8V
C12
.01uF
.01µF
C10
C11
GN D
GN D
U20
CKP
C1
DP24
DP23
DP22
DP21
DP20
DP19
DP18
DP17
DP16
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
J5
J4
J3
F3
J2
J1
F2
F1
E2
E1
D2
D1
C2
B1
B2
A1
C3
A2
B3
A3
C4
A4
B4
A5
PIXCLK_S
LCD_ENABLE_S
LCD_VSYNC_S
LCD_HSYNC_S
LCD17_S
LCD16_S
LCD15_S
LCD14_S
LCD13_S
LCD12_S
LCD11_S
LCD
LCD10_S
LCD9_S
Display
LCD8_S
In
LCD7_S
LCD6_S
LCD5_S
LCD4_S
LCD3_S
LCD2_S
LCD1_S
LCD0_S
E3
D4
VDDP
GN D
GN D
TP6
2.2uF 1nF
2.2µF
Assumptions:
1) 18-bit Unidirectional RGB Application
2) Mode 3 Operation (10 Mhz to 20Mhz CKREF)
3) VDDP= (1.65V to 3.6V)
Figure 5. FIN224AC RGB
SerDes Serializer
F6
F5
J6
DIRI
S2
S1
J5
J4
J3
F3
J2
J1
F2
F1
E2
E1
D2
D1
C2
B1
B2
A1
C3
A2
B3
A3
C4
A4
B4
A5
DP24
DP23
DP22
DP21
DP20
DP19
DP18
DP17
DP16
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
U23
J6
F5
F6
DIRO
B6
B5
A6
STROBE
CKREF
B6
DIRO
DSO-/DSI+
DSO+/DSI-
CKP
DSO+/DSIDSO-/DSI+
D6
D5
D5
D6
CKSOCKSO+
C6
C5
E6
E5
CKSICKSI+
CKSICKSI+
E6
E5
C6
C5
CKSOCKSO+
VDDA
VDDS
VDDP
F4
E4
D3
F4
E4
D3
VDDA
VDDS
VDDP
2.8V
TP3
2.8V
1.8V
C5
1nF
FIN224AC
S1
S2
DIRI
C1
D4
E3
LCD_/CS_M
LCD_ADDRESS_M
LCD17_M
LCD16_M
LCD15_M
LCD14_M
LCD13_M
LCD12_M
LCD
LCD11_M
LCD10_M
Controller
LCD9_M
Out
LCD8_M
LCD7_M
LCD6_M
LCD5_M
LCD4_M
LCD3_M
LCD2_M
LCD1_M
LCD0_M
TP1
CKREF
STROBE
2.8V
C9
C2
.01uF
.01F
.01uF
.01F
C8
C7
2.2uF
2.2F
1nF
GN D
GN D
GPIO_MODE
A6
B5
SerDes Deserializer
FIN224AC
CKP
C1
LCD_/WRITE_ENABLE_S
DP24
DP23
DP22
DP21
DP20
DP19
DP18
DP17
DP16
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
J5
J4
J3
F3
J2
J1
F2
F1
E2
E1
D2
D1
C2
B1
B2
A1
C3
A2
B3
A3
C4
A4
B4
A5
LCD_/CS_S
LCD_ADDRESS_S
LCD17_S
LCD16_S
LCD15_S
LCD14_S
LCD13_S
LCD12_S
LCD11_S
LCD10_S
LCD9_S
LCD8_S
LCD7_S
LCD6_S
LCD5_S
LCD4_S
LCD3_S
LCD2_S
LCD1_S
LCD0_S
LCD
Display
In
E3
D4
REFCLK
LCD_/WRITE_ENABLE_M
U21
VDDP
GN D
GN D
TP2
Assumptions:
1) 18-bit Unidirectional Controller Application
2) Mode 3 Operation (10 Mhz to 20Mhz CKREF)
3) VDDP= (1.65V to 3.6V)
4) REFCLK is a continously running clock with a frequency
greater than /WRITE_ENABLE.
Figure 6. FIN224AC Microcontroller
Flex Circuit Design Guidelines
The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex
cable. The following best practices should be used when developing the flex cabling or Flex PCB:
Keep all four differential wires the same length.
Allow no noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential wires.
Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom.
Do not place test points on differential serial wires.
Use differential serial wires a minimum of 2cm away from the antenna.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
8
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
Application Mode Diagrams
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
Symbol
VDD
IOS
TSTG
Parameter
Min.
Max.
Unit
Supply Voltage
-0.5
+4.6
V
ALL Input/Output Voltage
-0.5
+4.6
V
+150
°C
CTL Output Short-Circuit Duration
Continuous
Storage Temperature Range
-65
TJ
Maximum JunctionTemperature
+150
°C
TL
Lead Temperature (Soldering 4 Seconds)
+260
°C
IEC61000-4-2
15.0
Human Body Model, JESD22-A114, Serial I/O Pin
8.0
Human Body Model, JESD22-A114, All Pins
2.5
Charged Device Model, JESD22-C101
2.0
ESD
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Unit
2.5
3.3
V
Supply Voltage
1.65
3.60
V
Operating Temperature(2.)
-30
+70
°C
100
mVPP
VDDA, VDDS Supply Voltage
VDDP
TA
VDDA-PP
Supply Noise Voltage
Note:
2. Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired.
The datasheet specification should be met, without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside
datasheet specifications.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
9
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
Absolute Maximum Ratings
Values are for over-supply voltage and operating temperature ranges, unless otherwise specified. Typical values are
given for VDD = 2.775V and TA = 25°C. Positive current values refer to the current flowing into the device and negative
values refer to the current flowing out of the pins. Voltages are referenced to GROUND unless otherwise specified
(except ∆VOD and VOD).
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
LVCMOS I/O
VIH
Input High Voltage
0.65 x VDDP
VDDP
VIL
Input Low Voltage
GND
0.35 x VDDP
V
VDDP = 3.3±0.30
VOH
Output High Voltage
IOH = 2.0mA
VDDP = 2.5±-0.20
0.75 x VDDP
V
VDDP = 1.8±0.18
VDDP = 3.3±0.30
VOL
Output Low Voltage
IOL = 2.0mA
VDDP = 2.5±0.20
0.25 x VDDP
V
5.0
µA
VDDP = 1.8±0.18
IIN
Input Current
VIN = 0V to 3.6V
-5.0
DIFFERENTIAL I/O
IODH
Output HIGH source current VOS = 1.0V
-1.75
mA
IODL
Output LOW sink current
VOS = 1.0V
0.950
mA
IOS
Short-Circuit Output
Current
VOUT = 0V
IOZ
Disabled Output
Leakage Current
CKSO, DSO = 0V to VDDS
S2 = S1 = 0V
ITH
Differential Input Threshold
High Current
ITL
Differential Input Threshold
Low Current
IIZ
Disabled Input Leakage
Current
CKSI, DSI = 0V to VDDS
S2 = S1 = 0V
IIS
Short-Circuit Input Current
VOUT = VDDS
VICM
Input Common Mode
Range
VDDS = 2.775 ±5%
RTRM
CKSI, DS Internal Receiver VID = 50mV, VIC = 925mV, DIRI = 0
Termination Resistor
| CKSI+ – CKSI– | = VID
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
Driver Enabled
mA
Driver Disabled
±1
±5
µA
±5
µA
50
µA
±1
-50
µA
±5
µA
mA
0.5
VDDS-1
100
V
Ω
www.fairchildsemi.com
10
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
DC Electrical Characteristics
Typical values are given for VDD = 2.775V and TA = 25°C. Positive current values refer to the current flowing into the
device and negative values refer to the current flowing out of the pins. Voltages are referenced to GROUND unless
otherwise specified (except ∆VOD and VOD).
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Unit
IDDA1
VDDA Serializer Static Supply
Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 1
450
µA
IDDA2
VDDA Deserializer Static Supply
Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 0
550
µA
IDDS1
VDDS Serializer Static Supply
Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 1
4
mA
IDDS2
VDDS Deserializer Static Supply
Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 0
4.5
mA
VDD Power-Down Supply Current
IDD_PD = IDDA
S1 = S2 = 0 All Inputs at GND or VDD
0.1
µA
IDD_PD
1.2MHz
S2 = 0
S1 = 1 5MHz
26:1 Dynamic Serializer
IDD_SER1 Power Supply Current
IDD_SER1 = IDDA+IDDS+IDDP
CKREF = STROBE S2 = 1 5MHz
DIRI = H
S1 = 0 15MHz
S2 = 1 10MHz
S1 = 1 26MHz
S2 = 0 2MHz
S1 = 1 5MHz
26:1 Dynamic Deserializer
IDD_DES1 Power Supply Current
IDD_DES1 = IDDA+IDDS+IDDP
CKREF = STROBE S2 = 1 5MHz
S1 = 0 15MHz
DIRI = L
S2 = 1 10MHz
S1 = 1 26MHz
26:1 Dynamic Serializer
IDD_SER2 Power Supply Current
IDD_SES2 = IDDA+IDDS+IDDP
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
NO CKREF
STROBE Active
CKSI = 15x STROBE
DIRI = H
9
14
9
mA
17
9
16
5
6
4
mA
5
7
11
2MHz
8
5MHz
8
10MHz
10
15MHz
12
mA
www.fairchildsemi.com
11
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
Power Supply Currents
Characteristics at recommended over-supply voltage and operating temperature ranges, unless otherwise specified.
Typical values are given for VDD = 2.775V and TA = 25°C. Positive current values refer to the current flowing into
device and negative values means current flowing out of the pins. Voltages are referenced to GROUND unless otherwise specified (except ∆VOD and VOD).
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Serializer Input Operating Conditions
S2=0 S1=1
tTCP
fREF
CKREF Clock Period
(2MHz – 26MHz)
CKREF Frequency Relative to
STROBE
CKREF = STROBE
Figure 7.
CKREF does not =
STROBE
200
500
S2=1 S1=0
66
200
S2=1 S1=1
38.46
100.00
S2=0 S1=1
2.25 x
fSTROBE
ns
MHz
tCPWH
CKREF Clock High Time
0.2
0.5
T
tCPWL
CKREF Clock Low Time
0.2
0.5
T
tCLKT
LVCMOS Input Transition Time
Figure 9.
tSPWH
STROBE Pulse Width HIGH/LOW
Figure 9.
fMAX
Maximum Serial Data Rate
tSTC
DP(n) Setup to STROBE
tHTC
DP(n) Hold to STROBE
CKREF x 26
90.0
ns
(Tx4)/26
(Tx22)/26
ns
S2=0 S1=1
52
130
S2=1 S1=0
130
390
S2=1 S1=1
260
676
DIRI = 1
Mb/s
2.5
ns
2.0
ns
Serializer AC Electrical Characteristics
tTCCD
Transmitter Clock Input to Clock
Output Delay
tSPOS
CKSO Position Relative to DS(3.)
CKREF = STROBE
33a+1.5
35a+6.5
ns
-50
250
ps
PLL AC Electrical Characteristics
tTPLLS0
Serializer Phase Lock Loop
Stabilization Time
Figure 11.
200
µs
tTPLLD0
PLL Disable Time Loss of Clock
Figure 12.
30
µs
Figure 13.
20
ns
tTPLLD1
PLL Power-Down
Time(4.)
Deserializer Input Operating Conditions
tS_DS
Serial Port Setup Time,
DS-to-CKSI(5.)
1.4
ns
tH_DS
Serial Port Hold Time,
DS-to-CKS(5.)
-250
ps
Deserializer AC Electrical Characteristics
tRCOP
Deserializer Clock Output
(CKP OUT) Period(6.)
tRCOL
CKP OUT Low Time(6.)
tRCOH
CKP OUT High Time
Figure 10.
(Rising Edge STROBE) Serializer
source STROBE = CKREF
Figure 10.
50
500
ns
13a-3
13a+3
ns
13a-3
13a+3
ns
8a-6
8a+1
ns
tPDV
Data Valid to CKP LOW
(Rising Edge STROBE)
Figure 10.
tROLH
Output Rise Time (20% to 80%)
CL = 8pF
Figure 7.
18
ns
tROHL
Output Fall Time (20% to 80%)
CL = 8pF
Figure 7.
18
ns
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
12
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
AC Electrical Characteristics
Control Logic Timing Controls
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
tPHL_DIR,
tPLH_DIR
Propagation Delay
DIRI-to-DIRO
DIRI LOW-to-HIGH or HIGH-to-LOW
17
ns
tPLZ, tPHZ
Propagation Delay
DIRI-to-DP
DIRI LOW-to-HIGH
25
ns
tPZL, tPZH
Propagation Delay
DIRI-to-DP
DIRI HIGH-to-LOW
25
ns
tPLZ, tPHZ
DIRI = 0,
Deserializer Disable Time:
S1(2) = 0 and S2(1) = LOW-to-HIGH,
S0 or S1 to DP
Figure 14.
25
ns
DIRI = 0,(7.)
S1(2) = 0 and S2(1) = LOW-to-HIGH
Figure 14.
2
µs
Deserializer Enable Time:
tPZL, tPZH
S0 or S1 to DP
tPLZ, tPHZ
Serializer Disable Time:
S0 or S1 to CKSO, DS
DIRI = 1,
S1(2) = 0 and S2(1) = HIGH-to-LOW,
Figure 13.
25
ns
tPZL, tPZH
Serializer Enable Time:
S0 or S1 to CKSO, DS
DIRI = 1,
S1(2) and S2(1) = LOW-to-HIGH,
Figure 13.
65
ns
Note:
7. Deserializer Enable Time includes the time required for internal voltage and current references to stabilize. This time
is significantly less than the PLL Lock Time and therefore does not limit overall system startup time.
Capacitance
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
CIN
Capacitance of Input Only Signals, DIRI = 1, S1 = S2 = 0,
CKREF, STROBE, S1, S2, DIRI
VDD = 2.5V
2
pF
CIO
Capacitance of Parallel Port Pins
DP1:12
DIRI = 1, S1 = S2 = 0,
VDD = 2.5V
2
pF
Capacitance of Differential I/O
Signals
DIRI = 0, S1 = S2 = 0,
VDD = 2.775V
2
pF
CIO-DIFF
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
13
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
Notes:
3. Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO).
Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid.
4. The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the
state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies
dependent upon the operating mode of the device.
5. Signals are transmitted from the serializer source synchronously. Note that, in some cases, data is transmitted when
the clock remains at a HIGH state. Skew should only be measured when data and clock are transitioning at the same
time. Total measured input skew would be a combination of output skew from the serializer, load variations, and ISI
and jitter effects.
6. a = (1/f)/13) Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling
edge of CKP occurs approximately eight bit times after a data transition or six bit times after the falling edge of
CKSO. Variation of the data with respect to the CKP signal is due to internal propagation delay differences of the
data and CKP path and propagation delay differences on the various data pins. Note that if the CKREF is not equal
to STROBE for the serializer, the CKP signal does not maintain a 50% duty cycle.The low time of CKP remains 13
bit times.
Setup Time
STROBE
tROHL
tROLH
80%
tSTC
DP[1:12]
80%
DPn 20%
Data
20%
Hold Time
DPn
tHTC
STROBE
DP[1:12]
8pF
Data
Setup: MODE0 = “0” or “1”, MODE1 = “1”, SER/DES = “1”
Figure 7. LVCMOS Output Load and Transition
Times
Figure 8. Serial Setup and Hold Times
Data Time
tCLKT
tPDV
tCLKT
90%
90%
CKP
Data
DP[1:12]
10%
10%
tRCOP
tTCP
CKREF
50%
CKREF
VIH
VIL
tCPWH
50%
75%
50%
25%
50%
tRCOH
tRCOL
tCPWL
Setup: EN_DES = “1”, CKSI and DSI are valid signals
Figure 9. LVCMOS Clock Parameters
Figure 10. Deserializser Data Valid Window Time and
Clock Output Parameters
tTPLLS0
VDD/VDDA
S1 or S2
CKREF
CKS0
Note: CKREF Signal is free running.
Figure 11. Serializer PLL Lock Time
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
14
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
AC Loading and Waveforms
tTPPLD0
CKREF
CKS0
Note: CKREF Signal can be stopped either High or LOW
Figure 12. PLL Loss of Clock Disable Time
tPZL(ZH)
tPLZ(HZ)
S1 or S2
tTPPLD1
DS+,CKS0+
S1 or S2
HIGHZ
DS+,CKS0-
CKS0
Note: CKREF must be active and PLL must be stable
Figure 13. PLL Power-Down Time
Figure 14. Serializer Enable and Disable Time
tPLZ(HZ)
tPZL(ZH)
S1 or S2
DP
Note: If S1(2) transitioning then S2(1) must = 0 for test to be valid
Figure 15. Deserializer Enable and Disable Times
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
15
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
AC Loading and Waveforms (Continued)
MLP Embossed Tape Dimension
Dimensions are in millimeters.
D
P0
P2
T
E
F
K0
W
Wc
B0
Tc
A0
P1
D1
User Direction of Feed
Package
A0
±0.1
B0
±0.1
D
±0.05
D1
Min.
E
±0.1
F
±0.1
K0
±0.1
P1
Typ.
P0
Typ.
P2
±0/05
T
Typ.
TC
±0.005
5x5
5.35
5.35
1.55
1.50
1.75
5.50
1.40
8.00
4.00
2.00
0.30
0.07
W
±0.3
WC
Typ.
12.00 9.30
6x6
6.30 6.30 1.55 1.50 1.75 5.50 1.40 8.00 4.00 2.00 0.30
0.07 12.00 9.30
Notes:
Ao, Bo, and Ko dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement
requirements (see sketches A, B, and C).
Shipping Reel Dimension
Dimensions are in millimeters.
1.0mm
maximum
10° maximum
Typical component
cavity center line
Typical component
center line
B0
10° maximum component rotation
1.0mm
maximum
Sketch A (Side or Front Sectional View)
Sketch C (Top View)
A0
Sketch B (Top View)
Component Rotation
Component lateral movement
Component Rotation
W2 max Measured at Hub
W1 Measured at Hub
B Min
Dia C
Dia A
max
Dia D
min
Dia N
DETAIL AA
See detail AA
W3
Tape
Width
Dia A
Max.
Dim B
Min.
Dia C
+0.5/–0.2
Dia D
Min.
Dim N
Min.
Dim W1
+2.0/–0
Dim W2
Max.
Dim W3
(LSL–USL)
8
330.0
1.5
13.0
20.2
178.0
8.4
14.4
7.9 ~ 10.4
12
330.0
1.5
13.0
20.2
178.0
12.4
18.4
11.9 ~ 15.4
16
330.0
1.5
13.0
20.2
178.0
16.4
22.4
15.9 ~ 19.4
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
16
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
Tape and Reel Specification
0.15 C
6.00
B
A
(0.80)
6.00
PIN #1 IDENT
6.38MIN
4.37MAX
0.15 C
4.77MIN
0.80 MAX
0.10 C
0.08 C
(0.20)
0.05
0.00
0.20MIN
X4
C
0.28 MAX
SEATING
PLANE
4.20
4.00
X40
0.50TYP
E
0.50
0.30
0.50
4.20
4.00
(DATUM B)
PIN #1 ID
(DATUM A)
0.18-0.30
0.50
0.10
0.05
C A B
C
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION
WJJD-2 WITH EXCEPTION THAT THIS IS A SAWN VERSION..
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994.
D. LAND PATTERN PER IPC SM-782.
E. WIDTH REDUCED TO AVOID SOLDER BRIDGING.
F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR
TIE BAR PROTRUSIONS.
G. DRAWING FILENAME: MKT-MLP40Arev3.
Figure 16. 40-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO0220, 6mm Square
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
17
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
Physical Dimensions
2X
3.50
0.10 C
2X
(0.35)
(0.5)
0.10 C
(0.6)
2.5
(0.75)
TERMINAL
A1 CORNER
INDEX AREA
4.50
3.0
0.5
0.5
Ø0.3±0.05
BOTTOM VIEW
X42
0.15
0.05
C A B
C
0.89±0.082
(QA CONTROL VALUE)
0.45±0.05
1.00 MAX
0.21±0.04
0.10 C
C
0.2+0.1
-0.0
0.08 C
0.23±0.05
SEATING PLANE
LAND PATTERN
RECOMMENDATION
Figure 17. 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide
Note: Click here for tape and reel specifications, available at:
http://www.fairchildsemi.com/products/analog/packaging/bga42.html.
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
18
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
Physical Dimensions (Continued)
FIN224AC — 22-Bit Bi-Directional Serializer/Deserializer
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
19