TI1 DS38C86AVB Ds38c86a cmos btl 9-bit latching data transceiver Datasheet

DS38C86A
DS38C86A CMOS BTL 9-Bit Latching Data Transceiver
Literature Number: SNOS802A
DS38C86A
CMOS BTL 9-Bit Latching Data Transceiver
General Description
The DS38C86A is a 9-bit BTL Latching Data Transceiver
designed specifically for proprietary bus interfaces. The device is implemented in CMOS technology, and delivers all of
the performance of its Bi-CMOS counterparts while consuming less then half of the power supply current of the
DS3886A. The DS38C86A conforms to the IEEE 11941.1
(Backplane Transceiver Logic - BTL) Standard.
The DS38C86A incorporates an edge-triggered latch in the
driver path which can be bypassed during fall-through mode
of operation and a transparent latch in the receiver path. The
DS38C86A driver output configuration is an open drain
which allows Wired-OR connection on the bus. A unique
design reduces the bus loading to 3 pF typical. The driver
also has high sink current capability to comply with the bus
loading requirements defined within IEEE 11941.1 BTL
specification.
Backplane Transceiver Logic (BTL) is a signaling standard
that was invented and first introduced by National Semiconductor, then developed by the IEEE to enhance the performance of backplane buses. BTL transceivers feature low
output capacitance drivers to minimize bus loading, a 1V
nominal signal swing for reduced power consumption and
receivers with precision thresholds for maximum noise immunity. The BTL standard eliminates settling time delays that
severely limit TTL bus performance, and thus provide significantly higher bus transfer rates. The backplane bus is intended to be operated with termination resistors (selected to
match the bus impedance) connected to a 2.1V at both ends.
The low voltage is typically 1V.
The DS38C86A provides an alternative to high power Bipolar and BiCMOS devices with the use of CMOS technology.
The CMOS technology enables the DS38C86A to operate at
50% of the ICC required by the Bi-CMOS DS3886A. This can
have a major impact on system power consumption. For
example, if a backplane is 128 bits wide, 16 devices (9 bits
each) required per card. Also assume the backplane is one
rack with 20 slots. Power dissipation savings for this application is calculated by the following equation:
P = ICC-savings x Power supply voltage x number of devices
P = 32 mA x 5.5V x 320 = 56 Watts
The power dissipation savings may increase even more
when; the system bus is wider than 128 bits, there are
multiple racks in the system, or if the system includes a hot
backup. This may double the power dissipation savings.
Separate ground pins are provided for each BTL output
minimize induced ground noise during simultaneous switching.
The unique driver circuitry provides a maximum slew rate of
0.9V/ns which allows controlled rise and fall times to reduce
noise coupling to adjacent lines.
The transceiver’s high impedance control and driver inputs
are fully TTL compatible.
The receiver is a high speed comparator that utilizes a
Bandgap reference for precision threshold control allowing
maximum immunity to the BTL 1V signaling level.
Separate QVCC and QGND pins are provided to minimize
the effects of high current switching noise. The receiver
output is TRI-STATE ® and fully TTL compatible.
The DS38C86A supports live insertion as defined in IEEE
896.2 through the LI (Live Insertion) pin. To implement live
insertion the LI pin should be connected to the live insertion
power connector. If this function is not supported, the LI pin
must be tied to the VCC pin. The DS38C86A also provides
glitch free power up/down protection during power sequencing.
The DS38C86A has two types of power connections in addition to the LI pin. They are the Logic VCC (VCC) and the
Quiet VCC (QVCC). There are two Logic VCC pins on the
DS38C86A that provide the supply voltage for the logic and
control circuitry. Multiple connections are provided to reduce
the effects of package inductance and thereby minimize
switching noise. A voltage delta between VCC and QVCC
should never exceed ± 0.5V because of ESD circuitry.
When CD (Chip Disable) is high, An is in high impedance
state and Bn is high. To transmit data (An to Bn), the T/R
signal is high.
When RBYP is high, the positive edge triggered flip-flop is in
the transparent mode. When RBYP is low, the positive edge
of the ACLK signal clocks the data.
In addition, the ESD circuitry between the VCC pins and all
other pins except for BTL I/O’s and LI pins requires that any
voltage on these pins should not exceed the voltage on VCC
+0.5V.
There are three different types of ground pins on the
DS38C86A; the logic ground (GND), BTL grounds
(B0GND–B8GND) and the Bandgap reference ground
(QGND). All of these ground reference pins are isolated
within the chip to minimize the effects of high current switching transients. For optimum performance the QGND should
be returned to the connector through a quiet channel that
does not carry transient switching current. The GND and
B0GND–B8GND should be connected to the nearest backplane ground pin with the shortest possible path.
Since many different grounding schemes could be implemented and ESD circuitry exists on the DS38C86A, it is
important to note that any voltage between ground pins,
QGND, GND or B0GND–B8GND should not exceed ± 0.5V
including power up/down sequencing.
The DS38C86A is offered in a 48-pin 7 x 7 space saving
PQFP package.
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 2001 National Semiconductor Corporation
DS012623
www.national.com
DS38C86A CMOS BTL 9-Bit Latching Data Transceiver
July 1998
DS38C86A
n 1V Signal swings with 80 mA sink capability
n Open drain bus-port outputs allow Wired-OR connection
n Controlled rise and fall time to reduce noise coupling to
adjacent lines
n TTL compatible Driver and Control inputs
n Built in Bandgap reference with separate QVCC and
QGND pins for precise receiver thresholds
n Individual bus-port ground pins
n Tight skew —
— Driver 2.0 ns max
— Receiver 2.5 ns max
Features
n > 50% Less ICC then Bi-CMOS DS3886A
n 9-Bit inverting BTL latching transceiver
n Meets IEEE 1194.1 Standard on Backplane Transceiver
Logic (BTL)
n Very low bus-port capacitance — 3 pF typical
n Supports live insertion
n Glitch free power-up/down protection
n Fast propagation delays
— An to Bn (Fall-Thru Mode) 6.0 ns max
— Bn to An (Bypass Mode) 7.0 ns max
Connection Diagram
DS012623-3
Ordering Information
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NSID
Package
NS Package Number
DS38C86AVB
PQFP (7x7)
VBH48A
2
Power Dissipation at 25˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
PQFP (7x7) (VF48B)
−0.5V to VCC + 0.5V
−0.5V to VCC + 0.5V
Receiver Input Current
260˚C
Recommended Operating
Conditions
Driver Input and Receiver
Output (An)
−65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec.)
+6.5V
Control Input Voltage
12.5 mW/˚C
Storage Temperature Range
Supply Voltage
(VCC, QVCC, LI)
1.56W
Derate PQFP Package
± 15 mA
Bus Voltage (Bn)
+6.5V
Supply Voltage (VCC)
Bus Termination Voltage
+2.4V
Bus Termination Voltage
ESD Bn Pins (HBM)
≥2 kV
Operating Free Air
ESD other Pins (HBM)
Temperature
Min
Typ
Max
Units
+4.5
+5.0
+5.5
V
+2.06
+2.1
+2.14
V
0
+25
+70
˚C
≥1.5 kV
(Note 12)
DC Electrical Characteristics (Notes 2, 3)
TA = 0˚C to +70˚C unless otherwise noted, VCC = 5V ± 10%
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER AND CONTROL INPUTS (CD, T/R, An, ACLK, LE and RBYP)
VIH
Minimum Input High Voltage
2.0
V
VIL
Maximum Input Low Voltage
0.8
V
IIH
Input High Current
VIN = VCC
40
µA
IIL
Input Low Current
VIN = 0V, (except An)
−10
µA
IIL
Input Low Current
VIN = 0V, (An)
−100
µA
VCL
Input Diode Clamp Voltage
ICLAMP = −12 mA
−1.2
V
1.1
V
DRIVER OUTPUT/RECEIVER INPUT (Bn)
VOLB
Output Low Bus Voltage
(Note 5)
An = T/R = VCC, CD = 0V,
IOL = 80 mA
IOFF
Output Low Bus Current
An = CD = 0V, T/R = VCC,
Bn = 0.75V
−200
µA
Output High Bus Current
An = CD = 0V, T/R = VCC,
Bn = 2.1V
300
µA
IOLBZ
Output Low Bus Current
T/R = CD = VCC, Bn = 0.75V
(Chip Disabled)
−100
µA
IOHBZ
Output High Bus Current
T/R = CD = VCC, Bn = 2.1V
(Chip Disabled)
100
µA
VTH
Receiver Input Threshold
T/R = CD = 0V
1.47
1.55
1.62
V
VCLP
Positive Clamp Voltage
VCC = Max or 0V, IBn = 1 mA
2.4
3.8
4.5
V
VCLN
Negative Clamp Voltage
ICLAMP = −12 mA
−1.2
V
0.75
0.9
RECEIVER OUTPUT (An)
VOH
VOL
IOZ
Voltage Output High
Voltage Output Low
TRI-STATE Leakage Current
Bn = 1.1V, IOH = −2 mA,
T/R = CD = 0V
2.5
Bn = 1.1V, IOH = −100 µA,
T/R = CD = 0V
4.0
4.8
V
V
Bn = 2.1V, T/R = CD = 0V,
IOL = 24 mA
0.2
0.5
V
Bn = 2.1V T/R = CD = 0V,
IOL = 8 mA
0.1
0.3
V
VIN = VCC, CD = VCC,
T/R = 0V, Bn = 0.75V
10
µA
VIN = 0.0V, CD = VCC,
T/R = 0V, Bn = 0.75V
−10
µA
3
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DS38C86A
Absolute Maximum Ratings (Notes 1, 2)
DS38C86A
DC Electrical Characteristics (Notes 2, 3)
(Continued)
TA = 0˚C to +70˚C unless otherwise noted, VCC = 5V ± 10%
Symbol
Parameter
Conditions
Min
Typ
Max
Units
−120
µA
RECEIVER OUTPUT (An)
IOS
Output Short Circuit Current
Bn = 1.1V, T/R = CD = 0V
(Note 4)
−40
SUPPLY CURRENT
ICC_DIS
Standby Current (No Load)
T/R = All An = VCC, CD = VCC,
ACLK = LE = RBYP = VCC
15
22
mA
ICCT
Sum of QVCC, VCC, LI
All Bn = 2.1, T/R = CD = LE =
0.5V, ACLK = RBYP = 3.4
24
31
mA
ILI
Live Insertion Current
T/R = An = CD = RBYP =
ACLK = 0.0V
1
3
mA
T/R = All An = RBYP = VCC,
CD = ACLK = 0V
1
3
mA
AC Electrical Characteristics
(Note 6)
TA = 0˚C to +70˚C, VCC = 5V ± 10%
DRIVER (REN = 0V for all conditions)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER TIMING REQUIREMENTS
tPHL
An to Bn, Prop Delay
CD = 0V, T/R = RBYP = 3V
2.0
4.3
6.0
ns
tPLH
Fall-Thru Mode
(Figures 1, 2)
2.0
3.8
6.0
ns
tPHL
ACLK to Bn, Prop. Delay
CD = RBYP = 0V, T/R = 3V
2.0
4.5
6.0
ns
tPLH
Transparent Latch Mode
(Figures 1, 4)
2.0
4.0
6.0
ns
tPHL
CD to Bn
tPLH
tPHL
T/R to Bn
CD = RBYP = 0V, T/R = 3V
3
5.3
7.5
ns
Disable Time
(Figures 1, 3)
2.5
4.3
7.5
ns
Enable Time
CD = 0V, RBYP = 3V
9.0
16.0
22.0
ns
(Figures 10, 11)
2.0
6.6
8.0
ns
Transition Time-Rise/Fall for Bn
(20% to 80%)
CD = RBYP = 0V, T/R = 3V
0.8
1.4
3.0
ns
(Figures 1, 3)(Note 10)
1.0
Slew Rate is Calculated from 1.3V to 1.8V
for Bn
CD = RBYP = 0V, T/R = 3V
tPLH
tr
Enable Time
Disable Time
tf
SR
1.7
3.0
ns
0.5
0.9
V/ns
(Figures 1, 2)(Note 10)
tSKEW
ACLK to Bn, Same
Package
Output to
Output
(Note 7)
0.9
2.5
ns
An to Bn, Same Package
Output to
Output
(Note 7)
0.9
2.0
ns
DRIVER TIMING REQUIREMENTS (Figure 4)
tS
An to ACLK (Set-Up Time)
3.0
ns
tH
ACLK to An (Hold Time)
1.0
ns
tPW
ACLK Pulse Width
3.0
ns
CD = RBYP = 0V, T/R = 3V
RECEIVER
tPHL
Bn to An, Prop Delay
CD = T/R = 0V, LE = 3V
3.0
4.8
7.0
ns
ns
tPLH
Bypass Mode
(Figures 5, 6)
3.0
5.0
7.0
tPHL
LE to An, Prop Delay
CD = T/R = 0V
4.0
5.7
7.5
ns
tPLH
Latch Mode
(Figures 5, 7)
4.0
5.7
7.5
ns
tPLZ
CD to An
Disable Time
LE = VCC, Bn = 2.1V, T/R = 0V
3.0
6.3
10.0
ns
tPZL
Enable Time
(Figures 8, 9)
2.5
3.5
10.0
ns
tPHZ
Disable Time
LE = VCC, Bn = 1.1V, T/R = 0V
4.0
7.3
10.0
ns
tPZH
Enable Time
(Figures 8, 9)
3.5
5.5
8.5
ns
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4
DS38C86A
AC Electrical Characteristics
(Note 6) (Continued)
TA = 0˚C to +70˚C, VCC = 5V ± 10%
DRIVER (REN = 0V for all conditions)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RECEIVER
tPLZ
Disable Time
LE = VCC, Bn = 2.1V, CD = 0V
3.0
6.0
9.0
ns
tPZL
T/R to An
Enable Time
(Figures 10, 11)
3.0
5.0
9.0
ns
tPHZ
Disable Time
LE = VCC, Bn = 1.1 CD = 0V
3.0
7.3
12.0
ns
tPZH
Enable Time
(Figures 8, 9)
3.0
5.5
12.0
ns
tSKEW
LE to An, Same Package
(Note 7)
0.6
2.5
ns
Bn to An, Same Package
(Note 7)
0.7
2.5
ns
RECEIVER TIMING REQUIREMENTS (Figure 7)
tS
Bn to LE (Set-Up Time)
3
ns
tH
LE to Bn (Hold Time)
1
ns
tPW
LE Pulse Width
5
ns
CD = 0V, T/R = 0V
PARAMETERS NOT TESTED
COUTPUT
Capacitance at Bn
(Note 9)
3
pF
tNR
Noise Rejection
(Note 10)
1
ns
Note 1: “Absolute Maximum Ratings” are these beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2: All input and/or output pins shall not exceed VCC+0.5V and shall not exceed the absolute maximum rating at any time, including power-up and power-down.
This prevents the ESD structure from being damaged due to excessive currents flowing from the input and/or output pins to QVCC and VCC. There is a diode between
each input and/or output to VCC which is forward biased when incorrent sequencing is applied. LI and Bn pins do not have power sequencing requirements with
respect to VCC and QVCC. Furthermore, the difference between VCC and QVCC should never be greater than 0.5V at any time including power-up.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified.
All typical values are specified under these conditions: VCC = 5V and TA = 25˚C, unless otherwise stated.
Note 4: Only one output should be shorted at a time, and duration of the short should not exceed one second.
Note 5: Referenced to appropriate signal ground. Do not exceed maximum power dissipation of package.
Note 6: Input waveforms shall have a rise and fall time of 3 ns.
Note 7: tSKEW is the absolute value defined as the difference seen in propagation delay between drivers (receivers) in the same package with identical load
conditions.
Note 8: This parameter is tested using TDR techniques described in 1194.0 BTL Backplane Design Guide.
Note 9: This parameter is tested during device characterization. The measurements revealed that the part will reject 1 ns pulse width.
Note 10: Futurebus+ transceivers are required to limit bus signal rise and fall times to no faster then 0.5 V/ns, measured between 1.3V to 1.8V (approximately 20%
to 80% of the nominal voltage swing). The rise and fall times are measured with a transceiver loading equivalent to 12.5Ω ties to +2.1 VDC.
Note 11: Capacitance includes jig and probe capacitance.
Note 12: All pins meet 2 kV typical, one device failure observed between An and QVCC in ESD rel sample.
Pin Description
Pin Name
No. of
Pins
Input/Output
A0–A8
9
I/O
ACLK
1
I
Description
TTL driver input and TRI-STATE receiver output
Clock input for latch mode
B0–B8
9
I/O
BTL receiver input and driver output
B0 GND–B8 GND
9
NA
Driver output ground reduces ground bounce due to high current switching of
driver outputs. (Note 11)
CD
1
I
GND
2
NA
Chip disable
LE
1
I
LI
1
NA
Power supply for live insertion. Boards that require live insertion should connect
LI to the live insertion pin on the connector. (Note 12)
NC
9
NA
No connect
QGND
1
NA
Ground reference for receiver input bandgap reference and non-switching
circuits (Note 12)
QVCC
1
NA
RBYP
1
I
Ground reference for switching circuits (Note 11)
Latch enable
Power supply for bandgap reference and non-switching circuits (Note 12)
Register bypass enable
5
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DS38C86A
Pin Description
(Continued)
Pin Name
No. of
Pins
T/R
1
I
VCC
2
NA
CD
Input/Output
Description
Transmit/Receive (bar) — transmit (An to Bn), receive (Bn to An)
Power supply for switching circuits (Note 12)
T/R
LE
RBYP
ACLK
An
Bn
H
X
L
H
X
X
X
Z
H
X
H
X
L
L
H
H
X
H
X
H
L
L
H
X
L
X
X
Bn0
L
H
X
L
↑
H
L
L
H
X
L
↑
L
H
L
L
H
X
X
H
L
L
L
H
X
X
L
H
L
L
L
X
X
An0
X
X = High or Low Logic state.
Z = High impedance state.
L = Low state.
H = High state.
↑ = Low to High transition.
An0 = No change from previous state.
Bn0 = Np change from previous state.
BTL = High and Low state are nominally 2.1V and 1.2V, respectively.
CMOS = High and Low state are nominally VCC and 0V, respectively.
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6
DS38C86A
Logic Diagram
DS012623-15
7
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DS38C86A
Test Circuits and Timing Waveforms
(Note 11)
DS012623-9
FIGURE 6. Receiver: Bn to An
DS012623-4
FIGURE 1. Driver Propagation Delay Set-Up
DS012623-5
FIGURE 2. Driver: An to Bn, CD to An
DS012623-10
FIGURE 7. Receiver: Enable/Disable Set-Up
DS012623-6
FIGURE 3. Driver: CD to Bn
DS012623-11
FIGURE 8. Receiver: Enable/Disable Set-Up
DS012623-7
FIGURE 4. Driver: ACLK to Bn, tS, tH, tPW
DS012623-12
FIGURE 9. Receiver: CD to An, T/R to An
(tPHZ and tPZH only)
DS012623-8
FIGURE 5. Receiver: Propagation Delay Set-Up
DS012623-13
FIGURE 10. T/R to An, T/R to Bn
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8
DS38C86A
Test Circuits and Timing Waveforms
(Note 11) (Continued)
DS012623-14
FIGURE 11. T/R to Bn (tPHL and tPLH only)
T/R to An (tPZL and tPLZ only)
9
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DS38C86A CMOS BTL 9-Bit Latching Data Transceiver
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead (7mm x 7mm) Molded PQFP, JEDEC
Order Number DS38C86AVB
NS Package Number VBH48A
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