MOTOROLA MCM20014IBMN 1/3â color vga digital image sensor Datasheet

MOTOROLA
Order this document by MCM20014/D
SEMICONDUCTOR TECHNICAL DATA
MCM20014
1/3” Color VGA Digital Image Sensor
640 x 480 pixel progressive/interlace scan
solid state image sensor with integrated CDS/PGA/ADC,
digital programming, control, timing, and pixel correction
features
ImageMOS
Features:
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VGA resolution, active CMOS image sensor with square pixel unit cells
7.8µm pitch pixels with patented pinned photodiode architecture
Bayer-RGB color filter array with optional micro lenses
High sensitivity, quantum efficiency, and charge conversion efficiency
Low fixed pattern noise / Wide dynamic range
Antiblooming and continuous variable speed shutter
Single master clock operation
Digitally programmable via I2C interface
Ordering Information
Integrated on-chip timing/logic circuitry
CDS sample and hold for suppression of low frequency and correlated reset
Device
Package
noise
48X programmable variable gain to optimize dynamic range and facilitate white MCM20014IBMN
48 CLCC-IB
balance and iris adjustment
Monochrome
10-bit, pipelined algorithmic RSD ADC
MCM20014IBB
48 CLCC-IB
User selectable digital output formats:
8-bit companded data
Color
10-bit linear data
Column offset correction, and Bad Pixel Replacement for noise suppression
Pixel addressability to support ‘Window of Interest’ windowing, resolution, and subsampling
30fps full VGA at 10Mhz Master Clock Rate
Single 3.3V power supply
48 pin CLCC package
The MCM20014 is a fully integrated, high performance CMOS image sensor with features such as integrated timing
control, and analog signal processing for digital imaging applications. The part provides designers a complete imaging solution with a monolithic image capture and processing engine thus making it a true “camera on a chip”. System benefits enable design of smaller, portable, low cost and low power systems. Thereby making the product
suitable for a variety of consumer applications including still/full motion imaging, security/surveillance, and automotive among others.
The imaging pixels are based on active CMOS pixels using pinned photodiodes that are realized using Motorola’s
sub-micron ImageMOSTM technology. The frame rate is completely adjustable from 0 to 30 frames per second
without adjusting the system clock from 10Mhz. Each pixel on the sensor is individually addressable allowing the
user to control “Window of Interest” (WOI) panning and zooming, sub-sampling, resolution, exposure, gain, and
other image processing features via a two pin I2C interface. Programmable digital signal processing blocks
included in the data path are bad-pixel replacement and noise compensation for image enhancement. The sensor
is run by supplying a single Master Clock. The sensor output is 8 or 10 digital bits depending on output mode
selected.
This document contains information on a new product.
Specifications and information herein are subject to change without notice.
November 2000
 MOTOROLA, INC. 2000
MCLK
INIT
Sensor
Interface
Block
640 x 480 pixels
(704 x 512 total including
STBY
SYNC
SCLK
SDATA
I2C Serial
dark and isolation)
Interface
CDS
FRC
Post ADC
Column
Offset
White
Balance
Global
Gain
Global
Offset
10 Bit
ADC
Bad Pixel Replace
Noise Companding
ADC(9:0)
HCLK
VCLK
SOF
Figure 1. MCM20014 Simplified Block Diagram
Specifications
Image Size: 5.0mm x 3.7mm (1/3”)
Resolution: 640 x 480 pixels, available digital zoom and region of interest (ROI) windowing
Pixel Size: 7.8µm x 7.8µm
Monochrome Sensitivty: 3.0 V/Lux-sec
Min. Detectable Light Level: 5 Lux at 30FPS/F2 lens
Scan Modes: Progressive/Interlace
Shutter Modes: Continuous (Video)/ Single (Still)
Readout Rate: 13.5MSPS
Frame Rate: 0-40 frames per second @ 13.5Mhz
Max Master Clock Frequency: 13.5MHz
System Dynamic Range: 50dB
On Chip programmable gain: -2.7dB to 27dB
On Chip Image Correction: Column offset calibration, data companding, bad pixel replacement
Analog to Digital Converter: 10-bit, RSD ADC
Power Dissipation: 215mW (dynamic) / 25mW (standby)
Package: 48 pin ceramic LCC
Temperature Operating Range: 0-40oC
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MCM20014
DVSS TEST_IN_0 TEST_IN_1 TEST_IN_2 TEST_IN_3 TEST_IN_4 TEST_IN_5 TEST_IN_6 TEST_IN_7 TEST_IN_8 TEST_IN_9
41
42
40
39
38
37
36
35
34
33
32
DVDD1
31
30 SYNC
704
10
8Dark + 8Dummy
43
BLANK
4Dark + 8Dummy
40Dark + 8Dummy
44
Row Decoder
and Drivers
VCLK
HCLK
and Timing Generation
45
Master Row Sequencer,
Integration Control
512
SOF
DVGA CMOS Imager
TM
IMOS
Array
SensorPixel
Array
480
480
512
640
2
1
12Dark + 8Dummy
1 2
704
Column
Sequencer
and Drivers
704
Column Decode, Sensing and Muxing
29
TS
28
INIT
27 STDBY
EXT_VINS 14
26 SDATA
I2C
Serial
Color
Sequencer
25 SCLK
Analog
Switch
6
6
6
24
6
Column
Offset
Calibration
TST_VOU 15
MCLK
I2C Register Decode
23 AVSS1
22 AVDD1
6
Line
Rate
Clamp
CLRCA
20
CLRCB
21
DOV
Single Stage
DPGA 1X8X
0.9 - 4.8x
-0.8 to 13.6 dB
1.0X
6.0dB
6
6
Single Stage
1XDPGA
8X
1.0 - 8.9x
0 to 19 dB
DOV
10 Bit
RSD
Pipelined
2.0X
6.0dB
10
Post ADC
Processing
(Bad Pixel,
Companding.)
CVREFM 18
nc
Test
Monitor
Logic
Vrefp
Bandgap
Reference
and
Bias
Generation
CVREFP 19
CVBG
6
10
Vrefm
7
ADC0
6
ADC1
5
ADC2
4
ADC3
3
ADC4
2
ADC5
1
ADC6
48 ADC7
1
47 ADC8
46 ADC9
0
Analog Circuits
Vcm
Digital Logic
Ibias
8
9
11
12
nc
CVBG2
nc
CVBG1
13
EXTRES
nc
AVSS3
nc
CVBG
16
17
AVDD2 AVSS2
Figure 2. MCM20014 Detailed Block Diagram
MCM20014
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1.0 MCM20014 Overview
The MCM20014 is a solid state CMOS Active CMOS
Imager (ACITM) that integrates the functionality of a
complete analog image acquistion, digitizer, and digital
signal processing system on a single chip. The image
sensor comprises a 1/3” format pixel array with 640x480
(VGA) active elements. The image size is fully programmable to user defined windows of interest. The pixels
are on a 7.8µm pitch. High sensitivity and low noise are
a characteristic of the pinned photodiode architecture
utilized in the pixels. Optional microlenses are available
to further enhance the sensitivity. The sensor is available with Bayer patterned Color Filter Arrays (CFAs) for
color output or as a monochrome imager.
Integrated timing and programming controls allow video
(CFCM) or still (SFCM) image capture mode supporting
progressive or interlace scan modes. Frame rates are
programmable while keeping Master Clock frequency
constant. User programmable row and column start/
stop allow windowing to a minimum 1x1 pixel window.
Windowing can also be performed by subsampling in
multiple pixel increments to allow digital zoom.
A high performance analog signal processing chain
helps establish a new benchmark for digital image capture. The sensor has an unprecedented level of integration. The analog video output of the pixel array is
processed by an on chip processing pipeline. Correlated Double Sampling (CDS) eliminates low frequency
correlated noise. The Frame Rate Clamp (FRC) enables real time optical black level calibration and offset
correction. Digitally Programmable Amplifiers (DPGAs)
allow real time color gain correction for Auto White Balance (AWB) as well as global gain adjustment; offset
calibration can be done on a per column basis or globally. This per-column offset correction can be applied automatically or by using stored values in the on chip
SRAM. A 10-bit Redundant Signed Digit (RSD) ADC
converts the analog data to a 10-bit digital word stream.
The fully differential analog signal processing pipeline
serves to improve noise immunity, signal to noise ratio,
and system dynamic range.
A digital signal post processing block includes programmable features for output data companding and pixel
correction. User programmable thresholding allows replacement of pixels beyond preset maximum and minimum levels by average, trailing, or leading pixels. A
noise core allows companding of data that allows users
to accentuate dark pixels. Data companding can be
done by loading any one of eight hard coded compression curves which performs a 10 to 8 bit transformation
on the data.
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The sensor uses an industry standard two line I2C serial
interface. It operates with a single 3.3V power supply
with no additional biases and requires only a single
Master Clock for operation upto 13.5MHz. It is housed
in a 48 pin ceramic LCC package.
The MCM20014 is designed taking into consideration
interfacing requirements to standard video encoders. In
addition to the 10 bit bayer encoded data stream, the
sensor outputs the valid frame, line and pixel sync signals needed for encoding. The sensor interfaces with a
variety of commercially available video image processors to allow encoding into various standard video formats .
The MCM20014 is an elegant and extremely flexible
single chip solution that simplifies a system designer’s
tasks of image sensing, processing, digital conversion,
and digital signal processing to a high performance, low
cost, low power IC. One that supports among others a
wide range of low power, portable consumer digital imaging applications.
2.0 MCM20014 Theory of Operation
This section reviews the concepts behind the operation
of the image sensing and capture mechanisms employed in the MCM20014.
2.1 Sensor Interface
2.1.1 Pixel Architecture
The MCM20014 ImageMOSTM (1) sensor comprises a
640x480 active pixel array and supports both progressive and interlaced scan readout modes. The basic operation of the pixel relies on the photoelectric effect
where due to its physical properties silicon is able to detect photons of light. The photons generate electronhole pairs in direct proportion to the intensity and wavelength of the incident illumination. The application of an
appropriate bias allows the user to collect the electrons
and meter the charge in the form of a useful parameter
such as voltage.
The pixel architecture is based on a four transistor (4T)
Advanced CMOS ImagerTM(2) pixel which requires all
pixels in a row to have common Reset, Transfer, and
Row Select controls. In addition all pixels have common
supply (VDD) and ground (VSS) connections. An optimized cell architecture provides enhancements such as
noise reduction, fill factor maximizations, and antiblooming. The use of pinned photodiodes (3) and proprietary transfer gate devices in the photoelements
1. ImageMOS is a Motorola trademark
2. Advanced CMOS Imager is a Kodak trademark
3. Patents held jointly by Motorola and Kodak
MCM20014
enables enhanced sensitivity in the entire visual spectral range and a lag free operation.
The nominal photoresponse of the MCM20014 is shown
in Figure 3.
Figure 3. MCM20014 Nominal spectral response
In addition to the imaging pixels, there are additional
pixels called dark and dummy pixels at the periphery of
the imaging section (see Figure 2). The dark pixels are
covered by a light blocking shield rendering the pixels
underneath insensitive to photons. These pixels provide
the sensor means to measure the dark level offset
which is used downstream in the signal processing
chain to perform auto black level calibration. The dummy pixels are provided at the array’s periphery to eliminate inexact measurements due to light piping into the
dark pixels adjacent to active pixels. The output of these
pixels should be discarded.
Electronic shuttering, also known as electronic exposure timing in photographic terms, is a standard feature.
The pixel integration time can be widely varied from a
small fraction of a given frame readout time to the entire
frame time. This feature can be especially useful in situations such as imaging of fast moving objects where
maximum available integration time is long enough to
cause smear or blurring or when imaging a bright scene
where there are enough photons to cause an early saturation of the pixel.
MCM20014
2.1.2 Color Separation and Fill Factor Enhancement
The MCM20014 family is offered with the option of
monolithic polymer color filter arrays (CFAs). The combination of an extremely planarized process and propriatary color filter technology result in CFAs with superior
spectral and transmission properties. The standard option (Part # MCM20014IBBN) is a primary (RGB) “Bayer” pattern (see Figure 4), however, facility to produce
customized CFAs including complementary (CMYG)
mosaics also exists. Depending on the application, the
choice between primary or complementary filter mosaics should be made. In general, primary mosaics are
used in still video while complementary are used in real
time video applications.
Applications requiring higher sensitivity can benefit from
the optional micro-lens arrays shown in Figure 5. The
lenslet arrays can improve the fill factor (aperture ratio)
of the sensor by 1.5-2x depending on the F number of
the main lens used in the camera system. Microlenses
yield greatest benefits when the main lens has a high F
number. As a caution, unoptimized F numbers can lead
to optical aberrations hence, care should be taken when
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incorporating microlens equipped imagers into camera
systems/heads. The fill factor of the pixels without microlenses is 35%.
G1
R
G1
R
B
G2
B
G2
G1
R
G1
R
B
B B
G2
B
G2
Figure 4. Optional on-chip Bayer CFA
enough to produce a reasonable overlap of the sequential rows. If this is not the case then image artifacts may
be produced in instances where the target is moving
very fast or the illumination is varying.
The second available capture mode is called Single
Frame Capture Mode (SFCM). This mode consists of
global integration of all pixels, next a simultaneous
transfer to the Floating Diffusion (FD) node of all pixels
followed by a sequential read out of all rows. This mode
is best suited for still or “single snap shot” capture of an
image where a flash illumination is utilized.
SFCM should only be used when the ambient lighting
will not cause the pixels to saturate during the readout
time.
The user chooses the scan mode via the Capture Mode
Control Register, (Table 24), on page 31.
2.1.4 Image Scan Modes
The MCM20014 has two available image scanning
modes: interlaced and progressive.
Iris
microlenses
Figure 5. Improvement in pixel sensitivity results
from focusing incident light on photo sensitive portions of the pixel by using microlenses.
2.1.3 Frame Capture Modes
Depending on the application the user may choose between the two available Frame Capture Modes (FCMs).
An overview of the operation of the two modes and suggested guidelines for selection are given in this section.
The default mode of image capture is the Continuous
Frame Capture Mode (CFCM). This mode is most suitable for full motion video capture and will yield VGA
sized frame rates up to 36fps at 13.5 MHz MCLK. In this
mode the image integration and row readout take place
in parallel. While a row of pixels is being read out, another row or rows are being integrated. Since the integration time (Tint ) is equal for all rows, the start of the
integration periods for rows is staggered out. This mode
relies on the integration periods of the rows being long
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Interlacing is a technique used in TV systems that is
used to enhance the vertical resolution of the picture
without increasing the bandwidth of the transmission
system. A spatial offset is introduced on the display system between the odd and even fields. An odd field consists of rows 1,3,5,7,9.... while an even field comprises
rows 2,4,6,8..... Since the spatial offset is exactly half
the vertical pitch of the sensor, the even and odd fields
appear interdigitated when displayed on top of one another, thus appearing to improve the sensor’s vertical
resolution. By definition two interlaced fields comprise a
frame. It should be noted that at high frame rates, motion between fields in interlaced video can cause smear
and/or serrations to appear in the image.
Progressive scanning refers to non-interlaced or sequential row by row scanning of the entire sensor in a
single pass. The image capture happens at one instant
of time. This mode is primarily used in applications
where vertical resolution is of prime importance and
available bandwidth of the transmission system does
not impose any limitations.
The user chooses the scan mode via the Sub-sample
Control Register, (Table 25), on page 32.
2.1.5 Window of Interest Control
The pixel data to be read out of the device is defined as
a ‘Window of Interest’ (WOI). The window of interest
can be defined anywhere on the pixel array at any size.
The user provides the upper-left pixel location and the
size in both rows and columns to define the WOI. The
MCM20014
0
0
vcw[13:0]
0
WOI Pointer (wcp,wrp)
703
0
Window of Interest (WOI)
WOI Pointer (wcp,wrp)
Window of Interest (WOI)
WOI Row Depth (wrd)
ACTIVE PIXEL ARRAY
WOI Row Depth (wrd)
WOI is defined using the WOI Pointer, WOI Depth, and
WOI Width registers, (Table 29 on page 35 through Table 36 on page 37). Please refer to Figure 6 for a pictorial representation of the WOI within the active pixel
array.
WOI Column Width (wcw)
Virtual Frame
vrd[13:0]
Figure 8. Virtual Frame Definition
WOI Column Width (wcw)
511
Figure 6. WOI Definition
2.1.6 WOI Sub-sampling Control
The WOI can be sub-sampled per user control. The
user can read out the pixel data in either monochrome
or bayer pixel space in four different sampling rates in
each direction: full, 1/2, 1/4, or 1/8. The user controls
the subsampling via the Sub-sample Control Register,
(Table 25), on page 32. An example of Bayer space
sub-sampling is shown in Figure 7.
G
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Frame Time = vrdd * Trow + Tfc
for Trow < Tlim
Frame Time = (vrdd + 1) * Trow
for Trow > Tlim
where vrdd defines the number of rows in the virtual
frame. The user controls vrdd via the CFCM Virtual
Frame Row Depth registers (Table 40 on page 39 and
Table 41 on page 40).
Row Time (Trow) is the length of time required to read
one row of the virtual frame and can be defined as:
Trow = (vcwd + shsd + shrd + 19) * MCLKperiod
Sub-sample Control Register =
x01x0101b =
Progressive Scan
Bayer Pattern
Read 1 Pattern, Skip 1 Pattern
in both directions
Figure 7. Bayer Space Sub-sampling Example
2.1.7 CFCM Frame Rate and Integration Time
Control
In addition to the minimum time required to readout the
selected resolution and WOI, the user has the ability to
control the frame rates while operating in CFCM. This is
done by varying the size of a Virtual Frame surrounding
the WOI. Please refer to Figure 8 for a pictorial description of the Virtual Frame and its relationship to the WOI.
MCM20014
The frame rate (time required to readout an entire frame
of data plus the required boundary timing) is completely
defined by the size of the Virtual Frame and can be expressed as:
where vcwd defines the number of columns in the virtual
frame and shsd and shrd are internal timing control registers. The user controls vcwd via the CFCM Virtual
Frame Column Width registers (Table 42 on page 40
and Table 43 on page 41). The user controls the shsd
and shrd values via the Internal Timing Control Register;
Table 28 and is strongly encouraged to write an 00h to
this register.
Tlim is the minimum amount of time required for the internally generated frame clamp signal and is defined as:
Tlim = 719 * MCLKperiod
Tfc is the minimum amount of time required to perform
a frame clamp with timing overhead and is defined as:
Tfc = (719 + shsd + shrd + 19) * MCLKperiod
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The Integration Time for CFCM is defined by a combination of the width of the virtual frame and the integration time register, (Table 38 on page 38 and Table 39 on
page 39); and can be expressed as:
reference level from the signal output. Double sampling
of the signal eliminates correlated noise sources.
CDSP1
S/H1
Integration Time = (cintd + 1) * Trow
V+
Integration Timecintdrows = Tfc + (cintd * Trow)
By using the default values in the Virtual Frame definition and Integration Time registers, an 00h loaded into
the Internal Timing Control Register, and assuming a
standard video square pixel clock rate of 13.5Mhz, we
can calculate the frame rate and integration time as:
Row Time = (749 + 16 + 16 + 19) / 13.5e6 = 59.26µs
Frame Time = (524 + 1) * 59.26µs = 31.11ms which results in a Frame Rate of 32.21 frames per second.
AMP
AVIN
where cintd is the number of virtual frame row times desired for integration time. Therefore, the integration time
in CFCM mode can be adjusted in steps of virtual frame
row times. This equation for Integration Time is valid
only for Trow > Tlim. For virtual frames where Trow < Tlim,
the integration time is different for the first cintd rows
and is defined as:
VCDSP2
S/H2
Figure 9. Conceptual block diagram of CDS
implementation.
2.2.2 Frame Rate Clamp (FRC)
The FRC (Figure 10) is designed to provide a feed forward dark level subtract reference level measurement.
In the automatic FRC mode, the optical black level reference is re-established each time the image sensor
begins a new frame. The MCM20014 uses optical black
(dark) pixels to aid in establishing this reference.
CapLRCA
0.1µf
Integration Time = (524 + 1) * 59.26µs = 31.26ms.
2.1.8 SFCM Integration Time Control
The Integration Time for the SFCM is defined by the integration time register (Table 37 on page 38 through Table 39 on page 39) and can be expressed as:
Integration Time = sintd * 16 * MCLKperiod
where sintd is a number. Therefore, the user can adjust
integration time in steps of 16 MCLK periods.
2.2 Analog Signal Processing Chain Overview
The MCM20014’s analog signal processing (ASP)
chain incorporates Correlated Double Sampling (CDS),
Frame Rate Clamp (FRC), two Digitally Programmable
Gain Amplifiers (DPGA), Offset Correction (DOVA), and
a 10-bit Analog to Digital Converter (ADC).
2.2.1 Correlated Double Sampling (CDS)
The uncertainty associated with the reset action of a capacitive node results in a reset noise which is equal to
kTC; C being the capacitance of the node, T the temperature and k the Boltzmann constant. A common way of
eliminating this noise source in all image sensors is to
use Correlated Double Sampling. The output signal is
sampled twice, once for its reset (reference) level and
once for the actual video signal. These values are sampled and held while a difference amplifier subtracts the
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LRCLMP
LRCLMP
FRC
BUF
+
1X
Previous
Vcm
Stage
+
BUF
-
1X
LRCLMP
CLRCA
Vcm
LRCLMP
+
Diff
Amp
-
V+
VLRCLMP
Vcm
CLRCB
LRCLMP
CapLRCB
0.1µf
Figure 10. FRC Conceptual Block Diagram
On the MCM20014, dark pixel input signals should be
sampled for a minimum of 137µs to allow the two 0.1µF
capacitors at the CLRCA and CLRCB pins sufficient
time to charge for 10-bit accuracy. This guarantees that
the FRC’s “droop” will be maintained at <750 µV, thus
assuring the specified ADC 10-bit accuracy at +0.5
LSB. Therefore, at maximum operational frequency
(13.5 MHz), the imager would require 6 frames to establish the dark pixel reference for subsequent active pixel
processing. The dark pixel sample period is automatically controlled internally and it is set to skip the first 2
dark rows and then sample the next dark row. When
MCM20014
“dark clamping” is active, each dark pixel is processed
and held to establish pixel reference level at the CLRCA
and CLRCB pins. During this period, the FRC’s differential outputs (V+ and V- on the Diff Amp, Figure 10) are
clamped to Vcm. Together, these actions help to eliminate the dark level offset, simultaneously establishing
the desired zero code at the ADC output.
Care should be exercised in choosing the capacitors for
the CLRCA, B pins to reflect different frame rates.
The user can disable this function via the Capture Mode
Control Register, (Table 24), on page 31 which will allow the ASP chain to drift in offsetPer-Column Digital
Offset Voltage Adjust (DOVA)
A programmable per-column offset adjustment is available on the MCM20014. A user defined offset value can
be loaded via a 4-bit signed magnitude programming
code. This programmable DOVA allows the user to select offset coefficients for FPN & PRNU corrections and
channel offset normalization, and is used to correct for
column induced errors. In the default mode, data is automatically loaded into an onchip RAM that stores 704,
4 bit words representing offset coefficients for each individual column in the imaging array. Figure 11 depicts
a conceptual view of how the automatic generation of
the per-column offsets is accomplished.
Reference
AutoCal Math
Column Offset
Caliberation RAM (704 x 4)
4
DOVA 2.0x
ADC
Figure 11. Conceptual illustration of the auto caliberation scheme for offset adjustment
The user can generate and load data for this function as
well. A dark frame can be analyzed to determine the appropriate values to be loaded into the Per-Column
DOVA RAM (Column DOVA RAM, (Table 19), on page
27).
When the per-column feature is not used or necessary,
the user loads a 5-bit value into the Column DOVA DC
Register, (Table 17), on page 26 to perform a global offset adjust prior to the gain stages of the ASP.
MCM20014
2.2.3 Digitally Programmable Gain Amplifiers
(DPGA)
Two DPGAs are available in the analog signal processing chain. These are used to perform white balance and
exposure gain functions. Both are linearly programmable via 6-bit registers.
2.2.3.1 White Balance Control PGA
The sensor produces three primary color outputs, Red,
Green and Blue. These are monochrome signals that
represent luminance values in each of the primary colors. When added in equal amounts they mix to make
neutral color. White balancing is a technique where the
gain coefficients of the green(0), red, blue, and green(3)
pixels comprising the Bayer pattern (see Figure 12.) are
set so as to equalize their outputs for neutral color
scenes. Since the sensitivity of the two green pixels in
the Bayer pattern may not be equal, an individual color
gain register is provided for each component of the Bayer pattern.
Once all color gain registers are loaded with the desired
gain coefficients, white balance is achieved in real time
and in analog space. The appropriate values are selected and applied to the pixel output via a high speed path,
the delay of which is much shorter than the pixel clock
rate. Real time updates can be performed to any of the
gain registers. However, latency associated with the I2C
interface should be taken into consideration before
changes occur. In most applications, users will be able
to assign predefined settings such as daylight, fluorescent, tungsten, and halogen to cover a wide gamut of illumination conditions.
Both DPGA designs use switched capacitors to minimize accumulated offset and improve measurement accuracy and dynamic range. The white balance gain
registers are 6-bits and can be programmed to allow
gain of 0.9x to 4.6x in steps of 0.06x.
The user programs the individual gain coefficients into
the MCM20014 via the Color Gain Registers (Table 3
through Table 6). For the default Bayer configuration of
the color filter array; Figure 4, the Color Gain Register
addresses are as follows: Reg (00h): green pixel of a
green-red row; Reg (01h): red pixel; Reg (02h): blue pixel; and Reg (03h): green pixel of a blue-green row.
The MCM20014 is presently available with only a Bayer
CFA, however, it is designed to support other novel color configurations. This is accomplished via the Color
Tile Configuration Register, (Table 7), on page 20 and
the Color Tile Row Definition registers (Table 8 through
Table 11).
MOTOROLA
9
Green (0)
Red (1)
Blue (2)
Green (3)
6
6
6
6
DPGA
0.9x-4.6x
6
G(0)
R(1)
B(2)
G(3)
Figure 12. Color Gain Register Selection
2.2.3.2 Global Gain PGA
The global gain DPGA provides a 1.0x to 8.0x programmable gain adjustment for dynamic range. The gain of
the amplifier is linearly programmable using a six bit
gain coefficient in steps of 0.12x. The user programs the
global gain via the DPGA Global Gain Register, (Table
16), on page 25.
2.2.4 Global Digital Offset Voltage Adjust (DOVA)
A programmable global offset adjustment is available
on the MCM20014. A user defined offset value is loaded
via a 6-bit signed magnitude programming code via the
Global DOVA Register, (Table 20), on page 28.
Offset correction allows fine-tuning of the signal to remove any additional residual error which may have accumulated in the analog signal path. This function is
performed directly before analog to digital conversion
and introduces a fixed gain of 2.0X. This feature is useful in applications that need to insert a desired offset to
adjust for a known system noise floor relative to AVSS
and offsets of amplifiers in the analog chain.
2.2.5 Analog to Digital Converter (ADC)
The ADC is a fully differential, low power circuit. A pipelined, Redundant Signed Digit (RSD) algorithmic technique is used to yield an ADC with superior
characteristics for imaging applications.
Integral Noise Linearity (INL) and Differential Noise Linearity (DNL) performance is specified at +1.0 and +0.5,
respectively, with no missing codes. The input voltage
resolution is 2.44 mV with a full-scale 2.5 Vpp input (2.5
Vpp/210). The input dynamic range of the ADC is programmed via a Programmable Voltage Reference Generator. The positive reference voltage (VREFP) and
negative reference voltages (VREFM) can be programmed from 2.5V to 1.25V and 0V to 1.25V respec-
MOTOROLA
10
tively in steps of 5mV via the Reference Voltage
Registers (Table 12 and Table 13). This feature is used
independently or in conjunction with the DPGAs to maximize the system dynamic range based on incident illumination. The default input range for the ADC is 1.9V for
VREFP and 0.6V for VREFM hence allowing a 10 bit
digitization of a 1.3V peak to peak signal.
2.3 Digital Signal Post Processing
The post ADC functions provide means for manipulating
the 10-bit imager data. These functions are replacing
bad pixels and output signal companding.
2.3.1 Bad Pixel Replacement
This block conditionally monitors and replaces any defective pixels on the imager. The user sets threshold
values for extreme black and extreme white to detect
bad pixels and independently enables/disables one or
both detections. Threshold values are input via the
White and Black Pixel Threshold Registers (Table 21
and Table 22 respectively) while the functions themselves are enabled via the Post ADC Control Register,
(Table 23), on page 29.
The black threshold input sets the 8 LSBs of the minimum detection level. The 2 MSBs are hard coded to 00
hence giving a range of 0-255 for setting the black
threshold levels. Any pixel value below the predefined
black threshold level is replaced. Similarly the white
threshold input sets the 8 LSBs of the maximum detection level. The 2 MSBs are hard coded to 11 allowing a
range white threshold level settings between 768 and
1023 code levels. Any pixels value above the definedwhite threshold level is replaced. The replacement value in either case is determined automatically by the
control bus. Based on the location of the pixel, a decision to replace the pixel value by the same color average, leading or trailing pixel value is made.
2.3.2 Data Compander
The Data Compander allows coring of the lower order
bits. In effect, it expands the values of lower signal levels and compresses high light scenes thereby allowing
for on-chip contrast adjustments. The companding
function performs an 8-bit transformation on the in-coming 10-bit data stream. The output is made available on
the upper 8 MSBs of the 10 bit output bus. The user can
select one of the 8 transformation curves shown in Figure 13 via the Post ADC Control Register, (Table 23),
on page 29. The bottom curve is linear in which the input
is divided by four. For other choices, the I/O relationship
is kept 1:1 up to a certain breakpoint. There onwards a
straight line equation is used to transform the remaining
input values.
MCM20014
The default is the linear curve, breakpoints can be selected via the slope and breakpoint control bits on the
Post ADC Control Register. This function can be bypassed to output 10-bit linear data.
Data OUT (8-bit)
255
Reg 32h = 8Fh
127
111
95
79
Reg 32h = 8Bh
63
47
31
15
0
0
63
127
191
255
511
Data IN (10-bit)
1023
Figure 13. Available Companding Curves
2.4 Additional Operational Conditions
The MCM20014 includes initialization, standby modes,
and external reference voltage outputs to afford the
user additional applications flexibility.
2.4.1 Initialization
The INIT input pin (#28) controls reinitialization of the
MCM20014. This serves to assure controlled chip and
system startup. Control is asserted via a logic high input. This state must be held a minimum of 1 ms and a 1
ms “wait period” should be allowed before chip processing to ensure that the start-up routines within the
MCM20014 have run to completion, and to guarantee
that all holding and bypass capacitors, etc. have
achieved their required steady state values.
Tasks which are accomplished during startup include:
reset of the utility programming registers and initialization to their default values (please refer to previous sec-
MCM20014
tion for settings), reset of all internal counters and
latches, and setup of the analog signal processing
chain.
2.4.2 Standby Mode
The standby mode option is implemented to allow the
user to reduce system power consumption during periods which do not require operation of the MCM20014.
This feature allows the user to extend battery life in low
power applications.
By utilizing this mode, the user may reduce dynamic
power consumption from 400mW, in the active processing, 13 Million Samples per Second mode, to <50 mW
in the standby mode (note that dynamic power consumption is also reduced in slower conversion speed
applications).
MOTOROLA
11
The standby mode is activated by applying an active
high signal to the STBY pin (#27). The sensor can also
be put in the stand by mode via bit <0> on the Power
Configuration Register (OCh)
The user may also reduce power consumption in the active processing mode by placing the MCM20014’s outputs in the tri-state mode. This action may be
accomplished by placing the TS pin in the active high
state. This action can also accomplished by setting the
dbt bit on the Power Configuration Register; Table 14,
(0Ch).
2.4.3 References CVREFP, CVREFM
The MCM20014 contains all internally generated references and biases on-chip for system simplification. An
internally generated differential bandgap regulator derives all the ADC and other analog signal processing required references. The user should connect 0.1µF
capacitors to the CVREFP and CVREFM pins (#19 and
#18 respectively) to accurately hold the biases.
2.4.4 Internal Timing Control Register
The Internal Timing Control Register; Table 28 allows
control over pulse widths of critical internal timing signals. The user must write an 00h into this address location to assure proper operation of the MCM20014.
2.4.5 Internal Bias Current Control
The ASP chain has internally generated bias currents
that result in an operating power consumption of nearly
400mW. By attaching a resistor between pin 13, EXTRES; and ground, the user can reduce the power consumption of the device. This feature is enabled by
writing a 1b to bit res of the Power Configuration Register. Figure 14 depicts the power savings that can be
achieved with an external resistor at a specific clock
rate. Additional power savings can be acheived at lower
clock rates.
Average Power Consumption (mW)
600
500
Internal Resistor Power Consumption
400
300
200
100
10
20
30
40
External Resistor (kΩ)
50
60
Figure 14. External Resistor Effect on Power Consumption at 13.5Mhz MCLK
3.0 MCM20014 Waveform Diagrams
The following set of diagrams depict the input/output
waveform relationships for the pixel data.
3.1 CFCM Data Waveforms
The following set of waveforms depict the CFCM output
data stream from a complete frame down to individual
signal relationships. Figure 15 depicts a complete frame
MOTOROLA
12
of a CFCM output data stream in default mode. Figure
16 depicts the first row of data in the frame.
Figure 17 and Figure 18 depict the same CFCM waveforms with the Internal Timing Control Register loaded
with an 00h.
MCM20014
Figure 19 depicts a single frame output using CFCM.
This is created by setting the cms bit of the Capture
Mode Control Register, (Table 24), on page 31 to1b.
Figure 20 depicts the CFCM in interlaced output mode.
This is created by setting the sm bit of the Sub-sample
Control Register, (Table 25), on page 32 to1b.
Frame Time = 525 row times
Row Time = 780 MCLKs
WOI = 640 Columns x 480 Rows
starting at row 12, column 48
SOF
VCLK
HCLK
row 490
row 491
row 490
row 491
row 489
row 15
row 14
row 13
row 12
row 491
row 490
row 489
row 15
row 14
row 13
row 12
BLANK
Figure 15. CFCM Default Frame Waveform
105
106
14
15
1
2
3
1
2
3
31
32
1
2
3
4
5
6
7
8
1
2
3
MCLK
SOF
Row Time = vcwd + 31
VCLK
row 12
row 13
col. 48
col. 49
col. 50
col. 686
col. 687
HCLK
Pixel Array Values
BLANK
ADC[9:0]
Valid Pixel Data
Figure 16. CFCM Default Line Waveform
Frame Time = 525 row times
Row Time = 800 MCLKs
WOI = 640 Columns x 480 Rows
starting at row 12, column 48
SOF
VCLK
HCLK
row 489
row 15
row 14
row 13
row 12
row 491
row 490
row 489
row 15
row 14
row 13
row 12
BLANK
Figure 17. CFCM Frame Waveform with Internal Timing Control Register = 00h
MCM20014
MOTOROLA
13
MCLK
SOF
VCLK
Row Time = vcwd + shsd + shrd + 19
= 749 + 16 + 16 + 19 = 800 MCLK’s
row 12
row 13
Tx
col. 48
col. 49
col. 50
Tx = 21 + shrd + shsd
= 21 + 16 + 16
= 53 MCLK’s
col. 686
col. 687
HCLK
BLANK
ADC[9:0]
Valid Pixel Data
Figure 18. CFCM Line Waveform with Internal Timing Control Register = 00h
SYNC
T = (cintd + 1) * Row Time
SOF
VCLK
Standard Frame
Timing (Figure 18)
row 491
row 489
row 15
row 14
row 13
row 12
BLANK
row 490
HCLK
Figure 19. CFCM Single Frame Mode Waveform
Odd Field Marker
Pulse Width = 4 * MCLKperiod
Positioned at mid-point of
final Row Time of Field Blanking
Field Blanking
For even vrdd: blank time = vrdd/2 * Row Time
For odd vrdd: blank time = (vrdd + 1)/2 * Row Time
Frame Blanking
For even vrdd: blank time = vrdd/2 * Row Time
For odd vrdd: blank time = (vrdd - 1)/2 * Row Time
SOF
VCLK
HCLK
row 14
row 12
row 491
row 489
row 487
row 19
row 17
row 15
row 13
row 490
row 488
row 486
row 18
row 16
row 14
row 12
BLANK
Figure 20. CFCM Interlaced Scan Mode Waveform
MOTOROLA
14
MCM20014
of a SFCM output data stream in default mode. Figure
22 depicts the first row of data in the frame.
3.2 SFCM Data Waveforms
The following set of wave forms depict the SFCM output
data stream from a complete frame down to individual
signal relationships. Figure 21 depicts a complete frame
Figure 23 and Figure 24 depict the same SFCM waveforms with the Internal Timing Control Register loaded
with an 00h.
Frame Time = 525 row times
Row Time = 780 MCLKs
WOI = 640 Columns x 480 Rows
starting at row 12, column 48
SYNC
SOF
VCLK
row 491
row 489
row 15
row 14
row 13
row 12
BLANK
row 490
HCLK
Figure 21. SFCM Default Frame Waveform
T = (16 * sintd) + 771
for vcwd < 719
T = (16 * sintd) + vcwd + 52
for vcwd > 718
SYNC
105
106
14
15
1
2
3
1
2
3
25
26
1
2
3
4
5
6
7
8
1
2
3
T
1
2
3
1
2
3
MCLK
SOF
VCLK
Row Time = vcwd + 31
row 12
row 13
col. 48
col. 49
col. 50
Pixel Array Values
col. 686
col. 687
HCLK
BLANK
ADC[9:0]
Valid Pixel Data
Figure 22. SFCM Default Line Waveform
MCM20014
MOTOROLA
15
Frame Time = 525 row times
Row Time = 780 MCLKs
WOI = 640 Columns x 480 Rows
starting at row 12, column 48
SYNC
SOF
VCLK
row 491
row 489
row 15
row 14
row 13
row 12
BLANK
row 490
HCLK
Figure 23. SFCM Frame Waveform with Internal Timing Control Register = 00h
T = (16 * sintd) + 771
for vcwd < 719
T = (16 * sintd) + vcwd + 52
for vcwd > 718
SYNC
MCLK
T
SOF
Row Time = vcwd + shrd + shsd+ 19
= 749 + 16 + 16 + 19 = 800 MCLK’s
VCLK
row 12
row 13
Ty
col. 48
col. 49
col. 50
Ty = 14 + shrd + shsd
= 14 + 16 + 16
= 46 MCLK’s
col. 686
col. 687
HCLK
BLANK
ADC[9:0]
Valid Pixel Data
Figure 24. SFCM Line Waveform with Internal Timing Control Register = 00h
4.0 MCM20014 Utility Programming Registers
4.1 Register Reference Map
The I2C addressing is broken up into groups of 16 and
assigned to a specific digital block. The designated
block is responsible for driving the internal control bus,
when the assigned range of addresses are present on
the internal address bus. The grouping designation and
assigned range are listed in Table 1. Each block contains registers which are loaded and read by the digital
and analog blocks to provide configuration control via
the I2C serial interface.
Table 2 contains all the I2C address assignments. The
table includes a column indicating whether the register
values are shadowed with respect to the sensor interMOTOROLA
16
Address Range
Block Name
00h - 0Fh
Analog Register Interface
10h - 1Fh
Global Gain
20h - 2Fh
Offset Calibration
30h - 3Fh
Post ADC
40h - 60h
Sensor Interface
61h - FFh
Factory Use
Table 1. I2C Address Range Assignments
MCM20014
face. If the register is shadowed, the sensor interface
will only be updated upon frame boundaries, thereby
Hex
Address
eliminating intraframe artifacts resulting from register
changes.
Register Function
Defa
ult
Ref.
Table
Shadow
ed?
00h
DPGA Color 1 Gain Register (Green of Green-Red
Row)
02h
Table 3, page 19
Yes
01h
DPGA Color 2 Gain Register (Red)
02h
Table 4, page 19
Yes
02h
DPGA Color 3 Gain Register (Blue)
02h
Table 5, page 20
Yes
03h
DPGA Color 4 Gain Register (Green of Blue-Green
Row)
02h
Table 6, page 20
Yes
Unused
04h
05h
Color Tile Configuration Register
05h
Table 7, page 20
No
06h
Color Tile Row 1 Definition Register
44h
Table 8, page 21
No
07h
Color Tile Row 2 Definition Register
EEh
Table 9, page 22
No
08h
Color Tile Row 3 Definition Register
00h
Table 10, page 22
No
09h
Color Tile Row 4 Definition Register
00h
Table 11, page 23
No
0Ah
Negative Voltage Reference Code Register
76h
Table 12, page 23
No
0Bh
Positive Voltage Reference Code Register
80h
Table 13, page 24
No
0Ch
Power Configuration Register
00h
Table 14, page 24
No
Table 15, page 25
No
0Dh
Factory Use Only (set to 00h)
00h
0Eh
Reset Control Register
00h
0Fh
Device Identification (read only)
23h
10h
DPGA Global Gain Register
00h
Table 16, page 25
Yes
11h - 1Fh
No
Unused
20h
Column DOVA DC Register
00h
Table 17, page 26
Yes
21h
Column DOVA Control Register
00h
Table 18, page 27
No
22h
Column DOVA RAM
00h
Table 19, page 27
No
23h
Global DOVA Register
00h
Table 20, page 28
Yes
FEh
Table 21, page 29
No
24 - 2Fh
30h
Unused
White Pixel Threshold Register
Table 2. I2C Address Assignments
MCM20014
MOTOROLA
17
Hex
Address
Register Function
Defa
ult
Ref.
Table
Shadow
ed?
31h
Black Pixel Threshold Register
01h
Table 22, page 29
No
32h
Post ADC Control Register
30h
Table 23, page 29
No
33h - 3Fh
Unused
40h
Capture Mode Control Register
35h
Table 24, page 31
Yes
41h
Sub-sample Control Register
00h
Table 25, page 32
Yes
42h - 44h
Unused
45h
WOI Row Pointer MSB Register
00h
Table 29, page 35
Yes
46h
WOI Row Pointer LSB Register
0Ch
Table 30, page 35
Yes
47h
WOI Row Depth MSB Register
01h
Table 33, page 36
Yes
48h
WOI Row Depth LSB Register
DFh
Table 34, page 36
Yes
49h
WOI Column Pointer MSB Register
00h
Table 31, page 35
Yes
4Ah
WOI Column Pointer LSB Register
30h
Table 32, page 36
Yes
4Bh
WOI Column Width MSB Register
02h
Table 35, page 37
Yes
4Ch
WOI Column Width LSB Register
7Fh
Table 36, page 37
Yes
4Dh
Integration Time MSB Register
00h
Table 37, page 38
Yes
4Eh
Integration Time ISB Register
02h
Table 38, page 38
Yes
4Fh
Integration Time LSB Register
0Ch
Table 39, page 39
Yes
50h
CFCM Virtual Frame Row Depth MSB Register
02h
Table 40, page 39
Yes
51h
CFCM Virtual Frame Row Depth LSB Register
0Ch
Table 41, page 40
Yes
52h
CFCM Virtual Frame Column Width MSB Register
02h
Table 42, page 40
Yes
53h
CFCM Virtual Frame Column Width LSB Register
EDh
Table 43, page 41
Yes
54h
SOF Control Register
C0h
Table 26, page 33
No
55h
VCLK Control Register
90h
Table 27, page 33
No
66h
Table 28, page 34
Yes
56h - 5Fh
60h
Unused
Internal Timing Control Register
61h - 64h
Factory Use Only
65h - FFh
Unused
Table 2. I2C Address Assignments (Continued)
MOTOROLA
18
MCM20014
5.0 Detailed Register Block Assignments
This section describes in further detail the functional operation of the various MCM20014 programmable registers. The registers are subdivided into various blocks for
ease of addressability and use (see Table 1).
In each table where a suffix code is used; h = hex, b =
binary, and d = decimal.
5.1 Analog Register Interface Block
The address range for this block is 00h to 0Fh.
Address
00h
5.1.1 Analog Color Configuration
The four Color Gain Registers, Color Tile Configuration
Register, and four Color Tile Row definitions define how
white balance is achieved on the device. Six-bit gain
codes can be selected for four separate colors: Table 3,
Table 4, Table 5, and Table 6. Gain for each individual
color register is programmable given the gain function
defined in the table. The user programs these registers
to account for changing light conditions to assure a
white balanced output. The default value in each register is provides for a unity gain. In addition, the default
CFA pattern color is listed in the title of each register.
Default
02h
DPGA Color 1 Gain Code
Green of Green-Red Row
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
cg1[5]
cg1[4]
cg1[3]
cg1[2]
cg1[1]
cg1[0]
Bit
Number
Function
7-6
Unused
5-0
Gain
Description
Reset
State
Unused
xx
Gain = 0.88 + (0.06 * cg1d)
000010b
Table 3. DPGA Color 1 Gain Register
Address
01h
Default
02h
DPGA Color 2 Gain Code
Red
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
cg2[5]
cg2[4]
cg2[3]
cg2[2]
cg2[1]
cg2[0]
Bit
Number
Function
7-6
Unused
5-0
Gain
Description
Unused
Gain = 0.88 + (0.06 * cg2d)
Reset
State
xx
000010b
Table 4. DPGA Color 2 Gain Register
MCM20014
MOTOROLA
19
Address
02h
Default
02h
DPGA Color 3 Gain Code
Blue
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
cg3[5]
cg3[4]
cg3[3]
cg3[2]
cg3[1]
cg3[0]
Bit
Number
Function
7-6
Unused
5-0
Gain
Description
Reset
State
Unused
xx
Gain = 0.88 + (0.06 * cg3d)
000010b
Table 5. DPGA Color 3 Gain Register
Address
03h
Default
02h
DPGA Color 4 Gain Code
Green of Blue-Green Row
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
cg4[5]
cg4[4]
cg4[3]
cg4[2]
cg4[1]
cg4[0]
Bit
Number
Function
7-6
Unused
5-0
Gain
Description
Reset
State
Unused
xx
Gain = 0.88 + (0.06 * cg4d)
000010b
Table 6. DPGA Color 4 Gain Register
The Color Tile Configuration Register; Table 7, defines
the maximum number of lines and the maximum number of colors per line. A maximum of four row and four
column definitions are permitted. The Color Tile Configuration Register defaults to two lines and two colors per
Address
05h
line. The user should leave this register in default unless
a unique CFA option has been ordered.
This register can be configured to any pattern combination of 1, 2, or 4 rows and 1, 2, or 4 columns.
Default
05h
Color Tile Configuration
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
x
x
nc[1]
nc[0]
nr[1]
nr[0]
Bit
Number
Function
7-4
Unused
Description
Unused
Reset
State
xxxx
Table 7. Color Tile Configuration Register
MOTOROLA
20
MCM20014
Address
05h
Default
05h
Color Tile Configuration
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
x
x
nc[1]
nc[0]
nr[1]
nr[0]
3-2
Columns
1-0
Rows
00b = 1 Column in tile.
01b = 2 Columns in tile.
1xb = 4 Columns in tile.
01b
00b = 1 Row in tile.
01b = 2 Rows in tile.
1xb = 4 Rows in tile.
01b
Table 7. Color Tile Configuration Register
leave these registers in default unless a unique CFA option has been ordered.
The Color Tile Row Definition registers; Table 8, Table
9, Table 10, and Table 11 define the sequence of colors
for each respective line. Each byte wide line definition
allows a maximum of four unique color definitions using
2 bits per color in a given line. Gain programming for
each color was described earlier in this section. The default line definitions are colors 00b, 01b, 00b, 01b for row
1 and 10b, 11b, 10b, 11b for row 2 which supports a Bayer pattern as defined in section 2.1.2. The user should
Address
06h
For the default Bayer configuration of the color filter array; Figure 4, the Color Gain Register addresses are as
follows: Reg (00h): green pixel of a green-red row; Reg
(01h): red pixel; Reg (02h): blue pixel; and Reg (03h):
green pixel of a blue-green row. The predefined gain
values programmed in the respective registers are applied to pixel outputs as they are being read.
Default
44h
Color Tile Row 1 Definition
Green - Red Row
msb (7)
6
5
4
3
2
1
lsb (0)
r1c4[1]
r1c4[0]
r1c3[1]
r1c3[0]
r1c2[1]
r1c2[0]
r1c1[1]
r1c1[0]
Bit
Number
Function
7-6
Color 4
Fourth Color in Row 1(Red)
01b
5-4
Color 3
Third Color in Row 1 (Green)
00b
3-2
Color 2
Second Color in Row 1 (Red)
01b
1-0
Color 1
First Color in Row 1 (Green)
00b
Description
Reset
State
Table 8. Color Tile Row 1 Definition Register
MCM20014
MOTOROLA
21
Address
07h
Default
EEh
Color Tile Row 2 Definition
Blue - Green Row
msb (7)
6
5
4
3
2
1
lsb (0)
r2c4[1]
r2c4[0]
r2c3[1]
r2c3[0]
r2c2[1]
r2c2[0]
r2c1[1]
r2c1[0]
Bit
Number
Function
7-6
Color 4
Fourth Color in Row 2 (Green)
11b
5-4
Color 3
Third Color in Row 2 (Blue)
10b
3-2
Color 2
Second Color in Row 2 (Green)
11b
1-0
Color 1
First Color in Row 2 (Blue)
10b
Description
Reset
State
Table 9. Color Tile Row 2 Definition Register
Address
08h
Default
00h
Color Tile Row 3 Definition
Unused
msb (7)
6
5
4
3
2
1
lsb (0)
r3c4[1]
r3c4[0]
r3c3[1]
r3c3[0]
r3c2[1]
r3c2[0]
r3c1[1]
r3c1[0]
Bit
Number
Function
7-6
Color 4
Fourth Color in Row 3
00b
5-4
Color 3
Third Color in Row 3
00b
3-2
Color 2
Second Color in Row 3
00b
1-0
Color 1
First Color in Row 3
00b
Description
Reset
State
Table 10. Color Tile Row 3 Definition Register
MOTOROLA
22
MCM20014
Address
09h
Default
00h
Color Tile Row 4 Definition
Unused
msb (7)
6
5
4
3
2
1
lsb (0)
r4c4[1]
r4c4[0]
r4c3[1]
r4c3[0]
r4c2[1]
r4c2[0]
r4c1[1]
r4c1[0]
Bit
Number
Function
7-6
Color 4
Fourth Color in Row 4
00b
5-4
Color 3
Third Color in Row 4
00b
3-2
Color 2
Second Color in Row 4
00b
1-0
Color 1
First Color in Row 4
00b
Description
Reset
State
Table 11. Color Tile Row 4 Definition Register
5.1.2 Reference Voltage Adjust Registers
The analog register block allows programming the input
voltage range of the analog to digital converter to match
the saturation voltage of the pixel array. The voltage reference generator can be programmed via two registers;
nrv (0 to 1.25V) Table 12, prv (2.5V to 1.25V) Table 13,
in 5mV steps. A 00h value in the prv register represents
Address
0Ah
a reference output voltage of 2.5V. A 00h value in the
nrv register represents output voltage of 0V. The default settings for the two registers produce a 1.9V reference on prv and 0.6V on nrv outputs. When adjusting
these values, the user should keep the voltage range
centered around 1.25V.
Default
76h
Voltage Reference “Negative” Code
msb (7)
6
5
4
3
2
1
lsb (0)
nrv[7]
nrv[6]
nrv[5]
nrv[4]
nrv[3]
nrv[2]
nrv[1]
nrv[0]
Bit
Number
Function
7-0
Reference
Description
Voltage = 0.0 + (5mV * nrcd)
Reset
State
01110110b
(0.6V)
Table 12. Negative Voltage Reference Code Register
MCM20014
MOTOROLA
23
Address
0Bh
Default
80h
Voltage Reference “Positive” Code
msb (7)
6
5
4
3
2
1
lsb (0)
prv[7]
prv[6]
prv[5]
prv[4]
prv[3]
prv[2]
prv[1]
prv[0]
Bit
Number
Function
7-0
Reference
Description
Reset
State
Voltage = 2.5 - (5mV * prvd)
10000000b
(1.9V)
Table 13. Positive Voltage Reference Code Register
5.1.3 Analog Control Registers
The Analog Register Block also contains a Power Configuration Register; Table 14, and a Reset Control Register; Table 15.
The Power Configuration Register controls the internal
analog functionality that directly effect power consumption of the device. An external precision resistor pin is
available on the MCM20014 that may be used to more
accurately regulate the internal current sources. This
serves to minimize variations in power consumption that
are caused by variations in internal resistor values as
well as offer a method to reduce the power consumption
of the device. The default for this control uses the interAddress
0Ch
nally provided resistor which is nominally 12.5kΩ. This
feature is enabled by setting the res bit of the Power
Configuration Register and placing a resistor between
the pin; EXTRES, and ground. Figure 14 depicts the
power savings that can be achieved with an external resistor at a specific clock rate. Power is further reduced
at lower clock rates.
The databus output; ADC[9:0], is tristated using the
Power Configuration Register by setting the dbt bit.
The MCM20014 is put into a standby mode via the I2C
interface by setting the sby bit of the Power Configuration Register.
Default
00h
Power Configuration
msb (7)
6
5
4
3
2
1
lsb (0)
x
res
fuo
fuo
fuo
fuo
dbt
sby
Bit
Number
Function
7
Unused
Unused
x
6
Int/Ext
Resistor
0b = Internal Resistor
1b = External Resistor
0b
5-2
FUO
1
Tristate
Enable
0
Software
Standby
Description
Factory Use Only
Reset
State
0000b
0b = Output Data Bus enabled
1b = Output Data Bus in Tristate
0b
0b = Soft Standby inactive
1b = Soft Standby active
0b
Table 14. Power Configuration Register
MOTOROLA
24
MCM20014
Additional control of the MCM20014 can be had using
the Reset Control Register; Reset Control Register; Table 15. Setting the clt bit of this register will tristate the
sync signals SOF, VLCK, and HCLK.
Setting the ssr bit of this register will reset all the nonuser programmable registers to a known reset state.
This is useful in situations when control of the
MCM20014 has been lost due to system interrupts and
Address
0Eh
the device needs only to be restarted using the earlier
user programmed values.
Setting the sit bit allows the user to completely reset the
MCM20014 to the default state via the serial control interface.
For both reset bits, ssr and sit, the user must return
those bits to 0 to enable continued operation.
Default
00h
Reset Control
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
x
x
x
clt
ssr
sit
Bit
Number
Function
7-3
Unused
Unused
2
Tristate
0b = SOF, VCLK, and HCLK Output Enabled
1b = SOF, VCLK, and HCLK Output in Tristate
0b
1
State
Reset
0b = Normal Mode
1b = Reset all non-programmable registers to the default state
0b
0
Soft Reset
0b = Normal Mode
1b = Reset all registers to default state
0b
Description
Reset
State
xxxxx
Table 15. Reset Control Register
5.2 Gain Caliberation Block
The DPGA Global Gain Register; Table 16, allows the
user to set a global gain via a 6 bit register this is applied
universally to all the pixel outputs. This enables the user
Address
10h
to account for varying light conditions using a gain
range of 1x to 8x in steps of 0.12x. The default value for
this register results in unity gain.
Default
00h
Global Gain
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
gg[5]
gg[4]
gg[3]
gg[2]
gg[1]
gg[0]
Bit
Number
Function
7-6
Unused
5-0
Gain
Description
Unused
Gain = 1 + (0.12 * ggd)
Reset
State
xx
000000b
Table 16. DPGA Global Gain Register
MCM20014
MOTOROLA
25
5.3 Offset Calibration Block
Offset adjustments for the MCM20014 are done in separate sections of the ASP to facilitate FPN removal and
final image black level set.
The Column DOVA DC Register; Table 17, is used to
set the initial offset of the pixel output in a range that will
facilitate per-column offset data generation for varying
Address
20h
operational conditions. In most operational scenarios,
this register can be left in its default state of 00h.
This register can also be used to apply a global offset
adjust. In this case, the user must take into account the
Color Gain and Global Gain registers to determine the
resulting offset at the output.
Default
00h
Column DOVA DC
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
cdd[5]
cdd[4]
cdd[3]
cdd[2]
cdd[1]
cdd[0]
Bit
Number
Function
7-6
Unused
5
Sign
4-0
Column
DC Offset
Description
Reset
State
Unused
xx
0b = Positive Offset
1b = Negative Offset
0b
Offset = 2 * cddd
00000b
Table 17. Column DOVA DC Register
The Column DOVA Control Register; Table 18, is used
to control the Column DOVA functionality and operational modes.
using their own algorithm and load this data via the I2C
bus as defined in this section.
Setting bit ece enables the per-column DOVA to be
used and the per-column offset values loaded into the
DOVA RAM will be applied to the pixel output. The global DOVA adjust circuit is enabled by default.
Setting the cntr bit resets the internal counter used to
repetitively load the RAM with user defined data. This is
used in cases where the system controller loses control
of the I2C bus while writing to the Column DOVA RAM.
Setting the cal bit configures the Column DOVA RAM
using internally generated offset data. When the
MCM20014 is first initiated, it will automatically generate and load the Column DOVA RAM with the appropriate data. However, if operational conditions such as
temperature or operating frequency change, the user
can use the cal bit to re-determine the appropriate column data.
The automatic calibration data is calculated using the
average differential offset across four dark rows. This
feature does not create the most effective data for reducing the column oriented fixed pattern noise of the
device. The user can calculate the column offset data
MOTOROLA
26
MCM20014
Address
21h
Default
00h
Column DOVA Control
msb (7)
6
5
4
3
2
1
lsb (0)
fuo
fuo
fuo
ece
fuo
fuo
cntr
cal
Bit
Number
Function
7-5
FUO
4
Column
DOVA
Enable
3-2
FUO
1
Counter
Reset
0
Calibration
Description
Reset
State
Factory Use Only
000b
1b = Column DOVA enabled (Register 22h)
0b = Global DOVA enabled (Register 20h)
0b
Factory Use Only
00b
0b = Counter Reset inactive
1b = Counter Reset active
0b
0b = Self Calibration disabled
1b = Self Calibration enabled
0b
Table 18. Column DOVA Control Register
The Column DOVA RAM; Table 19, is a 704 by 4-bit
vector that contains the per-column offset adjustment
used to eliminate column based offset FPN. This RAM
is automatically loaded with internally generated data
upon initialization and can be automatically reloaded as
defined earlier in this section.
The user can generate the DOVA RAM contents and
then load them into the RAM by performing a repetitive
write cycle to the same I2C address. An internal counter
will step the internal RAM address automatically from
Address
22h
column 0 to column 703 where column 0 is defined as
the left-most column of the pixel array. The user should
set and reset the cntr bit of the Column DOVA Control
Register, prior to loading the Column DOVA RAM to assure proper addressing.
When the user is calculating values to be loaded into
the DOVA RAM, the fixed gain of 2x in the ASP after
the Column DOVA circuit must be taken into account.
Therefore, each code value in the DOVA RAM represents 2 code values in the 10-bit ADC output.
Default
00h
Column DOVA RAM
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
x
x
cor[3]
cor[2]
cor[1]
cor[0]
Bit
Number
Function
7-4
Unused
3
Sign
Description
Reset
State
Unused
xxx
0b = Positive Offset
1b = Negative Offset
auto
Table 19. Column DOVA RAM
MCM20014
MOTOROLA
27
Address
22h
Default
00h
Column DOVA RAM
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
x
x
cor[3]
cor[2]
cor[1]
cor[0]
2-0
Offset
Offset = 2 * cord
auto
Table 19. Column DOVA RAM
The Global DOVA Register; Table 20 performs a final
offset adjustment in analog space prior to the ADC. The
6-bit register uses its MSB to indicate positive or negative offset. Each bit value changes the offset value by 4
Address
23h
LSB code levels hence giving an offset range of +/-124
LSB. As an example, to program an offset of +92 LSB,
the binary representation of +23d i.e. 010111b should
be loaded.
Default
00h
Global DOVA
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
gd[5]
gd[4]
gd[3]
gd[2]
gd[1]
gd[0]
Bit
Number
Function
7-6
Unused
5
Sign
5-0
Offset
Description
Reset
State
Unused
xx
0b = Positive Offset
1b = Negative Offset
0b
Offset = gdd
00000b
Table 20. Global DOVA Register
5.4 Post ADC Block
The post ADC block contains the bad-pixel replacement
registers and a general output control register.
The White Pixel Threshold Register; Table 21, and
Black Pixel Threshold Register; Table 22, are used to
set the thresholds for white and black pixel replacements. The MSBs on the Black Pixel Threshold Register are hard coded to 00b hence a black replacement
threshold value between 0d - 255d can be set. This forces the sensor to replace any pixel value at or below the
threshold by the average value of the neighboring same
color pixels. Similarly the MSBs on the White Pixel
Threshold Register are hard coded to 11b hence a white
replacement threshold level between 768d - 1023d can
be set. Again; as in the dark thresholding, if the sensor
encounters any pixel value that exceeds the set threshold, it will replace it with the average value of the neighboring same color pixels.
MOTOROLA
28
Care should be taken in assigning these thresholds.
This function performs an averaging effect on the image, therefore, the greater the code distance the thresholds move from the voltage rail, the more averaging
occurs between pixels.
MCM20014
Address
30h
Default
FEh
White Pixel Threshold
msb (7)
6
5
4
3
2
1
lsb (0)
wpt[7]
wpt[6]
wpt[5]
wpt[4]
wpt[3]
wpt[2]
wpt[1]
wpt[0]
Bit
Number
Function
7-0
Threshold
Description
Reset
State
Threshold = wpt[1b,1b,7:0]
11111110b
Table 21. White Pixel Threshold Register
Address
31h
Default
01h
Black Pixel Threshold
msb (7)
6
5
4
3
2
1
lsb (0)
bpt[7]
bpt[6]
bpt[5]
bpt[4]
bpt[3]
bpt[2]
bpt[1]
bpt[0]
Bit
Number
Function
7-0
Threshold
Description
Reset
State
Threshold = bpt[0b,0b,7:0]
00000001b
Table 22. Black Pixel Threshold Register
The Post ADC Control Register; Table 23, performs certain rudimentary transformations on the digitized data.
The wpe and bpe bits are used to enable or disable the
White Bad-pixel replacement and Black Bad-pixel replacement algorithms respectively. These algorithms
are described in section 2.3.1 and above.
Address
32h
The cpe bit enables the compander which provides for
the 10 to 8 bit noise coring described in section 2.3.2.
One of 8 available transform curves can be selected by
using the cps and cpb[2:0] bits. The slope of the transform is defined using cps while cpb[2:0] defines the
breakpoint. Please see Figure 13, on page 11.
Default
30h
Post ADC Control
msb (7)
6
5
4
3
2
1
lsb (0)
cpe
fuo
wpe
bpe
cps
cpb[2]
cpb[1]
cpb[0]
Bit
Number
Function
7
Compander
Enable
Description
0b = Compander Disabled
1b = Compander Enabled
Reset
State
0b
Table 23. Post ADC Control Register
MOTOROLA
29
MCM20014
Address
32h
Default
30h
Post ADC Control
msb (7)
6
5
4
3
2
1
lsb (0)
cpe
fuo
wpe
bpe
cps
cpb[2]
cpb[1]
cpb[0]
6
FUO
5
FUO
0b
White
Enable
0b = Disable White Bad Pixel Replacement
1b = Enable White Bad Pixel Replacement
1b
4
Black
Enable
0b = Disable Black Bad Pixel Replacement
1b = Enable Black Bad Pixel Replacement
1b
3
Compander
Slope
0b = Invalid when cpb[2:0] ≠ 000b
1b = 1:1 input:output
0b
2-0
Compander
Knee
000b = linear
001b = 15 on the output axis.
010b = 31 on the output axis.
011b = 47 on the output axis.
100b = 63 on the output axis.
101b = 79 on the output axis.
110b = 95 on the output axis.
111b = 127 on the output axis.
000b
Table 23. Post ADC Control Register
5.5 Sensor Interface Block
5.5.1 Sensor Output Control
The sensor output control registers define how the window of interest is captured and what data is output from
the MCM20014.
The frc bit is used to enable or disable the Frame Rate
Clamp. Unsetting this bit will turn off the frame rate
clamp and the output dark level will begin to drift over
frames. The frame rate clamp is enabled in default
mode.
The Capture Mode Control Register; Table 24, defines
how the data is captured and how the data is to be provided at the output.
The sp bit is used to define whether SOF is active high
or low. SOF is active high in default.
The sms bit defines the shutter mode, CFCM or SFCM,
of the device as described in section 2.1.3. CFCM is the
default mode.
Setting the cms bit will stop the current CFCM output
data stream at the end of the current frame. Unsetting
this bit (cms = 0b) will resume the output of the frame
stream. The MCM20014 is in CFCM in default. The user
may use this bit to capture data in the CFCM mode
while using the SYNC pin. The SYNC pin triggers a single frame of data to be output from the device in the
CFCM mode. Please refer to Figure 19, on page 14 for
a timing diagram of this mode.
MOTOROLA
30
The ve bit is used to determine whether VCLK is output
at the beginning of all the rows including virtual frame
rows or for the WOI rows only. The default is WOI only.
The vp bit is used to define whether VCLK is active high
or low. VCLK is active high in default.
The he bit is used to determine whether HCLK is output
continously or for the WOI pixels only. The default is
WOI only.
The hp bit is used to define whether HCLK is active high
or low. HCLK is active high in default.
MCM20014
Address
40h
Default
35h
Capture Mode Control
msb (7)
6
5
4
3
2
1
lsb (0)
sms
cms
frc
sp
ve
vp
he
hp
Bit
Number
Function
7
Shutter
Mode
0b = CFCM
1b = SFCM
0b
6
CFCM
Mode
0b = Continous Frame Stream
1b = Single Frame
0b
5
Frame
Clamp
1b = Frame Rate Clamp enabled
0b = Frame Rate Clamp disabled
1b
4
SOF
Phase
1b = SOF active high
0b = SOF active low
1b
3
VCLK
Enable
1b = All virtual frame rows
0b = Window of Interest rows only
0b
2
VCLK
Phase
1b = Active high
0b = Active low
1b
1
HCLK
Enable
1b = Continous
0b = Window of Interest Pixels only
0b
0
HCLK
Phase
1b = Active high
0b = Active low
1b
Description
Reset
State
Table 24. Capture Mode Control Register
The Sub-sample Control Register; Table 25, is used to
define what pixels of the WOI are read and the method
they are read.
The sm bit determines the readout mode, defined in
section 2.1.4, of the MCM20014, progressive scan or interlaced. In default, data is read out in progressive scan
mode.
Using the cm bit, the user can sample the pixel array in
either monochrome or Bayer pattern color space. This
means that when sampling the rows or columns, the set
of pixels read will be gathered as individual pixels
(monochrome) or in color tiles of pixels (Bayer pattern).
The pixels will be read in monochrome mode in default.
MCM20014
The ptm bit is used to define how the pixels are output
in time. Setting this bit to a 1b will cause the MCM20014
to output the pixels at the same point in time it would
have if the pixel array was fully sampled. Setting this bit
to a 0b (default) will cause the device to burst each row
of pixels out at the normal MCLK rate.
The row sampling rate is defined by rf[1:0] while the column sampling rate is defined by cf[1:0]. The pixel array
is fully sampled in default.
MOTOROLA
31
Address
41h
Default
00h
Sub-sample Control
msb (7)
6
5
4
3
2
1
lsb (0)
x
sm
cm
ptm
rf[1]
rf[0]
cf[1]
cf[0]
Bit
Number
Function
7
Unused
6
Scan Mode
5
Color
Mode
4
Description
Reset
State
Unused
x
1b = Interlaced scan
0b = Progressive scan
0b
1b = Bayer Pattern Sampling
0b = Monochrome Pattern Sampling
0b
Pixel Timing Mode
1b = Output sampled pixels at same time interval as in full sampling
0b = Output sampled pixels at MCLK rate
0b
3-2
Row Frequency
11b = read one pattern, skip 7 (1/8 sampled)
10b = read one pattern, skip 3 (1/4 sampled)
01b = read one pattern, skip one (1/2 sampled)
00b = full sampling
00b
1-0
Column
Frequency
11b = read one pattern, skip 7 (1/8 sampled)
10b = read one pattern, skip 3 (1/4 sampled)
01b = read one pattern, skip one (1/2 sampled)
00b = full sampling
00b
Table 25. Sub-sample Control Register
MOTOROLA
32
MCM20014
The SOF Control Register and VCLK Control Register;
Table 26 and Table 27 respectively, are used to define
Address
54h
the size of the SOF and VCLK signals. In default, SOF
is one row wide while VLCK is 32 MCLKs wide.
Default
C0h
SOF Control
msb (7)
6
5
4
3
2
1
lsb (0)
sof[7]
sof[6]
sof[5]
sof[4]
sof[3]
sof[2]
sof[1]
sof[0]
Bit
Number
Function
7-6
SOF Control
5-0
FUO
Description
Reset
State
11b
sof[7:6] = 00b = 1 MCLK Wide
sof[7:6] = 01b = 8 MCLKs Wide
sof[7:6] = 10b = 32 MCLKs Wide
sof[7:6] = 11b = Full Row Wide
Factory Use Only
000000b
Table 26. SOF Control Register
Address
55h
Default
90h
VCLK Control
msb (7)
6
5
4
3
2
1
lsb (0)
vck[7]
vck[6]
vck[5]
vck[4]
vck[3]
vck[2]
vck[1]
vck[0]
Bit
Number
Function
7-6
VCLK Control
5-0
FUO
Description
vck[7:6] = 00b = 1 MCLK Wide
vck[7:6] = 01b = 8 MCLKs Wide
vck[7:6] = 10b = 32 MCLKs Wide
vck[7:6] = 11b = Full Row Wide
Factory Use Only
Reset
State
10b
010000b
Table 27. VCLK Control Register
MCM20014
MOTOROLA
33
The Internal Timing Control Register; Table 28, is used
to define the size of internal timing pulse widths. In default, both shs and shr are 6 MCLK’s wide. The user is
Address
60h
strongly encouraged to write an 00h to this register; thus
making these pulse widths 16 MCLKs wide.
Default
66h
Internal Timing Control
msb (7)
6
5
4
3
2
1
lsb (0)
shs[3]
shs[2]
shs[1]
shs[0]
shr[3]
shr[2]
shr[1]
shr[0]
Bit
Number
Function
7-4
shs
shs[3:0] = 0000b = 16 MCLKs Wide
shs[3:0] = 0001b = 1d MCLKs Wide
shs[3:0] = 0010b = 2d MCLKs Wide
|
shs[3:0] = 0110b = 6d MCLKs Wide
|
shs[3:0] = 1111b = 15d MCLKs Wide
0110b
3-0
shr
shr[3:0] = 0000b = 16 MCLKs Wide
shr[3:0] = 0001b = 1d MCLKs Wide
shr[3:0] = 0010b = 2d MCLKs Wide
|
shr[3:0] = 0110b = 6d MCLKs Wide
0110b
Description
Reset
State
|
shr[3:0] = 1111b = 15d MCLKs Wide
Table 28. Internal Timing Control Register
5.5.2 Programmable “Window of Interest”
The WOI is defined by a set of registers that indicate the
upper-left starting point for the window and another set
of registers that define the size of the window. Please
refer to Figure 6, on page 7 for a pictorial representation
of the WOI within the active pixel array.
The WOI Row Depth; wrd[8:0], has a range of 0d to
511d whereas the WOI Column Depth; wcd[9:0], has a
range of 0d to 703d.
The user should be careful to create a WOI that contains active pixels only. There is no logic in the sensor
The WOI Row Pointer; wrp[8:0] (Table 29 and Table
30), and the WOI Column Pointer; wcp[9:0] (Table 31
and Table 32), mark the upper-left starting point for the
WOI.
The WOI Row Pointer; wrp[8:0], has a range of 0d to
511d whereas the WOI Column Pointer; wcp[9:0] has a
usable range of 0d to 703d. The pointer can be placed
anywhere within the active pixel array.
The WOI Row Depth; wrd[8:0] (Table 29 and Table 30),
and the WOI Column Depth; wcd[9:0] (Table 31 and
Table 32), indicate the size of the WOI.
MOTOROLA
34
MCM20014
interface to prevent the user from defining an WOI that
addresses non-existant pixels.
Address
45h
Default
00h
WOI Row Pointer MSB
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
x
x
x
x
x
wrp[8]
Bit
Number
Function
7-1
Unused
0
WOI Row
Pointer
Description
Reset
State
Unused
xxxxxxxx
In conjunction with the WOI Row Pointer LSB Register (Table 30),
forms the 9-bit WOI Row Pointer wrp[8:0]
0b
Table 29. WOI Row Pointer MSB Register
Address
46h
Default
0Ch
WOI Row Pointer LSB
msb (7)
6
5
4
3
2
1
lsb (0)
wrp[7]
wrp[6]
wrp[5]
wrp[4]
wrp[3]
wrp[2]
wrp[1]
wrp[0]
Bit
Number
Function
7-0
WOI Row
Pointer
Description
Reset
State
In conjunction with the WOI Row Pointer MSB Register (Table 29),
forms the 9-bit WOI Row Pointer wrp[8:0]
00001100b
(row 12)
Table 30. WOI Row Pointer LSB Register
Address
49h
Default
00h
WOI Column Pointer MSB
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
x
x
x
x
wcp[9]
wcp[8]
Bit
Number
Function
7-2
Unused
Unused
1-0
WOI Col.
Pointer
In conjunction with the WOI Column Pointer LSB Register (Table 32),
forms the 10-bit WOI Column Pointer wcp[9:0]
Description
Reset
State
xxxxxx
00b
Table 31. WOI Column Pointer MSB Register
MCM20014
MOTOROLA
35
Address
4Ah
Default
30h
WOI Column Pointer LSB
msb (7)
6
5
4
3
2
1
lsb (0)
wcp[7]
wcp[6]
wcp5]
wcp[4]
wcp[3]
wcp[2]
wcp[1]
wcp[0]
Bit
Number
Function
7-0
WOI Col.
Pointer
Description
Reset
State
In conjunction with the WOI Column Pointer MSB Register (Table
31), forms the 10-bit WOI Column Pointer wcp[9:0]
00110000b
(col. 48)
Table 32. WOI Column Pointer LSB Register
Address
47h
Default
01h
WOI Row Depth MSB
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
x
x
x
x
x
wrd[8]
Bit
Number
Function
7-1
Unused
0
WOI Row
Depth
Description
Reset
State
Unused
xxxxxxx
In conjunction with the WOI Row Depth LSB Register (Table 34),
forms the 9-bit WOI Row Depth wrd[8:0].
1b
Table 33. WOI Row Depth MSB Register
Address
48h
Default
DFh
WOI Row Depth LSB
msb (7)
6
5
4
3
2
1
lsb (0)
wrd[7]
wrd[6]
wrd[5]
wrd[4]
wrd[3]
wrd[2]
wrd[1]
wrd[0]
Bit
Number
Function
7-0
WOI Row
Pointer
Description
In conjunction with the WOI Row Depth MSB Register (Table 33),
forms the 9-bit WOI Row Depth wrd[8:0].
Desired = wrdd + 1.
Reset
State
11011111b
(480 rows)
Table 34. WOI Row Depth LSB Register
MOTOROLA
36
MCM20014
Address
4Bh
Default
02h
WOI Column Width MSB
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
x
x
x
x
wcw[9]
wcw[8]
Bit
Number
Function
7-2
Unused
Unused
1-0
WOI Col.
Width
In conjunction with the WOI Column Width LSB Register (Table 36),
forms the 10-bit WOI Column Width wcw[9:0].
Description
Reset
State
xxxxxx
10b
Table 35. WOI Column Width MSB Register
Address
4Ch
Default
7Fh
WOI Column Width LSB
msb (7)
6
5
4
3
2
1
lsb (0)
wcw[7]
wcw[6]
wcw[5]
wcw[4]
wcw[3]
wcw[2]
wcw[1]
wcw[0]
Bit
Number
Function
Description
Reset
State
7-0
WOI Row
Pointer
In conjunction with the WOI Column Width MSB Register (Table 35),
forms the 10-bit WOI Column Width wcw[9:0].
Desired = wcwd + 1.
01111111b(
640 col.)
Table 36. WOI Column Width LSB Register
5.5.3 Integration Time Control
The Integration Time registers; Table 37, Table 38, and
Table 39, control the integration time for the pixel array.
Integration time for SFCM; sint[20:0], is measured in
MCLK cycles while the integration time for CFCM;
cint[15:0], is measured in Virtual Row times. Please refer to Figure 8 for a pictorial description of the Virtual
Frame and its relationship to the WOI.
The user should be careful to create a Virtual Frame
that is larger than the WOI. There is no logic in the sensor interface to prevent the user from defining a Virtual
Frame smaller than the WOI. Therefore, pixel data may
be lost.
A virtual frame is the mechanism by which the user controls the integration time and frame time for the output
data stream. By adding additional rows or columns as
‘blanking’ to the WOI to form the Virtual Frame, the user
can control the amount of blanking in both horizontal
and vertical space.
The Virtual Frame completely defines the integration
time in CFCM. Any changes to the WOI or how the WOI
is sampled has no effect on integration time.
The Virtual Frame must be 1 row and 6 columns larger
than the WOI.
Both the Virtual Frame Row Depth; vrd[13:0], and the
Virtual Frame Column Width; vcw[9:0] have a range of
0d to 16384d.
MCM20014
MOTOROLA
37
Address
4Dh
Default
00h
Integration Time MSB
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
x
x
sint[19]
sint[18]
sint[17]
sint[16]
Bit
Number
Function
7-4
Unused
3-0
Integration
Time
Description
Reset
State
Unused
xxxx
SFCM: In conjunction with the Integration Time ISB (Table 38) and
Integration Time LSB (Table 39) Registers, forms the 20-bit Integration Time sint[19:0].
CFCM: Unused
0000b
Table 37. Integration Time MSB Register
Address
4Eh
Default
02h
Integration Time ISB
msb (7)
6
5
4
3
2
1
lsb (0)
sint[15]
cint[15]
sint[14]
cint[14]
sint[13]
cint[13]
sint[12]
cint[12]
sint[11]
cint[11]
sint[10]
cint[10]
sint[9]
cint[9]
sint[8]
cint[8]
Bit
Number
Function
Description
Reset
State
7-0
Integration
Time
SFCM: In conjunction with the Integration Time MSB (Table 37) and
Integration Time LSB (Table 39) Registers, forms the 20-bit Integration Time sint[19:0].
CFCM: In conjunction with the Integration Time LSB (Table 39) Register, forms the 16-bit Integration Time cint[15:0].
00000010b
Table 38. Integration Time ISB Register
MOTOROLA
38
MCM20014
Address
4Fh
Default
0Ch
Integration Time LSB
msb (7)
6
5
4
3
2
1
lsb (0)
sint[7]
cint[7]
sint[6]
cint[6]
sint[5]
cint[5]
sint[4]
cint[4]
sint[3]
cint[3]
sint[2]
cint[2]
sint[1]
cint[1]
sint[0]
cint[0]
Bit
Number
Function
Description
Reset
State
7-0
Integration
Time
SFCM: In conjunction with the Integration Time MSB (Table 37) and
Integration Time ISB (Table 38) Registers, forms the 20-bit Integration Time sint[19:0].
Integration Time = sintd * 16 * MCLKperiod.
CFCM: In conjunction with the Integration Time ISB (Table 38) Register, forms the 16-bit Integration Time cint[15:0].
Integration Time = (cintd + 1) * Trow
00001100b
(SFCM:
8400
MCLKs
CFCM: 525
Rows)
Table 39. Integration Time LSB Register
Address
50h
Default
02h
CFCM Virtual Frame Row Depth MSB
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
vrd[13]
vrd[12]
vrd[11]
vrd[10]
vrd[9]
vrd[8]
Bit
Number
Function
7-6
Unused
5-0
Virtual Row
Depth
Description
Unused
In conjunction with the CFCM Virtual Frame Row Depth LSB (Table
41) Register, forms the 14-bit Virtual Frame Row Depth vrd[13:0].
Reset
State
xx
000010b
Table 40. CFCM Virtual Frame Row Depth MSB Register
MCM20014
MOTOROLA
39
Address
51h
Default
0Ch
CFCM Virtual Frame Row Depth LSB
msb (7)
6
5
4
3
2
1
lsb (0)
vrd[7]
vrd[6]
vrd[5]
vrd[4]
vrd[3]
vrd[2]
vrd[1]
vrd[0]
Bit
Number
Function
Description
Reset
State
7-0
Virtual Row
Depth
In conjunction with the CFCM Virtual Frame Row Depth MSB (Table
40) Register, forms the 14-bit Virtual Frame Row Depth vrd[13:0].
WOI is always top-left justified in Virtual Frame.
vrdd minimum = wrdd + 1
00001100b
(525 rows)
Table 41. CFCM Virtual Frame Row Depth LSB Register
Address
52h
Default
02h
CFCM Virtual Frame Column Width MSB
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
vcw[13]
vcw[12]
vcw[11]
vcw[10]
vcw[9]
vcw[8]
Bit
Number
Function
7-6
Unused
5-0
Virtual Column Width
Description
Unused
In conjunction with the CFCM Virtual Frame Column Width LSB
(Table 43) Register, forms the 14-bit Virtual Frame Column Width
vcw[13:0].
Reset
State
xx
000010b
Table 42. CFCM Virtual Frame Column Width MSB Register
MOTOROLA
40
MCM20014
Address
53h
Default
EDh
CFCM Virtual Frame Column Width LSB
msb (7)
6
5
4
3
2
1
lsb (0)
vcw[7]
vcw[6]
vcw[5]
vcw[4]
vcw[3]
vcw[2]
vcw[1]
vcw[0]
Bit
Number
Function
7-0
Virtual Column Width
Description
In conjunction with the CFCM Virtual Frame Column Width MSB
(Table 42) Register, forms the 14-bit Virtual Frame Column Width
vcw[13:0]. WOI is always top-left justified in Virtual Frame.
vcwd minimum = wcwd + 11 (CFCM)
vcwd minimum = wcwd + 14 (SFCM)
Reset
State
11101101b
(750 col.)
Table 43. CFCM Virtual Frame Column Width LSB Register
6.0 I2C Serial Interface
The I2C is an industry standard which is also compatible
with the Motorola bus (called M-Bus) that is available on
many microprocessor products. The I2C contains a serial two-wire half-duplex interface that features bidirectional operation, master or slave modes, and multimaster environment support. The clock frequency on
the system is governed by the slowest device on the
board. The SDATA and SCLK are the bidirectional data
and clock pins, respectively. These pins are open drain
and will require a pull-up resistor to VDD of 1.5 kΩ to 10
kΩ (see page 48).
The I2C is used to write the required user system data
into the Program Control Registers in the MCM20014.
The I2C bus can also read the data in the Program Control Register for verification or test considerations. The
MCM20014 is a slave only device that supports a maximum clock rate (SCLK) of 100 kHz while reading or
writing only one register address per I2C start/stop cycle. The following sections will be limited to the methods
for writing and reading data into the MCM20014 register.
For a complete reference to I2C, see “The I2C Bus from
Theory to Practice” by Dominique Paret and CarllFenger, published by John Wiley & Sons, ISBN
0471962686.
6.1 MCM20014 I2C Bus Protocol
The MCM20014 uses the I2C bus to write or read one
register byte per start/stop I2C cycle as shown in Figure
25 and Figure 26. These figures will be used to describe
MCM20014
the various parts of the I2C protocol communications as
it applies to the MCM20014.
MCM20014 I2C bus communication is basically composed of following parts: START signal, MCM20014
slave address (0110011b) transmission followed by a R/
W bit, an acknowledgment signal from the slave, 8 bit
data transfer followed by another acknowledgment signal, STOP signal, Repeated START signal, and clock
synchronization.
6.2 START Signal
When the bus is free, i.e. no master device is engaging
the bus (both SCLK and SDATA lines are at logical “1”),
a master may initiate communication by sending a
START signal. As shown in Figure 25, a START signal
is defined as a high-to-low transition of SDATA while
SCLK is high. This signal denotes the beginning of a
new data transfer and wakes up all the slaves on the
bus.
6.3 Slave Address Transmission
The first byte of a data transfer, immediately after the
START signal, is the slave address transmitted by the
master. This is a 7-bit calling address followed by a R/
W bit. The seven-bit address for the MCM20014, starting with the MSB (AD7) is 0110011b. The transmitted
calling address on the SDATA line may only be
changed while SCLK is low as shown in Figure 25. The
data on the SDATA line is valid on the High to Low signal transition on the SCLK line. The R/W bit following
the 7-bit tells the slave the desired direction of data
transfer:
MOTOROLA
41
•
•
1 = Read transfer, the slave transitions to a slave
transmitter and sends the data to the master
0 = Write transfer, the master transmits data to the
slave
6.4 Acknowledgment
Only the slave with a calling address that matches the
one transmitted by the master will respond by sending
back an acknowledge bit. This is done by pulling the
SDATA line low at the 9th clock (see Figure 25). If a
transmitted slave address is acknowledged, successful
slave addressing is said to have been achieved. No two
slaves in the system may have the same address. The
MCM20014 is configured to be a slave only.
6.5 Data Transfer
Once successful slave addressing is achieved, data
transfer can proceed between the master and the selected slave in a direction specified by the R/W bit sent
by the calling master. Note that for the first byte after a
start signal (in Figure 25 and Figure 26), the R/W bit is
always a “0” designating a write transfer. This is required since the next data transfer will contain the register address to be read or written.
as a low-to-high transition of SDATA while SCLK is at
logical “1” (see Figure 25).
The master can generate a STOP even if the slave has
generated an acknowledge bit at which point the slave
must release the bus.
6.7 Repeated START Signal
A Repeated START signal is a START signal generated
without first generating a STOP signal to terminate the
communication. This is used by the master to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing
the bus.
As shown in Figure 26, a Repeated START signal is being used during the read cycle and to redirect the data
transfer from a write cycle (master transmits the register
address to the slave) to a read cycle (slave transmits
the data from the designated register to the slave).
All transfers that come after a calling address cycle are
referred to as data transfers, even if they carry sub-address information for the slave device.
Each data byte is 8 bits long. Data may be changed only
while SCLK is low and must be held stable while SCLK
is high as shown in Figure 25. There is one clock pulse
on SCLK for each data bit, the MSB being transferred
first.
Each data byte has to be followed by an acknowledge
bit, which is signalled from the receiving device by pulling the SDATA low at the ninth clock. So one complete
data byte transfer needs nine clock pulses. If the slave
receiver does not acknowledge the master, the SDATA
line must be left high by the slave. The master can then
generate a stop signal to abort the data transfer or a
start signal (repeated start) to commence a new calling.
If the master receiver does not acknowledge the slave
transmitter after a byte transmission, it means 'end of
data' to the slave, so the slave releases the SDATA line
for the master to generate STOP or START signal.
6.6 Stop Signal
The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling
command without generating a STOP signal first. This
is called a Repeated START. A STOP signal is defined
MOTOROLA
42
MCM20014
LSB
MSB
SCLK
SDATA
1
2
3
4
5
6
MSB
7
8
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1
“0” “1” “1” “0” “0” “1” “1”
MCM20014 I2C Bus Address
Start
Signal
1
D7
LSB
2
3
D6 D5
4
5
6
7
D4
D3
D2 D1
MCM20014 Register Address
Write Ack
Bit
from
MCM20014
MSB
8
9
D0
Ack
Bit
from
MCM20014
LSB
SCLK 1
2
3
4
5
6
7
SDATA D7
D6
D5
D4
D3
D2
D1 D0
Data to write MCM20014 Register
8
9
Ack Stop
Bit Signal
from
MCM20014
Figure 25. WRITE Cycle using I2C Bus
6.8 I2C Bus Clocking and Synchronization
Open drain outputs are used on the SCLK outputs of all
master and slave devices so that the clock can be synchronized and stretched using wire-AND logic. This
means that the slowest device will keep the bus from
going faster than it is capable of receiving or transmitting data.
After the master has driven SCLK from High to Low, all
the slaves drive SCLK Low for the required period that
is needed by each slave device and then releases the
SCLK bus. If the slave SCLK Low period is greater than
the master SCLK Low period, the resulting SCLK bus
signal Low period is stretched. Therefore, synchronized
clocking occurs since the SCLK is held low by the device with the longest Low period. Also, this method can
be used by the slaves to slow down the bit rate of a
transfer. The master controls the length of time that the
SCLK line is in the High state. The data on the SDATA
line is valid when the master switches the SCLK line
from a High to a Low.
Slave devices may hold the SCLK low after completion
of one byte transfer (9 bits). In such case, it halts the bus
clock and forces the master clock into wait states until
the slave releases the SCLK line.
MCM20014
6.9 Register Write
Writing the MCM20014 registers is accomplished with
the following I2C transactions (see Figure 25):
•
•
•
•
•
•
•
•
Master transmits a START
Master transmits the MCM20014 Slave Calling Address with “WRITE” indicated (BYTE=66h, 102d,
01100110b)
MCM20014 slave sends acknowledgment by forcing the SDATA Low during the 9th clock, if the Calling Address was received
Master transmits the MCM20014 Register Address
MCM20014 slave sends acknowledgment by forcing the SDATA Low during the 9th clock after receiving the Register Address
Master transmits the data to be written into the register at the previously received Register Address
MCM20014 slave sends acknowledgment by forcing the SDATA Low during the 9th clock after receiving the data to be written into the Register
Address
Master transmits STOP to end the write cycle
MOTOROLA
43
•
•
6.10 Register Read
Reading the MCM20014 registers is accomplished with
the following I2C transactions (see Figure 26):
•
•
•
•
•
Master transmits a START
Master transmits the MCM20014 Slave Calling Address with “WRITE” indicated (BYTE=66h, 102d,
01100110b)
MCM20014 slave sends acknowledgment by forcing the SData Low during the 9th clock, if the Calling
Address was received
Master transmits the MCM20014 Register Address
MCM20014 slave sends acknowledgment by forcing the SData Low during the 9th clock after receiving the Register Address
SCLK
1
2
3
4
5
6
MSB
SDATA
7
8
9
MCM20014 I2C Bus Address
SCLK
1
2
3
4
5
6
MSB
D7
•
•
•
2
3
4
5
6
7
7
8
LSB
9
8
9
LSB
D6 D5
D4
D3
D2 D1
MCM20014 Register Address
Write Ack
Bit
from
MCM20014
MCM20014 I2C Bus Address Read
1
2
3
4
5
6
7
D7
8
9
LSB
MSB
SDATA
•
D0
XX
Ack
Repeated
Bit
Start
from
Signal
MCM20014
At this point the MCM20014
transitions from a “SLAVE-receiver”
to a “SLAVE- transmitter”
AD7 AD6 AD5 AD4 AD3 AD2 AD1
“0” “1” “1” “0” “0” “1” “1”
SDATA
SCLK
•
MSB
LSB
AD7 AD6 AD5 AD4 AD3 AD2 AD1
“0” “1” “1” “0” “0” “1” “1”
Start
Signal
1
Master transmits a Repeated START
Master transmits the MCM20014 Slave Calling Address with “READ” indicated (BYTE = 67h, 103d,
01100111b)
MCM20014 slave sends acknowledgment by forcing the SDATA Low during the 9th clock, if the Calling Address was received
At this point, the MCM20014 transitions from a
“Slave-Receiver” to a “Slave-Transmitter”
MCM20014 sends the SCLK and the Register Data
contained in the Register Address that was previously received from the master; MCM20014 transitions to slave-receiver
Master does not send an acknowledgment (NAK)
Master transmits STOP to end the read cycle
D6
D5
D4
D3
D2
Ack Bit fromMCM20014
The MCM20014
transitions from a “SLAVE-transmitter”
to a “SLAVE-receiver” after the
register data is sent
D1 D0
Data from MCM20014 Register
No Ack. Bit from MASTER terminates the transfer
Stop
Signal from MASTER
Single Byte Transfer to Master
Figure 26. READ Cycle using I2C Bus
MOTOROLA
44
MCM20014
7.0 Electrical Characteristics
ABSOLUTE MAXIMUM RATINGS1 (Voltages Referenced to VSS)
1
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage
-0.5 to 3.8
V
Vin
DC Input Voltage
0.5 to VDD + 0.5
V
Vout
DC Output Voltage
-0.5 to VDD + 0.5
V
I
DC Current Drain per Pin, Any Single Input or Output
±50
mA
I
DC Current Drain, VDD and VSS Pins
±100
mA
TSTG
Storage Temperature Range
-65 to +150
°C
TL
Lead Temperature (10 second soldering)
300
°C
Maximum Ratings are those values beyond which damage to the device may occur.
VSS = AVSS = DVSS = VSSO (DVSS = VSS of Digital circuit, AVSS = VSS of Analog Circuit)
VDD = AVDD = DVDD = VDDO (DVDD = VDD of Digital circuit, AVDD = VDD of Analog Circuit)
RECOMMENDED OPERATING CONDITIONS (to guarantee functionality; voltage referenced to VSS)
Symbol
Parameter
Min
Max
Unit
VDD
DC Supply Voltage, VDD = 3.3V (Nominal)
3.0
3.6
V
TA
Commercial Operating Temperature
0
40
°C
TJ
Junction Temperature
0
55
°C
Notes:
- All parameters are characterized for DC conditions after thermal equilibrium has been established.
- Unused inputs must always be tied to an appropriate logic level, e.g., either VSS or VDD.
- This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage higher than the maximum rated voltages to this high impedance circuit.
- For proper operation it is recommended that Vin and Vout be constrained to the range VSS < (Vin or Vout) < VDD.
DC ELECTRICAL CHARACTERISTICS (VDD = 3.3V ± 0.3V; VDD referenced to VSS; Ta = 0°C to 40°C)
TA = 0°C to 40°C
Symbol
Characteristic
Min
Max
Unit
Input High Voltage
2.0
VDD+0.3
V
Input Low Voltage
-0.3
0.8
V
Vin = VDD or VSS
-5
5
µA
Output High Current
VDD = Min, VOH Min = 0.8 * VDD
-3
mA
IOL
Output Low Current
VDD = Min, VOL Max = 0.4 V
3
mA
VOH
Output High Voltage
VDD = Min, IOH = -100µA
VDD - 0.2
V
VOL
Output Low Voltage
VDD = Min, IOL = 100µA
IOZ
3-State Output Leakage Current
Output = High Impedance, Vout = VDD or VSS
Maximum Standby Supply Current
Iout = 0mA, Vin = VDD or VSS
VIH
VIL
Iin
Input Leakage Current, No Pull-up Resistor
IOH
IDD
MCM20014
Condition
0.2
V
-10
10
µA
0
15.0
mA
MOTOROLA
45
POWER DISSIPATION (VDD = 3.0V, VDD referenced to VSS; Ta = 25°C)
Symbol
Parameter
Condition
Typ
Unit
PDYN
Dynamic Power
13.5 MHz MCLK Clock frequency
400
mW
PSTDBY
Standby Power
STDBY Pin Logic High
50
mW
PAVG
Average Power
13.5 MHz Operation (using STDBY)
200
mW
MCM20014 MONOCHROME CMOS IMAGE SENSOR ELECTRO-OPTICAL CHARACTERISTICS
Symbol
Parameter
Typ
Unit
Notes
Esat
Saturation Exposure
0.14
µJ/cm2
1
QE
Peak Quantum Efficiency (@550nm)
18
%
2
PRNU
Photoresponse Non-uniformity
12
% pk-pk
3
Notes:
1.For λ = 550 nm wavelength.
2.Refer to typical values from Figure 3, MCM20014 nominal spectral response.
3.For a 100 x 100 pixel region under uniform illumination with output signal equal to 80% of saturation signal.
MCM20014 COLOR CMOS IMAGE SENSOR ELECTRO-OPTICAL CHARACTERISTICS
Symbol
Esat
QEr
QEg
QEb
Parameter
Typ
Unit
Notes
Saturation Exposure
0.3
µJ/cm2
1
Red Peak Quantum Efficiency @ λ = 650 nm
12
%
2
Green Peak Quantum Efficiency @ λ = 550 nm
11
%
2
Blue Peak Quantum Efficiency @ λ = 450 nm
8
%
2
Notes:
1.For λ = 550 nm wavelength.
2.Refer to typical values from Figure 3, MCM20014 nominal spectral response.
CMOS IMAGE SENSOR CHARACTERISTICS
Symbol
Parameter
Typ
Unit
Notes
Sensitivity
3.0
V/lux-sec
Id
Photodiode Dark Current
0.2
nA/cm2
DSNU
Dark Signal Non-Uniformity (Entire Field)
0.4
% rms
CTE
Pixel Charge Transfer Efficiency
0.9995
%
1
fH
Horizontal Imager Frequency
11.5
MHz
4
Xab
Blooming Margin - shuttered light
200
2,3
Notes:
1. Transfer efficiency of photosite
2. Xab represents the increase above the saturation-irradiance level (Hsat) that the device can be exposed to before blooming of the pixel will
occur.
3. No column streaking
4. At 30fps VGA
MOTOROLA
46
MCM20014
GENERAL
Symbol
Parameter
Typ
ne- total
Total System (equivalent) Noise Floor
70
Unit
e rms
DR
System Dynamic Range
50
dB
-
Notes
1
Notes:
1.Includes amplifier noise, dark pattern noise and dark current shot noise at 13.5 MHz data rates.
ANALOG SIGNAL PROCESSOR CHARACTERISTICS
Analog to Digital Converter (ADC)
Symbol
Parameter
Resolution
VIN
Input Dynamic
Min
Typ
Max
Units
10
bits
Range8
2.5
Vpp
INL
Integral Non-Linearity
+1.0
LSB
DNL
Differential Non-Linearity
+0.5
LSB
fmax
ADC Clock Rate
13.5
MHz
Notes:
Effective differential signal dynamic range
9. INL & DNL test limits are adjusted to compensate for the effects of the LRC, DOVA and DPGA stages between teh EXT_VINS inpt and the
input of the ADC.
8
MCM20014
MOTOROLA
47
I2C SERIAL INTERFACE6 TIMING SPECIFICATIONS (see Figure 27)
Symbol
Characteristic
Min
Max
Unit
fmax
SCLK maximum frequency
50
400
KHz
M1
Start condition SCLK hold time
4
-
TMCLK7
M2
SCLK low period
8
-
TMCLK
M3
SCLK/SDATA rise time [from VIL = (0.2)*VDD to VIH = (.8)*VDD]
-
.3
µs8
M4
SDATA hold time
4
-
TMCLK7
M5
SCLK/SDATA fall time (from Vh = 2.4V to Vl = 0.5V)
-
.3
µs8
M6
SCLK high period
4
-
TMCLK
M7
SDATA setup time
4
-
TMCLK7
M8
Start / Repeated Start condition SCLK setup time
4
-
TMCLK
M9
Stop condition SCLK setup time
4
-
TMCLK
CI
Capacitive for each I/O pin
-
10
pF
Cbus
Capacitive bus load for SCLK and SDATA
-
200
pF
Rp
Pull-up Resistor on SCLK and SDATA
1.5
10
kΩ9
6 2
I C is a proprietary Philips interface bus
The unit TMCLK is the period of the input master clock; The frequency of MCLK is assumed 13.5 MHz
8
The capacitive load is 200 pF
9
A pull-up resistor to VDD is required on each of the SCLK and SDATA lines; for a maximum bus capacitive load of 200 pf, the minimum
value of Rp should be selected in order to meet specifications
7
M2
M6
M5
VIH
VIL
SCLK
M1
M4
M7
M8
M3
M9
M8
SDATA
Figure 27. I2C Bus Timing Diagram
MOTOROLA
48
MCM20014
PIXEL DATA BUS INTERFACE TIMING SPECIFICATIONS (see Figure 28)
Symbol
Characteristic
Min
Typ
Max
Unit
fmax
MCLK maximum frequency
1
11.5
13.5
MHz
thsync
SYNC hold time w.r.t MCLK
3.5
-
9
ns
tsusync
SYNC setup time w.r.t MCLK
3.0
-
8.5
ns
8
13
21.5
ns
tdsof
MCLK to SOF delay time
tdvclk
MCLK to VCLK delay time
8.5
13.5
22
ns
tdrhclk
Rising edge of MCLK to rising edge of HCLK delay time
7.5
13
22
ns
tdfhclk
Falling edge of MCLK to falling edge of HCLK delay time
3
5
10.5
ns
tdadc
MCLK to ADC[9:0] delay time
8
13
21.5
ns
MCLK to BLANK delay time
8
13
21.5
ns
tdblank
MCLK
tsusync
thsync
SYNC
tdsof
SOF
tdvclk
VCLK
tdrhclk
tdfhclk
HCLK
tdadc
ADC[9:0]
tdblank
BLANK
Figure 28. Pixel Data Bus Timing Diagram
MCM20014
MOTOROLA
49
Table 44. MCM20014 Pin Definitions
Pin Pin
No. Name
Pin Pin
No. Name
Pin
Power
Type
Description
Description
Pin
Power
Type
1
ADC6
Output Bit 6 = 6410 Weight
O
25
SCLK
I2C Serial Clock
I/O
2
ADC5
Output Bit 5 = 3210 Weight
O
26
SDATA
I2C Serial Data
I/O
3
ADC4
Output Bit 4 = 1610 Weight
O
27
STBY
Power Down Standby Enable
4
ADC3
Output Bit 3 = 810 Weight
O
28
INIT
Sensor Intialize
I
5
ADC2
Output Bit 2 = 410 Weight
O
29
TS
Three State Ouput Enable
I
6
ADC1
Output Bit 1 = 210 Weight
O
30
SYNC
Sensor Sync Signal
I
7
ADC0
Output Bit 0 = 110 Weight
O
31
DVDD
Digital Power
P
8
DVDD
Digital Power
P
D
32
TEST_IN9 Test Input 9
I
D
33
TEST_IN8 Test Input 8
I
34
TEST_IN7 Test Input 7
I
I
9
DVSS
Digital Ground
G
10
BLANK
Pixel In-valid
O
11
AVDD
Analog Power
P
A
35
TEST_IN6 Test Input 6
I
12
AVSS
Analog Ground
G
A
36
TEST_IN5 Test Input 5
I
13
EXTRES
External Bias Resisitor Input
I
37
TEST_IN4 Test Input 4
I
14
TEST_AI
Test Analog Chain Input
I
38
TEST_IN3 Test Input 3
I
15
TEST_AO Test Analog Video Output
O
39
TEST_IN2
I
16
AVDD
Analog Power
P
A
40
TEST_IN1 Test Input 1
I
17
AVSS
Analog Ground
G
A
41
TEST_IN0 Test Input 0
I
18
CVREFM
Bias Reference Bottom Output
O
42
DVSS
Digital Ground
G
19
CVREFP
Bias Reference Top Output
O
43
HCLK
Pixel Sync
O
Test Input 2
20
CLRCB
Line Rate Clamp Output
O
44
VCLK
Line Sync
O
21
CLRCA
Line Rate Clamp Output
O
45
SOF
Start Of Frame
O
22
AVDD
Analog Power
P
A
46
ADC9
Output Bit 9 = 51210 Weight
O
23
AVSS
Analog Ground
G
A
47
ADC8
Output Bit 8 = 25610 Weight
O
24
MCLK
Master Clock
I
48
ADC7
Output Bit 7 = 12810 Weight
O
TEST_IN3
TEST_IN2
TEST_IN5
TEST_IN4
TEST_IN6
TEST_IN8
TEST_IN7
DVDD
TEST_IN9
39
36
37
35
33
34
31
D = Digital
A = Analog
SOF
ADC9
ADC8
ADC7
ADC6
ADC5
ADC1
4 5 6
ADC4
ADC3
ADC2
Top-View
D
note: pins 27,29-30, 32-41 should
be pulled down when not in use
30 29 28 27 26 25 24 23 22 21 20 19
I = Input
O = Output
HCLK
VCLK
32
TEST_IN1
40
G = VSS
43 44 45 46 47 48 1 2 3
P = VDD
38
TEST_IN0
41
42
DVSS
Legend:
D
SYNC
TS
INIT
STBY
SDATA
SCLK
MCLK
AVSS
AVDD
CLRCA
CLRCB
CVREFP
18
AVSS
AVDD
TEST_AO
CVREFM
EXTRES
TEST_AI
17
16
15
14
AVSS
AVDD
13
12
11
BLANK
10
9
DVDD
DVSS
ADC0
8
7
Figure 29. MCM20014 Pinout Diagram
MOTOROLA
50
MCM20014
Dim
Min
Max
A
0.555
0.572
B
0.525
0.545
C
---
0.120
D
0.016
0.024
E
0.067
0.083
F
0.075
G
0.095
0.040 BSC
H
0.033
0.047
J
0.555
0.572
K
0.525
L
0.545
0.028 REF
R
0.028 REF
R1
0.028 REF
Figure 30. 48 Terminal ceramic leadless chip carrier (bottom view)
MCM20014
MOTOROLA
51
Active Pixel Array Center
x-axis pixel offset
181.5µm (7.1mils)
y-axis pixel offset
1225.5µm (48.2mils)
Die Placement Positional Tolerance
200µm (7.9mils)
Note: Pictured elements are shown for reference, not to scale.
.200" Ref
Figure 31. Center of the focal plane array with respect to the die cavity (top view)
Notes:
1. Dimensions are in inches.
2. Interpret dimensions and tolerances per
ASME Y14.5-1994
MOTOROLA
52
MCM20014
Lid to Die
Die
Dimensional
Surface to
Analysis
Seating Plane
Mils
Minimum
Maximum
Nominal
A
19.65
23.65
21.65
B
45
55
50
C
27.76
29.33
28.54
D
E
F
22
0.5
0.5
28
4
2
25
2
1
Maximum possible variation:
G
31.82
52.39
42.11
20.57
H
12.17
28.74
20.46
16.57
50.25585
61.33065
55.5433
11.07
mm
Minimum
Maximum
Nominal
A
0.50
0.60
0.55
B
1.14
1.40
1.27
C
0.705
0.745
0.725
D
E
F
0.56
0.01
0.01
0.71
0.10
0.05
0.64
0.05
0.03
Maximum possible variation:
G
0.81
1.33
1.07
0.5226
H
0.31
0.73
0.52
0.421
1.28
1.56
1.41
0.28
A
F - Lid Seal thickness
G
H
B
D
E - Die Attach thickness
C - Die
Figure 32. Focal plane with respect to package.
MCM20014
MOTOROLA
53
Note: For the most current information regarding this product, contact Motorola
on the World Wide Web at http://www.motorola.com/adc/Image_Capture/
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MCM20014