LAPIS ML630Q464 Ultra low power 32-bit microcontroller Datasheet

FEDL630Q464-01
Issue Date: Oct. 26, 2016
ML630Q464/Q466
Ultra Low Power 32-bit Microcontroller
■ GENERAL DESCRIPTION
This LSI is a high-performance low power 32-bit microcontroller. Equipped with a 32-bit CPU core Cortex -M0+, it
implements a 128 KB flash memory, 16 KB RAM, rich peripheral circuits, such as USB Full speed device, synchronous serial
port, UART, I2C bus interface, supply voltage level detect circuit, RC oscillation type A/D converter, successive approximation
type A/D converter, and LCD driver. The Flash ROM that is installed as program memory achieves low-voltage low-power
consumption operation (read operation) is most suitable for battery-driven applications.
TM
■ FEATURES
• CPU
− 32-bit RISC CPU (CPU name: ARM Cortex -M0+)
− Thumb®/Thumb®-2 instruction supported
− Serial Wire Debug Port
− Minimum instruction execution time
30.5 µs (@32.768 kHz system clock)
41.7ns (@24 MHz system clock)
TM
• Internal memory
− Re-writing the program memory area by software
− Number of segments
Product name
ML630Q464
ML630Q466
Flash memory
Program area
Data area
64KB (16K × 32bit)
2KB (0.5K × 32bit)
128KB (32K × 32bit)
2KB (0.5K × 32bit)
SRAM
8KB (2K × 32bit)
16KB (4K × 32bit)
• Interrupt controller (NVIC)
− 1 non-maskable interrupt source (Internal source: 1)
− 31 maskable interrupt sources (Internal sources: 30, External sources: 1)
− Priority level (4-level) can be set for each interrupt
• DMA controller (DMAC)
− 2 channels
− Enable to allocate multiple DMA transfer request sources for each channel.
− Channel priority: fixed mode/round robin mode
− DMA transfer mode: cycle steal mode/burst mode
− DMA request type: software requests/hardware requests
− Maximum transfer count: 65,536
− Data transfer size: 8 bits/16 bits/32 bits
− Transfer request source: SSIOF, UART, UARTF, I2CF, RC-ADC, SA-ADC
• Time base counter (TBC)
− Low-speed time base counter ×1 channel
• 1 kHz Timer
− 10 Hz / 1 Hz interrupt function
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• Timers (TMR)
− 8 bits × 8 channels
(Timer0-7: 16-bit x 4 configuration available by using Timer0-1 or Timer2-3, Timer4-5, Timer6-7)
− Selection of one shot timer mode is possible
− External clock can be selected as timer clock.
• Function Timers (FTM)
− 16-bit × 4 channels
− Equipped with the timer/capture/PWM functions using a 16-bit counter
− An event trigger (external pin input interrupt or timer interrupt request) can control start/stop/clear of the timer (however,
the minimum pulse width of pin input is timer clock 3φ)
− 1 to 64 dividing of LSCLK/OSCLK/HSCLK/external input selectable as timer clock
− Two types of PWM with the same period and different duties and complementary PWM with the dead time set can be
output.
• Real Time Clock (RTC)
− 1 channels (99 years calendar, alarm, revision of the clock)
• Watchdog timer (WDT)
− Non-maskable interrupt and reset
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s when LSCLK = 32.768 kHz)
• Synchronous serial port (SSIOF/SSIO)
− without FIFOs (SSIO) : 1 channel
− with 16-byte transmits and receives FIFOs (SSIOF) : 1 channel
− Master/slave selectable
− LSB first/MSB first selectable
− Clock polarity (data out at rising edge and data in at falling edge/data out at falling edge and data in at rising edge)
selectable
− 8-bit length/16-bit length selectable
− Initial clock level (High start/Low start) selectable
− supports slave-select signal (only SSIOF)
• UART (UARTF/UART)
− without FIFOs (UART) : 1channel
− with 16-byte transmits and receives FIFOs (UARTF) :1 channels
− Full duplex buffer system
− Communication speed: Settable within the range of 2400bps to 115200bps.
− Programmable interface (data length, parity, stop bits selectable)
• I2C bus interface (I2CF/I2C)
− without FIFOs(I2C) :1 channel
− with 16-byte transmits and receives FIFOs (I2CF) : 1 channels
− Master/slave function (only I2CF)
− Fast mode (400 kHz), standard mode (100 kHz)
• USB full-speed device
− Compliant with Universal Serial Bus (USB)
− Full speed (12 Mbps) 1 port.
− End points: 5 or 6
− Supports all data transfer types (control transfer, bulk transfer, interrupt transfer, isochronous transfer).
− Built-in SOF generation and CRC5/16 generation functions
− Access size to data transfer FIFOs: 8 bits/16 bits/32 bits
• General-purpose ports (PORT)
− Input/output port × 38 channels (including secondary or tertiary or quaternary or quinary functions).
(ML630Q464 and ML630Q466: including LCD com/seg ports ( each 20 ports ))
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• RC oscillation type A/D converter (RC-ADC)
− Time division × 2 channels
− Starting by trigger of Timer/FTM function.
− 24-bit counter
• Successive approximation type A/D converter (SA-ADC)
− Input × 12 channels
− 12-bit A/D converter
− Starting by trigger of Timer/FTM function.
− Capacitive touch sense function
• Analog Comparator (CMP)
− Input × 2ch
− Common mode input voltage:
0.2V to VDD－0.2V
− Input offset voltage:
30mV(max)
− Interrupt allow edge selection and sampling selection
• Voltage Level Supervisor (VLS)
− Threshold voltages: One of 64 levels
− Acuraccy: ±3%
− Interrupt or Reset generation are slectable
− Voltage measurement with voltage input pin or VDD pin
• Low Level Detector(LLD)
− Judgment Voltage: 1.8V±0.2V
− Can be used as low level detection reset.
• LCD driver
− Maximun 400 dots (50 segment x 8 common)
− 1/1 to 1/8 duty
− 1/2, 1/3 bias (built-in bias generation circuit)
− Frame frequency selecable
− Bias voltage multiplying clock selectable (5 types)
− Contrast adjustment (32 steps)
− 4 operating mode: LCD drive stop, LCD display, all LCDs on, all LCDs off
− Programmable display allocation function
• Random number generator (RANDOM)
− Generates 8-bit random numbers
• AES
− 128-bit Common key
− Supports key sizes of 128, 192, and 256 bits
− Supports ECB, CBC, and CTR modes
• Reset
− Reset by the RESET_N pin input
− Reset by power-on detection
− Reset by overflow of watchdog timer (WDT)
− Reset by threshold detection in Voltage Level Supervisor(VLS)
− Reset by low level detection in Low Level Detector(LLD)
− Reset by the low-speed crystal oscillation stop detection
− Reset by SYSRESETREQ of Cortex -M0+ (software reset)
TM
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• Clock
− Low-speed clock:
− Crystal oscillation (32.768 kHz)
− Built-in RC oscillation (32.768kHz)
− High-speed clock:
− PLL (24 MHz) generated from Crystal oscillation (32.768 kHz)
− Built-in RC oscillation (16MHz)
• Power management
− HALT mode: Instruction execution by CPU is suspended. All peripheral circuits can keep in operating states.
− HALT-H mode: Instruction execution by CPU is suspended. Stop of high-speed oscillation automatically. All peripheral
circuits can keep in operating states.
− DEEP-HALT mode: Instruction execution by CPU is suspended. Some peripheral circuits(Timer, LTBC etc.) can keep in
operating states.
− ULTRA-DEEP-HALT mode: Instruction execution by CPU is suspended. Some peripheral circuits(Timer, LTBC etc.) can
keep in operating states, at VDD>2.5V.
− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8,1/16,1/32 of the
oscillation clock)
− Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals.
• Guaranteed operating range
− Operating temperature (ambient) : −40°C to +85°C
− Operating voltage: VDD = 1.8V to 3.6V
• Supply current (Typ)
− High-speed operation (24 MHz) : 250uA/MHz
− ULTRA-DEEP-HALT : 0.80uA
● Package
− 100-pin plastic TQFP
− Tray
ML630Q464-xxxTBZWAX
ML630Q466-xxxTBZWAX
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■ BLOCK DIAGRAM
ML630Q464/Q466 Block Diagram
CPU (Cortex-m0+)
SWC
SWD
DAP
Cortex-m0+
MTB
WIC
Data-bus
(AMBA AHB/APB)
SCK0
SIN0
SOUT0
SCKF0
SINF0
SOUTF0
SSF0
RXD0
TXD0
RXDF0
TXDF0
SDA1
SCL1
SDAF0
SCLF0
DP
DM
PUCTL
IN0
CS0
RS0
RT0
RCT0
RCM
IN1
CS1
RS1
RT1
VREF
SSIO×1
SSIOF×1
UART×1
UARTF×1
I2C ×1
I CF ×1
INT
1
Program
Memory
(Flash)
64K/128KB
INT
2
Data Memory
(Flash)
2KB
INT
2
2
RAM
8K/16KB
INT
2
USB
INT
8
INT
4
INT
1
INT
1
DMAC
INT
1
RC-ADC
Interrupt
Controller
INT
1
LTBC
Timer
×8
TMOUT0-9
Function
Timer ×4
WDT
P00 to P05
GPIO
SA-ADC
INT
1
RND
INT
1
INT
1
LCD
Driver
TMCKI0-7
1kHz Timer
×1
INT
1
INT
1
TMOUTA-F
RTC
×1
AES
AIN0 to AIN11
COM0 to COM7
SEG0 to SEG49
Data-bus
(Single cycle IO)
INT
2
INT
1
NVIC
Analog
Comparator
×2
INT
1
P20 to P23
P30 to P37
P40 to P47
P50 to P57
P60 to P63
CMP0P
CMP0M
CMP1P
CMP1M
VLS
VL1, VL2, VL3
C1, C2
LLD
LCD
BIAS
VDD
VSS
VDDL
RESET
RESET_N
OSC
XT0
XT1
32kCLKO0
Power
CH1, CH2
VHF
Figure 1.
ML630Q464/Q466 Block Diagram
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■ PIN CONFIGURATION
Figure 2. Pin Layout of ML630Q464/Q466
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■ PIN LIST
PIN
No.
.Reset
State
Primary Function
Secondary Function
Tertiary Function
Quaternary Function
Quinary Function
Pin name
I/O
Pin name
I/O
pin name
I/O
pin name
I/O
pin name
I/O
–
VSS
–
–
–
–
–
–
–
–
–
–
VDD
–
–
–
–
–
–
–
–
–
80
–
VDDL
–
–
–
–
–
–
–
–
–
70
–
VHF
–
–
–
–
–
–
–
–
–
90
–
VREF
–
–
–
–
–
–
–
–
–
74
–
XT0
–
–
–
–
–
–
–
–
–
14
68
79
65
81
73
78
77
76
75
–
Pull-up
Input
Pull-up
Input
Pull-up
Input
Pull-down
Input
95
Hi-Z
output
96
Hi-Z
output
97
Hi-Z
output
98
Hi-Z
output
99
100
Hi-Z
output
Hi-Z
output
91
Hi-Z
output
92
Hi-Z
output
93
Hi-Z
output
94
Hi-Z
output
82
Hi-Z
output
83
Hi-Z
output
84
Hi-Z
output
85
Hi-Z
output
86
Hi-Z
output
87
Hi-Z
output
88
Hi-Z
output
89
Hi-Z
output
13 to
10
9
8
7
6
15 to
48
49
Low Level
Output
Hi-Z
output
Hi-Z
output
Hi-Z
output
Hi-Z
output
Low Level
Output
Hi-Z
output
XT1
–
–
–
–
–
–
–
–
–
RESET_N
I
–
–
–
–
–
–
–
–
SWC
I
–
–
–
–
–
–
–
–
SWD
I/O
–
–
–
–
–
–
–
–
BRMP
I
–
–
–
–
–
–
–
–
I/O
IN0
I
SOUT0
O
RXDF0
I
–
–
I/O
CS0
O
SIN0
I
TXDF0
O
–
–
I/O
RCT0
O
SCK0
I/O
TMOUT0
O
–
–
I/O
RS0
O
–
–
TMOUT1
O
–
–
I/O
RT0
O
–
–
–
–
–
–
I/O
RCM
O
–
–
–
–
–
–
I/O
IN1
I
SOUTF0
O
–
–
–
–
I/O
CS1
O
SINF0
I
–
–
–
–
I/O
RS1
O
SCKF0
I/O
TMOUT2
O
–
–
I/O
RT1
O
SSF0
I/O
TMOUT3
O
–
–
I/O
SDAF0
I/O
SOUT0
O
–
–
–
–
I/O
SCLF0
I/O
SIN0
I
–
–
–
–
I/O
RXDF0
I
SCK0
I/O
TMOUT4
O
–
–
I/O
TXDF0
O
32kCLKO
O
TMOUT5
O
–
–
I/O
SDA1
I/O
SOUTF0
O
–
–
–
–
I/O
SCL1
O
SINF0
I
–
–
–
–
I/O
RXD0
I
SCKF0
I/O
TMOUT6
O
–
–
I/O
TXD0
O
SSF0
I/O
TMOUT7
O
–
–
O
–
–
–
–
–
–
–
–
I/O
COM4
O
–
–
–
–
–
–
I/O
COM5
O
–
–
–
–
–
–
I/O
COM6
O
–
–
–
–
–
–
P00/
EXI00/
AIN8
P01/
EXI01/
AIN9
P02/
EXI02/
AIN10
P03/
EXI03/
AIN11
P04/
EXI04
P05/
EXI05
P20/
EXI20/
AIN4
P21/
EXI21/
AIN5
P22/
EXI22/
AIN6
P23/
EXI23/
AIN7
P30/
EXI30/
CMP0P
VVLSP
P31/
EXI31/
CMP0M
P32/
EXI32/
CMP1P/
AIN2
P33/
EXI33/
CMP1M/
AIN3
P34/
EXI34/
AIN0
LED
P35/
EXI35/
AIN1
LED
P36/
EXI36/
TMCKI4
P37/
EXI37/
TMCKI5
COM0 to COM3
P60/
EXI60
P61/
EXI61
P62/
EXI62
P63/
EXI63
I/O
COM7
O
–
–
–
–
–
–
SEG0 to SEG33
O
–
–
–
–
–
–
–
–
P40/
EXI40/
LED
I/O
SDAF0
I/O
SOUT0
O
–
–
SEG34
O
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PIN
No.
.Reset
State
Primary Function
Pin name
Secondary Function
Tertiary Function
Quaternary Function
Quinary Function
I/O
Pin name
I/O
pin name
I/O
pin name
I/O
pin name
I/O
I/O
SCLF0
I/O
SIN0
I
–
–
SEG35
O
I/O
RXDF0
I
SCK0
I/O
TMOUT8
O
SEG36
O
I/O
TXDF0
O
32kCLKO
O
TMOUT9
O
SEG37
O
I/O
SDA1
I/O
SOUTF0
O
–
–
SEG38
O
I/O
SCL1
O
SINF0
I
–
–
SEG39
O
I/O
RXD0
I
SCKF0
I/O
TMOUTA
O
SEG40
O
I/O
TXD0
O
SSF0
I/O
TMOUTB
O
SEG41
O
I/O
SDAF0
I/O
SOUT0
O
–
–
SEG42
O
I/O
SCLF0
I/O
SIN0
I
–
–
SEG43
O
I/O
RXDF0
I
SCK0
I/O
TMOUTC
O
SEG44
O
Hi-Z
output
Hi-Z
output
Hi-Z
output
P41/
EXI41/
LED
P42/
EXI42/
TMCKI0
P43/
EXI43/
TMCKI1
P44/
EXI44
P45/
EXI45
P46/
EXI46/
TMCKI2
P47/
EXI47/
TMCKI3
P50/
EXI50
P51/
EXI51
P52/
EXI52
60
Hi-Z
output
P53/
EXI53
I/O
TXDF0
O
32kCLKO
O
TMOUTD
O
SEG45
O
61
Hi-Z
output
P54/
EXI54
I/O
SDA1
I/O
SOUTF0
O
–
–
SEG46
O
62
Hi-Z
output
I/O
SCL1
O
SINF0
I
–
–
SEG47
O
63
Hi-Z
output
I/O
RXD0
I
SCKF0
I/O
TMOUTE
O
SEG48
O
64
Hi-Z
output
P55/
EXI55
P56/
EXI56/
TMCKI6
P57/
EXI57/
TMCKI7
I/O
TXD0
O
SSF0
I/O
TMOUTF
O
SEG49
O
DP
I/O
–
–
–
–
–
–
–
–
50
Hi-Z
output
51
Hi-Z
output
52
Hi-Z
output
53
54
Hi-Z
output
Hi-Z
output
55
Hi-Z
output
56
Hi-Z
output
57
58
59
66
67
69
3
4
5
1
2
71
72
Hi-Z
output
Hi-Z
output
Low
output
–
–
–
–
–
–
–
DM
I/O
–
–
–
–
–
–
–
–
PUCTL
O
–
–
–
–
–
–
–
–
VL1
VL2
VL3
C1
C2
CH1
CH2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
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■ PIN DESCRIPTION
In the table below indicates the functional pin description.
The pin name represents the function pin name of the primary function of each terminal, The pin mode represents the set of
mode register of Port Control.
(1st:primary function, 2nd:secondary function, 3rd: tertiary function, 4th: quaternary function, 5th:quinary function)
Pin name
System
RESET_N
I/O
Description
Reset input pin. When this pin is set to a “L” level,
system reset mode is set and the internal section is
initialized. When this pin is set to a “H” level
subsequently, program execution starts. A pull-up
resistor is internally connected.
BRMP
I Remapping control input (for firmware update)
Based on the BRMP pin setting at the time of the reset
release, Bank0 is remapped.
Crystal connection pin for low-speed clock.
XT0
I
XT1
O Capacitors CDL and CGL are connected across this pin
and VSS as required.
Low-speed clock output pin
32kCLKO
O
General-purpose input/output port
P00-P05
I/O General-purpose input/output port.
P20-P23
I/O General-purpose input/output port.
P30-P37
I/O General-purpose input/output port.
P40-P47
I/O General-purpose input/output port.
P50-P57
I/O General-purpose input/output port.
P60-P63
I/O General-purpose input/output port.
External interrupt
EXI00-05
I External maskable interrupt input pins. It is possible, for
each bit, to specify whether the interrupt is enabled and
EXI20-23
select the interrupt edge by software.
EXI30-37
I
EXI40-47
EXI50-57
EXI60-63
LED
LED
O
UART
TXD0
O
RXD0
I
TXDF0
O
RXDF0
I
2
I C bus interface
SDA1
I/O
SCL1
SDAF0
SCLF0
LSI pin name
Pin mode
Logic
RESET_N
–
L
BRMP
–
H
–
–
–
–
XT0
XT1
P33,P43,P53
2
nd
st
P00-P05
P20-P23
P30-P37
P40-P47
P50-P57
P60-P63
1
st
1
st
1
st
1
st
1
st
1
P00-P05
P20-P23
P30-P37
P40-P47
P50-P57
P60-P63
1
st
N-channel open drain output pins to drive LED.
P34,P35,P40,P41
1
st
UART data output pin.
UART data input pin.
UARTF with FIFO data output pin.
UARTF with FIFO data input pin.
P37,P47,P57
P36,P46,P56
P01,P33,P43,P53
P00,P32,P42,P52
2
nd
2
nd
2
nd
2
I2C1 data input/output pin. This pin has an NMOS open
drain output. When using this pin as a function of the
2
I C, externally connect a pull-up resistor.
O I2C1 clock output pin. This pin has an NMOS open
drain output. When using this pin as a function of the
2
I C, externally connect a pull-up resistor.
I/O I2CF0 data input/output pin. This pin has an NMOS
open drain output. When using this pin as a function of
2
the I C, externally connect a pull-up resistor.
I/O I2CF0 clock input/output pin. This pin has an NMOS
open drain output. When using this pin as a function of
2
the I C, externally connect a pull-up resistor.
nd
P34,P44,P54
2
nd
P35,P45,P55
2
nd
P30,P40,P50
2
nd
P31,P41,P51
2
nd
–
–
–
–
–
–
H/L
–
–
–
–
–
–
–
–
–
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ML630Q464/Q466
Pin name
I/O
Synchronous serial
SCK0
I/O
SIN0
I
SOUT0
O
SCKF0
I/O
SINF0
SOUTF0
SSF0
Description
Synchronous serial (SSIO) clock input/output pin.
Synchronous serial (SSIO) data input pin.
Synchronous serial (SSIO) data output pin.
Synchronous serial with FIFO (SSIOF) clock
input/output pin.
I Synchronous serial with FIFO (SSIOF) data input pin.
O Synchronous serial with FIFO (SSIOF) data output pin.
I/O Synchronous serial with FIFO (SSIOF) select
input/output pin.
FTM
TMOUT0-9
TMOUTA-F
O
FTM output pin.
TMCKI0-7
I
External clock input pin for FTM.
LSI pin name
Pin mode
P02,P32,P42,P52
P01,P31,P41,P51
P00,P30,P40,P50
P22,P36,P46,P56
3
rd
3
rd
3
rd
3
P21,P35,P45,P55
P20,P34,P44,P54
P23,P37,P47,P57
3
rd
3
rd
3
P02,P03,P22,P23
P32,P33,P36,P37
P42,P43,P46,P47
P52,P53,P56,P57
P42,P43,P46,P47
P36,P37,P56,P57
4
rd
rd
th
1
st
Logic
–
–
–
–
–
–
L
–
–
RC oscillation type A/D converter
IN0
I
Oscillation input pin of Channel 0.
P00
2
nd
CS0
O
Reference capacitor connection pin of Channel 0.
P01
2
nd
RS0
O
Reference resistor connection pin of Channel 0.
P03
2
nd
RT0
O
P04
2
nd
RCT0
O
P02
2
nd
RCM
O
Resistor sensor connection pin for measurement of
Channel 0.
Resistor/capacitor sensor connection pin of Channel 0
for measurement.
RC oscillation monitor pin.
P05
2
nd
IN1
I
Oscillation input pin of Channel 1.
P20
2
nd
CS1
O
Reference capacitor connection pin of Channel 1.
P21
2
nd
O
Reference resistor connection pin of Channel 1.
2
nd
2
nd
RS1
P22
Resistor sensor connection pin for measurement of
Channel 1.
Successive approximation type A/D converter
P23
Reference power supply pin for successive
approximation type A/D converter.
Analog input for successive approximation type A/D
converter.
VREF
RT1
O
VREF
I
AIN0-11
I
–
(AIN0-3) P32-35,
(AIN4-7) P20-23,
(AIN8-11) P00-03
1
st
–
–
–
–
–
–
–
–
–
–
–
–
Analog comparator
CMP0P
I
Comparator0 Non-inverted input pin.
P30
1
st
CMP0M
I
Comparator0 Inverted input pin.
P31
1
st
CMP1P
I
Comparator1 Non-inverted input pin.
P32
1
st
CMP1M
I
Comparator1 Inverted input pin.
P33
1
st
–
–
–
–
USB FS Device
DP
DM
PUCTL
I/O USB dev D+ pin.
I/O USB dev D- pin.
O
USB dev pull-up control
DP
–
–
DM
–
–
PUCTL
–
–
SWC
–
–
SWD
–
–
DEBUG Interface
SWC
SWD
I
Serial clock of Serial Wire Debug Port
I/O Serial I/O data of Serial Wire Debug Port
10/37
FEDL630Q464-01
ML630Q464/Q466
Pin name
Power supply
VSS
VDD
VDDL
VHF
CH1 – CH2
LCD driver
COM0 –
COM3
COM4 –
COM7
SEG0 –
SEG33
SEG34 –
SEG49
C1 – C2
VL1 – VL3
I/O
Description
LSI pin name
–
Negative power supply pin.
Positive power supply pin.
Positive power supply pin (internally generated) for
internal logic. Capacitors CL is connected between this
pin and VSS.
Positive power supply pin (internally generated) for
built-in halver circuit. Capacitor CVH is connected
between this pin and VSS.
Capacitor pins of built-in halver circuit
–
Common pins of LCD driver
COM0 – COM3
–
Common pins of LCD driver
P60-P63
–
Segment pins of LCD driver
SEG0 – SEG33
–
Segment pins of LCD driver
P40-P47
P50-P57
C1 – C2
VL1 – VL3
–
–
–
–
–
–
Capacitor pins of built-in generation bias circuit
Reference voltage input pins of built-in bias generation
circuit
VSS
VDD
VDDL
Pin
mode
Logic
–
–
–
–
–
–
VHF
–
–
CH1 – CH2
–
–
–
–
2
nd
–
5
th
–
–
–
–
–
–
–
11/37
FEDL630Q464-01
ML630Q464/Q466
■ TERMINATION OF UNUSED PINS
Table 1 shows methods of terminating the unused pins.
Table 1 Termination of Unused Pins
Pin
RESET_N
BRMP
SWC
SWD
VREF
P00 to P05
P20 to P23
P30 to P37
P40 to P47
P50 to P57
P60 to P63
COM0 to COM3
SEG0 to SEG33
DP, DM, PUCTL
VL1, VL2, VL3
C1, C2
Recommended pin termination
open
Connect a pull-down resistor.
Connect a pull-up resistor.
Connect a pull-up resistor.
Connect to VDD
open
open
open
open
open
open
open
open
open
open
open
[Note]
For unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance
inputs and left open, the supply current may become excessively large. Therefore, it is recommended to configure
those pins as either inputs with a pull-down resistor/pull-up resistor or outputs.
12/37
FEDL630Q464-01
ML630Q464/Q466
■ Electrical Characteristics
● ABSOLUTE MAXIMUM RATINGS
（VSS=0V）
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage 1
VDD
Ta=25°C
-0.3 to +4.6
V
Power supply voltage 2
VDDL
Ta=25°C
-0.3 to +2.0
V
Power supply voltage 3
VL1-3
Ta=25°C
-0.3 to +6.0
V
VIN
Ta=25°C
-0.3 to VDD+0.3
V
Input voltage (5 V tolerant)
(P36, P37, P40-P47,
P50-P57, P60-P63)
VINT
Ta=25°C
-0.3 to +6.0
V
Output voltage 1
VOUT1
Ta=25°C
-0.3 to VDD+0.3
V
Output voltage 2
(COM0 to COM7
SEG0 to SEG49)
VOUT2
Ta=25°C
-0.3 to VL1-3+0.3
V
Output current 1
IOUT1
Ta=25°C
-12 to +11
mA
Output current 2
IOUT2
Ta=25°C
-12 to +20
mA
Power dissipation
PD
Ta=25°C
0.9
W
Storage temperature
TSTG
–
-55 to +150
°C
Input voltage(P00-P05,
P20-P23,
P30-P35,
SWC, SWD, BRMP,
RESET_N, DP, DM)
13/37
FEDL630Q464-01
ML630Q464/Q466
● RECOMMENDED OPERATING CONDITIONS
（VSS=0V）
Parameter
Symbol
Condition
Range
Unit
Operating temperature
(Ambience)
TOP
–
-40 to +85
°C
Operating voltage
VDD
–
1.8 to 3.6
V
Reference voltage
VREF
–
1.8 to VDD
V
fOP
–
LSCLK:32.768k
HSCLK:500k to 24M
Hz
fXTL
–
32.768k
Hz
Operating frequency
(CPU)
Low speed crystal
oscillation frequency
Low speed crystal
oscillation external
capacitor 1
Low speed crystal
oscillation external
capacitor 2
*1
Low speed crystal
oscillation external
capacitor 3
VDDL external capacitor
VL1,2,3pin
external capacitor
C1-C2
external capacitor
CH1, CH2
external capacitor
VHF
external capacitor
CDL
CGL
CDL
CGL
CDL
CGL
*2
Using VT-200-FL(from SII）
Using DT-26(from Daishinku)
Using VT-200-F(from SII）
6.8 to 12
6.8 to 12
12 to 16
12 to 16
12 to 22
12 to 22
pF
pF
pF
CL
ESR ≦500mΩ
2.2 ± 30%
µF
Ca,b,c
–
1.0 ± 30%
µF
C12
–
1.0 ± 30%
µF
CH12
–
1.0 ± 30%
µF
CHF
–
1.0 ± 30%
µF
*1 : Please use this crystal except DEEPHALT mode because this LSI may not be functioning at DEEPHALT mode with the crystal.
Please evaluate the matching when other crystal oscillator/ceramic oscillator is used.
*2：Please evaluate on user’s conditions, put on CL0( = 0.1uF) if necessary.
14/37
FEDL630Q464-01
ML630Q464/Q466
●
Operating Conditions of Flash Memory
Parameter
Symbol
Operating temperature
(Ambience)
TOP
Operating voltage
Write time
Erase unit
（VSS= 0V）
Unit
Condition
Range
Data area : write/erase
-40 to +85
°C
Program area : write/erase
0 to +40
°C
VDD
Write/erase
1.8 to 3.6
V
CEPD
Data area (1,024B x 2)
10,000
times
CEPP
Program area
100
times
–
Block erase
Program area
8
Data area
2
KB
Sector erase
1
KB
Erase time(Maximum)
–
Block erase/Sector erase
100
ms
Write unit
–
–
1 word (4 byte)
–
15/37
FEDL630Q464-01
ML630Q464/Q466
● AC characteristics (Oscillation, reset)
Parameter
Symbol
Low speed crystal
oscillation start time
TXTL
Low speed built-in RC
*1*2*3
oscillation frequency
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
Condition
Unit
circuit
Max.
Min.
Typ.
–
–
–
2
Ta=25°C
Typ
-1.5%
32.768
Typ
+1.5%
Ta=-40 to 85°C
typ-5%
32.768
typ+5%
Ta=25°C
typ
-1%
16
typ
+1%
Ta=-40 to 85°C
typ
-5%
16
typ
+5%
fLCR
s
kHz
High speed build-in RC
*1*2
oscillation frequency
fHCR
PLL frequency
fPLL
fXTL=32.768kHz
typ
-0.25%
24
typ
+0.25%
MHz
Low speed crystal
oscillation stop
detection time
TSTOP
–
–
600
–
µs
Reset pulse width
PRST
–
200
–
–
µs
Reset noise elimination
pulse width
PNRST
–
–
–
0.3
µs
Power-on reset activation
power rise time
TPOR
–
–
–
10
ms
MHz
1
*1 : Mean value of 1024 cycle.
*2 : Guarantee value at the time of the shipment.
*3 : Except DeepHALT mode and Ultra-DeepHALT mode.
VDD
0.9*VDD
0.3*VDD
RESET_N
0.3*VDD
PRST
0.3*VDD
PRST
External reset sequence
0.9*VDD
VDD
0.1*VDD
TPOR
Power on reset sequence
16/37
FEDL630Q464-01
ML630Q464/Q466
DC Characteristics (IDD)
●
Parameter
Symbol
Power
consumption 1
IDD1
IDD2-1
Power
consumption 2
IDD2-2
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
*1
Rating
Measuring
Condition
Unit
circuit
Min.
Typ. Max.
CPU is Stopped
Low/High-speed oscillation is stopped
ULTRA-DEEP-HALT mode *3*4
(LBTC function)
Low-speed crystal oscillating
(32.768kHz)
High-speed oscillation is stopped.
2.5V≦VDD
DEEP-HALT mode *3*4
(LBTC function)
Low-speed crystal oscillating
(32.768kHz)
High-speed oscillation is stopped.
HALT mode *3*4
(LTBC function)
Low-speed crystal oscillating
(32.768kHz)
High speed oscillation is stopped.
Power
consumption 3
IDD3
Power
consumption 4
IDD4
CPU Low-speed *2*4
Low-speed crystal oscillating
High speed oscillation is stopped.
Power
consumption 5
IDD5
CPU High-speed(16MHz) *2*4
High-speed Built-in RC oscillating
Power
consumption 5
IDD5
CPU High-speed(24MHz) *2*4
High-speed PLL oscillating
Ta=25°C
–
0.70
2.5
Ta=-40 to 85°C
–
–
28
Ta=25°C
–
0.80
2.5
Ta=-40 to 85°C
–
–
20
Ta=25°C
–
1.30.
3.0
Ta=-40 to 85°C
–
–
28
Ta=25°C
–
2.2
5.0
Ta=-40 to 85°C
–
–
32
Ta=25°C
–
9.0
14
Ta=-40 to 85°C
–
–
45
Ta=25°C
–
3.8
5.0
Ta=-40 to 85°C
–
–
5.5
Ta=25°C
–
6.0
7.0
Ta=-40 to 85°C
–
–
7.5
µA
µA
µA
1
µA
µA
mA
mA
1
* ：typ.rating is VDD=3.0V
2
* ：at CPU activity rate =100%（No HALT state）
3
* : using 32.768KHz crystal oscillator VT-200-FL (from SII)(CGL/CDL＝12pF)
using 32.768KHz crystal oscillator DT-26(from Daishinku)(CGL/CDL＝12pF）
4
* : CLKCON valid bits are “0”, RSTCON valid bits are “1”
17/37
FEDL630Q464-01
ML630Q464/Q466
●
DC Characteristics (VLS)
Parameter
Symbol
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
Condition
Unit
circuit
Min.
Typ.
Max.
*1
1.200
*1
1.225
*1
1.250
*1
1.275
*1
1.300
*1
1.325
VLSLV[5:0] = 00H
VLSLV[5:0] = 01H
VLSLV[5:0] = 02H
VLSLV[5:0] = 03H
VLSLV[5:0] = 04H
VLSLV[5:0] = 05H
*1
1.350
*1
1.375
*1
1.400
*1
1.425
*1
1.450
*1
1.475
*1
1.500
*1
1.525
*1
1.550
VLSLV[5:0] = 06H
VLSLV[5:0] = 07H
VLSLV[5:0] = 08H
VLSLV[5:0] = 09H
VLSLV[5:0] = 0AH
VLSLV[5:0] = 0BH
VLSLV[5:0] = 0CH
VLSLV[5:0] = 0DH
VLSLV[5:0] = 0EH
*1
1.575
*1
1.600
*1
1.625
*1
1.650
*1
1.675
*1
1.700
VLSLV[5:0] = 0FH
VLSLV[5:0] = 10H
VLSLV[5:0] = 11H
VLSLV[5:0] = 12H
VLSLV[5:0] = 13H
VLSLV[5:0] = 14H
VLS judge
voltage
(VDD=fall)
*1
VLSLV[5:0] = 15H
VVLS
*1
VLSLV[5:0] = 16H
*1
VLSLV[5:0] = 17H
Typ.
-3%
1.725
1.750
1.775
VLSLV[5:0] = 18H
1.800
VLSLV[5:0] = 19H
1.825
VLSLV[5:0] = 1AH
1.850
VLSLV[5:0] = 1BH
1.875
VLSLV[5:0] = 1CH
1.900
VLSLV[5:0] = 1DH
1.925
VLSLV[5:0] = 1EH
1.950
VLSLV[5:0] = 1FH
1.975
VLSLV[5:0] = 20H
2.000
VLSLV[5:0] = 21H
2.050
VLSLV[5:0] = 22H
2.100
VLSLV[5:0] = 23H
2.150
VLSLV[5:0] = 24H
2.200
VLSLV[5:0] = 25H
2.250
VLSLV[5:0] = 26H
2.300
VLSLV[5:0] = 27H
2.350
VLSLV[5:0] = 28H
2.400
VLSLV[5:0] = 29H
2.450
VLSLV[5:0] = 2AH
2.500
VLSLV[5:0] = 2BH
2.550
VLSLV[5:0] = 2CH
2.600
Typ.
+3%
V
1
18/37
FEDL630Q464-01
ML630Q464/Q466
VLSLV[5:0] = 2DH
2.650
VLSLV[5:0] = 2EH
2.700
VLSLV[5:0] = 2FH
2.750
VLSLV[5:0] =30H
2.800
VLSLV[5:0] = 31H
2.850
VLSLV[5:0] = 32H
2.900
VLSLV[5:0] = 33H
2.950
VLSLV[5:0] = 34H
3.000
VLSLV[5:0] = 35H
VLSLV[5:0] = 36H
VLSLV[5:0] = 37H
Typ.
-3%
Parameter
Symbol
LLD judge Voltage
VLLR
3.100
3.150
VLSLV[5:0] = 38H
3.200
VLSLV[5:0] = 39H
3.250
VLSLV[5:0] = 3AH
3.300
VLSLV[5:0] = 3BH
3.350
VLSLV[5:0] = 3CH
3.400
VLSLV[5:0] = 3DH
3.450
VLSLV[5:0] = 3EH
3.500
VLSLV[5:0] = 3FH
VVLS Hysteresis
VVLS
–
width
HVLS
X
1.0%
(VDD=rise)
VLSLV[3:0] are bits of the VLSCON register to change detection voltage level.
*1
: Setable only at the time of select to VVLSP pin.
● DC characteristics (LLD)
3.050
Typ.
+3%
V
1
3.550
VVLS
X
2.7%
VVLS
X
4.5%
V
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
Condition
Unit
circuit
Max.
Min.
Typ.
–
1.60
1.80
2.00
V
1
● DC/AC characteristics (Analog comparator)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
Condition
Unit
circuit
Min.
Typ.
Max.
Parameter
Symbol
Common Input
voltage range
VCMPIN
–
0.2
–
VDD
-0.2
V
Input offset voltage
VCMPOF
–
-30
–
30
mV
Comparator judge
time
TCMP
CMPP- CMPM =40mV
–
–
2
µs
1
19/37
FEDL630Q464-01
ML630Q464/Q466
●
DC characteristics (LCD Driver)
Parameter
VL1 voltage
VL1 temperature
1
deviation*
VL1 voltage
1
dependency*
Symbol
VL1
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
Condition
Unit
circuit
Min.
Typ.
Max.
LCN[4:0] = 00H*2
0.89
0.94
0.99
LCN[4:0] = 01H*2
0.91
0.96
1.01
LCN[4:0] = 02H*2
0.93
0.98
1.03
LCN[4:0] = 03H*2
0.95
1.00
1.05
LCN[4:0] = 04H*2
0.97
1.02
1.07
LCN[4:0] = 05H*2
0.99
1.04
1.09
LCN[4:0] = 06H*2
1.01
1.06
1.11
LCN[4:0] = 07H*2
1.03
1.08
1.13
LCN[4:0] = 08H*2
1.05
1.10
1.15
LCN[4:0] = 09H*2
1.07
1.12
1.17
LCN[4:0] = 0AH*2
1.09
1.14
1.19
LCN[4:0] = 0BH*2
1.11
1.16
1.21
LCN[4:0] = 0CH*2
1.13
1.18
1.23
LCN[4:0] = 0DH*2
1.15
1.20
1.25
LCN[4:0] = 0EH*2
1.17
1.22
1.27
LCN[4:0]
=
0FH*
2
1.19
1.24
1.29
VDD = 3.0V,
V
Tj = 25°C
LCN[4:0] = 10H
1.21
1.26
1.31
LCN[4:0] = 11H
1.23
1.28
1.33
LCN[4:0] = 12H
1.25
1.30
1.35
LCN[4:0] = 13H
1.27
1.32
1.37
LCN[4:0] = 14H
1.29
1.34
1.39
1
LCN[4:0] = 15H
1.31
1.36
1.41
LCN[4:0] = 16H
1.33
1.38
1.43
LCN[4:0] = 17H
1.35
1.40
1.45
LCN[4:0] = 18H
1.37
1.42
1.47
LCN[4:0] = 19H
1.39
1.44
1.49
LCN[4:0] = 1AH
1.41
1.46
1.51
LCN[4:0] = 1BH
1.43
1.48
1.53
LCN[4:0] = 1CH
1.45
1.50
1.55
LCN[4:0] = 1DH
1.47
1.52
1.57
LCN[4:0] = 1EH
1.49
1.54
1.59
LCN[4:0] = 1FH
1.51
1.56
1.61
∆VL1
VDD = 3.0V
–
−0.06
–
%/°C
∆VL1
VDD = 1.8 to 3.6V
–
5
20
mV/V
VDD = 3.0V, Tj = 25°C
1MΩ load (VL3−VSS)
Typ.
−10%
Typ.
−10%
Typ.
+4%
Typ.
+4%
V
VL2 voltage
VL2
VL3 voltage
VL3
VL1×2
VL1×3
LCD bias voltage
TBIAS
–
–
–
600
ms
generation time
1
* :VL1 can not exceed VDD level. The maximum VL1 becomes VDD level when the VL1 calculated by the temperature deviation
and voltage dependency is going to exceed the VDD level.
2
* : 1/3 bias only.
20/37
FEDL630Q464-01
ML630Q464/Q466
●
DC characteristics (VOHL, IOHL)
Parameter
Output voltage 1
( P00-P05, P20-P23,
P30-P37, P40-P47,
P50-P57,, P60-P63,
SWD,PUCTL)
Symbol
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
Condition
Unit
circuit
Min.
Typ.
Max.
VOH1
IOH=-1.0mA
VDD
-0.5
–
–
VOL1
IOL=+0.5mA
–
–
0.4
2.7V ≤VDD ≤3.6V IOL=+5.0mA
–
–
0.6
IOL=+2.0mA
–
–
0.4
–
–
0.4
Output voltage 2
( P34, P35,
P40, P41 )
(LED mode
is selected)
VOL2
Output voltage 3
(P30, P31, P34, P35,
P40, P41, P44, P45,
P50, P51, P54, P55 )
2
(I C mode is
selected)
VOL3
IOL3= +3mA (I Cspec)
(VDD ≥2V)
Output voltage 4
( P30, P31, P34, P35,
P40, P41, P44, P45,
P50, P51, P54, P55 )
2
(I C mode is
selected)
VOL4
IOL4= +2mA(I Cspec)
(VDD < 2V)
–
–
VDD
×0.2
VOH5
1/3bias, IOH5=-0.02mA,
VL1=1.2V
VL3
-0.2
–
–
VOM5
1/3bias, IOM5=+0.02mA,
VL1=1.2V
–
–
VL2
+0.2
VOM5S
1/3bias, IOM5S=-0.02mA,
VL1=1.2V
VL2
-0.2
–
–
VOML5
1/3bias, IOML5=+0.02mA,
VL1=1.2V
–
–
VL1
+0.2
VOML5S
1/3bias, IOML5S=-0.02mA,
VL1=1.2V
VL1
-0.2
–
–
VOL5
1/3bias, IOL5=+0.02mA,
VL1=1.2V
–
–
0.2
VOH5
1/2bias, IOH5=-0.01mA,
VL1=1.4V
VL3
-0.3
―
―
VOM5
1/2bias, IOM5=+0.01mA,
VL1=1.4V
―
―
VL2
+0.3
VOM5S
1/2bias, IOM5S=-0.01mA,
VL1=1.4V
VL2
-0.3
―
―
VOML5
1/2bias, IOML5=+0.01mA,
VL1=1.4V
―
―
VL1
+0.3
VOML5S
1/2bias, IOML5S=-0.01mA,
VL1=1.4V
VL1
-0.3
―
―
VOL5
1/2bias, IOL5=+0.01mA,
VL1=1.4V
―
―
0.3
Output voltage 5
(COM0～7)
(SEG00～49)
(LCD mode is
selected)
Output voltage 5
(COM0～7)
(SEG00～49)
(LCD mode is
selected)
2
2
V
2
21/37
FEDL630Q464-01
ML630Q464/Q466
Output leak 1
( P00-P05,
P20-P23,
P30-P37,
P40-P47,
P50-P57,
P60-P63,
SWD,PUCTL )
IOOH1
VOH=VDD (at high impedance)
–
–
+1
µA
IOOL1
VOL=VSS (at high impedance)
-1
–
3
–
22/37
FEDL630Q464-01
ML630Q464/Q466
● DC characteristics (IIHL)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
Condition
Unit
circuit
Min.
Typ.
Max.
Parameter
Symbol
Input current 1
(RESET_N)
IIH1
VIH1=VDD
–
–
1
IIL1
VIL1=VSS
-900
-300
-20
Input current 3
IIH3
VIH3=VDD (at pull down)
1
15
200
IIL3
VIL3=VSS (at pull up)
-200
-15
-1
IIH3Z
VIH3=VDD
(at high impedance)
–
–
1
IIL3Z
VIL3=VSS
(at high impedance)
-1
–
–
IIH4Z
VIH4=5.0V
(at high impedance)
–
–
1
(P00-P05,
P20-P23,
P30-P37,
P40-P47,
P50-P57,
P60-P63,
SWC, SWD, BRMP)
µA
4
Input current 4
(P36, P37,
P40-P47,
P50-P57,
P60-P63)
1
* ：typ.rating is VDD=3.0V, Ta=25°C
●
DC characteristics (VIHL)
Parameter
Symbol
Input voltage 1
VIH1
(RESET_N,
SWD, SWC,
BRMP,
P00-P05,
P20-P23,
P30-P37,
P40-P47,
P50-P57,
P60-P63 )
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Measuring
Condition
Unit
circuit
Min.
Typ.
Max.
–
0.7
×VDD
–
VDD
VIL1
–
0
–
0.3
×VDD
CIN
f=10kHz
Vrms=50mV
Ta=25°C
–
–
10
V
5
pF
–
Input terminal
capacitance
(RESET_N,
SWD, SWC,
BRMP,
P00-P05,
P20-P23,
P30-P37,
P40-P47,
P50-P57,
P60-P63 )
23/37
FEDL630Q464-01
ML630Q464/Q466
● DC characteristics (USB)
(VDD=3.0 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Differential input sensitivity
VDI
Differential common mode range
Single end input threshold
voltage
*1
Unit
Min.
Typ.
Max.
Absolute value of the difference
between the DP and DM pins
0.2
-
-
V
VCM
Includes VDI range
0.8
-
2.5
V
VSE
-
0.8
-
2.0
V
High level output voltage
VOH
15k W RL is connected
to GND
2.8
-
-
V
Low level output voltage
VOL
1.5k W RL to 3.6 V
-
-
0.3
V
Hi-Z state input/output leakage
current
ILO
0 V < VIN < 3.3 V
-10
10
uA
ZDRV
Steady state
28
44
Ω
Driver output resistance
Measu
ring
circuit
24/37
FEDL630Q464-01
ML630Q464/Q466
● MEASURING CIRCUITS
MEASURING CIRCUIT1
CGL
XT0
32.768kHz
crystal
XT1
C2
CDL
C1
VDD
VDDL
V
C12
VSS
VL1 VL2 VL3
A
CV
CL
Ca Cb Cc
CV
: 1µF
CL
: 2.2µF
Ca,Cb,Cc
: 1µF
C12
: 1µF
CGL
: 12pF
CDL
:12pF
32.768kHz crystal oscilation:
(DT-26 from Daishinku)
MEASURING CIRCUIT 2
(*2)
VIL
Input pins
(*1)
Output pins
VIH
VDD VDDL VL1
VL2
VL3
V
VSS
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
25/37
FEDL630Q464-01
ML630Q464/Q466
MEASURING CIRCUIT 3
(*2)
Input pins
Output pins
VIH
(*1)
VIL
VDD VDDL VL1
VL2
VL3
A
VSS
*1: Input logic circuit to determine the specified measuring conditions.
*2: Measured at the specified output pins.
MEASURING CIRCUIT 4
Input pins
Output pins
(*3)
A
VDD VDDL VL1
VL2
VL3
VSS
*3: Measured at the specified output pins.
MEASURING CIRCUIT 5
VIL
Output pins
Input pins
(*1)
VDD VDDL VL1
VL2
VL3
VSS
Waveform monitoring
VIH
*1: Input logic circuit to determine the specified measuring conditions.
26/37
FEDL630Q464-01
ML630Q464/Q466
● AC characteristics (USB)
Parameter
Rise time (*1)
Fall time (*1)
Output
signal
voltage
crossover
(VDD=3.0 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Rating
Symbol
Condition
Unit
Min.
Typ.
Max.
TR
TF
CL = 50 pF
CL = 50 pF
4
4
–
–
20
20
ns
ns
VCRS
CL = 50 pF
0.8
–
2.5
V
Applied
pin
DP, DM
Average bit rate
11.97
–
12.03
Mbps
(12Mbps ±0.25%)
* 1: TR and TF: Rise time and fall time between 10% and 90% of the pulse amplitude, respectively
Data rate
TDRATE
27/37
FEDL630Q464-01
ML630Q464/Q466
● AC charctoristics (synchronous serial port)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Parameter
Symbol
SCK input cycle
(slave mode)
tSCYC
SCK output cycle
(master mode)
tSCYC
Rating
Conditon
Unit
Min.
Typ.
Max.
High-speed oscillation
is not active
10
–
–
µs
High-speed oscillation is active
500
–
–
ns
–
–
SCK*
–
s
High-speed oscillation
is not active
4
–
–
µs
High-speed oscillation is active
200
–
–
ns
1
SCK input pulse width
(slave mode)
tSW
SCK output pulse width
(master mode)
tSW
–
tSCYC
×0.4
tSCYC
×0.5
tSCYC
×0.6
s
SOUT output delay time
(slave mode)
tSD
–
–
–
180
ns
SOUT output delay time
(master mode)
tSD
–
–
–
80
ns
SIN input
Setup time
(slave mode)
tSS
–
50
–
–
ns
SIN input
Setup time
(master mode)
tSS
–
130
–
–
ns
SINinput
Hold time
tSH
–
50
–
–
ns
1
* : The clock period which is selected by the below registers(min:250ns@ regularly, min:500ns@P02,P22 is used)
In case of SSIO : S0CK2-0 of serial port 0 mode register(SIO0MOD).
In case of SSIOF : SF0BR9-0 of SIOF0 port register(SF0BRR)
tSCYC
tSW
tSW
SCK0/SCKF0
("0" during transmission/reception)
SCK0/SCKF0
("1" during transmission/reception)
tSD
tSD
SOUT0/SOUTF0
tSS
tSH
SIN0/SINF0
28/37
FEDL630Q464-01
ML630Q464/Q466
● AC characteristics（I2C Bus interface : Standard mode 100kHz）
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
Parameter
Symbol
Condition
SCL clock frequency
SCL hold time
(Start/restart condition)
SCL”L” level time
fSCL
tHD:STA
SCL”H” level time
SCL setup time
(restart condition)
SDA setup time
SDA setup time
(stop condition)
Bus-free time
Rating
Unit
Min.
Typ.
Max.
–
0
–
100
kHz
–
4.0
–
–
µs
tLOW
–
4.7
–
–
µs
tHIGH
–
4.0
–
–
µs
tSU:STA
–
4.7
–
–
µs
tSU:DAT
–
0.25
–
–
µs
tSU:STO
–
4.0
–
–
µs
tBUF
–
4.7
–
–
µs
● AC characteristics（I2C bus interface : fast mode 400kHz）
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified)
*1:
Parameter
Symbol
Condition
SCL clock frequency
fSCL
SCLhold time
(start/restart condition)
Rateing
Unit
Min.
Typ.
Max.
–
0
–
400
kHz
tHD:STA
–
0.6
–
–
µs
SCL”L” level time
tLOW
–
1.3
–
–
µs
SCL”H” level time
tHIGH
–
0.6
–
–
µs
SCL setup time
(restart condition)
tSU:STA
–
0.6
–
–
µs
SDA setup time
tSU:DAT
–
0.1
–
–
µs
SDA setup time
(stop condition)
tSU:STO
–
0.6
–
–
µs
Bus-free time
tBUF
–
1.3
–
–
µs
Only at the time of SYSCLK=16MHz or 24MHz
Start
condition
Restart
condition
Stop
condition
SDA
SCL
tHD:STA
tLOW
tHIGH
tSU:STA tHD:STA
tSU:DAT
tSU:STO
tBUF
29/37
FEDL630Q464-01
ML630Q464/Q466
● AC characteristics (RC-ADC)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40~+85°C, unless otherwise specified)
Rating
Symbol
Condition
unit
Min.
Typ.
Max.
RS0,RS1,RT0,
–
1
–
400
kΩ
RT0-1,RT1
Parameter
Resister for oscillation
Oscillation freqency
VDD = 3.0V
CVR=820pF
CS=560pF
fOSC1_0
Resister for oscillation
=1kΩ
–
528
–
kHz
fOSC2_0
Resister for oscillation
=10kΩ
–
59
–
kHz
fOSC3_0
Resister for oscillation
=100kΩ
–
5.9
–
kHz
Kf1_0
RT0, RT0-1, RT1=1kΩ
8.225
8.94
9.655
–
Kf2_0
RT0, RT0-1, RT1=10kΩ
0.99
1
1.01
–
Kf3_0
RT0, RT0-1, RT1=100kΩ
0.093
0.101
0.109
–
RS to RT oscillation
1
frequency ratio *
VDD = 3.0V
CVR=820pF
CS=560pF
1
* ：Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same
conditions.
Kfx =
fOSCX
(RT0-CS0 oscillation)
fOSCX
(RS0-CS0 oscillation)
( x = 1, 2, 3 )
fOSCX
(RT0-1-CS0 oscillation)
fOSCX
(RS0-CS0 oscillation)
,
fOSCX
(RT1-CS1 oscillation)
fOSCX
(RS1-CS1 oscillation)
,
Measuring circuit
IN0 CS0 RCT0
(*1)
Input pins
VIH
VIL
RT1
RS1
CS1
RT0
RS0 RT0
VDDL
RT0, RT0-1, RT1: 1kΩ/10kΩ/100kΩ
RS0, RS1: 10kΩ
CS0, CT0, CS1: 560pF
CVR0, CVR1: 820pF
IN1 CS1 RS1 RT1
RCM
VDD
CV
RS0
CVR1
RT0-1
CT0
CS0
CVR0
Measure frequency
(fOSCX)
VSS
CL1 CL0
(*1) Input logic circuit to determine the specified measuring conditions.
【Note】
・Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and
IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling capacitance on the
wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node.
・When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please shield the signal by VSS(GND).
・Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved components
may affect to the A/D conversion operation by noise the components itself may have.
30/37
FEDL630Q464-01
ML630Q464/Q466
●
AC characteristics (Low speed clock output)
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40~+85°C, unless otherwise specified)
Parameter
Symbol
Condition
Clock output frequency
tclk
–
Rating
Min.
Typ.
Max.
–
32.768
–
Unit
kHz
31/37
FEDL630Q464-01
ML630Q464/Q466
● Electrical Characteristics of SA-ADC
(VDD=1.8 to 3.6V, VSS=0V, Ta=-40~+85°C, unless otherwise specified)
Parameter
Symbol
Condition
Resolution
n
–
Integral non-linearity error
Rating
2.7V ≤ VREF ≤ 3.6V
2.2V ≤ VREF < 2.7V
1.8V ≤ VREF < 2.2V
(using Low-speed clock)
2.7V ≤ VREF ≤ 3.6V
2.2V ≤ VREF < 2.7V
1.8V ≤ VREF < 2.2V
(using Low-speed clock)
INL
Min.
Typ.
Max.
–
−4
−6
12
–
–
–
+4
+6
−10
–
+10
−3
−5
–
–
+3
+5
−9
–
+9
Unit
bit
Differential non-linearity
error
DNL
2.2V ≤ VREF ≤ 3.6V
−6
–
+6
Zero-scale error
VOFF
1.8V ≤ VREF < 2.2V
(using Low-speed clock)
−10
–
+10
2.2V ≤ VREF ≤ 3.6V
−6
–
+6
Full-scale error
FSE
−10
–
+10
Input impidance
RI
1.8V ≤ VREF < 2.2V
(using Low-speed clock)
–
–
–
5k
Ω
Reference voltage
VREF
–
1.8
–
VDD
V
Using High-speed clock(max. 4MHz)
–
170
–
Using Low-speed clock
–
16
–
Conversion time
tCONV
LSB
clk
Measuring circuit
VDD
Reference
Voltage
VREF
1μF
A
10μF
-
RI ≤ 5kΩ
AIN
+
0.47μF
VSS
32/37
FEDL630Q464-01
ML630Q464/Q466
●
Power-on and shutdown Procedures
In case of power-on or shutdown of VDD, the procedures and constraints are shown as following.
0.9*VDD
VDD
0.1*VDD
30mV or less
(VSS = 0)
TPOR
VDDL
100mV or less
(VSS = 0)
Power down/on and power on reset sequence
Note:
If VDDL level is 100mV or more over, reset the IC by RESET_N pin after power-on.
33/37
FEDL630Q464-01
ML630Q464/Q466
APPLICATION CIRCUIT EXAMPLE
3.3V
P00/IN0
VDD
CS0
P01/CS0
CV
RESET_N
CL
RT0
P04/RT0
P02/RCT0
P05/RCM
VDDL
CL0
P20/IN1
CS1
P21/CS1
CH1
CH12
ML630Q464/
CH2
CGL
CDL
RT1
P23/RT1
P30/SDAF0
P31/SCLF0
Vss
P32
XT0
(Output)
XL
32.768KHz
Xtal
CVR1
RS1
P22/RS1
Q466
VHF
CVH
CVR0
RS0
P03/RS0
RESET_N
WP SDA
SCL
Vcc
2
I C EEPROM
XT1
A0 A1 A2
Vss
SWC
SWD
VREF
C1 C2
VL1 VL2 VL3
P34
/LED
P35
/LED
CAV
Ca Cb Cc
C12
LED
CV
CL
CGL,CDL
Ca~Cc
CH12
CAV
CS0, CS1
RT0, RT1
XL
: 1uF*
: 2.2uF
: 12 to 16pF*
: 1uF*
: 1uF*
: 1uF*
: 560 pF
: Thermistor (103AT/Semitec)
: DT-26, Daishinku
CL0
: open*
C12
CVH
RS0, RS1
CVR0, CVR1
: 1uF*
: 1uF*
: 10 KΩ
: 820 pF
*: Make a decision the parameters after evaluating on user’s conditions when designing circuits for mass production.
34/37
FEDL630Q464-01
ML630Q464/Q466
PACKAGE DIMENSIONS
ML630Q464/Q466 PACKAGE DIMENSIONS
Figure B-1
TQFP100
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number,
package code and desired mounting conditions(reflow method, temperature and times).
35/37
FEDL630Q464-01
ML630Q464/Q466
REVISION HISTORY
Document No.
Date
FEDL630Q464-01
Oct. 26. 2016
Page
Previous Current
Edition
Edition
-
-
Description
Final Edition
36/37
FEDL630Q464-01
ML630Q464/Q466
Notes
1) The information contained herein is subject to change without notice.
2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can
break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure,
please take safety measures such as complying with the derating characteristics, implementing redundant and fire
prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for
any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor.
3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate
the standard usage and operations of the Products.The peripheral conditions must be taken into account when designing
circuits for mass production.
4) The technical information specified herein is intended only to show the typical functions of the Products and examples of
application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property
rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this
document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights
owned by third parties, arising out of the use of such technical information.
5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems,
gaming/entertainment sets) as well as the applications indicated in this document.
6) The Products specified in this document are not designed to be radiation tolerant.
7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and
consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary
communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and
power transmission systems.
8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power
control systems, and submarine repeaters.
9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the
recommended usage conditions and specifications contained herein.
10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document.
However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have
no responsibility for any damages arising from any inaccuracy or misprint of such information.
11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.
For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no
responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.
12) When providing our Products and technologies contained in this document to other countries, you must abide by the
procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US
Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.
13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor.
Copyright
2016 LAPIS Semiconductor Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,
Yokohama 222-8575, Japan
http://www.lapis-semi.com/en/
37/37