LINER LTC3851 Synchronous step-down switching regulator controller Datasheet

LTC3851
Synchronous
Step-Down Switching
Regulator Controller
DESCRIPTION
FEATURES
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The LTC®3851 is a high performance synchronous
step-down switching regulator controller that drives
an all N-channel synchronous power MOSFET stage. A
constant frequency current mode architecture allows a
phase-lockable frequency of up to 750kHz.
Wide VIN Range: 4V to 38V Operation
RSENSE or DCR Current Sensing
±1% Output Voltage Accuracy
Phase-Lockable Fixed Frequency: 250kHz to 750kHz
Dual N-Channel MOSFET Synchronous Drive
Very Low Dropout Operation: 99% Duty Cycle
Adjustable Output Voltage Soft-Start or Tracking
Output Current Foldback Limiting
Output Overvoltage Protection
5V Internal Regulator
OPTI-LOOP® Compensation Minimizes COUT
Selectable Continuous, Pulse-Skipping or
Burst Mode® Operation at Light Loads
Low Shutdown IQ: 20μA
VOUT Range: 0.8V to 5.5V
16-Lead Narrow SSOP or 3mm × 3mm QFN Package
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The LTC3851 features a precision 0.8V
reference that is compatible with a wide 4V to 38V input
supply range.
The TK/SS pin ramps the output voltage during start-up.
Current foldback limits MOSFET heat dissipation during
short-circuit conditions. The MODE/PLLIN pin selects
among Burst Mode operation, pulse skipping mode or
continuous inductor current mode at light loads and allows
the IC to be synchronized to an external clock.
APPLICATIONS
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, LT, LTC, LTM, Burst Mode and OPTI-LOOP are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5408150, 5481178, 5705919, 5929620, 6304066,
6498466, 6580258, 6611131.
Automotive Systems
Telecom Systems
Industrial Equipment
Distributed DC Power Systems
TYPICAL APPLICATION
High Efficiency Synchronous Step-Down Converter
VIN
FREQ/PLLFLTR TG
RUN
VIN
4V TO 38V
150μF
0.68μH
0.22μF
0.1μF
330μF
10k
INTVCC
10nF
BG
ITH
1k
90
75
SENSE+
60
0.22μF
SENSE–
POWER LOSS
70
65
PLLIN/MODE
1000
80
GND
100pF
EFFICIENCY
85
POWER LOSS (mW)
LTC3851
BOOST
TK/SS
VIN = 12V
95 VOUT = 3.3V
VOUT
3.3V
10A
SW
10000
100
EFFICIENCY (%)
ILIM
Efficiency and Power Loss
vs Load Current
100
55
13k
62.5k
50
10
VFB
20k
100
1000
LOAD CURRENT (mA)
10
10000
3851TA01b
3851 TA01a
3851f
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LTC3851
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Supply Voltage (VIN) ......................... 40V to –0.3V
Topside Driver Voltage (BOOST) ................ 46V to –0.3V
Switch Voltage (SW) ..................................... 40V to –5V
INTVCC, (BOOST – SW), RUN ...................... 6V to –0.3V
TK/SS, ILIM............................................ INTVCC to –0.3V
SENSE+, SENSE–.......................................... 6V to –0.3V
MODE/PLLIN, FREQ/PLLFLTR ............... INTVCC to –0.3V
ITH, VFB Voltages .......................................... 3V to –0.3V
INTVCC Peak Output Current ..................................50mA
Operating Temperature Range (Note 2).... –40°C to 85°C
Junction Temperature (Note 3) ............................. 125°C
Storage Temperature Range
GN ..................................................... –65°C to 150°C
UD ......................................................... –65 to 125°C
Lead Temperature (Soldering, 10 sec)
GN .................................................................... 300°C
PIN CONFIGURATION
1
16 SW
2
15 TG
RUN
3
14 BOOST
TK/SS
4
13 VIN
ITH
5
12 INTVCC
ITH 3
FB
6
11 BG
FB 4
SENSE–
7
10 GND
SENSE+
8
9
TG
MODE/PLLIN
FREQ/PLLFLTR
SW
TOP VIEW
MODE/PLLIN
FREQ/PLLFLTR
TOP VIEW
16 15 14 13
RUN 1
12 BOOST
TK/SS 2
6
7
8
ILIM
GND
9
5
SENSE+
GN PACKAGE
16-LEAD PLASTIC SSOP NARROW
10 INTVCC
SENSE–
ILIM
11 VIN
17
BG
UD PACKAGE
16-LEAD (3mm s 3mm) PLASTIC QFN
TJMAX = 125°C, θJA = 90°C/W
TJMAX = 125°C, θJA = 68°C/W, θJC = 4.2°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3851EGN#PBF
LTC3851EGN#TRPBF
3851
16-Lead Plastic SSOP
–40°C to 85°C
LTC3851EUD#PBF
LTC3851EUD#TRPBF
LCXN
16-Lead (3mm × 3mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3851f
2
LTC3851
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
VIN
Operating Input Voltage Range
VFB
Regulated Feedback Voltage
ITH = 1.2V (Note 4)
IFB
Feedback Current
(Note 4)
VREFLNREG
Reference Voltage Line Regulation
VIN = 6V to 38V (Note 4)
VLOADREG
Output Voltage Load Regulation
(Note 4)
Measured in Servo Loop,
ΔITH = 1.2V to 0.7V
(Note 4)
Measured in Servo Loop,
ΔITH = 1.2V to 1.6V
gm
Transconductance Amplifier gm
l
4
l
0.792
38
V
0.800
0.808
V
–10
–50
nA
0.002
0.02
%/V
l
0.01
0.1
%
l
–0.01
–0.1
%
ITH = 1.2V, Sink/Source = 5μA (Note 4)
2
mmho
MHz
gm GBW
Transconductance Amp Gain Bandwidth
ITH = 1.2V
3
IQ
Input DC Supply Current
Normal Mode
Shutdown
(Note 5)
VOUT = 5V
VRUN = 0V
1.2
20
UVLO
Undervoltage Lockout on INTVCC
VINTVCC Ramping Down
3.25
V
UVLO Hys
UVLO Hysteresis
0.4
V
Measured at VFB
l
VOVL
Feedback Overvoltage Lockout
ISENSE
SENSE Pins Total Current
ITK/SS
Soft-Start Charge Current
VTK/SS = 0V
VRUN
RUN Pin On Threshold
VRUN Rising
l
VRUNHYS
RUN Pin On Hysteresis
l
l
l
0.86
35
mA
μA
0.88
0.90
V
±1
±2
μA
0.6
1
2
μA
1.10
1.22
1.35
V
130
20
40
65
30
50
75
mV
VSENSE(MAX)
Maximum Current Sense Threshold
VFB = 0.7V, VSENSE = 3.3V, ILIM = 0V
VFB = 0.7V, VSENSE = 3.3V, ILIM = Float
VFB = 0.7V, VSENSE = 3.3V, ILIM = INTVCC
40
65
90
mV
mV
mV
TG RUP
TG Driver Pull-Up On-Resistance
TG High
2.6
Ω
TG RDOWN
TG Driver Pull-Down On-Resistance
TG Low
1.5
Ω
BG RUP
BG Driver Pull-Up On-Resistance
BG High
2.4
Ω
BG RDOWN
BG Driver Pull-Down On-Resistance
BG Low
1.1
Ω
TG tr
TG tf
TG Transition Time
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
25
ns
ns
BG tr
BG tf
BG Transition Time
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
25
ns
ns
TG/BG t1D
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver
30
ns
BG/TG t2D
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver
30
ns
tON(MIN)
Minimum On-Time
(Note 7)
90
ns
INTVCC Linear Regulator
VINTVCC
Internal VCC Voltage
6V < VIN < 38V
VLDO INT
INTVCC Load Regulation
ICC = 0mA to 50mA
4.8
5
5.2
V
0.5
2
%
3851f
3
LTC3851
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillator and Phase-Locked Loop
fNOM
Nominal Frequency
RFREQ = 60k
480
500
530
kHz
fLOW
Lowest Frequency
RFREQ = 160k
220
250
280
kHz
fHIGH
Highest Frequency
RFREQ = 36k
710
750
790
kHz
RMODE/PLLIN
MODE/PLLIN Input Resistance
IFREQ
Phase Detector Output Current
Sinking Capability
Sourcing Capability
fMODE > fOSC
fMODE < fOSC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3851E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formulas:
LTC3851EGN: TJ = TA + (PD • 90°C/W)
LTC3851EUD: TJ = TA + (PD • 68°C/W)
100
kΩ
–10
10
μA
μA
Note 4: The LTC3851 is tested in a feedback loop that servos VITH to a
specified voltage and measures the resultant VFB.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ~40% of IMAX (see Minimum On-Time
Considerations in the Applications Information section).
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Output Current and
Mode (Figure TBD)
Efficiency vs Output Current
and Mode
100
90
80
80
70
70
EFFICIENCY(%)
VIN = 12V
90 VOUT = 1.2V
BURST
60
PULSE
SKIP
50
40
CCM
30
80
BURST
PULSE
SKIP
50
40
CCM
30
20
10
10
0
0
100
1000
LOAD CURRENT (mA)
VIN = 12V
90 VOUT = 5V
60
20
10
100
10000
3851 G01
EFFICIENCY (%)
100
EFFICIENCY(%)
Efficiency vs Output Current and
Mode (Figure TBD)
PULSE
SKIP
60
50
CCM
40
30
VIN = 12V
VOUT = 3.3V
FIGURE 11 CIRCUIT
10
BURST
70
100
1000
LOAD CURRENT (mA)
10000
3851 G02
20
10
0
10
100
1000
LOAD CURRENT (mA)
10000
3851 G03
3851f
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LTC3851
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step
(Burst Mode Operation)
Efficiency and Power Loss vs
Input Voltage
10000
100
POWER LOSS,
IOUT = 5A
90
EFFICIENCY,
IOUT = 5A
1000
85
80
POWER LOSS,
IOUT = 0.5A
POWER LOSS (mW)
EFFICIENCY (%)
VIN = 12V
VOUT = 3.3V
95 FIGURE 11 CIRCUIT
ILOAD
5A/DIV
0.2A TO 7.5A
ILOAD
5A/DIV
0.2A TO 7.5A
IL
5A/DIV
IL
5A/DIV
VOUT
100mV/DIV
AC COUPLED
VOUT
100mV/DIV
AC COUPLED
70
4
8
12
3851 G05
VOUT = 1.5V
100μs/DIV
VIN = 12V
FIGURE 11 CIRCUIT
EFFICIENCY,
IOUT = 0.5A
75
Load Step
(Forced Continuous Mode)
16 20 24 28 32
INPUT VOLTAGE (V)
3851 G06
VOUT = 1.5V
100μs/DIV
VIN = 12V
FIGURE 11 CIRCUIT
100
36
40
3851 G04
Load Step
(Pulse-Skip Mode)
Start-Up with Prebiased Output
at 2V
Inductor Current at Light Load
ILOAD
5A/DIV
0.2A TO 7.5A
FORCED
CONTINOUS
MODE
5A/DIV
IL
5A/DIV
VOUT
2V/DIV
Burst Mode
OPERATION
5A/DIV
VOUT
100mV/DIV
AC COUPLED
VFB
0.5V/DIV
PULSE SKIP
MODE
5A/DIV
3851 G07
VOUT = 1.5V
100μs/DIV
VIN = 12V
FIGURE 11 CIRCUIT
3851 G08
VOUT = 1.5V
1μs/DIV
VIN = 12V
ILOAD = 1mA
FIGURE 11 CIRCUIT
3851 G09
20ms/DIV
Ratiometric Tracking with Master
Supply
Coincident Tracking with Master
Supply
TK/SS
0.5V/DIV
Input DC Supply Current vs Input
Voltage
3.0
2.5
VMASTER
0.5V/DIV
VOUT
2A LOAD
0.5V/DIV
SUPPLY CURRENT (mA)
VMASTER
0.5V/DIV
VOUT
2A LOAD
0.5V/DIV
10ms/DIV
3851 G10
10ms/DIV
3851 G11
2.0
1.5
1.0
0.5
0
4
8
12
16 20 24 28 32
INPUT VOLTAGE (V)
36
40
3851 G12
3851f
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LTC3851
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense Threshold
vs Common Mode Voltage
INTVCC Line Regulation
90
90
5.1
ILOAD = 0mA
80
4.9
ILOAD = 25mA
70
4.7
4.5
4.3
4.1
3.9
3.7
60
60
ILIM = FLOAT
50
40
ILIM = GND
30
8
12
16 20 24 28 32
INPUT VOLTAGE (V)
36
40
–20
0.5 1 1.5 2 2.5 3 3.5 4 4.5
VSENSE COMMON MODE VOLTAGE (V)
Maximum Current Sense
Threshold vs Feedback Voltage
(Current Foldback)
90
30
MINIMUIM
10 ILIM = FLOAT
BURST COMPARATOR FALLING THESHOLD:
VITH = 0.4V
0
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VITH (V)
ILIM = INTVCC
80
70
60
ILIM = FLOAT
50
40
ILIM = GND
30
60
40
10
10
0
0
0
20
60
40
DUTY CYCLE (%)
0
100
80
REGULATED FEEDBACK VOLTAGE (mV)
RUN PIN VOLTAGE (V)
RUN RISING THRESHOLD (ON)
1.2
RUN FALLING THRESHOLD (OFF)
1.1
1.0
0.7
0.6
100
125
3851 G19
0.9
–50
0.8
806
1.3
1.3
0.7
3851 G18
1.4
0.8
0.2 0.3 0.4 0.5 0.6
FEEDBACK VOLTAGE (V)
Regulated Feedback Voltage vs
Temperature
1.4
0.9
0.1
3851 G17
1.5
1.0
ILIM = GND
30
Shutdown (RUN) Threshold vs
Temperature
1.1
ILIM = FLOAT
50
20
TK/SS Pull-Up Current vs
Temperature
50
25
0
75
TEMPERATURE (°C)
70
20
3851 G16
1.2
ILIM = INTVCC
80
MAXIMUM VSENSE (mV)
40
CURRENT SENSE THRESHOLD (mV)
VSENSE (mV)
3851 G15
90
20
TK/SS CURRENT (μA)
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VITH (V)
5
Maximum Current Sense
Threshold vs Duty Cycle
50
ILIM = GND
20
3851 G14
60
–25
30
0
0
Burst Mode Peak Current Sense
Threshold vs ITH Voltage
MAXIMUIM
ILIM = FLOAT
40
–10
3851 G13
0.5
–50
50
10
20
0
4
ILIM = INTVCC
70
10
3.5
DUTY CYCLE RANGE: 0% TO 100%
80
ILIM = INTVCC
VSENSE (mV)
VSENSE THRESHOLD (mV)
INTVCC VOLTAGE (V)
5.3
Maximum Peak Current Sense
Threshold vs ITH Voltage
–25
50
25
0
75
TEMPERATURE (°C)
100
125
3851 G20
804
802
800
798
796
794
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
3851 G21
3851f
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LTC3851
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency vs
Temperature
Oscillator Frequency vs Input
Voltage
420
415
RFREQ = 36k
410
FREQUENCY (kHz)
700
600
RFREQ = 60k
500
400
RFREQ = 150k
400
395
385
50
25
75
0
TEMPERATURE (°C)
100
125
380
10
5
30
25
20
INPUT VOLTAGE (V)
15
3851 G22
35
SHUTDOWN INPUT DC SUPPLY CURRENT (μA)
30
25
20
15
10
5
5
10
15 20 25 30
INPUT VOLTAGE (V)
3
INTVCC RAMPING DOWN
2
1
–25
50
25
0
75
TEMPERATURE (°C)
100
125
3851 G24
Shutdown Input DC Supply
Current vs Temperature
35
0
INTVCC RAMPING UP
3851 G23
40
0
4
0
–50
40
Shutdown Input DC Supply
Current vs Input Voltage
SHUTDOWN SUPPLY CURRENT (mA)
35
40
40
35
30
25
20
15
10
5
0
–50 –25
75
50
25
TEMPERATURE (°C)
0
100
3851 G25
125
3851 G26
Input DC Supply Current vs
Temperature
Maximum Current Sense
Threshold vs INTVCC Voltage
3.0
90
80
ISET = INTVCC
2.5
MAXIMUM VSENSE (mV)
200
–50 –25
405
390
300
INPUT DC SUPPLY CURRENT (mA)
FREQUENCY (kHz)
800
5
RFREQ = 80k
INTVCC VOLTAGE AT UVLO THRESHOLD (V)
900
Undervoltage Lockout Threshold
(INTVCC) vs Temperature
2.0
1.5
1.0
70
60
ISET = FLOAT
50
40
30
ISET = GND
20
0.5
10
0
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
3851 G27
0
3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0
INTVCC VOLTAGE(V)
38511 G28
3851f
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LTC3851
PIN FUNCTIONS
(GN/UD)
MODE/PLLIN (Pin 1/Pin 15): Force Continuous Mode,
Burst Mode or Pulse-Skipping Mode Selection Pin and
External Synchronization Input to Phase Detector Pin.
Connect this pin to INTVCC to force continuous conduction
mode of operation. Connect to GND to enable pulse-skipping mode of operation. To select Burst Mode operation,
tie this pin to INTVCC through a resistor no less than 50k,
but no greater than 250k. A clock on the pin will force the
controller into pulse skip mode of operation and synchronize the internal oscillator.
FREQ/PLLFLTR (Pin 2/Pin 16): The phase-locked loop’s
lowpass filter is tied to this pin. Alternatively, a resistor
can be connected between this pin and GND to vary the
frequency of the internal oscillator.
RUN (Pin 3/Pin 1): Run Control Input. A voltage above
1.25V on this pin turns on the IC. However, forcing this
pin below 1.1V causes the IC to shut down the IC. There
is a 2μA pull-up current on this pin.
ILIM (Pin 9/Pin 7): Current Comparator Sense Voltage
Range Input. Tying this pin to GND, FLOAT or INTVCC
selects the maximum current sense threshold from three
different levels.
GND (Pin 10/Pin 8): Ground. All small-signal components
and compensation components should be Kelvin connected
to this ground. The (–) terminal of CVCC and the (–) terminal
of CIN should be closely connected to this pin.
BG (Pin 11/Pin 9): Bottom Gate Driver Output. This pin
drives the gate of the bottom N-channel MOSFET between
GND and INTVCC.
INTVCC (Pin 12/Pin 10): Internal 5V Regulator Output. The
control circuit is powered from this voltage. Decouple this
pin to GND with a minimum 2.2μF low ESR tantalum or
ceramic capacitor.
VIN (Pin 13/Pin 11): Main Input Supply. Decouple this pin
to GND with a capacitor.
TK/SS (Pin 4/Pin 2): Output Voltage Tracking and Soft-Start
Input. A capacitor to ground at this pin sets the ramp rate
for the output voltage. An internal soft-start current of of
1μA charges this capacitor.
BOOST (Pin 14/Pin 12): Boosted Floating Driver Supply.
The (+) terminal of the boost-strap capacitor is connected
to this pin. This pin swings from a diode voltage drop
below INTVCC up to VIN + INTVCC.
ITH (Pin 5/Pin 3): Current Control Threshold and Error
Amplifier Compensation Point. The current comparator
tripping threshold increases with its ITH control voltage.
TG (Pin 15/Pin 13): Top Gate Driver Output. This is the
output of a floating driver with a voltage swing equal to
INTVCC superimposed on the switch node voltage.
FB (Pin 6/Pin 4): Error Amplifier Feedback Input. This pin
receives the remotely sensed feedback voltage from an
external resistive divider across the output.
SW (Pin 16/Pin 14): Switch Node Connection to the Inductor. Voltage swing at this pin is from a Schottky diode
(external) voltage drop below ground to VIN.
SENSE– (Pin 7/Pin 5): Current Sense Comparator Inverting
Input. The (–) input to the current comparator is connected
to the output.
Exposed Pad (Pin 17, UD Package Only): Ground. Must
be soldered to PCB, providing a local ground for the IC.
SENSE+ (Pin 8/Pin 6): Current Sense Comparator Noninverting Input. The (+) input to the current comparator
is normally connected to the DCR sensing network or
current sensing resistor.
3851f
8
LTC3851
FUNCTIONAL DIAGRAM
FREQ/PLLFLTR
VIN
MODE/PLLIN
VIN
+
CIN
100k
5V REG
0.8V
MODE/SYNC
DETECT
+
–
PLL-SYNC
BOOST
BURSTEN
OSC
CB
TG
S
R
PULSE SKIP
Q
M1
SW
5k
+
ON
–
ICMP
IREV
+
–
SWITCH
LOGIC
AND
ANTISHOOT
THROUGH
SENSE+
DB
L1
VOUT
SENSE–
RUN
INTVCC
+
ILIM
COUT
BG
OV
M2
CVCC
SLOPE COMPENSATION
GND
INTVCC
UVLO
+
1
100k
UV
0.72V
R2
VFB
–
ITHB
R1
+
SLEEP
VIN
OV
–
–
+
SS
+
–
RUN
–
0.88V
+
1μA
EA
– + +
0.8V
REF
0.64V
1.25V
2μA
0.4V
3851 FD
ITH
RC
RUN
TK/SS
CSS
CC1
3851f
9
LTC3851
OPERATION
Main Control Loop
The LTC3851 is a constant frequency, current mode stepdown controller. During normal operation, the top MOSFET
is turned on when the clock sets the RS latch, and is turned
off when the main current comparator, ICMP , resets the
RS latch. The peak inductor current at which ICMP resets
the RS latch is controlled by the voltage on the ITH pin,
which is the output of the error amplifier EA. The VFB pin
receives the voltage feedback signal, which is compared
to the internal reference voltage by the EA. When the
load current increases, it causes a slight decrease in VFB
relative to the 0.8V reference, which in turn causes the
ITH voltage to increase until the average inductor current
matches the new load current. After the top MOSFET has
turned off, the bottom MOSFET is turned on until either
the inductor current starts to reverse, as indicated by the
reverse current comparator, IREV, or the beginning of the
next cycle.
INTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin. An
internal 5V low dropout linear regulator supplies INTVCC
power from VIN.
The top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during each
off cycle through an external diode when the top MOSFET
turns off. If the input voltage, VIN, decreases to a voltage
close to VOUT, the loop may enter dropout and attempt
to turn on the top MOSFET continuously. The dropout
detector detects this and forces the top MOSFET off for
about 1/10 of the clock period every tenth cycle to allow
CB to recharge. However, it is recommended that there is
always a load present during the drop-out transition to
ensure CB is recharged.
Shutdown and Start-Up (RUN and TK/SS)
The LTC3851 can be shut down using the RUN pin. Pulling
this pin below 1.1V disables the controller and most of the
internal circuitry, including the INTVCC regulator. Releasing
the RUN pin allows an internal 2μA current to pull up the
pin and enable that controller. Alternatively, the RUN pin
may be externally pulled up or driven directly by logic.
Be careful not to exceed the absolute maximum rating of
6V on this pin.
The start-up of the controller’s output voltage, VOUT , is
controlled by the voltage on the TK/SS pin. When the
voltage on the TK/SS pin is less than the 0.8V internal
reference, the LTC3851 regulates the VFB voltage to the
TK/SS pin voltage instead of the 0.8V reference. This allows the TK/SS pin to be used to program a soft-start by
connecting an external capacitor from the TK/SS pin to
GND. An internal 1μA pull-up current charges this capacitor
creating a voltage ramp on the TK/SS pin. As the TK/SS
voltage rises linearly from 0V to 0.8V (and beyond), the
output voltage VOUT rises smoothly from zero to its final
value. Alternatively, the TK/SS pin can be used to cause
the start-up of VOUT to “track” another supply. Typically,
this requires connecting to the TK/SS pin an external
resistor divider from the other supply to ground (see the
Applications Information section). When the RUN pin
is pulled low to disable the controller, or when INTVCC
drops below its undervoltage lockout threshold of 3.2V,
the TK/SS pin is pulled low by an internal MOSFET. When
in undervoltage lockout, the controller is disabled and the
external MOSFETs are held off.
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Continuous Conduction)
The LTC3851 can be enabled to enter high efficiency Burst
Mode operation, constant frequency pulse-skipping mode
or forced continuous conduction mode. To select forced
continuous operation, tie the MODE/PLLIN pin to INTVCC.
To select pulse-skipping mode of operation, float the
MODE/PLLIN pin or tie it to GND. To select Burst Mode
operation, tie MODE/PLLIN to INTVCC through a resistor
no less than 50k, but no greater than 250k.
When the controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-forth of the maximum sense voltage even though
the voltage on the ITH pin indicates a lower value. If the
average inductor current is higher than the load current,
3851f
10
LTC3851
OPERATION
the error amplifier, EA, will decrease the voltage on the ITH
pin. When the ITH voltage drops below 0.4V, the internal
sleep signal goes high (enabling “sleep” mode) and both
external MOSFETs are turned off.
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
efficiency than forced continuous mode, but not nearly as
high as Burst Mode operation.
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output
begins to rise. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When a controller is
enabled for Burst Mode operation, the inductor current is
not allowed to reverse. The reverse current comparator,
IREV , turns off the bottom external MOSFET just before the
inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates in
discontinuous operation. In forced continuous operation,
the inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in
normal operation. In this mode the efficiency at light loads
is lower than in Burst Mode operation. However, continuous mode has the advantages of lower output ripple and
less interference to audio circuitry.
Frequency Selection and Phase-Locked Loop
(FREQ/PLLFLTR and MODE/PLLIN Pins)
When the MODE/PLLIN pin is connected to GND, the
LTC3851 operates in PWM pulse-skipping mode at light
loads. At very light loads the current comparator, ICMP, may
remain tripped for several cycles and force the external top
MOSFET to stay off for the same number of cycles (i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuous operation, exhibits low output ripple as well as
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency
of the LTC3851 can be selected using the FREQ/PLLFLTR
pin. If the MODE/PLLIN pin is not being driven by an external clock source, the FREQ/PLLFLTR pin can be used
to program the controller’s operating frequency from
250kHz to 750kHz.
A phase-locked loop (PLL) is available on the LTC3851
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The
controller operates in forced continuous mode of operation
when it is synchronized. A series RC should be connected
between the FREQ/PLLFLTR pin and GND to serve as the
PLL’s loop filter.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious conditions that may overvoltage the output. In such cases,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.
3851f
11
LTC3851
APPLICATIONS INFORMATION
The Typical Application on the first page of this data sheet
is a basic LTC3851 application circuit. The LTC3851 can
be configured to use either DCR (inductor resistance)
sensing or low value resistor sensing. The choice of the
two current sensing schemes is largely a design trade-off
between cost, power consumption and accuracy. DCR
sensing is becoming popular because it saves expensive
current sensing resistors and is more power efficient,
especially in high current applications. However, current
sensing resistors provide the most accurate current limits
for the controller. Other external component selection
is driven by the load requirement, and begins with the
selection of RSENSE (if RSENSE is used) and the inductor
value. Next, the power MOSFETs and Schottky diodes are
selected. Finally, input and output capacitors are selected.
The circuit shown on the first page can be configured for
operation up to 38V at VIN.
Current Limit Programming
The ILIM pin is a tri-level logic input to set the maximum
current limit of the controller. When ILIM is grounded, the
maximum current limit threshold of the current comparator is programmed to be 30mV. When ILIM is floated, the
maximum current limit threshold is 50mV. When ILIM is
tied to INTVCC, the maximum current limit threshold is
set to 75mV.
SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are the inputs to the current
comparators. The common mode input voltage range of
the current comparators is 0V to 5.5V. Both SENSE pins
are high impedance inputs with small base currents of
less than 1μA. When the SENSE pins ramp up from 0V to
1.4V, the small base currents flow out of the SENSE pins.
When the SENSE pins ramp down from 5V to 1.1V, the
small base currents flow into the SENSE pins. The high
impedance inputs to the current comparators allow accurate DCR sensing. However, care must be taken not to
float these pins during normal operation.
Low Value Resistors Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 1. RSENSE is chosen based on the required output
current.
VIN
INTVCC
VIN
BOOST
TG
LTC3851
RSENSE
SW
VOUT
BG
GND
SENSE+
SENSE–
FILTER COMPONENTS
PLACED NEAR SENSE PINS
3851 F01
Figure 1. Using a Resistor to Sense Current with the LTC3851
The current comparator has a maximum threshold, VMAX,
determined by the ILIM setting. The current comparator
threshold sets the maximum peak of the inductor current,
yielding a maximum average output current, IMAX, equal to
the maximum peak value less half the peak-to-peak ripple
current, ΔIL. Allowing a margin of 20% for variations in
the IC and external component values yields:
RSENSE = 0.8 •
VMAX
IMAX + ΔIL/ 2
Inductor DCR Sensing
For applications requiring the highest possible efficiency,
the LTC3851 is capable of sensing the voltage drop across
the inductor DCR, as shown in Figure 2. The DCR of the
inductor represents the small amount of DC winding
resistance of the copper, which can be less than 1mΩ for
today’s low value, high current inductors. If the external
R1||R2 • C1 time constant is chosen to be exactly equal
to the L/DCR time constant, the voltage drop across the
external capacitor is equal to the voltage drop across
the inductor DCR multiplied by R2/(R1 + R2). Therefore,
R2 may be used to scale the voltage across the sense
terminals when the DCR is greater than the target sense
resistance. R2 also resets the sense capacitor, C1, during DCM operation. Check the manufacturer’s data sheet
for specifications regarding the inductor DCR, in order
to properly dimension the external filter components.
3851f
12
LTC3851
APPLICATIONS INFORMATION
VIN
INTVCC
Accepting larger values of ΔIL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ΔIL = 0.3(IMAX). The maximum
ΔIL occurs at the maximum input voltage.
VIN
BOOST
INDUCTOR
TG
L
SW
DCR
LTC3851
VOUT
BG
GND
R1
SENSE+
C1*
R2
SENSE–
*PLACE C1 NEAR SENSE+, SENSE– PINS
R1||R2 • C1 =
L
DCR
RSENSE(EQ) = DCR
3851 F02
R2
R1 + R2
The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average
inductor current required results in a peak current below
≈10% of the current limit determined by RSENSE. Lower
inductor values (higher ΔIL) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to increase.
Figure 2. Current Mode Control Using the Inductor DCR
The DCR of the inductor can also be measured using a
good RLC meter.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at high duty cycles. It is accomplished internally
by adding a compensating ramp to the inductor current
signal. Normally, this results in a reduction of maximum
inductor peak current for duty cycles >40%. However, the
LTC3851 uses a novel scheme that allows the maximum
inductor peak current to remain unaffected throughout
all duty cycles.
Inductor Value Calculation
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of
smaller inductor and capacitor values. A higher frequency
generally results in lower efficiency because of MOSFET
gate charge losses. In addition to this basic trade-off, the
effect of inductor value on ripple current and low current
operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current ΔIL decreases with higher
inductance or frequency and increases with higher VIN:
ΔIL =
⎛ V ⎞
1
VOUT ⎜1 – OUT ⎟
f •L
VIN ⎠
⎝
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on inductance
selected. As inductance increases, core losses go down.
Unfortunately, increased inductance requires more turns
of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode (Optional)
Selection
Two external power MOSFETs must be selected for the
LTC3851 controller: one N-channel MOSFET for the top
(main) switch, and one N-channel MOSFET for the bottom
(synchronous) switch.
3851f
13
LTC3851
APPLICATIONS INFORMATION
The peak-to-peak drive levels are set by the INTVCC voltage.
This voltage is typically 5V during start-up. Consequently,
logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); then, sub-logic level threshold MOSFETs
(VGS(TH) < 3V) should be used. Pay close attention to the
BVDSS specification for the MOSFETs as well; most of the
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the onresistance, RDS(ON), Miller capacitance, CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode, the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle =
VOUT
VIN
Synchronous Switch Duty Cycle =
VIN – VOUT
VIN
The MOSFET power dissipations at maximum output
current are given by:
V
2
PMAIN = OUT (IMAX ) (1+ δ)RDS(ON) +
VIN
⎞
(VIN)2 ⎛⎜⎝ IMAX
(R )(C
)•
2 ⎟⎠ DR MILLER
⎡
1
1 ⎤
+
⎥ ( f)
⎢
⎢⎣ VINTVCC – VTH(MIN) VTH(MIN) ⎥⎦
PSYNC =
VIN – VOUT
2
IMAX ) (1+ δ)RDS(ON)
(
VIN
where δ is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTH(MIN) is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V,
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V, the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
short-circuit when the synchronous switch is on close to
100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diode shown on the first page
conducts during the dead time between the conduction
of the two power MOSFETs. This prevents the body diode
of the bottom MOSFET from turning on, storing charge
during the dead time and requiring a reverse recovery
period that could cost as much as 3% in efficiency at high
VIN. A 1A to 3A Schottky is generally a good size due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
Soft-Start and Tracking
The LTC3851 has the ability to either soft-start by itself
with a capacitor or track the output of another channel
or external supply. When the LTC3851 is configured to
soft-start by itself, a capacitor should be connected to
the TK/SS pin. The LTC3851 is in the shutdown state if
the RUN pin voltage is below 1.25V. TK/SS pin is actively
pulled to ground in this shutdown state.
Once the RUN pin voltage is above 1.25V, the LTC3851
powers up. A soft-start current of 1μA then starts to charge
its soft-start capacitor. Note that soft-start or tracking is
achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
according to the ramp rate on the TK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
3851f
14
LTC3851
APPLICATIONS INFORMATION
0V to 0.8V on the TK/SS pin. The total soft-start time can
be calculated as:
t SOFT-START = 0.8 •
CSS
1.0μA
Regardless of the mode selected by the MODE/PLLIN pin,
the regulator will always start in pulse-skipping mode up
to TK/SS = 0.64V. Between TK/SS = 0.64V and 0.72V, it
will operate in forced continuous mode and revert to the
selected mode once TK/SS > 0.72V. The output ripple
is minimized during the 80mV forced continuous mode
window.
When the regulator is configured to track another supply,
the feedback voltage of the other supply is duplicated by a
resistor divider and applied to the TK/SS pin. Therefore, the
voltage ramp rate on this pin is determined by the ramp rate
of the other supply’s voltage. Note that the small soft-start
capacitor charging current is always flowing, producing
a small offset error. To minimize this error, one can select
the tracking resistive divider value to be small enough to
make this error negligible.
In order to track down another supply after the soft-start
phase expires, the LTC3851 must be configured for forced
continuous operation by connecting MODE/PLLIN to
INTVCC.
Output Voltage Tracking
The LTC3851 allows the user to program how its output
ramps up and down by means of the TK/SS pins. Through
this pin, the output can be set up to either coincidentally or
ratiometrically track with another supply’s output, as shown
in Figure 3. In the following discussions, VMASTER refers to
a master supply and VOUT refers to the LTC3851’s output
as a slave supply. To implement the coincident tracking
in Figure 3a, connect a resistor divider to VMASTER and
connect its midpoint to the TK/SS pin of the LTC3851. The
ratio of this divider should be selected the same as that of
the LTC3851’s feedback divider as shown in Figure 4a. In
this tracking mode, VMASTER must be higher than VOUT.
To implement ratiometric tracking, the ratio of the resistor
divider connected to VMASTER is determined by:
VMASTER R2 ⎛ R3 + R4⎞
=
VOUT
R4 ⎜⎝ R1+ R2 ⎟⎠
So which mode should be programmed? While either
mode in Figure 4 satisfies most practical applications,
the coincident mode offers better output regulation.
This concept can be better understood with the help of
Figure 5. At the input stage of the error amplifier, two
common anode diodes are used to clamp the equivalent
reference voltage and an additional diode is used to match
the shifted common mode voltage. The top two current
sources are of the same amplitude. In the coincident
VOUT
VMASTER
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VMASTER
VOUT
TIME
TIME
(3a) Coincident Tracking
3851 F03
(3b) Ratiometric Tracking
Figure 3. Two Different Modes of Output Voltage Tracking
3851f
15
LTC3851
APPLICATIONS INFORMATION
VMASTER
VOUT
R3
VMASTER
R3
TO
TK/SS
PIN
TO
VFB
PIN
R4
VOUT
R1
TO
TK/SS
PIN
R4
R3
TO
VFB
PIN
R2
R4
3851 F04
(4a) Coincident Tracking Setup
(4b) Ratiometric Tracking Setup
Figure 4. Setup for Coincident and Ratiometric Tracking
I
I
+
D1
D2
EA
TK/SS
0.8V
VFB
–
D3
3851 F05
Figure 5. Equivalent Input Circuit of Error Amplifier
mode, the TK/SS voltage is substantially higher than
0.8V at steady-state and effectively turns off D1. D2 and
D3 will therefore conduct the same current and offer
tight matching between VFB and the internal precision
0.8V reference. In the ratiometric mode, however, TK/SS
equals 0.8V at steady-state. D1 will divert part of the bias
current to make VFB slightly lower than 0.8V.
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a finite amount
of output voltage deviation. Furthermore, when the master
supply’s output experiences dynamic excursion (under
load transient, for example), the slave channel output will
be affected as well. For better output regulation, use the
coincident tracking mode instead of ratiometric.
what type of bulk capacitor is used, an additional 0.1μF
ceramic capacitor placed directly adjacent to the INTVCC
and GND pins is highly recommended. Good bypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3851 to be
exceeded. The INTVCC current, which is dominated by the
gate charge current, is supplied by the 5V LDO.
Power dissipation for the IC in this case is highest and
is approximately equal to VIN • IINTVCC. The gate charge
current is dependent on operating frequency as discussed
in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given
in Note 3 of the Electrical Characteristics. For example,
the LTC3851 INTVCC current is limited to less than 17mA
from a 36V supply in the GN package:
TJ = 70°C + (17mA)(36V)(90°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (MODE/PLLIN
= INTVCC) at maximum VIN.
INTVCC Regulator
Topside MOSFET Driver Supply (CB, DB)
The LTC3851 features a PMOS low dropout linear regulator
(LDO) that supplies power to INTVCC from the VIN supply.
INTVCC powers the gate drivers and much of the LTC3851
’s internal circuitry. The LDO regulates the voltage at the
INTVCC pin to 5V.
An external bootstrap capacitor CB connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFET. Capacitor CB in the Functional Diagram is charged
though external diode DB from INTVCC when the SW pin
is low. When the topside MOSFET is to be turned on, the
driver places the CB voltage across the gate source of the
MOSFET. This enhances the MOSFET and turns on the
topside switch. The switch node voltage, SW, rises to VIN
The LDO can supply a peak current of 50mA and must
be bypassed to ground with a minimum of 2.2μF ceramic
capacitor or low ESR electrolytic capacitor. No matter
3851f
16
LTC3851
APPLICATIONS INFORMATION
and the BOOST pin follows. With the topside MOSFET on,
the boost voltage is above the input supply:
VBOOST = VIN + VINTVCC
The value of the boost capacitor CB needs to be 100 times
that of the total input capacitance of the topside MOSFET.
The reverse breakdown of the external Schottky diode
must be greater than VIN(MAX).
COUT Selection
The selection of COUT is primarily determined by the
effective series resistance, ESR, to minimize voltage
ripple. The output ripple, ΔVOUT, in continuous mode is
determined by:
⎛
1 ⎞
ΔVOUT ≈ ΔIL ⎜ESR +
8 fCOUT ⎟⎠
⎝
Undervoltage Lockout
The LTC3851 has two functions that help protect the
controller in case of undervoltage conditions. A precision
UVLO comparator constantly monitors the INTVCC voltage
to ensure that an adequate gate-drive voltage is present.
It locks out the switching action when INTVCC is below
3.2V. To prevent oscillation when there is a disturbance
on the INTVCC, the UVLO comparator has 400mV of precision hysteresis.
Another way to detect an undervoltage condition is to monitor the VIN supply. Because the RUN pin has a precision
turn-on reference of 1.25V, one can use a resistor divider
to VIN to turn on the IC when VIN is high enough.
CIN Selection
In continuous mode, the source current of the top N-channel MOSFET is a square wave of duty cycle VOUT/VIN. To
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
⎛ V
⎞
V
IRMS ≅ IO(MAX ) OUT ⎜ IN – 1⎟
VIN ⎝ VOUT ⎠
1/ 2
This formula has a maximum at VIN = 2VOUT, where IRMS =
IO(MAX)/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
size or height requirements in the design. Always consult
the manufacturer if there is any question.
where f = operating frequency, COUT = output capacitance
and ΔIL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ΔIL increases
with input voltage. Typically, once the ESR requirement
for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. With ΔIL =
0.3IOUT(MAX) and allowing 2/3 of the ripple to be due to
ESR, the output ripple will be less than 50mV at maximum
VIN if the ILIM pin is configured to float and:
COUT Required ESR < 2.2RSENSE
COUT >
1
8 fRSENSE
The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guarantees
that the output capacitance does not significantly discharge
during the operating frequency period due to ripple current.
The choice of using smaller output capacitance increases
the ripple voltage due to the discharging term but can be
compensated for by using capacitors of very low ESR to
maintain the ripple voltage at or below 50mV. The ITH pin
OPTI-LOOP compensation components can be optimized
to provide stable, high performance transient response
regardless of the output capacitors selected.
The selection of output capacitors for applications with
large load current transients is primarily determined by the
voltage tolerance specifications of the load. The resistive
component of the capacitor, ESR, multiplied by the load
current change, plus any output voltage ripple must be
within the voltage tolerance of the load.
3851f
17
LTC3851
APPLICATIONS INFORMATION
The required ESR due to a load current step is:
RESR ≤
ΔV
ΔI
where ΔI is the change in current from full load to zero load
(or minimum load) and ΔV is the allowed voltage deviation
(not including any droop due to finite capacitance).
The amount of capacitance needed is determined by the
maximum energy stored in the inductor. The capacitance
must be sufficient to absorb the change in inductor
current when a high current to low current transition
occurs. The opposite load current transition is generally
determined by the control loop OPTI-LOOP components,
so make sure not to over compensate and slow down
the response. The minimum capacitance to assure the
inductors’ energy is adequately absorbed is:
L (ΔI)
>
2 (ΔV) VOUT
2
COUT
where ΔI is the change in load current.
Manufacturers such as Nichicon, United Chemi-Con and
Sanyo can be considered for high performance throughhole capacitors. The OS-CON semiconductor electrolyte
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.
In surface mount applications, ESR, RMS current handling
and load step specifications may require multiple capacitors in parallel. Aluminum electrolytic, dry tantalum and
special polymer capacitors are available in surface mount
packages. Special polymer surface mount capacitors offer
very low ESR but have much lower capacitive density per
unit volume than other capacitor types. These capacitors
offer a very cost-effective output capacitor solution and are
an ideal choice when combined with a controller having
high loop bandwidth. Tantalum capacitors offer the highest
capacitance density and are often used as output capacitors for switching regulators having controlled soft-start.
Several excellent surge-tested choices are the AVX TPS,
AVX TPSV or the KEMET T510 series of surface mount
tantalums, available in case heights ranging from 1.5mm
to 4.1mm. Aluminum electrolytic capacitors can be used
in cost-driven applications, provided that consideration is
given to ripple current ratings, temperature and long-term
reliability. A typical application will require several to many
aluminum electrolytic capacitors in parallel. A combination of the above mentioned capacitors will often result
in maximizing performance and minimizing overall cost.
Other capacitor types include Nichicon PL series, NEC
Neocap, Panasonic SP and Sprague 595D series. Consult
manufacturers for other specific recommendations.
Like all components, capacitors are not ideal. Each
capacitor has its own benefits and limitations. Combinations of different capacitor types have proven to be a very
cost effective solution. Remember also to include high
frequency decoupling capacitors. They should be placed
as close as possible to the power pins of the load. Any
inductance present in the circuit board traces negates
their usefulness.
Setting Output Voltage
The LTC3851 output voltage is set by an external feedback resistive divider carefully placed across the output,
as shown in Figure 6. The regulated output voltage is
determined by:
⎛ R ⎞
VOUT = 0.8 V ⎜1+ B ⎟
⎝ RA ⎠
To improve the transient response, a feed-forward capacitor, CFF , may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
VOUT
LTC3851
RB
CFF
VFB
RA
3851 F06
Figure 6. Settling Output Voltage
3851f
18
LTC3851
APPLICATIONS INFORMATION
Fault Conditions: Current Limit and Current Foldback
Phase-Locked Loop and Frequency Synchronization
The LTC3851 includes current foldback to help limit load
current when the output is shorted to ground. If the
output falls below 40% of its nominal output level, the
maximum sense voltage is progressively lowered from
its maximum programmed value to about 25% of the that
value. Foldback current limiting is disabled during softstart or tracking. Under short-circuit conditions with very
low duty cycles, the LTC3851 will begin cycle skipping in
order to limit the short-circuit current. In this situation
the bottom MOSFET will be dissipating most of the power
but less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time tON(MIN)
of the LTC3851 (≈90ns), the input voltage and inductor
value:
The LTC3851 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the top MOSFET
to be locked to the rising edge of an external clock signal
applied to the MODE/PLLIN pin. This phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
VIN
L
The resulting short-circuit current is:
ΔIL(SC) = tON(MIN) •
ISC =
1/ 4MaxVSENSE 1
– ΔIL(SC)
RSENSE
2
Programming Switching Frequency
To set the switching frequency of the LTC3851, connect
a resistor, RFREQ, between FREQ/PLLFLTR and GND. The
relationship between the oscillator frequency and RFREQ
is shown in Figure 7. A 0.1μF bypass capacitor should be
connected in parallel with RFREQ.
1000
OSCILLATOR FREQUENCY (kHz)
750
The output of the phase detector is a pair of complementary
current sources that charge or discharge the external filter
network connected to the FREQ/PLLFLTR pin. Note that
the LTC3851 can only be synchronized to an external clock
whose frequency is within range of the LTC3851’s internal
VCO.This is guaranteed to be between 250kHz and 750kHz.
A simplified block diagram is shown in Figure 8.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC , then current is sunk continuously from the phase detector output, pulling down the
FREQ/PLLFLTR pin. When the external clock frequency is
less than fOSC , current is sourced continuously, pulling up
the FREQ/PLLFLTR pin. If the external and internal frequencies are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to the
phase difference. The voltage on the FREQ/PLLFLTR pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor CLP holds the voltage.
2.7V
500
RLP
CLP
FREQ/PLLFLTR
250
MODE/
PLLIN
EXTERNAL
OSCILLATOR
DIGITAL
PHASE/
FREQUENCY
DETECTOR
VCO
100
10
36
60
160
RFREQ (k)
1000
3851F07
Figure 7. Relationship Between Oscillator Frequency
and Resistor Connected Between FREQ/PLLFLTR and GND
3851 F08
Figure 8. Phase-Locked Loop Block Diagram
3851f
19
LTC3851
APPLICATIONS INFORMATION
The loop filter components, CLP and RLP , smooth out
the current pulses from the phase detector and provide
a stable input to the voltage-controlled oscillator. The
filter components CLP and RLP determine how fast the
loop acquires lock. Typically RLP is 1k to 10k and CLP is
2200pF to 0.01μF.
The external clock (on MODE/PLLIN pin) input high
threshold is nominally 1.6V, while the input low threshold
is nominally 1.2V.
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest time duration
that the LTC3851 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <
VOUT
VIN( f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3851 is approximately
90ns. However, as the peak sense voltage decreases the
minimum on-time gradually increases. This is of particular concern in forced continuous applications with low
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3851 circuits: 1) IC VIN current, 2) INTVCC
regulator current, 3) I2R losses, 4) topside MOSFET
transition losses.
1. The VIN current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver current. VIN current typically results in a small
(<0.1%) loss.
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTVCC to ground. The resulting dQ/dt is a current
out of INTVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG
= f(QT + QB), where QT and QB are the gate charges of
the topside and bottom side MOSFETs.
3. I2R losses are predicted from the DC resistances of
the fuse (if used), MOSFET, inductor and current sense
resistor. In continuous mode, the average output current
flows through L and RSENSE, but is “chopped” between
the topside MOSFET and the synchronous MOSFET. If
the two MOSFETs have approximately the same RDS(ON),
then the resistance of one MOSFET can simply be
summed with the resistances of L and RSENSE to obtain
I2R losses. For example, if each RDS(ON) = 10mΩ, DCR
= 10mΩ and RSENSE = 5mΩ, then the total resistance
is 25mΩ. This results in losses ranging from 2% to
8% as the output current increases from 3A to 15A for
a 5V output, or a 3% to 12% loss for a 3.3V output.
Efficiency varies as the inverse square of VOUT for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
%Efficiency = 100% – (L1 + L2 + L3 + ...)
3851f
20
LTC3851
APPLICATIONS INFORMATION
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7)VIN2 • IO(MAX) • CRSS • f
Other “hidden” losses such as copper trace and the battery internal resistance can account for an additional 5%
to 10% efficiency degradation in portable systems. It is
very important to include these “system” level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
CIN has adequate charge storage and very low ESR at the
switching frequency. A 25W supply will typically require a
minimum of 20μF to 40μF of capacitance having a maximum of 20mΩ to 50mΩ of ESR. Other losses including
Schottky conduction losses during dead time and inductor core losses generally account for less than 2% total
additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ΔILOAD (ESR), where ESR is the effective
series resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the ITH pin not only allows optimization of
control loop behavior but also provides a DC coupled and
AC filtered closed-loop response test point. The DC step,
rise time and settling at this test point truly reflects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining the
rise time at the pin. The ITH external components shown
in the Typical Application circuit will provide an adequate
starting point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the ITH pin signal which is in
the feedback loop and is the filtered and compensated
control loop response. The midband gain of the loop will
be increased by increasing RC and the bandwidth of the
loop will be increased by decreasing CC. If RC is increased
by the same factor that CC is decreased, the zero frequency
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10μF capacitor would
require a 250μs rise time, limiting the charging current
to about 200mA.
3851f
21
LTC3851
APPLICATIONS INFORMATION
PC Board Layout Checklist
2. Does the VFB pin connect directly to the feedback resistors? The resistive divider R1, R2 must be connected
between the (+) plate of COUT and signal ground. The
47pF to 100pF capacitor should be as close as possible
to the LTC3851. Be careful locating the feedback resistors too far away from the LTC3851. The VFB line should
not be routed close to any other nodes with high slew
rates.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3851. These items are also illustrated graphically
in the layout diagram of Figure 9. Check the following in
your layout:
1. Are the board signal and power grounds segregated?
The LTC3851 GND pin should tie to the ground plane
close to the input capacitor(s). The low current or signal
ground lines should make a single point tie directly to
the GND pin. The synchronous MOSFET source pins
should connect to the input capacitor(s) ground.
3. Are the SENSE– and SENSE+ leads routed together
with minimum PC trace spacing? The filter capacitor between SENSE+ and SENSE– should be as close
as possible to the LTC3851. Ensure accurate current
sensing with Kelvin connections as shown in Figure
10. Series resistance can be added to the SENSE lines
to increase noise rejection and to compensate for the
ESL of RSENSE.
+
1
RFREQ
2
3
MODE/PLLIN
SW
FREQ/PLLFLTR
TG
RUN
15
M1
CIN
14
VIN
LTC3851
CSS
4
RC
BOOST
16
+
0.1μF
CC
TK/SS
VIN
13
CC2
5
ITH
INTVCC
VFB
BG
47pF
6
7
SENSE–
GND
8
SENSE+
ILIM
DB
12
11
CB
D1
+
M2
4.7μF
10
–
1000pF
9
L1
–
R1
COUT
+
R2
VOUT
RSENSE
3851 F09
+
Figure 9. LTC3851 Layout Diagram
3851f
22
LTC3851
APPLICATIONS INFORMATION
HIGH CURRENT PATH
3851 F10
SENSE+ SENSE–
CURRENT SENSE
RESISTOR
(RSENSE)
Figure 10. Kelvin Sensing RSENSE
The duty cycle percentage should be maintained from cycle
to cycle in a well designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can suggest noise pick-up at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required.
Reduce VIN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
6. Keep the switching node (SW), top gate node (TG) and
boost node (BOOST) away from sensitive small-signal
nodes, especially from the voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and therefore should be kept on
the “output side” (Pin 9 to Pin 16) of the LTC3851EGN
and occupy minimum PC trace area.
Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, the Schottky and the
top MOSFET to the sensitive current and voltage sensing traces. In addition, investigate common ground path
voltage pickup between these components and the GND
pin of the IC.
PC Board Layout Debugging
Design Example
It is helpful to use a DC-50MHz current probe to monitor
the current in the inductor while testing the circuit. Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator and probe the actual
output voltage as well. Check for proper performance over
the operating voltage and current range expected in the
application. The frequency of operation should be maintained over the input voltage range down to dropout and
until the output load drops below the low current operation threshold—typically 10% of the maximum designed
current level in Burst Mode operation.
As a design example, assume VIN = 12V (nominal), VIN = 22V
(maximum), VOUT = 1.8V, IMAX = 5A, and f = 250kHz.
4. Does the (+) terminal of CIN connect to the drain of
the topside MOSFET(s) as closely as possible? This
capacitor provides the AC current to the MOSFET(s).
5. Is the INTVCC decoupling capacitor connected closely
between INTVCC and GND? This capacitor carries the
MOSFET driver peak currents. An additional 1μF ceramic
capacitor placed immediately next to the INTVCC and
GND pins can help improve noise performance.
The inductance value is chosen first based on a 30%
ripple current assumption. The highest value of ripple
current occurs at the maximum input voltage. Connect a
160k resistor between the FREQ/PLLFLTR and GND pins,
generating 250kHz operation. The minimum inductance
for 30% ripple current is:
ΔIL =
⎛ V ⎞
1
VOUT ⎜1− OUT ⎟
VIN ⎠
(f)(L)
⎝
3851f
23
LTC3851
APPLICATIONS INFORMATION
A 4.7μH inductor will produce 28% ripple current and
a 3.3μH will result in 40%. The peak inductor current
will be the maximum DC value plus one-half the ripple
current, or 6A, for the 3.3μH value. Increasing the ripple
current will also help ensure that the minimum on-time
of 90ns is not violated. The minimum on-time occurs at
maximum VIN:
tON(MIN) =
VOUT
VIN(MAX ) (f)
=
1.8 V
= 327
7ns
22V (250kHz)
The RSENSE resistor value can be calculated by connecting ILIM to INTVCC and using the maximum current sense
voltage specification with some accommodation for tolerances. Tie ILIM to INTVCC.
75mV
RSENSE ≤
= 0.0125Ω
6A
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF. At
maximum input voltage with T (estimated) = 50°C:
PMAIN =
A short-circuit to ground will result in a folded back current of:
ISC =
29mV
1 ⎛ 90ns (22V)⎞
– ⎜
= 2.02A
0.0125Ω 2 ⎝ 3.3μH ⎟⎠
with a typical value of RDS(ON) and δ = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
22V
2
2.02A) (1.125)(0.022Ω)
(
22V
= 101.0mW
PSYNC =
which is less than under full-load conditions.
CIN is chosen for an RMS current rating of at least 3A at
temperature. COUT is chosen with an ESR of 0.02Ω for
low output ripple. The output ripple in continuous mode
will be highest at the maximum input voltage. The output
voltage ripple due to ESR is approximately:
VORIPPLE = RESR (ΔIL) = 0.02Ω (2A) = 40mVP-P
1.8 V 2
(5) ⎡⎣1+ (0.005)(50°C − 25°C)⎤⎦ •
22V
(0.035Ω) + (22V)2 ⎛⎜⎝ 52A⎞⎟⎠ (2Ω)(215pF) •
1⎤
⎡ 1
⎢5 − 2.3 + 2.3⎥ (250kHz) = 185mW
⎣
⎦
3851f
24
LTC3851
TYPICAL APPLICATIONS
VIN
4V TO 38V
MODE/PLLIN
VIN
FREQ/PLLFLTR
TG
CIN
180μF
RFREQ
80k
0.1μF
RUN
CSS
0.1μF
BOOST
LTC3851
TK/SS
CC
RC 3300pF
1k
M1
IRF7478PBF
CB
0.1μF
L1
0.68μH
SW
DB
CMDSH-4E
CC2
100pF
ITH
INTVCC
R27
10k
C15
47pF
+
R2
62.5k
1%
4.7μF
VFB
M2
IRF7478PBF
BG
R1
20k
1%
CMSH3-40M
SENSE–
GND
SENSE+
ILIM
VOUT
3.3V
15A
+
COUT
330μF
s2
C5
0.22μF
COUT: SANYO 2R5TPE330M9
CIN: SANYO 80UK150K
L1: SUMIDA CEP125-0R68
13k
3851 TA03
Figure 11. High Efficiency 3.3V/15A Step-Down Converter
1.8V/5A Converter from Design Example with Pulse Skip Operation
VIN
4.5V TO 22V
MODE/PLLIN
VIN
FREQ/PLLFLTR
TG
RFREQ
80k
0.1μF
CC
RC 470pF
33k
CSS
0.1μF
RUN
M1
Si4412DY
BOOST
LTC3851
TK/SS
CC2
220pF
CB
0.1μF
CIN
22μF
50V
CER
ITH
L1
3.3μH
SW
INTVCC
47pF
DB
CMDSH-3
RSENSE
0.01Ω
R2
32.4k
1%
+
4.7μF
VFB
BG
M2
Si4410DY
MBRS140T3
SENSE–
GND
SENSE+
ILIM
R1
25.5k
1%
VOUT
1.8V
5A
+
COUT
150μF
6.3V
s2
PANASONIC SP
1000pF
COUT: PANASONIC EEFUEOG151R
CIN: MARCON THCR70LE1H226ZT
L1: PANASONIC ETQP6F3R3HFA
RSENSE: IRC LR 2010-01-R010F
3851 TA02
3851f
25
LTC3851
TYPICAL APPLICATIONS
2.5V/15A Synchronized at 350kHz
VIN
6V TO 14V
C2
0.01μF
PLLIN
350kHz
R5
10k
CSS
0.1μF
C1
1000pF
MODE/PLLIN
VIN
FREQ/PLLFLTR
TG
RUN
CC2
100pF
M1
RJK0305DPB
CB
0.1μF
BOOST
LTC3851
TK/SS
CC
RC 1000pF
7.5k
CIN
180μF
ITH
SW
L1
0.68μH
DB
CMDSH-3
INTVCC
RSENSE
0.002Ω
C10
33pF
+
47pF
R2
43.2k
1%
4.7μF
VFB
M2
RJK0301DPB
D2
B34OLA
BG
SENSE–
GND
SENSE+
ILIM
R1
20k
1%
VOUT
2.5V
15A
+
COUT
330μF
s2
1000pF
COUT: SANYO 2R5TPE330M9
L1: SUMIDA CEP125-OR6MC
R22 100Ω
R20 100Ω
3851 TA04
4V to 40V Input to 12V Flyback Converter
VIN
4V TO 40V
CMDSH-3
FMMT625
CIN
22μF
50V
s2
10k
6.2V
3
7
•
1
RFREQ
80k
0.1μF
2
3
CSS
0.1μF
RC
1k
SW
FREQ/PLLFLTR
RUN
TG
BOOST
CC2
100pF 5
TK/SS
VIN
ITH
INTVCC
VFB
BG
C5
0.22μF
7
SENSE–
GND
8
SENSE+
ILIM
R2
113k
1%
M2
Si4850EY
15
M1
IRL2910S
14
RSENSE
0.004Ω
47Ω
MBRS1100
22Ω
1nF
100V
R1
8.06k
1%
+
COUT
220μF
16V
s4
1nF
100V
13
12
47pF
6
6
16
LTC3851
4
CC
10nF
MODE/PLLIN
VOUT
12V
3A
T1
10
•
VOUT
11
0.1μF
+
4.7μF
10
9
CIN: MARCON THCR70EIH226ZT
COUT: AVX TPSV227M016R0150
RSENSE: IRC LRF2512-01-R004F
T1: COILTRONICS VP5-0155
3851 TA05
3851f
26
LTC3851
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 p.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 p.0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 p .004
s 45o
(0.38 p 0.10)
.007 – .0098
(0.178 – 0.249)
2 3
4
5 6
7
.0532 – .0688
(1.35 – 1.75)
8
.004 – .0098
(0.102 – 0.249)
0o – 8o TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN16 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
BOTTOM VIEW—EXPOSED PAD
3.00 p 0.10
(4 SIDES)
0.70 p0.05
15
PIN 1
TOP MARK
(NOTE 6)
1
PACKAGE
OUTLINE
0.25 p0.05
0.50 BSC
16
0.40 p 0.10
1.45 p 0.10
(4-SIDES)
3.50 p 0.05
1.45 p 0.05
2.10 p 0.05 (4 SIDES)
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 s 45o CHAMFER
R = 0.115
TYP
0.75 p 0.05
2
(UD16) QFN 0904
0.200 REF
0.00 – 0.05
0.25 p 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3851f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC3851
TYPICAL APPLICATION
Dual Output 15W 3.3V/5V Power Supply
VIN
4.5V TO 28V
MODE/PLLIN
VIN
CIN
22μF
50V
RFREQ
80k
FREQ/PLLFLTR
0.1μF
CC
RC 4700pF
1k
CSS
0.1μF
RUN
CB
0.1μF
3
0.01μF
6
+
M3
Si4412DY
M1
Si4412DY
CMDSH-3
4.7k
MBRS140T3
COUT2
100μF
10V
s2
VOUT2
5V
1.5A
BOOST
DB
CMDSH-3
LTC3851
TK/SS
CC2
100pF
TG
T1C
•
SW
•
T1A
1
ITH
INTVCC
RSENSE
0.01Ω
T1B
•
8 2
7
R2
62.6k
1%
+
47pF
4.7μF
VFB
M2
Si4412DY
BG
SENSE–
GND
SENSE+
ILIM
VOUT1
3.3V
2.5A
+
R1
20k
1%
MBRS140T3
COUT1
100μF
10V
s2
1000pF
CIN: MARCON THCR70EIH226ZT
COUT1,2: AVX TPSD107M010R0065
RSENSE: IRC LRF2512-01-R010F
T1: BI TECHNOLOGIES HM00-93839
3851TA06
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PART NUMBER
DESCRIPTION
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PolyPhase is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation.
3851f
28 Linear Technology Corporation
LT 0708 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008