TI1 CY74FCT245TQCT 8-bit transceivers with 3-state output Datasheet

CY54FCT245T, CY74FCT245T
8-BIT TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS018B – MAY 1994 – REVISED NOVEMBER 2001
D
D
D
D
D
D
D
T/R
A0
A1
A2
A3
A4
A5
A6
A7
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE
B0
B1
B2
B3
B4
B5
B6
B7
CY54FCT245T . . . L PACKAGE
(TOP VIEW)
A2
A3
A4
A5
A6
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
B0
B1
B2
B3
B4
A7
GND
B7
B6
B5
description
OE
D
CY54FCT245T . . . D PACKAGE
CY74FCT245T . . . P, Q, OR SO PACKAGE
(TOP VIEW)
T/R
VCC
D
Function, Pinout, and Drive Compatible
With FCT and F Logic
Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
Ioff Supports Partial-Power-Down Mode
Operation
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
CY54FCT245T
– 48-mA Output Sink Current
12-mA Output Source Current
CY74FCT245T
– 64-mA Output Sink Current
32-mA Output Source Current
3-State Outputs
A1
A0
D
The ’FCT245T devices contain eight noninverting
bidirectional buffers with 3-state outputs and are
intended for bus-oriented applications.
The transmit/receive (T/R) input determines the direction of data flow through these bidirectional transceivers.
Transmit (active high) enables data from A ports to B ports. The output enable (OE), when high, disables both
the A and B ports by putting them in the high-impedance state.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CY54FCT245T, CY74FCT245T
8-BIT TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS018B – MAY 1994 – REVISED NOVEMBER 2001
ORDERING INFORMATION
TOP-SIDE
MARKING
Tape and reel
3.8
CY74FCT245DTQCT
FCT245D
QSOP – Q
Tape and reel
4.1
CY74FCT245CTQCT
FCT245C
Tube
4.1
CY74FCT245CTSOC
Tape and reel
4.1
CY74FCT245CTSOCT
DIP – P
Tube
4.6
CY74FCT245ATPC
CY74FCT245ATPC
QSOP – Q
Tape and reel
4.6
CY74FCT245ATQCT
FCT245A
Tube
4.6
CY74FCT245ATSOC
Tape and reel
4.6
CY74FCT245ATSOCT
Tape and reel
7
CY74FCT245TQCT
Tube
7
CY74FCT245TSOC
Tape and reel
7
CY74FCT245TSOCT
SOIC – SO
QSOP – Q
SOIC – SO
–55°C
55°C to 125°C
ORDERABLE
PART NUMBER
QSOP – Q
SOIC – SO
–40°C to 85°C
SPEED
(ns)
PACKAGE†
TA
FCT245C
FCT245A
FCT245
CDIP – D
Tube
4.5
CY54FCT245CTDMB
LCC – L
Tube
4.5
CY54FCT245CTLMB
CDIP – D
Tube
4.9
CY54FCT245ATDMB
LCC – L
Tube
4.9
CY54FCT245ATLMB
CDIP – D
Tube
7.5
CY54FCT245TDMB
LCC – L
Tube
7.5
FCT245
CY54FCT245TLMB
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OE
T/R
OPERATION
L
L
B data to bus A
L
H
A data to bus B
H
X
Z
H = High logic level, L = Low logic level,
X = Don’t care, Z = High-impedance
state
logic diagram (positive logic)
T/R
1
19
A0
2
18
To Seven Other Channels
2
OE
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
B0
CY54FCT245T, CY74FCT245T
8-BIT TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS018B – MAY 1994 – REVISED NOVEMBER 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θJA (see Note 1): P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
CY74FCT245T
CY74FCT245AT
CY74FCT245CT
CY74FCT245DT
CY54FCT245T
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
0.8
V
High-level output current
–12
–32
mA
IOL
TA
Low-level output current
48
64
mA
85
°C
High-level input voltage
2
Operating free-air temperature
–55
2
125
–40
V
V
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
CY54FCT245T, CY74FCT245T
8-BIT TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS018B – MAY 1994 – REVISED NOVEMBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
CY54FCT245T
TYP† MAX
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.75 V,
IIN = –18 mA
IIN = –18 mA
VCC = 4.5 V,
IOH = –12 mA
IOH = –32 mA
VCC = 4
4.75
75 V
MIN
–0.7
–1.2
–0.7
2.4
2.4
Vhys
All inputs
II
VCC = 5.5 V,
VCC = 5.25 V,
VIN = VCC
VIN = VCC
5
IIH
VCC = 5.5 V,
VCC = 5.25 V,
VIN = 2.7 V
VIN = 2.7 V
±1
IIL
VCC = 5.5 V,
VCC = 5.25 V,
VIN = 0.5 V
VIN = 0.5 V
±1
IOZH
VCC = 5.5 V,
VCC = 5.25 V,
VOUT = 2.7 V
VOUT = 2.7 V
10
IOZL
VCC = 5.5 V,
VCC = 5.25 V,
VOUT = 0.5 V
VOUT = 0.5 V
–10
IOS‡
VCC = 5.5 V,
VCC = 5.25 V,
VOUT = 0 V
VOUT = 0 V
VCC = 0 V,
VCC = 5.5 V,
VOUT = 4.5 V
VIN ≤ 0.2 V,
∆ICC
0.3
0.3
0.2
0.55
0.2
±1
±1
10
–10
–120
–225
–60
–120
±1
VIN ≥ VCC – 0.2 V
VIN ≥ VCC – 0.2 V
0.1
0.5
V
V
5
VIN ≤ 0.2 V,
VCC = 5.5 V, VIN = 3.4 V§, f1 = 0, Outputs open
VCC = 5.25 V,
3.3
0.55
IOL = 64 mA
–60
V
V
2
IOH = –15 mA
IOL = 48 mA
VCC = 4.5 V,
VCC = 4.75 V,
ICC
–1.2
UNIT
3.3
VOL
Ioff
CY74FCT245T
TYP† MAX
MIN
–225
±1
0.2
0.1
0.2
0.5
2
µA
µA
µA
µA
µA
mA
µA
mA
2
mA
VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open
VCC = 5.5 V, One input switching at 50% duty cycle,
Outputs open, T/R or OE = GND and
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
0.06
0.12
mA/
MHz
VCC = 5.25 V, One input switching at 50% duty cycle,
Outputs open, T/R or OE = GND and
0.06
0.12
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
† Typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or
sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, IOS tests should be performed last.
§ Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND
¶ This parameter is derived for use in total power-supply calculations.
ICCD¶
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CY54FCT245T, CY74FCT245T
8-BIT TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS018B – MAY 1994 – REVISED NOVEMBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
CY54FCT245T
TYP† MAX
TEST CONDITIONS
VCC = 5.5 V,
Outputs open,
open
T/R or OE = GND
IC#
VCC = 5.25 V,
Outputs open,
open
T/R or OE = GND
MIN
CY74FCT245T
TYP† MAX
MIN
One bit
switching
at f1 = 10 MHz
at 50% duty
cycle
VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
0.7
1.4
VIN = 3.4 V or GND
1.2
3.4
Eight bits
switching
at f1 = 2.5 MHz
at 50% duty
cycle
VIN ≤ 0.2V or
VIN ≥ VCC – 0.2 V
1.3
2.6||
VIN = 3.4 V or GND
3.3
10.6||
One bit
switching
at f1 = 10 MHz
at 50% duty
cycle
VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
0.7
1.4
VIN = 3.4 V or GND
1.2
3.4
Eight bits
switching
at f1 = 2.5 MHz
at 50% duty
cycle
VIN ≤ 0.2V or
VIN ≥ VCC – 0.2 V
1.3
2.6||
VIN = 3.4 V or GND
3.3
10.6||
UNIT
mA
Ci
Co
† Typical values are at VCC = 5 V, TA = 25°C.
# IC
= ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1)
Where:
= Total supply current
IC
ICC = Power-supply current with CMOS input levels
∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V)
DH
= Duty cycle for TTL inputs high
NT
= Number of TTL inputs at DH
ICCD = Dynamic current caused by an input transition pair (HLH or LHL)
f0
= Clock frequency for registered devices, otherwise zero
f1
= Input signal frequency
N1
= Number of inputs changing at f1
All currents are in milliamperes and all frequencies are in megahertz.
|| Values for these conditions are examples of the ICC formula.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
10
5
10
pF
9
12
9
12
pF
5
CY54FCT245T, CY74FCT245T
8-BIT TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS018B – MAY 1994 – REVISED NOVEMBER 2001
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPZH
tPZL
OE or T/R
A or B
tPHZ
tPLZ
OE or T/R
A or B
CY54FCT245T
CY54FCT245AT
CY54FCT245CT
MIN
MAX
MIN
MAX
MIN
MAX
1.5
7.5
1.5
4.9
1.5
4.5
1.5
7.5
1.5
4.9
1.5
4.5
1.5
10
1.5
6.5
1.5
6.2
1.5
10
1.5
6.5
1.5
6.2
1.5
10
1.5
6
1.5
5.2
1.5
10
1.5
6
1.5
5.2
UNIT
ns
ns
ns
switching characteristics over operating free-air temperature range (see Figure 1)
6
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPZH
tPZL
OE or T/R
A or B
tPHZ
tPLZ
OE or T/R
A or B
CY74FCT245T
CY74FCT245AT
CY74FCT245CT
CY74FCT245DT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.5
7
1.5
4.6
1.5
4.1
1.5
3.8
1.5
7
1.5
4.6
1.5
4.1
1.5
3.8
1.5
9.5
1.5
6.2
1.5
5.8
1.5
5
1.5
9.5
1.5
6.2
1.5
5.8
1.5
5
1.5
7.5
1.5
5
1.5
4.8
1.5
4.3
1.5
7.5
1.5
5
1.5
4.8
1.5
4.3
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
CY54FCT245T, CY74FCT245T
8-BIT TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS018B – MAY 1994 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
7V
From Output
Under Test
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
Open
TEST
GND
CL = 50 pF
(see Note A)
500 Ω
S1
500 Ω
S1
Open
7V
Open
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
LOAD CIRCUIT FOR
3-STATE OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
tsu
3V
1.5 V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
1.5 V
1.5 V
VOL
tPHL
Out-of-Phase
Output
tPLZ
≈3.5 V
1.5 V
tPZH
VOH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
Output
Waveform 1
(see Note B)
tPLH
1.5 V
1.5 V
tPZL
VOH
In-Phase
Output
3V
Output
Control
Output
Waveform 2
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9221401M2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629221401M2A
CY54FCT
245TLMB
5962-9221401MRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9221401MR
A
5962-9221403M2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629221403M2A
5962-9221403MRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9221403MR
A
CY54FCT245ATDM
B
5962-9221405M2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629221405M2A
CY54FCT
245CTLMB
5962-9221405MRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9221405MR
A
CY54FCT245ATDMB
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9221403MR
A
CY54FCT245ATDM
B
CY54FCT245CTLMB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629221405M2A
CY54FCT
245CTLMB
CY54FCT245TLMB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629221401M2A
CY54FCT
245TLMB
CY74FCT245ATPC
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
CY74FCT245ATPC
CY74FCT245ATPCE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
CY74FCT245ATPC
CY74FCT245ATQCT
ACTIVE
SSOP
DBQ
20
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FCT245A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2014
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CY74FCT245ATQCTE4
ACTIVE
SSOP
DBQ
20
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FCT245A
CY74FCT245ATQCTG4
ACTIVE
SSOP
DBQ
20
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FCT245A
CY74FCT245ATSOC
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT245A
CY74FCT245ATSOCE4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT245A
CY74FCT245ATSOCT
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT245A
CY74FCT245CTQCT
ACTIVE
SSOP
DBQ
20
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FCT245C
CY74FCT245CTSOC
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT245C
CY74FCT245TQCT
ACTIVE
SSOP
DBQ
20
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
FCT245
CY74FCT245TSOC
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT245
CY74FCT245TSOCG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT245
CY74FCT245TSOCT
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
FCT245
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2014
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CY74FCT245ATQCT
Package Package Pins
Type Drawing
SSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DBQ
20
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CY74FCT245ATSOCT
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
CY74FCT245CTQCT
SSOP
DBQ
20
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CY74FCT245TQCT
SSOP
DBQ
20
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CY74FCT245TSOCT
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CY74FCT245ATQCT
SSOP
DBQ
20
2500
367.0
367.0
38.0
CY74FCT245ATSOCT
SOIC
DW
20
2000
367.0
367.0
45.0
CY74FCT245CTQCT
SSOP
DBQ
20
2500
367.0
367.0
38.0
CY74FCT245TQCT
SSOP
DBQ
20
2500
367.0
367.0
38.0
CY74FCT245TSOCT
SOIC
DW
20
2000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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