FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Features Description ■ General Purpose PWM Regulator and LDO Controller The FAN5099 combines a high-efficiency pulse-width modulated (PWM) controller and an LDO (low drop out) linear regulator controller. The PWM controller is designed to operate over a wide frequency range (50kHz to 600kHz) to accommodate a variety of applications. Synchronous rectification provides high efficiency over a wide range of load currents. Efficiency is further enhanced by using the low-side MOSFET’s RDS(ON) to sense current. In addition, the capability to operate at low switching frequencies provides opportunities to boost power supply efficiency by reducing switching losses and gain cost savings using low-cost materials, such as powdered iron cores, on the output inductor. ■ Input Voltage Range: 3V to 24V ■ Output Voltage Range: 0.8V to 15V ■ VCC ■ ■ ■ ■ ■ ■ ■ ■ – 5V – Shunt Regulator for 12V Operation Support for Ceramic Cap on PWM Output Programmable Current Limit for PWM Output Wide Programmable Switching Frequency Range (50kHz to 600kHz) RDS(ON) Current Sensing Internal Synchronous Boot Diode Soft-Start for both PWM and LDO Multi-Fault Protection with Optional Auto-restart 16-Pin TSSOP Package Applications ■ High-Efficiency (80+) Computer Power Supplies ■ PC/Server Motherboard Peripherals – VCC_MCH (1.5V), VDDQ (1.5V) and VTT_GTL (1.25V) ■ Power Supply for – FPGA, DSP, Embedded Controllers, Graphic Card Processor, and Communication Processors ■ High-Power DC-to-DC Converters Both the linear and PWM regulator soft-start are controlled by a single external capacitor, to limit in rush current from the supply when the regulators are first enabled. Current limit for PWM is also programmable. The FAN5099’s ability to handle wide input voltage ranges makes this controller suitable for power solutions in a wide range of applications involving conversion input voltages from Silver box, battery, and adapters. The PWM regulator employs a summing-current-mode control with external compensation to achieve fast load transient response and provide system design optimization. FAN5099 is offered in both industrial temperature grade (-40°C to +85°C) as well as commercial temperature grade (-10°C to +85°C). Related Application Notes ■ AN-6020 FAN5099 Component Calculation and Simulation Tools ■ AN-6005 Synchronous Buck MOSFET Loss Calculations with Excel Model Ordering Information Part Number Operating Temperature Range Package Packing Method Qty/Reel FAN5099MTCX -10°C to +85°C 16-Lead TSSOP Tape and Reel 2500 FAN5099EMTCX -40°C to +85°C 16-Lead TSSOP Tape and Reel 2500 FAN5099MX -10°C to +85°C 16-Lead SOIC Tape and Reel 2500 FAN5099EMX -40°C to +85°C 16-Lead SOIC Tape and Reel 2500 All standard Fairchild Semiconductor products are RoHS compliant and many are also “GREEN” or going green. For Fairchild’s definition of “green” please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Contact Fairchild sales for availability of other package options. © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller May 2008 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Typical Application Figure 1. Typical Application Diagram © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 2 Figure 2. Pin Assignment Pin Description Pin No. Pin Name Pin Description 1 FBLDO LDO Feedback. This node is regulated to VREF. 2 R(T) Oscillator Set Resistor. This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 50kHz switching frequency is increased. 3 ILIM Current Limit. A resistor from this pin to GND sets the current limit. Soft-Start. A capacitor from this pin to GND programs the slew rate of the converter and the LDO during initialization. It also sets the time by which the converter delays when restarting after a fault occurs. SS has to reach 1.2V before fault shutdown feature is enabled. The LDO is enabled when SS reaches 2.2V. 4 SS 5 COMP 6 FB Feedback. This pin is the inverting input of the internal error amplifier. Use this pin, in combination with the COMP pin, to compensate the feedback loop of the converter. 7 EN Enable. Enables operation when pulled to logic high. Toggling EN resets the regulator after a latched fault condition. This is a CMOS input whose state is indeterminate if left open and needs to be properly biased at all times. 8 AGND Analog Ground. The signal ground for the IC. All internal control voltages are referred to this pin. Tie this pin to the ground island/plane through the lowest impedance connection available. 9 SW Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and drain of low-side MOSFET. 10 HDRV High-Side Gate Drive Output. Connect to the gate of the high-side power MOSFETs. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET is turned off. 11 BOOT Bootstrap Supply Input. Provides a boosted voltage to the high-side MOSFET driver. Connect to bootstrap capacitor as shown in Figure 1. 12 PGND Power Ground. The return for the low-side MOSFET driver. Connect to source of low-side MOSFET. 13 LDRV Low-Side Gate Drive Output. Connect to the gate of the low-side power MOSFETs. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET is turned off. 14 R(RAMP) Ramp Resistor. A resistor from this pin to VIN sets the ramp amplitude and provides voltage feed-forward. 15 VCC VCC. Provides bias power to the IC and the drive voltage for LDRV. Bypass with a ceramic capacitor as close to this pin as possible. This pin has a shunt regulator which draws current when the input voltage is above 5.6V. 16 GLDO COMP. The output of the error amplifier drives this pin. Gate Drive for the LDO. Turned off (low) until SS is greater than 2.2V. © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 3 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to AGND. Parameter Min. VCC to GND Continuous BOOT to GND BOOT to SW SW to GND HDRV to SW LDRV to PGND All Other Pins Unit 6.0 V Continuous -0.3 33 V Transient (t < 100ns, f < 500kHz) -0.5 35 V Continuous -0.5 6.0 V Transient (t < 50ns, f < 500kHz) -2.5 Continuous -0.5 33.0 V Transient (t < 50ns, f < 500kHz) -3.0 35.0 V Continuous -0.5 6.0 V Transient (t < 40ns, f < 500kHz) -2.5 Continuous -0.5 Transient (t < 40ns, f < 500kHz) -2.5 Continuous -0.3 V V 6.0 Human Body Model (Mil Std. 883E, Method 3015.7) 3.5 Charged Device Model (EIA/JESD22C101-A) 1.8 V V Maximum Shunt Current Electrostatic Discharge (ESD) Protection Level Max. VCC + 0.3 V 150 mA kV Thermal Information Symbols Max. Unit +150 °C Lead Soldering Temperature, 10 Seconds +300 °C Vapor Phase, 60 Seconds +215 °C Infrared, 15 Seconds +220 °C PD Power Dissipation, TA = 25°C 715 mW θJC Thermal Resistance – Junction-to-Case TSTG TL θJA Parameter Min. Storage Temperature Typ. -65 Thermal Resistance – Junction-to-Ambient (1) 37 °C/W 100 °C/W Notes: 1. Junction-to-ambient thermal resistance, θJA, is a strong function of PCB material, board thickness, thickness and number of copper planes, number of vias used, diameter of vias used, available copper surface, and attached heat sink characteristics. © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 4 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Absolute Maximum Ratings The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbols VCC Parameter Conditions Supply Voltage TA Ambient Temperature TJ Junction Temperature Min. Typ. Max. Unit VCC to GND 4.5 5.0 5.5 V Commercial -10 +85 °C Industrial -40 +85 °C +125 °C Electrical Characteristics Unless otherwise noted, VCC = 5V, TA = 25°C, using the circuit in Figure 1. The ‘•’ denotes that the specifications apply to the full ambient operating temperature range.(2,3) Symbol Parameter Conditions Min. Typ. Max. Unit 2.6 3.2 3.8 mA 200 400 μA 10 15 mA 5.9 V Supply Current IVCC VCC Current (Quiescent) HDRV, LDRV Open • IVCC(SD) VCC Current (Shutdown) EN = 0V, VCC = 5.5V • IVCC(OP) VCC Current (Operating) EN = 5V, VCC = 5.0V, QFET = 20nC, fSW = 200kHz VSHUNT VCC Voltage(4) Sinking 1mA to 100mA at VCC Pin 5.4 Under-Voltage Lockout (UVLO) UVLO(H) UVLO(L) Rising VCC UVLO Threshold • 4.00 4.25 4.50 V Falling VCC UVLO Threshold • 3.60 3.75 4.00 V VCC UVLO Threshold Hysteresis 0.5 V Current 10 μA VLDOSTART LDO Start Threshold 2.2 V 1.2 V Soft-Start ISS VSSOK PWM Protection Enable Threshold Oscillator fOSC Frequency R(T) = 25.5KΩ ± 1% 240 300 360 kHz R(T) = 199KΩ ± 1% 60 80 100 kHz R(T) = Open 50 Operating Frequency Range ΔVRAMP 40 kHz 600 kHz Ramp Amplitude (Peak-to-Peak) R(RAMP) = 330KΩ 0.4 V Minimum On Time f = 200kHz 200 ns Reference Voltage (Measured at FB Pin) TA = 0°C to 70°C • 790 800 810 mV TA = -40°C to 85°C • 788 800 812 mV Reference VREF Current Amplifier Reference (at SW node) 160 mV Continued on the following page... © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 5 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Recommended Operating Conditions Unless otherwise noted, VCC = 5V, TA = 25°C, using the circuit in Figure 1. The ‘•’ denotes that the specifications apply to the full ambient operating temperature range.(2, 3) Symbol Parameter Conditions Min. Typ. Max. Unit Error Amplifier GBWP S/R DC Gain 80 dB Gain-BW Product 25 MHz 8 V/μS Slew Rate Output Voltage Swing IFB 10pF across COMP to GND • No Load 0.5 4.0 V μA FB Pin Source Current Gate Drive RHUP HDRV Pull-up Resistor Sourcing • 1.8 3.0 Ω RHDN HDRV Pull-down Resistor Sinking • 1.8 3.0 Ω RLUP LDRV Pull-up Resistor Sourcing • 1.8 3.0 Ω RLDN LDRV Pull-down Resistor Sinking • 1.2 2.0 Ω 10 11 Protection/Disable 9 μA ILIM ILIMIT Source Current ISWPD SW Pull-down Current SW = 1V, EN = 0V VUV Under-Voltage Threshold As % of set point; 2μS noise filter • 65 75 80 % VOV Over-Voltage Threshold As % of set point; 2μS noise filter • 110 115 120 % Enable Condition • Disable Condition • mA Supply Current TSD VEN Thermal Shutdown Enable Threshold Voltage 160 °C 2.0 V 0.8 V Enable Source Current VCC = 5V 50 μA Enable Sink Current VCC = 5V and fault conditions (overload, short-circuit, over-voltage, under-voltage) 10 μA Low Drop-Out (LDO)(5) Reference Voltage VLDOREF (measured at FBLDO pin) Regulation VLDO_DO Drop-out Voltage External Gate Drive TA = 0°C to 70°C • 775 800 825 mV TA = -40°C to 85°C • 770 800 830 mV 0A ≤ ILOAD ≤ 5A • 1.17 1.20 1.23 V 0.3 V ILOAD ≤ 5A and RDS-ON < 50mΩ VCC = 4.75V • 4.5 V VCC = 5.6V • 5.3 V Gate Drive Source Current 1.2 mA Gate Drive Sink Current 400 μA Notes: 2. All limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality control. 3. AC specifications guaranteed by design/characterization (not production tested). 4. For a case when VCC is higher than the typical 5V VCC, voltage observed at VCC pin when the internal shunt regulator is sinking current to keep voltage on VCC pin constant. 5. Test Conditions: VLDO_IN = 1.5V and VLDO_OUT = 1.2V. © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 6 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Electrical Characteristics (Continued) VIN = 12V, Vdd = 5V, VOUT = 1.5V, Vldo = 1.2V, Iload = 5A, Ildo = 2A, fosc = 300kHz, unless otherwise noted. Ch1: HDRV; Ch2: LDRV. Dead times: 62ns, 32ns Ch1: VOUT; Ch3: IL, 5A/div Figure 6. PWM Load Transient (0 to 15A) Figure 3. Dead Time Waveform Ch1: VOUT_LDO; Ch3: ILDO, 1A/div Ch1: VOUT; Ch3: IL, 2.5A/div Figure 7. LDO Load Transient (0 to 2A) Figure 4. PWM Load Transient (0 to 5A) Ch1: VOUT_LDO; Ch3: ILDO, 2.5A/div Ch1: VOUT; Ch3: IL, 5A/div Figure 8. LDO Load Transient (0 to 5A) Figure 5. PWM Load Transient (0 to 10A) © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 7 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Typical Performance Characteristics VIN = 12V, Vdd = 5V, VOUT = 1.5V, Vldo = 1.2V, Iload = 5A, Ildo = 2A, fosc = 300kHz, unless otherwise noted. Ch1: VOUT; Ch2: SS; Ch3: EN Ch1: VOUT; Ch2:VOUT_LDO; Ch3: SS Figure 9. PWM/LDO Power Up Figure 12. Enable On (IPWM = 5A) Ch1: VOUT; Ch2: VOUT_LDO; Ch3: SS Ch1: VOUT; Ch2: SS; Ch3: EN Figure 13. Enable Off (IPWM = 5A) Figure 10. PWM/LDO Power Down Ch1: EN; Ch2: SS; Ch3: VOUT; Ch4: IL, 25A/div Figure 11. Auto Restart © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 Figure 14. PWM Line Regulation www.fairchildsemi.com 8 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Typical Performance Characteristics (Continued) VIN = 12V, Vdd = 5V, VOUT = 1.5V, Vldo = 1.2V, Iload = 5A, Ildo = 2A, fosc = 300kHz, unless otherwise noted. Figure 15. LDO Load Regulation Figure 18. RT vs. Frequency Figure 16. PWM Load Regulation Figure 19. 1.5V PWM Efficiency Figure 17. LDO Load Regulation Figure 20. Efficiency Comparison at VIN=12V © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 9 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Typical Performance Characteristics (Continued) Internal Vcc 5.6V Max. Vcc Shunt Reg RILIM BOOT CBOOT Internal Boot Diode 10μA Current Limit Comparator ILIM VIN COMP PW M Error Amplifier FB PWM Comparator RQ S Vref Vcc 10μA HDRV Adaptive Gate Drive Circuit LO Vout SW OSC CO SS V IN RRAMP Summing Current Sense Amplifier LDRV Ramp Generator R(RAMP) EN PGND Amplifier Enable Figure 21. Block Diagram Detailed Operation Description RVCC Selection (IC) FAN5099 combines a high-efficiency, fixed-frequency PWM controller designed for single-phase synchronous buck Point-Of-Load converters with an integrated LDO controller to support GTL-type loads. This controller is ideally suited to deliver low-voltage, high-current power supplies needed in desktop computers, notebooks, workstations, and servers. The controller comes with an integrated boot diode which helps reduce component cost and increase space savings. With this controller, the input to the power supply can be varied from 3V to 24V and the output voltage can be set to regulate at 0.8V to 15V on the switcher output. The LDO output can be configured to regulate between 0.8V to 3V and the input to the LDO can be from 1.5V to 5V, respectively. An internal shunt regulator at the VCC pin facilitates the controller operation from either a 5V or 12V power source. The selection of RVCC is dependent on: ■ Variation of the 12V supply ■ Sum of gate charges of top and bottom FETs (QFET) ■ Switching frequency (fSW) ■ Shunt regulator minimum current (1mA) ■ Quiescent Current of the IC (IQ) Calculate RVCC based on the minimum input voltage for the VCC: V I N MIN – 5.6 R VCC = --------------------------------------------------------------------------------------–3 ( I Q + 1 • 10 + Q FET • f SW • 1.2 ) (EQ. 1) For a typical example, where: VINMIN = 11.5V, IQ = 3mA, QFET = 30nC, fSW = 300kHz, RVCC is calculated to be 398.65Ω. VCC Bias Supply FAN5099 can be configured to operate from 5V or 12V for VCC. When 5V supply is used for VCC, no resistor is required to be connected between the supply and the VCC. When the 12V supply is used, a resistor RVCC is connected between the 12V supply and the VCC, as shown in Figure 1. The internal shunt regulator at the VCC pin is capable of sinking 150mA of current to ensure the controller’s internal VCC is maintained at 5.6V maximum. PWM Section The FAN5099’s PWM controller combines the conventional voltage mode control and current sensing through lower MOSFET RDS_ON to generate the PWM signals. This method of current sensing is loss-less and cost effective. For more accurate current sense requirements, an optional external resistor can be connected with the bottom MOSFET in series. Choose a resistor such that: ■ It is rated to handle the power dissipation. ■ Current sunk within the controller is minimized to prevent IC temperature rise. © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 10 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Block Diagram Refer to Figure 21 for the PWM control mechanism. The FAN5099 uses the summing mode method of control to generate the PWM pulses. The amplified output of the current-sense amplifier is summed with an internally generated ramp and the combined signal is amplified and compared with the output of the error amplifier to get the pulse width to drive the high-side MOSFET. The sensed current from the previous cycle is used to modulate the output of the summing block. The output of the summing block is also compared against the voltage threshold set by the RLIM resistor to limit the inductor current on a cycle-by-cycle basis. The controller facilitates external compensation for enhanced flexibility. V ( IN, nom ) – 1.8 R RAMP = ------------------------------------------- KΩ –8 6.3 ×10 × F OSC where fOSC is in Hz. For example, for fOSC = 80kHz and VIN = 12V, RRAMP = 2MΩ. Gate Drive Section The adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals and provides necessary amplification, level shifting, and shoot-through protection. It also has functions that help optimize the IC performance over a wide range of operating conditions. Since the MOSFET switching time can vary dramatically from device to device and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1V. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1V. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through. Initialization When the PWM is disabled, the SW node is connected to GND through an internal 500Ω MOSFET to slowly discharge the output. As long as the PWM controller is enabled, this internal MOSFET remains OFF. Soft-Start (PWM and LDO) When VCC exceeds the UVLO threshold and EN is high, the circuit releases SS and enables the PWM regulator. The capacitor connected to the SS pin and GND is charged by a 10µA internal current source, causing the voltage on the capacitor to rise. When this voltage exceeds 1.2V, all protection circuits are enabled. When this voltage exceeds 2.2V, the LDO output is enabled. The input to the error amplifier at the non-inverting pin is clamped by the voltage on the SS pin until it crosses the reference voltage. A low impedance path between the driver pin and the MOSFET gate is recommended for the adaptive deadtime circuit to work properly. Any delay along this path reduces the delay generated by the adaptive dead-time circuit, thereby increasing the chances for shoot-through. The time it takes the PWM output to reach regulation (tRise) is calculated using the following equation: t RISE = 8 × 10 –2 × C SS (CSS is in μf) (EQ. 4) (EQ. 2) Oscillator Clock Frequency (PWM) Protection The clock frequency on the oscillator is set using an external resistor, connected between R(T) pin and ground. The frequency follows the graph, as shown in Figure 18. The minimum clock frequency is 50kHz, which is when R(T) pin is left open. Select the value of R(T) as shown in the equation below. This equation is valid for all FOSC > 50kHz: In the FAN5099, the converter is protected against overload, short-circuit, over-voltage, and under-voltage conditions. All of these extreme conditions generate an internal “fault latch” which shuts down the converter. For all fault conditions, both the high-side and the low-side drives are off, except in the case of OVP, where the lowside MOSFET is turned on until the voltage on the FB pin goes below 0.4V. The fault latch can be reset either by toggling the EN pin or recycling VCC to the chip. 7 4 × 10 R ( t ) = ---------------------------------------------------------------5- kΩ 6.25 × f OSC – 2.99 × 10 (EQ. 3) Over-Current Limit (PWM) where, fOSC is in Hz. The PWM converter is protected against overloading through a cycle-by-cycle current limit set by selecting RILIM resistor. An internal 10µA current source sets the threshold voltage for the output of the summing amplifier. When the summing amplifier output exceeds this threshold level, the current limit comparator trips and the PWM starts skipping pulses. If the current limit tripping occurs for 16 continuous clock cycles, a fault latch is set and the For example, for fOSC = 80kHz, R(t) = 199kΩ. RRAMP Selection and Feedforward Operation The FAN5099 provides for input voltage feedforward compensation through RRAMP. The value of RRAMP effec© 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 11 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller tively changes the slope of the internal ramp, minimizing the variation of the PWM modulator gain when input voltage varies. The RRAMP effect on the current limit is explained in later sections. The RRAMP value can be approximated using the following equation: PWM Operation To achieve current limit, the FAN5099 monitors the inductor current during the OFF time by monitoring and holding the voltage across the lower MOSFET. The voltage across the lower MOSFET is sensed between the PGND and the SW pins. ) V OUT • 33.32 • 10 11 1.8 1 --------- • ---------------------------------------------------f SW • R RAMP V IN OFF VCC No restart after fault Cap to GND Restart after tDELAY (Sec.) = 0.85 x C where C is in μF The PWM converter output is monitored constantly for under voltage at the FB pin. If the voltage on the FB pin stays lower than 75% of internal VREF for 16 clock cycles, the fault latch is set and the converter shuts down. This shutdown feature is disabled during startup until the voltage on the SS capacitor reaches 1.2V. Over-Voltage Protection (PWM) The PWM converter output voltage is monitored constantly at the FB pin for over voltage. If the voltage on the FB pin stays higher than 115% of internal VREF for twoclock cycles, the controller turns OFF the upper MOSFET and turns ON the lower MOSFET. This crowbar action stops when the voltage on the FB pin comes down to 0.4V to prevent the output voltage from becoming negative. This over-voltage protection (OVP) feature is active when the voltage on the EN pin becomes HIGH. Set the current limit by choosing RILIM as follows: (( - Pull to GND Under Voltage Protection (PWM) For more accurate current limit setting, use resistor sensing. In a resistor sensing scheme, an appropriate current sense resistor is connected between the source terminal of the bottom MOSFET and PGND. 3 PWM/Restart The fault latch can also be reset by recycling the VCC to the controller. The output of the summing amplifier is a function of the inductor current, RDS_ON of the bottom FET and the gain of the current sense amplifier. With the RDS_ON method of current sensing, the current limit can vary widely from unit to unit. RDS_ON not only varies from unit to unit, but also has a typical junction temperature coefficient of about 0.4%/°C (consult the MOSFET datasheet for actual values). The set point of the actual current limit decreases in proportion to increase in MOSFET die temperature. A factor of 1.6 in the current limit set point typically compensates for all MOSFET RDS_ON variations, assuming the MOSFET's heat sinking keeps its operating die temperature below 125°C. K1 • I MAX • R DSON • 10 -+ R ILIM = 128 + ----------------------------------------------------------------1.43 EN Pin ) Turning ON the low-side MOSFETs on an OVP condition pulls down the output, resulting in a reverse current, which starts to build up in the inductor. If the output overvoltage is due to failure of the high-side MOSFET, this crowbar action pulls down the input supply or blows its fuse, protecting the system, which is very critical. (EQ. 5) where: RILIM is in KΩ; During soft-start, if the output overshoots beyond 115% of VREF, the output voltage is brought down by the lowside MOSFET until the voltage on the FB pin goes below 0.4V. The fault latch is NOT set until the voltage on the SS pin reaches 1.2V. Once the fault latch is set, the converter shuts down. IMAX is the maximum load current; and K1 is a constant to accommodate for the variation of MOSFET RDS(ON) (typically 1.6). With K1 = 1.6, IMAX = 20A, RDS(ON) = 7mΩ, VIN = 24V, VOUT = 1.5V, fSW = 300 kHz, RRAMP = 400 KΩ, RILIM calculates to be 323.17KΩ. 115% Vref Auto Restart (PWM) © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 S OV Delay 2 Clks FB The FAN5099 supports two modes of response when the internal fault latch is set. The user can configure it to keep the power supply latched in the OFF state OR in the auto restart mode. When the EN pin is tied to VCC, the power supply is latched OFF. When the EN pin is terminated with a 100nF to GND, the power supply is in auto restart mode. The table below describes the relationship between PWM restart and setting on EN pin. Do not leave the EN pin open without any capacitor. ILIM UV V SS >1.2V Q EN Fault Latch R S Q 0.4V LS Drive R Figure 22. Over-Voltage Protection Thermal Fault Protection The FAN5099 features thermal protection where the IC temperature is monitored. When the IC junction temperature exceeds +160°C, the controller shuts down and when the junction temperature gets down to +125°C, the converter restarts. www.fairchildsemi.com 12 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller controller shuts down the converter. This shutdown feature is disabled during the start-up until the voltage on the SS capacitor crosses 1.2V. The LDO controller is designed to provide ultra low voltages, as low as 0.8V for GTL-type loads. The regulating loop employs a very fast response feedback loop and small capacitors can be used to keep track of the changing output voltage during transients. For stable operation, the minimum capacitance on the output needs to be 100µF and the typical ESR needs to be around 100mΩ. operate at the boundary of continuous and discontinuous conduction modes. Setting the Output Voltage (PWM) The internal reference for the PWM controller is at 0.8V. The output voltage of the PWM regulator can be set in the range of 0.8V to 90% of its power input by an external resistor divider. The output is divided down by an external voltage divider to the FB pin (for example, R1 and RBIAS as in Figure 25). The output voltage is given by the following equation: The maximum voltage at the gate drive for the MOSFET can reach close to 0.5V below the VCC of the controller. For example, for a 1.2V output, the minimum enhancement voltage required with 4.75V on VCC is 3.05V (4.75V-0.5V-1.2V = 3.05V). The dropout voltage for the LDO is dependent on the load current and the MOSFET chosen. It is recommended to use low enhancement voltage MOSFETs for the LDO. In an application where LDO is not needed, pull up the FBLDO pin (Pin 1) higher than 1V to disable the LDO. R1 VOUT = 0.8V × ⎛ 1 + ----------------⎞ ⎝ R BIAS⎠ To minimize noise pickup on this node, keep the resistor to GND (RBIAS) below 10KΩ. Inductor Selection (PWM) The soft-start on the LDO output (ramp) is controlled by the capacitor on the SS pin to GND. The LDO output is enabled only when the voltage on the SS pin reaches 2.2V. Refer to Figure 9 for startup waveform. When the ripple current, switching frequency of the converter, and the input-output voltages are established, select the inductor using the following equation: VOUT 2 ⎛V – -------------- ⎞ ⎝ OUT V IN ⎠ L MIN = -------------------------------------------(EQ. 7) I Ripple × f SW Design Section General Design Guidelines where IRipple is the ripple current. Establishing the input voltage range and the maximum current loading on the converter before choosing the switching frequency and the inductor ripple current is highly recommended. There are design tradeoffs choosing optimum switching frequency and ripple current. This number typically varies between 20% to 50% of the maximum steady-state load on the converter. When selecting an inductor from the vendors, select the inductance value which is close to the value calculated at the rated current (including half the ripple current). The input voltage range should accommodate the worstcase input voltage with which the converter may ever operate. This voltage needs to account for the cable drop encountered from the source to the converter. Typically, the converter efficiency tends to be higher at lower input voltage conditions. Input Capacitor Selection (PWM) The input capacitors must have an adequate RMS current rating to withstand the temperature rise caused by the internal power dissipation. The combined RMS current rating for the input capacitor should be greater than the value calculated using the following equation: When selecting maximum loading conditions, consider the transient and steady-state (continuous) loading separately. The transient loading affects the selection of the inductor and the output capacitors. Steady-state loading affects the selection of MOSFETs, input capacitors, and other critical heat-generating components. ⎛ V OUT VOUT 2⎞ IINPUT ( RMS ) = I LOAD ( MAX ) × ⎜ -------------- – ⎛⎝ --------------⎞⎠ ⎟ V IN ⎠ (EQ. 8) ⎝ VIN Common capacitor types used for such application include aluminum, ceramic, POS CAP, and OSCON. The selection of switching frequency is challenging. While higher switching frequency results in smaller components, it also results in lower efficiency. Ideal selection of switching frequency takes into account the maximum operating voltage. The MOSFET switching losses are directly proportional to fSW and the square function of the input voltage. Output Capacitor Selection (PWM) The output capacitors chosen must have low enough ESR to meet the output ripple and load transient requirements. The ESR of the output capacitor should be lower than both of the values calculated below to satisfy both the transient loading and steady-state ripple conditions as given by the following equation: When selecting the inductor, consider the minimum and maximum load conditions. Lower inductor values produce better transient response, but result in higher ripple and lower efficiency due to high RMS currents. Optimum minimum inductance value enables the converter to © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 (EQ. 6) V STEP ESR ≤ ---------------------------------- and ΔI LOAD ( MAX ) V Ripple ESR ≤ ------------------I Ripple (EQ. 9) www.fairchildsemi.com 13 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller LDO Section Output Capacitor Selection (LDO) Figure 24. Drive Equivalent Circuit For stable operation, the minimum capacitance of 100µF with ESR around 100mΩ is recommended. For other values, contact the factory. The upper graph in Figure 23 represents Drain-toSource Voltage (VDS) and Drain Current (ID) waveforms. The lower graph details Gate-to-Source Voltage (VGS) versus time with a constant current charging the gate. The x-axis is representative of Gate Charge (QG). CISS = CGD + CGS and controls t1, t2, and t4 timing. CGD receives current from the gate driver during t3 (as VDS is falling). Obtain the gate charge (QG) parameters shown on the lower graph from the MOSFET datasheets. Power MOSFET Selection (PWM) The FAN5099 is capable of driving N-Channel MOSFETs as circuit switch elements. For better performance, MOSFET selection should address these key parameters: ■ The maximum Drain-to-Source Voltage (VDS) should be at least 25% higher than the worst-case input voltage. Assuming switching losses are about the same for both the rising edge and falling edge, Q1's switching losses occur during the shaded time when the MOSFET has voltage across it and current through it. ■ The MOSFETs should have low QG, QGD, and QGS. ■ The RDS_ON of the MOSFETs should be as low as possible. In typical applications for a buck converter, the duty cycles are lower than 20%. To optimize the selection of MOSFETs for both the high-side and low-side, follow different selection criteria. Select the high-side MOSFET to minimize the switching losses and the low-side MOSFET to minimize the conduction losses due to the channel and the body diode losses. Note that the gate drive losses also affect the temperature rise on the controller. Losses are given by Equations 10-12: PUPPER = PSW + PCOND V DS × I L P SW = ⎛⎝ --------------------- × 2 × t s⎞⎠ f SW 2 V OUT 2 × R DS ( ON ) PCOND = ⎛ --------------⎞ × IOUT ⎝ VIN ⎠ For loss calculation, refer to Fairchild's Application Note AN-6005 and the associated spreadsheet. (EQ. 10) (EQ. 11) (EQ. 12) where PUPPER is the upper MOSFET's total losses and PSW and PCOND are the switching and conduction losses for a given MOSFET RDS(ON) is at the maximum junction temperature (TJ) and tS is the switching period (rise or fall time) and equals t2+t3, as shown in Figure 23. High-Side Losses To understand losses in the MOSFET, follow the MOSFET switching interval shown in Figure 23. The MOSFET gate drive equivalent circuit is shown in Figure 24. The driver's impedance and CISS determine t2 while t3's period is controlled by the driver's impedance and QGD. Since most of tS occurs when VGS = VSP, assume a constant current for the driver to simplify the calculation of tS with the following equation: Q G ( SW ) Q G ( SW ) ts = -------------------- ≈ ---------------------------------------------I Driver ⎛ V CC – VSP ⎞ ---------------------------------------⎝ R Driver + R Gate⎠ (EQ. 13) Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as: QG(SW) = QGD + QGS – QTH where QTH is the gate charge required to reach the MOSFET threshold (VTH). Note that for the high-side MOSFET, VDS equals VIN, which can be as high as 20V in a typical portable application. Include the power delivered to the MOSFET's (PGATE) in calculating the power dissipation required for the FAN5099. Figure 23. Switching Losses and Qg © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 14 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller In the case of aluminum and polymer-based capacitors, the output capacitance is typically higher than normally required to meet these requirements. While selecting the ceramic capacitors for the output; although lower ESR can be achieved easily, higher capacitance values are required to meet the VOUT(MIN) restrictions during a load transient. From the stability point of view, the zero caused by the ESR of the output capacitor plays an important role in the stability of the converter. R-C components for the snubber are selected as follows: (EQ. 14) P Gate = Q G × VCC × fSW a) Measure the SW node ringing frequency (fring) with a low capacitance scope probe. where QG is the total gate charge to reach VCC. b) Connect a capacitor (CSNUB) from SW node to GND so that it reduces this ringing by half. Low-Side Losses Q2 switches on or off with its parallel Schottky diode simultaneously conducting, so the VDS ≈ 0.5V. Since PSW is proportional to VDS, Q2's switching losses are negligible and Q2 is selected based on RDS(ON) alone. c) Place a resistor (RSNUB) in series with this capacitor. RSNUB is calculated using the following equation: 2 R SNUB = ----------------------------------------------π × Fring × CSNUB (EQ. 17) Conduction losses for Q2 are given by the equation: d) Calculate the power dissipated in the snubber resistoras shown in the following equation: 2 P COND = ( 1 – D ) × IOUT × R DS ( ON ) (EQ. 15) 2 P R ( SNUB ) = C SNUB × V IN ( MAX ) × fSW where RDS(ON) is the RDS(ON) of the MOSFET at the highest operating junction temperature and D=VOUT/VIN is the minimum duty cycle for the converter. where, VIN(MAX) is the maximum input voltage and FSW is the converter switching frequency. Since DMIN < 20% for portable computers, (1-D) ≈ 1 produces a conservative result, simplifying the calculation. The snubber resistor chosen should be de-rated to handle the worst-case power dissipation. Do not use wirewound resistors for RSNUB. The maximum power dissipation (PD(MAX)) is a function of the maximum allowable die temperature of the lowside MOSFET, the θJA, and the maximum allowable ambient temperature rise. PD(MAX) is calculated using the following equation: TJ ( MAX ) – T A ( MAX ) P D ( MAX ) = ------------------------------------------------θ JA (EQ. 18) Loop Compensation Typically, the closed-loop crossover frequency (fcross), where the overall gain is unity, should be selected to achieve optimal transient and steady-state response to disturbances in line and load conditions. It is recommended to keep fcross below one-fifth of the switching frequency of the converter. Higher phase margin tends to have a more stable system with more sluggish response to load transients. Optimum phase margin is about 60°, a good compromise between steady-state and transient responses. A typical design should address variations over a wide range of load conditions and over a large sample of devices. (EQ. 16) θJA depends primarily on the amount of PCB area devoted to heat sinking. Selection of MOSFET Snubber Circuit The switch node (SW) ringing is caused by fast switching transitions due to energy stored in parasitic elements. This ringing on the SW node couples to other circuits around the converter if they are not handled properly. To dampen ringing, an R-C snubber is connected across the SW node and the source of the low-side MOSFET. VIN VIN Current Sense Amplifier RRAMP Ramp Generator Summing Q1 L PWM & DRIVER RDC VOUT C Q2 Amplifier RL RES C2 C1 R2 C3 RBIAS R3 R1 Reference Figure 25. Closed-Loop System with Type-3 Network © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 15 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller PGATE is determined by the following equation: Note: For critical applications requiring wide loop bandwidth using very low ESR output capacitors, use type-3 compensation. ■ Venable, H. Dean, "The K factor: A new mathematical tool for stability analysis and synthesis," Proceedings of Powercon, March 1983. Type-3 Feedback Component Calculations Use these steps to calculate feedback components: Notation: C 0 = Net Output Filter Capacitance G p ( s ) = Net Gain of Plant = control-to-output transfer function L = Inductor Value R DSON = On-State Drain-to Source Resistance of Low-side MOSFET R es = Net ESR of the output filter capacitors R L = Load Resistance t s = Switching Period Vi = Input Voltage fSW = Switching Frequency Equations: Effective current sense resistance = R i = 7 × R DSON (EQ. 19) RL Current modulator DC gain = M i = ------Ri (EQ. 20) ( V i – 1.8 ) × Ts Effective ramp amplitude = V m = 3.33 × 10 10 × -----------------------------------R ramp (EQ. 21) Vi Voltage modulator DC gain = M v = -------Vm (EQ. 22) Mv × Mi Plant DC gain = M o = M v || M i = -------------------Mv + Mi (EQ. 23) π Sampling gain natural frequency = ω n = -----Ts (EQ. 24) MO Mv × Ri Effective inductance = L e = -------- × ⎛ L + --------------------⎞ ⎝ ω n × Q z⎠ Mv (EQ. 25) Mv × Ri × RL R p = --------------------------------- = ( M v × R i ) || R L Mv × Ri + RL (EQ. 26) © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 16 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller FAN5099 has a high gain error amplifier around which the loop is closed. Figure 25 shows a type-3 compensation network. For type-2 compensation, R3 and C3 are not used. Since the FAN5099 architecture employs summing current mode, type-2 compensation can be used for most applications. For for further information about type-2 compensation networks, refer to the following: 1 Plant zero frequency = f z = -----------------------------------------2 × π × C o × Res (EQ. 27) 1 Plant 1st pole frequency = f p1 = ----------------------------------------------------------Le 2 × π × ⎛ C o × R p + -------⎞ ⎝ R L⎠ (EQ. 28) Rp 1 1 Plant 2nd pole frequency = f p2 = ------------ × ⎛ -------------------- + -------⎞ 2 × π ⎝ Co × RL Le ⎠ (EQ. 29) 2 ωn × Le Plant 3rd pole frequency = fp3 = -------------------------2 × π × Rp (EQ. 30) Plant gain (magnitude) response: f 2 1 + ⎛ ----⎞ ⎝ fz⎠ G p (f) = 20 × log M 0 + 10 × log --------------------------------------------------------------------------------------------------------2 f 2 f 2 f 1 + ⎛ -------⎞ × 1 + ⎛ -------⎞ × 1 + ⎛ -------⎞ ⎝ f p1⎠ ⎝ fp2⎠ ⎝ f p3⎠ (EQ. 31) Plant phase response: –1 f –1 f –1 f –1 f ∠G P (f) = tan ⎛⎝ ----⎞⎠ – tan ⎛⎝ -------⎞⎠ – tan ⎛⎝ -------⎞⎠ – – tan ⎛⎝ -------⎞⎠ fz f p1 f p2 fp3 (EQ. 32) Choose R1, RBIAS to set the output voltage using Equation 5. Choose the zero crossover frequency fcross of the overall loop. Typically Fcross should be less than 1/5th of fsw. Choose the desired phase margin. Typically this number should be between 60° to 90°. Calculate plant gain at fcross using Equation 30 by substituting fcross in place of f. The gain that the amplifier needs to provide to get the required crossover is given by: 1 (EQ. 33) G AMP = -----------------------------G p (fcross ) The phase boost required is calculated as given in (EQ. 34). Phase Boost = M – ∠G P (Fcross ) – 90° (EQ. 34) where M is the desired phase margin in degrees. The feedback component values are now calculated as given in equations below: ⎧ K = ⎨ Tan ⎩ 2 ⎫ ⎛ Boost ----------------⎞ + 45 ⎬ ⎝ 4 ⎠ ⎭ (EQ. 35) 1 C2 = ---------------------------------------------------------------------2 × π × fcross × G AMP × R1 (EQ. 36) C1 = C2 × ( K – 1 ) (EQ. 37) 1 C3 = -------------------------------------------------------------2 × π × f cross × K × R3 (EQ. 38) K R2 = -----------------------------------------------2 × π × f cross × C1 (EQ. 39) R1 R3 = -----------------(K – 1) (EQ. 40) © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 17 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Poles and Zeros of Plant Transfer Function: Layout Considerations Fairchild application note AN-6020 provides a PSPICE model and spreadsheet calculator for the PWM regulator, simplifying external component selections and verifying loop stability. The topics covered in the datasheet provide an understanding behind the calculations in the spreadsheet. The switching power converter layout needs careful attention and is critical to achieving low losses and clean and stable operation. Below are specific recommendations for a good board layout: The spreadsheet calculator, which is part of AN-6020 can be used to calculate all external component values for designing around FAN5099. The spreadsheet provides optimized compensation components and generates a Bode plot to ensure loop stability. ■ Use thick copper boards whenever possible to Based on the input values entered, AN-6020’s PSPICE model can be used to simulate Bode plots (for loop stability) as well as transient analysis that help customize the design for a wide range of applications. ■ ■ Keep the high current traces and load connections as short as possible. achieve higher efficiency. ■ Keep the loop area between the SW node, low-side ■ Use Fairchild application note AN-6005 for prediction of the losses and die temperatures for the power semiconductors used in the circuit. ■ Both AN-6020 and AN-6005 can be downloaded from www.fairchildsemi.com/apnotes/. ■ ■ ■ ■ ■ ■ © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 MOSFET, inductor, and the output capacitor as small as possible. Route high dV/dt signals, such as SW node, away from the error amplifier input/output pins. Keep components connected to these pins close to the pins. Place ceramic de-coupling capacitors very close to VCC pin. All input signals are referenced with respect to AGND pin. Dedicate one layer of the PCB for a GND plane. Use at least four layers for the PCB. Minimize GND loops in the layout to avoid EMI-related issues. Use wide traces for the lower gate drive to keep the drive impedances low. Connect PGND directly to the lower MOSFET source pin. Use wide land areas with appropriate thermal vias to effectively remove heat from the MOSFETs. Use snubber circuits to minimize high-frequency ringing at the SW nodes. Place the output capacitor for the LDO close to the source of the LDO MOSFET. www.fairchildsemi.com 18 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Design Tools VIN = 3 to 24V; VOUT =1.5V at 20A; fOSC = 300kHz. Figure 26. Application Board Schematic Bill of Materials Part Description Quantity Designator Vendor Vendor Part Number Capacitor, 1500pF, 10%, 50V, 0603, X7R 1 C1 Panasonic Capacitor, 220pF, 5%, 50V, 0603, NPO 1 C2 Panasonic ECJ1VB1H152K ECJ1VC1H221J Capacitor, 3300pF, 10%, 50V, 0603, X7R 1 C3 Panasonic ECJ1VB1H332K ECJ1VB1E104K Capacitor, 0.1µF, 10%, 25V, 0603, X7R 4 C4, C5, C6, C15 Panasonic Capacitor, 0.22µF, 20%, 25V, 0603, X7R 2 C7, C8 TDK C1608JB1E224K Capacitor, 0.01µF, 10%, 50V, 0603, X7R 1 C9 Panasonic ECJ1VB1H103K Capacitor, 820µF, 20%, 10X20, 25V, 20mΩ, 1.96A 2 C10, C11 Nippon-Chemicon KZH25VB820MHJ20 Capacitor, 820µF, 20%, 8X8, 2.5V, 7mΩ, 6.1A 1 C17 Nippon-Chemicon PSC2.5VB820MH08 Capacitor, 560µF, 20%, 8X11.5, 4V, 7mΩ, 5.58A 3 C12, C13, C14 Nippon-Chemicon PSA4VB560MH11 Capacitor, 3300pF, 10%, 50V, 0805, X7R 1 C16 Panasonic ECJ2VB1H332K Connector Header 0.100 Vertical, Tin – 2 Pin 1 J1 Molex 22-28-4360 Terminal Quickfit Male .052"Dia.187" Tab 6 J2–J7 Keystone 1212 Inductor, 1.8µH, 20%, 26Amps Max, 3.24mΩ 1 L1 Inter-Technical SC5018-1R8M MOSFET N-CH, 32mΩ, 20V, 21A, D-PAK, FSID: FDD6530A 1 Q1 Fairchild Semiconductor FDD6530A FDD6296 MOSFET N-CH, 8.8mΩ, 30V, 50A, D-PAK, FSID: FDD6296 1 Q2 Fairchild Semiconductor MOSFET N-CH, 6mΩ, 30V, 75A, D-PAK, FSID: FDD6606 2 Q3, Q4 Fairchild Semiconductor FDD6606 Resistor, 5.11k, 1%, 1/16W 1 R1 Panasonic ERJ3EKF5111V Resistor, 12.7k, 1%, 1/16W 1 R2 Panasonic ERJ3EKF1272V Resistor, 825, 1%, 1/16W 1 R3 Panasonic ERJ3EKF8250V Resistor, 25.5k, 1%, 1/16W 1 R4 Panasonic ERJ3EKF2552V Resistor, 210k, 1%, 1/16W 1 R5 Panasonic ERJ3EKF2103V Resistor, 453k, 1%, 1/16W 1 R6 Panasonic ERJ3EKF453V Resistor, 10k, 1%, 1/16W 1 R7 Panasonic ERJ3EKF1002V Resistor, 4.99k, 1%, 1/16W 1 R8 Panasonic ERJ3EKF4991V Resistor, 200, 1%, 1/4W 1 R9 Panasonic ERJ8ENF2000V Resistor, 5.90k, 1%, 1/16W 1 R10 Panasonic ERJ3EKF5901V Resistor, 2.2, 1%, 1/4W 1 R11 Panasonic ERJ8RQF2R2V Connector Header 0.100 Vertical, Tin – 1 Pin 3 TP1, TP2, Vcc Molex 22-28-4360 IC, System Regulator, TSSOP16, FSID: FAN5099 1 U1 Fairchild Semiconductor FAN5099 © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 19 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Application Board Schematic VIN = 3 to 24V; VOUT =1.5V at 20A; fOSC = 80kHz. Figure 27. Application Board Schematic Bill of Materials Part Description Quantity Designator Vendor Vendor Part Number Capacitor, 3900pF, 10%, 50V, 0603, X7R 1 C1 Panasonic Capacitor, 680pF, 5%, 50V, 0603, NPO 1 C2 Panasonic ECJ1VB1H392K ECJ1VC1H681J Capacitor, 6800pF, 10%, 50V, 0603, X7R 1 C3 Panasonic ECJ1VB1H682K Capacitor, 0.1µF, 10%, 25V, 0603, X7R 4 C4, C5, C6, C15 Panasonic ECJ1VB1E104K Capacitor, 0.22µF, 20%, 25V, 0603, X7R 2 C7, C8 TDK C1608JB1E224K Capacitor, 0.01µF, 10%, 50V, 0603, X7R 1 C9 Panasonic ECJ1VB1H103K Capacitor, 820µF, 20%, 10X20, 25V, 20mΩ, 1.96A 2 C10, C11 Nippon-Chemicon KZH25VB820MHJ20 PSC2.5VB820MH08 Capacitor, 820µF, 20%, 8X8, 2.5V, 7mΩ, 6.1A 1 C17 Nippon-Chemicon Capacitor, 560µF, 20%, 8X11.5, 4V, 7mΩ, 5.58A 3 C12, C13, C14 Nippon-Chemicon PSA4VB560MH11 Capacitor, 3300pF, 10%, 50V, 0805, X7R 1 C16 Panasonic ECJ2VB1H332K Connector Header 0.100 Vertical, Tin – 2 Pin 1 J1 Molex 22-28-4360 Terminal Quickfit Male .052"Dia.187" Tab 6 J2–J7 Keystone 1212 Inductor, 4.0µH at 25A, 9.0µH at 0A, 25A max, 4.4mΩ, wound on T80-52B core (Micrometals), 12 turns, 14 AWG wire 1 L1 Custom made MOSFET N-CH, 32mΩ, 20V, 21A, D-PAK, FSID: FDD6530A 1 Q1 Fairchild Semiconductor MOSFET N-CH, 8.8mΩ, 30V, 50A, D-PAK, FSID: FDD6296 1 Q2 Fairchild Semiconductor FDD6296 MOSFET N-CH, 6mΩ, 30V, 75A, D-PAK, FSID: FDD6606 2 Q3, Q4 Fairchild Semiconductor FDD6606 FDD6530A Resistor, 5.11k, 1%, 1/16W 1 R1 Panasonic ERJ3EKF5111V Resistor, 10.5k, 1%, 1/16W 1 R2 Panasonic ERJ3EKF1052V Resistor, 845, 1%, 1/16W 1 R3 Panasonic ERJ3EKF8450V Resistor, 200k, 1%, 1/16W 1 R4 Panasonic ERJ3EKF2003V Resistor, 287k, 1%, 1/16W 1 R5 Panasonic ERJ3EKF2873V Resistor, 453k, 1%, 1/16W 1 R6 Panasonic ERJ3EKF453V Resistor, 10k, 1%, 1/16W 1 R7 Panasonic ERJ3EKF1002V Resistor, 4.99k, 1%, 1/16W 1 R8 Panasonic ERJ3EKF4991V Resistor, 200, 1%, 1/4W 1 R9 Panasonic ERJ8ENF2000V Resistor, 5.90k, 1%, 1/16W 1 R10 Panasonic ERJ3EKF5901V Resistor, 2.2, 1%, 1/4W 1 R11 Panasonic ERJ8RQF2R2V Connector Header 0.100 Vertical, Tin – 1 Pin 3 TP1, TP2, Vcc Molex 22-28-4360 IC, System Regulator, TSSOP16, FSID: FAN5099 1 U1 Fairchild Semiconductor FAN5099 © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 20 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Application Board Schematic FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Typical Application Board Layout Figure 28. Assembly Diagram Figure 31. Mid Layer 2 Figure 29. Top Layer Figure 32. Bottom Layer Figure 30. Mid Layer 1 © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 21 5.00±0.10 4.55 5.90 4.45 7.35 0.65 4.4±0.1 1.45 5.00 0.11 12° MTC16rev4 Figure 33. 16-Lead Thin Shrink Small Outline Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 22 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Mechanical Dimensions 10.00 9.80 A 8.89 16 9 B 4.00 3.80 6.00 PIN ONE INDICATOR 1.75 1 5.6 8 0.51 0.35 1.27 (0.30) 0.25 M 1.27 C B A 0.65 LAND PATTERN RECOMMENDATION 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C 0.50 0.25 X 45° NOTES: UNLESS OTHERWISE SPECIFIED (R0.10) GAGE PLANE (R0.10) 8° 0° 0.36 A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AC, ISSUE C. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH AND TIE BAR PROTRUSIONS D) CONFORMS TO ASME Y14.5M-1994 E) LANDPATTERN STANDARD: SOIC127P600X175-16AM F) DRAWING FILE NAME: M16AREV12. SEATING PLANE 0.90 0.50 (1.04) DETAIL A SCALE: 2:1 Figure 34. 16-Lead Molded Small Outline Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 23 FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller Mechanical Dimensions (continued) FAN5099 — Wide Frequency Synchronous Buck PWM & LDO Controller © 2006 Fairchild Semiconductor Corporation FAN5099 Rev. 1.1.5 www.fairchildsemi.com 24