Sony CXA1866Q 6-bit 140msps flash a/d converter Datasheet

CXA1866Q
6-bit 140MSPS Flash A/D Converter
For the availability of this product, please contact the sales office.
Description
The CXA1866Q is a 6-bit ultra-high-speed flash
A/D converter IC capable of digitizing analog
signals at the maximum rate of 140MSPS. The
digital input level is compatible with ECL
100K/10KH/10K.
48 pin QFP (Plastic)
Features
• Ultra-high-speed operation with maximum
conversion rate of 140MSPS
• Low input capacitance: 7pF
• Wide analog input bandwidth: 210MHz
• Low power consumption: 325mW
• Low error rate
• Excellent temperature characteristics
• 1 : 2 demultiplexed output (TTL level)
Structure
Bipolar silicon monolithic IC
VRB 16
VIN
VRTS
Block Diagram
VRBS
Applications
• Magnetic recording (PRML)
• Communications (QPSK, QAM)
• Liquid crystal display
15
19
22
21
Reference Resistance Chain
VRT
COMPARATOR
6bit Latch
41 DVEE
6
INV 27
23
20 AGND
CLatchA
CCLK 26
AVEE
CD
NCCLK 25
46
DGND1
45 DGND2
42 DGND3
CLatchB
6
DCLK 11
CD
DVCC1
48
DVCC2
TTLOUT
P1D1
P1D0 (LSB)
P2D2
35 34 33 32 31 30
P1D2
P2D3
2
P1D3
P2D4
3
P1D4
4
P1D5 (MSB)
5
P2D1
6
P2D0 (LSB)
7
P2D5 (MSB)
NDCLK 12
CD; Clock Driver
47
6
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93Z35B77
CXA1866Q
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
AVEE, DVEE
DVCC∗1
• Analog input voltage
VIN
• Reference input voltage
VRT, VRB
I VRT – VRB I
• Digital input voltage
DIN∗2
I CCLK – NCCLK I, I DCLK – NDCLK I
• Digital output current
ID0 to ID6
• Storage temperature
Tstg
• Ambient operating temperature Ta
• Allowable power dissipation
PD
Recommended Operating Conditions
• Supply voltage
AVEE, DVEE
AVEE – DVEE
AGND – DGND∗3
DVCC∗1
40
40
–1.5
140
70
60
60
TPWH + 1
+75
NCCLK
CCLK
INV
DGND3
DVCC2
P1D3
∗3 DGND = DGND1, DGND2, DGND3
∗4 Refer to the Timing Chart 1 for TPWL, TPWH.
P1D4
DGND3
Pin Configuration.
Pins without names are NC pins
(not connected).
P1D5 (MSB)
∗1 DVCC = DVCC1, DVCC2
∗2 DIN = CCLK, NCCLK, DCLK, NDCLK, INV
Max.
–4.75
0.05
0.05
5.25
0.1
–0.8
VRT
50
50
0
–TPWL + 2
–20
P1D0 (LSB)
CCLK, NCCLK frequency
DCLK, NDCLK frequency
CCLK, NCCLK duty
DCLK, NDCLK duty
CCLK-DCLK time difference∗4
Operating temperature
Typ.
–5.2
0
0
5.0
0
–2.0
36 35 34 33 32 31 30 29 28 27 26 25
DVCC2 37
24
DVCC1 38
23
AVEE
DGND1 39
22
VRTS
DGND2 40
21
VRT
DVEE 41
CXA1866Q
DGND3 42
(Top View)
20
AGND
19
VIN
VRBS
14
AVEE
DVCC2 48
13
3
4
5
6
7
8
9 10 11 12
–2–
NDCLK
2
DCLK
1
DVCC2
15
DVCC1 47
DGND3
DGND1 46
P2D5 (MSB)
VRB
P2D3
16
P2D2
AGND
DGND2 45
P2D1
17
DGND3
18
DVEE 44
P2D0 (LSB)
DVCC2 43
P2D4
•
•
•
•
•
•
P1D1
• Analog input voltage
• Digital input voltage
VRT
VRB
VIN
DIN (H)
DIN (L)
Fcclk
Fdclk
Dcclk
Ddclk
tdcd
Ta
P1D2
• Reference input voltage
Min.
–5.5
–0.05
–0.05
4.75
–0.1
–2.2
VRB
–1.1
–7.0 to +0.5
0.5 to +7.0
–2.7 to +0.5
–2.7 to +0.5
2.5
–4.0 to +0.5
2.5
–30 to +30
–65 to +150
–20 to +75
750
V
V
V
V
V
V
V
mA
°C
°C
mW
V
V
V
V
V
V
V
V
MHz
MHz
%
%
ns
°C
CXA1866Q
Pin Description and I/O Pin Equivalent Circuit
Pin
No.
Symbol
I/O
Standard
voltage
level
Equivalent circuit
Description
VRT
21
VRT
I
0V
VRTS
Comparator 1
22
VRTS
O
0V
Comparator 2
VRT sense output.
This is the voltage sense pin for VRT.
Comparator 31
Bottom reference voltage input (= –2V).
This is the bottom reference voltage
supplied to the internal resistance
chain. The external input can be set in
accordance with the peak value on the
minus side of the input analog signal
amplitude.
Comparator 32
16
VRB
I
–2V
Comparator 63
VRBS
15
VRBS
O
–2V
Top reference voltage input (= 0V).
This is the top reference voltage supplied
to the internal resistance chain. The
external input can be set in accordance
with the peak value on the plus side of
the input analog signal amplitude.
VRB sense output.
This is the voltage sense pin for VRB.
VRB
AGND
19
VIN
I
VRTS
to
VRBS
VIN
Analog input.
The input range is 2Vp-p.
AVEE
26
CCLK
I
ECL
CCLK clock input.
This is the conversion clock, and is an
ECL level input.
ECL
CCLK inversion clock input.
This is an ECL level input. When left
open, this input goes to the ECL
threshold potential (–1.3V). Only
CCLK input can be used for operation
with the NCCLK input left open,but
complementary input is recommended
to attain fast and stable operation.
DGND1
25
NCCLK
I
r
11
DCLK
I
r
r
CCLK
(DCLK)
500
NCCLK
(NDCLK)
500
r
ECL
r
r
1.3V
DVEE
12
NDCLK
I
DCLK clock input.
This is the 1:2 DMPX latch clock; input
a clock of 1/2 frequency of CCLK.
Data are output from DMPX port 1
and port 2 synchronously with the
rising edge of this signal. This is an
ECL level input.
DCLK inversion clock input.
This is an ECL level input. When left
open, this input goes to the ECL
threshold potential (–1.3V). Only
DCLK input can be used for operation
with the NDCLK input left open, but
complementary input is recommended
to attain fast and stable operation.
ECL
–3–
CXA1866Q
Pin
No.
Symbol
I/O
Standard
voltage
level
Equivalent circuit
Description
DGND1
r
r
27
INV
I
ECL
INV
500
1.3V
r
r
1.3V
Digital output polarity inversion input.
This is an ECL level input.
This input inverts the polarity of the
digital outputs P1D0 to P1D5, and
P2D0 to P2D5. (Refer to the Output
Code Table.)
When left open, this signal is
maintained at the low level.
DVEE
30
P1D0
31
P1D1
32
P1D2
33
P1D3
34
P1D4
35
P1D5
2
P2D0
3
P2D1
4
P2D2
5
P2D3
6
P2D4
7
P2D5
DVCC1
O
DVCC2
TTL
These pins are for the 6 bits of digital
output data for DMPX port 1. P2D5 is
the MSB, and P2D0 is the LSB.
These are TTL level outputs.
P1D0 to D5
P2D0 to D5
100K
DGND2
DGND3
These pins are for the 6 bits of digital
output data for DMPX port 2. P2D5 is
the MSB, and P2D0 is the LSB.
These are TTL level outputs.
38, 47 DVCC1
—
+5.0V
+5V power supply for TTL level
internal circuit.
9, 28, 37,
DVCC2
43, 48
—
+5.0V
+5V power supply for TTL level
output buffers (P1D0 to P2D5).
39, 46 DGND1
—
0V
Ground for DVEE digital circuit.
40, 45 DGND2
—
0V
Ground for DVcc1 digital circuit.
1, 8, 29,
DGND3
36, 42
—
0V
Ground for DVcc2 digital circuit.
0V
Ground for AVEE analog circuit .
Used as the ground for the
comparator input buffers, latches, etc.
Separated from DGND.
17, 20 AGND
—
41, 44 DVEE
—
–5.2V
–5.2V power supply for digital circuit.
Connected internally with AVEE.
(Resistance is 4 to 6Ω.)
14, 23 AVEE
—
–5.2V
–5.2V power supply for analog circuit.
Connected internally with DVEE.
(Resistance is 4 to 6Ω.)
–4–
CXA1866Q
Electrical Characteristics
Item
(Ta = 25°C, AVEE = DVEE = –5.2V, DVCC = 5V, VRT = 0V, VRB = –2V)
Symbol
Resolution
n
DC characteristics
Integral linearity error
Differential linearity error
No missing code
EIL
EDL
Analog input
Analog input capacitance
Analog input resistance
Input bias current
Reference input
Reference resistance
Reference resistance
current
Offset voltage
VRT
VRB
Digital input
Logic high level
Logic low level
Logic high current
Logic low current
Input capacitance
Switching characteristics
Maximum conversion
frequency
Aperture jitter
Sampling delay
Digital output
Logic high level
Logic low level
Output delay
Output rising time
Output falling time
Dynamic characteristics
Analog amplitude
input bandwidth
S/N ratio
Error rate
Power supply
Supply current
Power consumption
Conditions
Min.
Typ.
Max.
bits
6
Fc = 140MHz
Fc = 140MHz
Unit
±0.2
±0.2
LSB
LSB
110
pF
kΩ
µA
Guaranteed
CIN
RIN
IIN
VIN = –1V + 0.07Vrms, DC ≤ VIN ≤ 70MHz
–2V ≤ VIN ≤ 0V
–2V ≤ VIN ≤ 0V
7
200
RREF
Iref
EOT
EOB
VIH
VIL
IIH
IIL
Ω
mA
225
9
25
25
mV
mV
–1.50
50
50
V
V
µA
µA
pF
–1.13
VIH = –0.8V
VIL = –1.6V
0
–50
3.5
FC
Error rate1E-9 TPS∗1
Taj
Tds
VOH
VOL
tdo
tr
tf
ps
ns
5.0
1.0
IOUT = –2mA
IOUT = 1mA
ZL = 25pF
ZL = 25pF, 0.5V to 2.4V
ZL = 25pF, 0.5V to 2.4V
Finb
VIN = 2Vp-p,
p-p value = 3dB down input frequency
SNR1 Fc = 140MHz, Fin = 1MHz
SNR2 Fc = 140MHz, Fin = 35MHz
SNR3 Fc = 140MHz, Fin = 70MHz
Fc = 140MHz, error > 4LSB
ICC
IEE
Pd
MSPS
140
DVCC = +5V
AVEE = DVEE = –5.2V
∗1 TPS: Times Per Sample
–5–
2.7
0.5
8.0
2.0
1.2
1.2
MHz
210
dB
dB
dB
TPS∗1
36
34
32
10–9
–60
V
V
ns
ns
ns
20
–40
325
32
mA
mA
mW
CXA1866Q
Output Code Table
VIN
STEP
0V
0
1
–1V
31
32
–2V
63
INV = 0
D5
INV = 1
D0 D5
000000
000001
:
011111
100000
:
111110
111111
D0
111111
111110
:
100000
011111
:
000001
000000
∗ INV = 0: low level; INV = 1: high level
Timing Chart 1
tds
V IN
N
N+1
N+2
N+3
N–1
N+4
tr
Dcclk
tf
TPW H
TPW L
–1.1V
–1.3V
CCLK
–1.5V
–1.3V
NCCLK
tf
tdcd
Ddclk
tr
–1.1V
–1.3V
DCLK
–1.5V
–1.3V
NDCLK
tdo
tdo
2.0V
P1D0-5
N–4
N–2
N
N–3
N–1
N+1
1.0V
2.0V
P2D0-5
1.0V
–6–
CXA1866Q
Timing Chart 2
6
6
COMPARATOR
VIN
6
CLatchA
6bit Latch
CLatchB
CCLK
6
TTLout
P1D0 to D5
DCLK
6
6
P2D0 to D5
TTLout
N–1
N
N+1
N+2
N+3
N+4
N+5
VIN
CCLK
COMPARATOR
(master)
COMPARATOR
(slave)
N+1
N
N–1
N–1
N
6bit Latch
N–2
N–1
CLatchA
N–3
N–2
CLatchB
N–4
N–3
N+2
N+1
N
N+3
N+2
N+4
N+3
N+5
N+4
N+1
N+2
N+3
N+4
N–1
N
N+1
N+2
N+3
N–2
N–1
N
N+1
N+2
DCLK
TTLout
(P2D0 to D5)
TTLout
(P1D0 to D5)
N+5
N–3
N–1
N+1
N–4
N–2
N
–7–
CXA1866Q
Electrical Characteristics Measurement Circuit
Maximum conversion rate measurement circuit
6
VIN
Signal Source
DUT
CXA1866Q
6
A
Latch
B
fCLK
–1kHz
4
2Vp-p Sin Wave
CCLK
Comparator
A>B
DCLK
+
Latch
Data 4
Signal Source
Amp
1/2
fCLK
Integral linearity error measurement circuit
Differential linearity error measurement circuit
+V
S1
S1: ON when A < B
S2: ON when A > B
S2
–V
(P1D0 to D5)
6
VIN
DUT
CXA1866Q
6
SW
(P2D0 to D5)
A<B A>B
Comparator
A6
B6
to
to
A1
B1
A0
B0
"0"
6
Buffer
"1"
CCLK DCLK
6
DVM
Controller
–8–
000000
to
111110
Pulse
Counter
CXA1866Q
NCCLK
CCLK
INV
DVCC2
DGND3
P1D0
P1D1
P1D2
P1D3
P1D4
31 30 29 28 27 26 25
P1D5
36 35 34 33 32
DGND3
Current consumption measurement circuit
Analog input bias measurement circuit
37 DVCC2
24
38 DVCC1
AVEE 23
39 DGND1
VRTS 22
40 DGND2
VRT 21
41 DVEE
42 DGND3
CXA1866Q
AGND 20
IIN
VIN 19
A
–1.0V
18
43 DVCC2
44 DVEE
AGND 17
DGND3
DVCC2
DCLK
1
2
3
4
5
6
7
8
9
10 11 12
–2.0V
NDCLK
P2D5
13
P2D4
AVEE 14
P2D3
47 DVCC1
48 DVCC2
P2D2
VRBS 15
P2D1
46 DGND1
DGND3
VRB 16
P2D0
45 DGND2
ICC
IEE
A
A
+5.0V
–5.2V
Sampling delay measurement circuit
Aperture jitter measurement circuit
6
VIN
Signal Source1
φ: variable
CXA1866Q
Logic Analizer
6 SW
Freq
Lock
CCLK
DCLK
Signal Source2
ECL
Buffer
–9–
1024
samples
CXA1866Q
Electrical Characteristics
Current comsumption vs. Ambient temperature
(VEE = –5.2V, VCC = +5.0V)
–30
25.0
–35
22.5
–40
20.0
–45
17.5
–50
–25
15.0
0
25
50
75
Ambient temperature [°C]
VOH vs. Ambient temperature
(VEE = –5.2V, VCC = 5.0V, IOUT = –2mA)
VOH – Digital output level [V]
3.6
3.5
3.4
3.3
3.2
3.1
–25
0
25
Ambient temperature [°C]
50
75
VOL vs. Ambient temperature
(VEE = –5.2V, VCC = 5.0V, IOUT = 1mA)
VOL – Digital output level [V]
0.40
0.38
0.36
0.34
0.32
0.30
–25
0
25
Ambient temperature [°C]
– 10 –
50
75
ICC – Current consumption [mA]
IEE – Current consumption [mA]
ICC
IEE
CXA1866Q
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
SNR vs. Input frequency
(CCLK = 140MHz, DCLK = 70MHz)
38
36
SNR [dB]
34
32
30
28
26
24
22
1
10
100
Input frequency [MHz]
Effective bit number vs. Input frequency
(CCLK = 140MHz, DCLK = 70MHz)
6.5
Effective bit number [bits]
6.0
5.5
5.0
4.5
4.0
3.5
1
AA
AA
AA
AA
AA
AA
AA
AA
10
100
Input frequency [MHz]
2nd, 3rd Harmonic distortion vs. Input frequency
(CCLK = 140MHz, DCLK = 70MHz)
2nd, 3rdHarmonic distortion [dB]
–20
2nd Harmonic distortion [dB]
3rd Harmonic distortion [dB]
–30
–40
–50
–60
–70
1
10
Input frequency [MHz]
– 11 –
100
CXA1866Q
Notes on Operation
The CXA1866Q is a high speed A/D converter with ECL level logic input and demultiplexed TTL level output.
Take notice of the followings to ensure optimum performance from this IC.
<<Power Supply and Grounding>>
• Grounding has a profound influence on converter performance. The higher the frequency is, the more
important the way of grounding becomes.
• The ground pattern should be as large as possible. It is recommended to make the power supply and ground
patterns wider at an inner layer using the multi-layer board.
• To prevent interference between the AGND and DGND patterns and between the AVEE and DVEE lines,
make sure the respective patterns are separated. To prevent a DC offset in the power supply pattern,
connect the AVEE and DVEE lines at one point each via a ferrite-bead filter. Shorting analog and digital ground
patterns in one place immediately under the A/D converter improves A/D converter performance.
• Ground the power supply pins (AVEE, DVEE, DVcc) as close to each pin as possible with a 0.1µF or larger
ceramic chip capacitor. (Connect the AVEE pin to the AGND pattern, DVEE to DGND, and DVcc to DGND.)
<<Analog Input>>
• Make the connection between the VIN pin and the analog input source as short as possible.
• There is a slight offset voltage at reference voltage pins VRT and VRB. If it presents no problem in the
application, the voltage can be applied directly. However, if the reference voltage is to be set precisely, apply
it via a feedback circuit created using the VRTS and VRBS pins.
• Make adequate by-pass for high frequency noise at VRT and VRB. The VRT pin is normally connected to
AGND on the board. Bypass the VRB pin to the AGND pattern with a 0.1µF or larger ceramic chip capacitor
as short as possible. The 10µF tantalum capacitor connected to VRB in the Application Circuit is to stop
oscillation in the reference voltage generation circuit.
<<Digital Input>>
• Noise at the INV pin may cause misoperation of which the cause is extremely hard to identify. If it is OK for
the set voltage level to be low only, leave the pin open. If a high level voltage have to be input, bypass the
INV pin to DGND with an about 0.1µF ceramic chip capacitor as short as possible. It is recommend that high
level input voltage is about –0.5V to –1.0V, and low level input voltage is about –1.6V to –2.5V. When
inputting a high level voltage, avoid connecting directly to DGND.
• The CXA1866Q has input pins for two clocks: CCLK and DCLK. For CCLK, which is used for the internal
comparator, input an ECL level clock with up to the maximum conversion frequency. For DCLK, which is
used for the multiplex output, input an ECL level clock with a rate half that of CCLK. Take notice of the timing
between CCLK and DCLK.
• It is recommended that differential signals be input to the clock input pins CCLK, NCCLK, DCLK and NDCLK.
The A/D converter can be driven only by the clock input pins CCLK and DCLK, but there is a risk of unstable
characteristics at maximum speeds.
• If the NCCLK and NDCLK pins are not used, bypass these pins to DGND with an about 0.1µF capacitor. In
this time, about –1.3V voltage is generated at the NCCLK and NDCLK pins. However, this is too weak to be
used as threshold voltage VBB; it can not directly drive even one ECL input load.
• The clock duty cycle is designed for use at 50%. Any diversion from this percentage will have a slight effect
on the maximum performance of the A/D converter, but there is no great need for adjustment.
<<Digital Output>>
• P1D0 (LSB) to P1D5 (MSB), and P2D0 (LSB) to P2D5 (MSB) are demultiplex digital outputs (2 systems),
and are output using the DCLK timing. The polarity of the output data can be inverted using the INV signal.
– 12 –
CXA1866Q
Application circuit
DGND
1 DGND3
DVCC2
DVCC1
DGND1
DVEE
DGND2
DGND3
DVEE
DGND1
DGND2
DVCC2
DVCC1
DVCC2
43 42 41 40 39 38 37
48 47 46 45 44
DGND3 36
(TTL) P2D0
2 P2D0
P1D5 35
P1D5 (TTL)
(TTL) P2D1
3 P2D1
P1D4 34
P1D4 (TTL)
(TTL) P2D2
4 P2D2
P1D3 33
P1D3 (TTL)
(TTL) P2D3
5 P2D3
P1D2 32
P1D2 (TTL)
(TTL) P2D4
6 P2D4
P1D1 31
P1D1 (TTL)
P1D0 30
P1D0 (TTL)
(TTL) P2D5
CXA1866Q
7 P2D5
8 DGND3
DGND3 29
9 DVCC2
DVCC2 28
INV
(ECL level)
INV 27
10
11 DCLK
CCLK 26
NCCLK 25
AVEE
VRTS
VRT
AGND
VIN
AGND
VRB
VRBS
AVEE
12 NDCLK
One point
shorting
13 14 15 16 17 18 19 20 21 22 23 24
AGND
–5.2V
10µF
+5.0V
Tantalum
capacitor
VRTS
VRB
–5.2V
Q
D
Q
CP
1/2 CLK
ECL
buffer
Analog Input
CLK (ECL level)
Capacitors, if not specified, are
0.1µF ceramic chip capacitors.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 13 –
CXA1866Q
CXA1866Q-PCB (6bit, 140MSPS, ADC Evaluation Board)
Description
The CXA1866Q PCB is a tool for customers to evaluate the performance of the CXA1866Q (6bit, 140MHz,
TTL demultiplexed output, high-speed A/D converter). In addition to indispensable features such as the
reference voltage generator, this tool equips.
The input voltage offset generator, clock decimator, output data latches, 10-bit high-speed DAC × 2, and 26pin cable connector for 2-system digital output.
This evaluation board provides full performance of the CXA1826Q and it is designed to facilitate evaluation.
Features
• Resolution: 6bits
• Maximum conversion rate: 140MHz
• Supply voltage: +5.0V, –5.2V
• Conversion for clock input level: Sine wave converted to ECL level signal
• Reference voltage adjustment circuit for the A/D converter
• Built-in clock frequency decimation circuit: (1/2)
Supply Current
Item
Min.
VEE (–5.2V)
Vcc (+5.0V)
Typ.
Max.
Unit
2.0
0.6
2.2
0.7
A
A
Typ.
Max.
Unit
+0.5
0
V
V
Ω
Max.
Unit
Analog Input
Item
Min.
Input voltage (AMP. IN)
(DIR. IN)
Input impedance
–0.5
–2.0
50
Clock Input
Item
Input voltage
(Peak to Peak)
Input impedance
Min.
Typ.
0.6
1.0
Vp-p
50
Ω
Digital Output
TTL level, demultiplexed output
Clock Output
TTL level, Single output
– 14 –
VRB
– 15 –
: ECL Buffer, delay = 2ns
B1
B1
B2
B1
B
: ECL Buffer, delay = 1ns
CLC404
A J1
B1
CLK
DIR.IN
AMP.IN
VIN Offset
(A/D Fullscale Adjust)
Block Diagram
CP
DCLK
ECL
to
TTL
Converter
Q
Q
D-Latch
with
MR 1/2
CCLK
D
SW1
CXA1866Q
VRB
INV
H L
B2
6
(P1D0
to D5)
(P2D0
to D5)
6
CLK
TTL
Data
Latch
CLK
TTL
Data
Latch
CLK
TTL
Data
Latch
CLK
TTL
Data
Latch
B2
4
2
2
4
TTL
to
ECL
Converter
TTL
to
ECL
Converter
TTL
to
ECL
Converter
6
6
4
2
2
4
B2
CLK
ECL
Data
Latch
CLK
ECL
Data
Latch
2
6
6
H
L
SW2
+5.0V
D/A OUT1
D/A OUT2
GND
DIGITAL
OUT
connector
–5.2V
CLK
(P1D0 to D5)
(P2D0 to D5)
CLK
INV
Vref
D/A
Converter 2
(P1D0 to D5)
CLK
INV
Vref
D/A
Converter 1
(P2D0 to D5)
D/A Fullscale
CXA1866Q
CXA1866Q
Timing Chart
N–1
N
N+5
N+1
Analog input
N+4
N+3
N+2
PCB CLK input
TPW1 = 3.5ns
TPW0 = 3.5ns
A/D CCLK
TPW1 = 7.0ns
TPW0 = 7.0ns
A/D DCLK
td = 2 to 8ns
A/D output
(P1 side)
N–4
N–2
N
N+2
N+4
A/D output
(P2 side)
N–3
N–1
N+1
N+3
N+5
TTL CLK
(CCLK/2)
td = 3 to 9ns
TTL Latch output
(P1 side)
N–6
N–4
N–2
N
N+2
Delay = 4.5 to 10.5ns
TTL to ECL output
(P1 side)
N–6
N–4
N–2
N
N+2
ECL CLK
(CCLK/2)
ECL Latch output
(P1 side)
N–8
th = 4ns
N–6
N–4
N–2
N
ts = 10ns
D/A CLK
Digital CLK output
td = 3 to 9ns
Digital output
(P1 side)
N–6
N–4
N–2
N
N+2
Digital output
(P2 side)
N–5
N–3
N–1
N+1
N+3
– 16 –
N+2
CXA1866Q
Adjustment Methods and Notes on Operation
1) VIN Offset (VR1)
The volume to adjust the AMP. IN input signal range (0V center assumed) with the A/D converter input
range.
2) A/D Full Scale (VR2)
The volume to adjust A/D converter VRB voltage (–2V typ.).
3) D/A Full Scale (VR3)
The volume to adjust D/A converter reference voltage (–1V typ.).
4) Input pins
DIR. IN ................Used to directly input to A/D converter from signal generator.
AMP. IN...............Used to input to A/D converter after amplifying the signal generator input to that of –2
times by operational amplifier.
CLK .....................Clock input for A/D converter and peripheral ICs. Input a sine wave of 1Vp-p.
5) Output pins
D/A OUT1 ...........Analog output of D/A converter for (P1D0 to D5) data from A/D converter.
D/A OUT2 ...........Analog output of D/A converter for (P2D0 to D5) data from A/D converter.
DIGITAL OUT .....Output of TTL CLK (1/4 decimation) and digital data (P1D0 to D5, P2D0 to D5).
6) J1 short bar is provided to use analog input pins AMP. IN and DIR. IN.
Analog input method
A
B
SHORT
OPEN
DIR. IN input with DC coupled
OPEN
SHORT
DIR. IN input with AC coupled
1kΩ
0.1µF
AMP. IN input
Offset
Adjust with VR1.
Input a offset signal.
Adjust with VR1.
7) SW1 (A/D INV), SW2 (D/A INV)
SW1: Output inversion (INV) switch of the CXA1866Q A/D converter
SW2: Output inversion (INV) switch of the CX20201 D/A converter
8) Waveform probe pins P5, P6, P7, P9 and P11 through P38 are devised to facilitate GND connection in
order to reduce the distortion. As shown in the diagram below, the distance between the probe point and
the GND is 300 mils, and there is φ1.2mm throughhole at each. The signal and GND locations are suit for a
Tektronix GND tip (part number 013-1185-00).
φ1.2mm
Probe point
GND
300mil
– 17 –
CXA1866Q
Digital Out Connector Pin Assignment
Pin No.
Assignment
Pin No.
Assignment
A1
P2D0
B1
GND
A2
P2D1
B2
GND
A3
P2D2
B3
GND
A4
P2D3
B4
GND
A5
P2D4
B5
GND
A6
P2D5
B6
GND
A7
P1D0
B7
GND
A8
P1D1
B8
GND
A9
P1D2
B9
GND
A10
P1D3
B10
GND
A11
P1D4
B11
GND
A12
P1D5
B12
GND
A13
CLK
B13
GND
– 18 –
CXA1866Q
Part list
RESISTOR:
R5, R6, R17, R18
R3, 4, 15, 20, 21, 22, 24, 27
R30, 33, 39, 41, 43, 45, 47
R49, 51, 53, 55, 57, 59, 61
R63, R78 to R91
R1, 2, 14, 19, 23, 25, 26, 28
R29, 32, 38, 40, 42, 44, 46
R48, 50, 52, 54, 56, 58, 60
R62, R64 to R77
R10, R12
R34 to R37, R93
R31, R94
R8
R16
R13, R92
R11
R7
R9
VARIABLE RESISTOR:
VR1, 2, 3
CAPACITOR:
C1
C5, C65, C67
C11, C12, C15
C68, C69
OTHER
51Ω
82Ω
82Ω
82Ω
82Ω
130Ω
130Ω
130Ω
130Ω
240Ω
270Ω
330Ω
510Ω
560Ω
1kΩ
1.3kΩ
11kΩ
22kΩ
TRANSISTOR:
Q1
2SA970
IC:
IC2
IC3
IC4
IC5
IC6 to 9
IC10, 11, 12
IC13, 14
IC15, 16
IC17, IC20
IC18
IC19
10H116
10H131
10116
10H125
74AS574
10H124
10H176
CX20201A
TL431CLP
CLC404AJP
TL4558P
DIODE:
D1 to D6
1S2076A
FERRITE BEAD:
L1, L2, L3
ZBF253D-00
SWITCH:
SW1, SW2
AT1D-2M3-10
2kΩ (RJ-5W202)
0.1µF (CERAMIC)
3.3µF (TANTALUM)
1µF (TANTALUM)
33µF (TANTALUM)
0.1µF (CHIP CAPACITOR)
OTHERS:
BNC CONNECTOR
BNC-R-PC
DIGITAL OUT CONNECTOR HIF3FB-26PA-2.54DS
JUMPER LINE
JX-1
– 19 –
Part Layout
CXA1866Q
– 20 –
Ptinted Pattern (Component plane)
CXA1866Q
– 21 –
Ptinted Pattern (Solder plane)
CXA1866Q
– 22 –
2
3
R7
11k
DGND
CLK
AGND
DIR.IN
1
R9
22k
R8
510
6
5
4
8
7
IC19-2
TL4558
7
C11
1µ
C13
0.1µ
VIN
R4
82
9
VEE 8
Aout 3
Aout 2
VCC1 1
Cout
Cout
VCC2
15
16
Ain 4
Cin
13
14
Ain 5
Bout 6
Bout 7
Cin
VBB
Bin
Bin
12
11
10
DGND
C3
0.1µ
R5
51
IC2: 10H116
R15
82
NC
AVEE
VRTS
VRT
AGND
VIN
NC
DGND
C8
0.1µ
R14
130
C7
0.1µ
VRB
AGND
–5.2V
DGND
(D)
–5.2V
(D)
NC
AVEE
C15 VRBS
1µ
–5.2V (A)
AVEE
P3
P4
VRTS
J1
A
B
P2
Q1
2SA970
VRBS P1
R17
R16
51
6 560
IC18
4
CLC404AJP
R18
AGND
51
C10
C12
1µ
0.1µ
–5.2V
AGND
(A)
AGND AGND
2
3
+5.2V
(A) AGND AGND
AGND –5.2V
(A)
C6
0.1µ
DGND
R3
82
C2
0.1µ
R2
130
R12
240
–5.2V (D)
R1
130
C5
3.3µ
R13
1k
AGNDAGND
C1
0.1µ
R6
51
R11
1.3k
VR2 2k
Full Scale
–5.2V AGND
(A)
R10
240
4 C4
0.1µ
8
AGND
AGND
AMP.IN
IC19-1
TL4558
AGND
VR1 2k
Off Set
C9
0.1µ
C18
0.1µ
C17
0.1µ
AGND
C16
0.1µ
13
24
23
22
21
20
19
18
17
16
15
14
DGND
C14
0.1µ
16
15
14
13
12
11
10
9
DGND –5.2V (D)
R20
82
P6
26
P8
27
D1 7
VCC2
Q2
Q2N
R2
S2
VCC1 1
Q1 2
Q1N 3
R1 4
S1 5
30
DGND
31
31
R30
82
DGND
C22
0.1µ
R29
130
–5.2V
(D)
C21
0.1µ
–5.2V
(D)
DGND
R31
330
D3
D2
D1
DGND
29
–5.2V (D)
L
H
CE2N CE1N 6
D2
28
SW1
VEE 8
IC3: 10H131
CC
R26
130
R23
130
C19
0.1µ
R27
82
R19
130
–5.2V
(D)
25
C23
0.1µ
30
28
29
27
26
25
32
32
9
33
33
16
15
14
13
12
11
10
DGND
IC1: CXA1866Q
3
3
4
4
5
5
6
6
7
7
8
C24
0.1µ
8
9
9
P9 NDCLK
10
10
R28
130
NCCLK CCLK INV
P5
NC
AVEE
VRTS
VRT
AGND
VIN
NC
AGND
VRB
VRBS
AVEE
NC
11
12
NDCLK
R24
DGND 82
L2
FERRITE BEAD
24
23
22
21
20
19
18
17
16
15
14
13
11
12
NCCLK
NCCLK
L1
FERRITE BEAD
NDCLK
DCLK
CCLK
+5V
(A) AGND
R25
130
DGND3
R22
82
DCLK
CCLK
P7 DCLK
NC
34
34
P1D2
R21
82
DVCC2
DVCC2
DVCC2
P1D1
–5.2V
(D)
NC
INV
DGND3
P1D0
IC20
TL431CP
DGND
DGND3
P2D5
P1D0
P1D4
P1D3
C20
0.1µ
VCC2
Cout
Cout
Cin
Cin
VBB
Bin
Bin
VCC1 1
Aout 2
Aout 3
Ain 4
Ain 5
Bout 6
Bout 7
+5V (D)
C25
0.1µ
+5V
(D)
9
DVCC2
16
15
14
13
12
11
GND
Din
DinN
Dout
Cout
Cin
CinN
VCC
6
–5.2V
(D)
C34
0.1µ
DGND
R33
82
DGND
C35
0.1µ
C36
0.1µ
–5.2V
DGND
(D)
R32
130
VBB 1
AinN 2
Ain 3
Aout 4
Bout 5
BinN
Bin 7
VEE 8
IC5: 10H125
–5.2V (D)
DVCC2
DVCC1
DGND1
DGND2
DVEE
DGND3
DVCC2
DVEE
DGND2
P10
DVCC
DGND1
DVCC1
10
DGND
C26
0.1µ
DGND
37
DVCC2 37
DGND
40
39
38
–5.2V
DGND
(D)
36
C29
0.1µ
38
DVCC1
DGND1 39
DGND2 40
41
42
C30
0.1µ
DGND3 42
DVEE 41
43
36
VEE 8
IC4: 10116
35
35
C27
0.1µ
44
DVEE 44
DVCC2 43
C31
0.1µ
45
DGND2 45
C32
0.1µ
46
48
DGND1 46
C33
0.1µ
DGND
47
DVCC2 48
C28
0.1µ
–5V
(D)
DVCC1 47
1
1
2
2
P2D0
DGND3
P14
P13
P12
P11
P2D3
P2D2
P2D1
P2D0
DGND
DGND
DGND
DGND
DGND
P1D0 P17
P1D1 P18
P1D2 P19
P1D3 P20
P1D4 P21
P1D5 P22
DGND
DGND
P15
P2D4
DGND
P16
P2D5
CLK 11
Q7 12
Q6 13
Q5 14
Q4 15
Q3 16
Q2 17
Q1 18
Q0 19
VCC 20
Q2 17
D7
GND
D6
10
8
D5
D4
D3
D2
D1
D0
Cont-
CLK 11
Q7 12
Q6 13
Q5 14
Q4 15
Q3 16
Q2 17
Q1 18
Q0 19
VCC 20
IC6: 74AS574
P24
CLK 11
Q7 12
Q6 13
Q5 14
Q4 15
TTL CLK2
GND
D7
D6
D5
D4
9
7
6
5
4
3
2
1
10
9
8
7
6
Q3 16
Q1 18
D2
D3
D1
3
4
5
Q0 19
VCC 20
D0
Cont-
IC7: 74AS574
GND
D7
D6
D5
D4
D3
D2
D1
D0
Cont-
IC8: 74AS574
2
1
10
9
8
7
6
5
4
3
2
1
CLK 11
GND
10
C41
0.1µ
+5V
(D) DGND
–5.2V
(D)
DGND
P23
C42
0.1µ
+5V (D)
DGND
+5V DGND
(D)
C38
0.1µ
+5V
(D)
R35
270
+5V (D)
DGND
9
C48
0.1µ
8
7
6
11
5
1
2
4
1
3
3
1
4
2
C43
0.1µ
10
11
12
13
14
1
DGND
1
6
16
1
DGND
15
2
9
1
15
3
14
2
4
13
3
5
12
4
6
11
5
7
10
6
8
C44
0.1µ
C45
0.1µ
9
7
10
C46
0.1µ
TTL CLK1
IC10: 10H124
–5.2V
(D)
DGND
+5V (D)
DGND
8
DGND
+5V
(D)
C47
0.1µ
IC11: 10H124
R36
270
C37
0.1µ
DGND
–5.2V
(D)
DGND
IC12: 10H124
R37
270
R34
270
DGND
C39
0.1µ
+5V
(D) DGND
C40
0.1µ
+5V DGND
(D)
Q7 12
Q6 13
Q5 14
Q4 15
Q3 16
Q2 17
Q1 18
Q0 19
VCC 20
D7
D6
D5
D4
D3
D2
D1
D0
Cont-
9
8
7
6
5
4
3
2
1
IC9: 74AS574
VEE
VCC
P2D4
DGND3
INV
Bin
Cin
P2D5
P2D3
P2D4
DVCC2
DGND3
P1D5
CS
CS
Din
DGND
P2D3
P1D2
P2D1
INV
NORM
P2D2
P1D3
P2D2
P1D1
P2D1
P1D4
P2D0
P1D5
Ain
Ain
DGND3
DGND3
VEE
VCC
VEE
VCC
Bin
Cin
Bin
Cin
Din
CS
Din
BoutN
Dout
BoutN
Dout
DoutN AoutN
DoutN AoutN
BoutN
DoutN AoutN
Dout
Bout
Bout
CoutN
Ain
CoutN
Aout
GND
Cout
CoutN
15
DGND
16
DGND
DIGITAL OUT
C50
0.1µ
CONNECTOR
(Top View)
8
7
6
R54
130
R55
82
5
5
4
R58
130
R60
130
R59
82
R61
82
4
13
R40
130
R41
82
R48
130
R49
82
R56
130
R57
82
13
12
R50
130
R52
130
R51
82
R53
82
12
R62
130
R63
82
11
10
R42
130
R44
130
R43
82
R45
82
11
9
R38
130
R39
82
10
6
8
9
7
C49
0.1µ
IC13: 10H176
–5.2V (D)
DGND
IC14: 10H176
–5.2V (D)
DGND
R46
130
R47
82
D4
Aout
VEE
D0
GND
Bout
D2
D3
CLK
D2
VEE
Q2
Q3
Cout
Aout
GND
Cout
CLK
A13
P1D5
A12
P1D4
A11
P1D3
A10
P1D2
A9
P1D1
A8
P1D0
A7
P2D5
A6
P2D4
A5
P2D3
A4
P2D2
A3
P2D1
A2
P2D0
A1
– 23 –
DGND
B13
DGND
B12
DGND
B11
DGND
B10
DGND
B9
DGND
B8
DGND
B7
DGND
B6
DGND
B5
DGND
B4
DGND
B3
DGND
B2
DGND
B1
D0
D1
D3
3
C54
0.1µ
2
3
C52
0.1µ
C53
0.1µ
14
C51
0.1µ
14
16
2
16
–5.2V (D)
DGND
15
1
–5.2V (D)
DGND
–5.2V (D)
DGND
15
1
–5.2V (D)
DGND
Q2
Q3
Q1
D4
CLK
Q1
D5
VCC1
VCC2
VCC1
VCC2
D5
D1
Q0
Q5
Q4
Q0
Q5
Q4
PCB Circuit Diagram
P37
P36
P35
P34
P33
P32
P31
P2D4
P2D3
P2D2
P2D1
P2D0
ECL
CLKN
ECL
CLK
R87
82
R86
82
R73
130
R72
130
–5.2V
(D)
DGND
DGND
R78
82
R79
82
R65
130
P1D1 P26
C55
0.1µ
R80
82
R66
130
P1D2 P27
R64
130
R81
82
R67
130
P1D3 P28
P1D0 P25
R82
82
R83
82
DGND
R84
82
R85
82
DGND
R68
130
R69
130
–5.2V
(D)
R70
130
R71
130
C56
0.1µ
R88
82
R74
130
DGND
R89
82
R75
130
–5.2V
(D)
R90
82
R76
130
C57
0.1µ
R91
82
R77
130
P1D4 P29
P30
P1D5
P38
P2D5
DGND 17
NC
12
DVEE 15
NC 19
LSB
NC
NC
10
11
12
CLK
14
–5.2V (D)
–5.2V (A)
DGND
AGND
+5V (D)
+5V (A)
CLKN
13
L3
C64
0.1µ
C58
0.1µ
C59
0.1µ
C63
0.1µ
DGND
AGND
–5.2V
(A)
C62 C65
0.1µ 3.3µ
P24 +5V
DGND
AGND
P26
P27
P25
P28
P29
(A)
–5.2V (D)
–5.2V (A)
DGND
AGND
+5V (D)
FERRITE BEAD
–5.2V (VEE)
C68
33µ
GND
C69
33µ
+5V (VCC)
NORM
SW2
D/A INV
INV
R94
330
D6
D5
D4
DGND
AGND
D/A OUT1
AGND
D/A OUT2
–5.2V
(A)
AGND
–5.2V (D)
L
H
C66 C67
0.1µ 3.3µ
IC17
TL431CP
R93
270
AGND
DGND
AGND
–5.2V
(D) DGND
C60
0.1µ
R92
1k
VR3 2k
D/A Full Scale
C61
0.1µ
–5.2V DGND
(D)
DVEE 15
INV 16
DGND 17
AGND1 18
OUT 20
NC 21
NC 22
NC 23
NC 24
NC 25
AVEE 26
VREF 27
D9
D8
D7
D6
D5
D4
D3
D2
MSB AGND2 28
IC15: CX20201A
CLK
9
8
7
6
5
4
3
2
1
14
INV 16
AGND1 18
NC
11
CLKN
NC 19
LSB
10
13
OUT 20
NC 21
NC 22
NC 23
NC 24
NC 25
AVEE 26
VREF 27
D9
D8
D7
D6
D5
D4
D3
D2
MSB AGND2 28
IC16: CX20201A
9
8
7
6
5
4
3
2
1
CXA1866Q
DGND
DGND
CXA1866Q
Package Outline
Unit: mm
48PIN QFP (PLASTIC)
15.3 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
12.0 – 0.1
36
25
0.15
24
13.5
37
48
+ 0.2
0.1 – 0.1
13
12
0.8
+ 0.15
0.3 – 0.1
± 0.12 M
0.9 ± 0.2
1
+ 0.35
2.2 – 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-48P-L04
LEAD TREATMENT
SOLDER / PALLADIUM
PLATING
EIAJ CODE
∗QFP048-P-1212-B
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
0.7g
JEDEC CODE
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 24 –
Similar pages