Intersil ISL6298 Li-ion/li-polymer battery charger Datasheet

ISL6298
®
Data Sheet
July 20, 2005
FN9173.3
Li-ion/Li-Polymer Battery Charger
Features
The ISL6298 is an integrated single-cell Li-ion or Li-polymer
battery charger optimized for low current applications. The
targeted applications include mini-disk (MD) players, Blue
Tooth headsets, or other applications that use low-capacity
battery cells.
• Complete Charger for Single-Cell Li-ion Batteries
The ISL6298 is a linear charger that charges the battery in a
CC/CV (constant current/constant voltage) profile. The
charge current is programmable with an external resistor up
to 450mA during the CC phase. Once the battery voltage
reaches 4.2V (or 4.1V), the charger enters CV mode and the
charge current starts to reduce. When the charger current
drops to a user-programmable threshold, the charger
indicates the end-of-charge with a STATUS pin. The charger
does not actually terminate until a user-programmable total
fast charge time is reached. If the battery voltage drops to a
recharge threshold after termination, the charger will recharge the battery to its full capacity. The charger
preconditions the battery with 20% of the programmed CC
current if the battery voltage is below 2.8V. The total
precharge time is limited to 1/8 of the total fast charge time.
• Programmable Current Limit up to 450mA
The ISL6298 features charge current thermal foldback to
guarantee safe operation when the printed circuit board is
space-limited for thermal dissipation. Additional features
include an NTC thermistor interface for monitoring the
ambient temperature, the ability to disable the time limit of
the fast charge, an FAULT indication, and a thermally
enhanced QFN or DFN package.
Ordering Information
• Thermally-Enhanced QFN Packages
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• MD Players, Blue-Tooth Headsets and MP3 Players
• Portable Instruments
• PDAs, Cell Phones and Smart Phones
• Stand-Alone Chargers
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
16 Ld 4x4 QFN
L16.4x4
• Technical Brief TB379 “Thermal Characterization of
Packaged Semiconductor Devices”
L10.3x3
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
16 Ld 4x4 QFN
Pinouts
L16.4x4
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
ISL6298 (16 LD QFN)
TOP VIEW
ISL6298 (10 LD DFN)
TOP VIEW
VBAT
10 Ld 3x3 DFN
16 Ld 4x4 QFN Tape and Reel
1
• Ambient Temperature Range: -20°C to 70°C
16 15 14 13
VIN 1
12 VBAT
FAULT 2
11 TEMP
STATUS 3
10 IMIN
TIME 4
9 IREF
5
6
7
8
V2P8
ISL6298-2CR4Z-T
• User Programmable Safety Timer
PKG.
DWG. #
10 Ld 3x3 DFN Tape and Reel
-20 to 70
• NTC Thermistor Interface for Battery Temperature Monitor
VBAT
ISL6298-2CR4Z
• Charge Current Thermal Foldback
VIN
ISL6298-2CR3Z-T
• 10% Accuracy at 250mA
PACKAGE
(Pb-FREE)
16 Ld 4x4 QFN Tape and Reel
-20 to 70
• Preconditioning with 20% Fast Charge Current
EN
ISL6298-2CR3Z
• Programmable End-of-Charge Current
VIN
ISL6298CR4Z-T
-20 to 70
• 1% Voltage Accuracy
GND
ISL6298CR4Z
TEMP.
RANGE (°C)
• No External Blocking Diode Required
TOEN
PART # (NOTE)
• Integrated Pass Element and Current Sensor
VIN
1
10 VBAT
FAULT
2
9
TEMP
STATUS
3
8
IREF
TIME
4
7
V2P8
GND
5
6
EN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2005. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL6298
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 7V
Output Pin Voltage (VBAT) . . . . . . . . . . . . . . . . . . . . . . -0.3 to 5.5V
Signal Input Voltage (TOEN, TIME, IREF, IMIN) . . . . . . -0.3 to 3.2V
Output Pin Voltage (STATUS, FAULT) . . . . . . . . . . . . . . . . -0.3 to 7V
Charge Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .1500V
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .150V
Thermal Resistance (Notes 1, 2)
θJA (°C/W)
θJC (°C/W)
4x4 QFN Package . . . . . . . . . . . . . . . .
41
4
3x3 DFN Package . . . . . . . . . . . . . . . .
46
4
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-20°C to 70°C
Supply Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3V to 6.5V
Charge Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 75mA to 450mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
Typical values are tested at VIN = 5V and 25°C Ambient Temperature, maximum and minimum values are
guaranteed over 0°C to 70°C Ambient Temperature with a supply voltage in the range of 4.3V to 6.5V, unless
otherwise noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Rising VIN Threshold
3.0
3.4
4.0
V
Falling VIN Threshold (Note 3)
2.25
2.4
2.65
V
VIN floating or EN = LOW
-
-
3.0
µA
POWER-ON RESET
STANDBY CURRENT
VBAT Pin Sink Current
ISTANDBY
VIN Pin Supply Current
IVIN
VBAT floating and EN pulled low
-
30
-
µA
VIN Pin Supply Current
IVIN
VBAT floating and EN floating
-
1
-
mA
Output Voltage
VCH
For ISL6298 only
4.059
4.10
4.141
V
Output Voltage
VCH
For ISL6298-2 only
4.158
4.20
4.242
V
-
0.5
-
Ω
VOLTAGE REGULATION
VBAT = 3.7V, ICHARGE = 0.3A
Power MOSFET On Resistance
CHARGE CURRENT
Constant Charge Current
ICHARGE
RIREF = 80kΩ, VBAT = 3.7V
225
250
275
mA
Trickle Charge Current
ITRICKLE
RIREF = 80kΩ, VBAT = 2.0V
45
55
64
mA
Constant Charge Current
ICHARGE
VIREF > 1.2V, VBAT = 3.7V
-
255
-
mA
Trickle Charge Current
ITRICKLE
VIREF > 1.2V, VBAT = 2.0V
-
52
-
mA
Constant Charge Current
ICHARGE
VIREF < 0.4V, VBAT = 3.7V, TA = 25°C
75
100
125
mA
Constant Charge Current
ICHARGE
VIREF < 0.4V, VBAT = 3.7V, 0°C ~ 50°C
70
100
130
mA
Trickle Charge Current
ITRICKLE
VIREF < 0.4V, VBAT = 2.0V
-
23
-
mA
14
25
36
mA
End-of-Charge Threshold
IEOC
RIMIN = 80kΩ
RECHARGE THRESHOLD
Recharge Voltage Threshold
VRECHRG
For ISL6298 only
-
3.9
-
V
Recharge Voltage Threshold
VRECHRG
For ISL6298-2 only
-
4.0
-
V
2
FN9173.3
July 20, 2005
ISL6298
Electrical Specifications
Typical values are tested at VIN = 5V and 25°C Ambient Temperature, maximum and minimum values are
guaranteed over 0°C to 70°C Ambient Temperature with a supply voltage in the range of 4.3V to 6.5V, unless
otherwise noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TRICKLE CHARGE THRESHOLD
Trickle Charge Threshold Voltage
VMIN
For ISL6298 only
2.63
2.73
2.93
V
Trickle Charge Threshold Voltage
VMIN
For ISL6298-2 only
2.7
2.8
3.0
V
VTMIN
V2P8 = 3.0V
1.45
1.51
1.57
V
V2P8 = 3.0V
-
220
-
mV
V2P8 = 3.0V
0.36
0.38
0.40
V
V2P8 = 3.0V
-
60
-
mV
V2P8 = 3.0V
-
2.25
-
V
TEMPERATURE MONITORING
Low Battery Temperature Threshold
Low Battery Temperature Hysteresis
High Battery Temperature Threshold
VTMAX
High Battery Temperature Hysteresis
Battery Removal Threshold
VRMV
Charge Current Foldback Threshold
TFOLD
85
100
115
°C
Current Foldback Gain (Note 4)
GFOLD
-
25
-
mA/°C
2.4
3.0
3.6
ms
2.0
-
-
V
TOEN and EN Input Low
-
-
0.8
V
IREF and IMIN Input High
1.2
-
-
V
IREF and IMIN Input Low
-
-
0.4
V
5
-
-
mA
OSCILLATOR
Oscillation Period
TOSC
CTIME = 15nF
LOGIC INPUT AND OUTPUT
TOEN Input High
STATUS/FAULT Sink Current
Pin Voltage = 0.8V
NOTES:
3. The POR falling edge voltage is guaranteed to be lower than the Trickle Charge Threshold Voltage (VMIN) by actual tests.
4. Guaranteed by design, not tested.
3
FN9173.3
July 20, 2005
ISL6298
The test conditions for the Typical Operating Performance are: VIN = 5V, TA = 25°C,
RIREF = RIMIN = 80kΩ, VBAT = 3.7V, Unless Otherwise Noted
4.25
4.216
4.24
4.214
4.23
OUTPUT VOLTAGE (V)
BATTERY VOLTAGE (V)
Typical Operating Performance
4.22
4.21
4.20
4.19
4.18
4.17
LOAD CURRENT = 10mA
4.212
4.210
4.208
4.206
4.204
4.202
4.16
4.200
4.15
0
0.05
0.1 0.15
0.2 0.25 0.3 0.35
0
0.4
20
FIGURE 1. CHARGER OUTPUT VOLTAGE vs CHARGE
CURRENT
60
80
100
FIGURE 2. CHARGER OUTPUT VOLTAGE vs TEMPERATURE
450
4.30
400
4.28
CHARGE CURRENT = 10mA
4.26
CHARGE CURRENT (mA)
BATTERY VOLTAGE (V)
40
TEMPERATURE (OC)
CHARGE CURRENT (A)
4.24
4.22
4.20
4.18
4.16
4.14
4.12
4.10
350
300
250
200
150
RIREF = 50kΩ
100
VIREF = 0 V
50
0
0
4.3 4.5 4.7 4.9 5.1 5.3 5.5 5.7 5.9 6.1 6.3 6.5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
BATTERY VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 3. CHARGER OUTPUT VOLTAGE vs INPUT
VOLTAGE CHARGE CURRENT IS 50mA
FIGURE 4. CHARGE CURRENT vs BATTERY VOLTAGE
500
0.45
450
CHARGE CURRENT (mA)
400
CHARGE CURRENT (A)
RIREF = 50kΩ
350
300
RIREF = 100kΩ
250
200
VIREF = 0 V
150
100
50
0.40
0.35
RIREF = 50kΩ
0.30
0.25
0.20
0.15
VIREF = 0 V
0.10
0.05
0
0.00
0
20
40
60
80
100
TEMPERATURE (OC)
FIGURE 5. CHARGE CURRENT vs AMBIENT TEMPERATURE
4
4.3 4.5 4.7 4.9 5.1 5.3 5.5 5.7 5.9 6.1 6.3 6.5
INPUT VOLTAGE (V)
FIGURE 6. CHARGE CURRENT vs INPUT VOLTAGE
FN9173.3
July 20, 2005
ISL6298
Typical Operating Performance
The test conditions for the Typical Operating Performance are: VIN = 5V, TA = 25°C,
RIREF = RIMIN = 80kΩ, VBAT = 3.7V, Unless Otherwise Noted (Continued)
2.920
3.00
V2P8 PIN VOLTAGE (V)
V2P8 PIN VOLTAGE (V)
2.95
2.915
2.910
2.905
2.90
2.85
2.80
2.75
LOAD CURRENT = 2 mA
2.70
2.900
3.5
4
4.5
5
5.5
6
0
6.5
2
INPUT VOLTAGE (V)
FIGURE 7. V2P8 OUTPUT vs INPUT VOLTAGE
8
10
770
MEASURED WITH THE 3X3
DFN PACKAGE
900
MOSFET ON RESISTANCE (mΩ)
MOSFET ON RESISTANCE (mΩ)
6
FIGURE 8. V2P8 OUTPUT vs ITS LOAD CURRENT
1000
800
700
600
500
400
730
RIREF = 50kΩ
MEASURED AT 250mA
690
650
3X3 PACKAGE
610
570
530
4X4 PACKAGE
490
450
0
20
40
60
80
100
120
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1
TEMPERATURE (OC)
BATTERY VOLTAGE (V)
FIGURE 9. rDS(ON) vs TEMPERATURE AT 3.7V OUTPUT
FIGURE 10. rDS(ON) vs OUTPUT VOLTAGE USING CURRENT
LIMITED ADAPTERS
1.2
50
INPUT QUIESCENT CURRENT (µA)
REVERSE CURRENT (µA)
4
LOAD CURRENT (mA)
1.0
0.8
0.6
0.4
0.2
0.0
0
20
40
60
TEMPERATURE
80
100
(OC)
FIGURE 11. REVERSE CURRENT vs TEMPERATURE
5
45
EN PIN GROUNDED
40
35
30
25
20
15
10
5
0
0
20
40
60
TEMPERATURE
80
100
(OC)
FIGURE 12. INPUT QUIESCENT CURRENT vs TEMPERATURE
FN9173.3
July 20, 2005
ISL6298
Typical Operating Performance
The test conditions for the Typical Operating Performance are: VIN = 5V, TA = 25°C,
RIREF = RIMIN = 80kΩ, VBAT = 3.7V, Unless Otherwise Noted (Continued)
1.10
45
INPUT QUIESCENT CURRENT (mA)
INPUT QUIESCENT CURRENT (µA)
50
40
35
30
25
20
15
10
5
0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.05
1.00
0.95
0.90
0.85
0.80
4.2
6.5
4.5
4.8
5.1
5.4
5.7
6.0
6.3
6.6
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 13. INPUT QUIESCENT CURRENT vs INPUT
VOLTAGE WHEN SHUTDOWN
FIGURE 14. INPUT QUIESCENT CURRENT vs INPUT
VOLTAGE WHEN NOT SHUTDOWN
28
24
CURRENT (mA)
20
16
12
8
4
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
PIN VOLTAGE (V)
FIGURE 15. STATUS/FAULT PIN VOLTAGE vs CURRENT WHEN THE OPEN-DRAIN MOSFET TURNS ON
6
FN9173.3
July 20, 2005
ISL6298
Pin Description
EN (Pin 7 for 4x4; Pin 6 for 3x3)
VIN (Pin 1, 15, 16 for 4x4; Pin 1 for 3x3)
EN is the enable logic input. Connect the EN pin to LOW to
disable the charger or leave it floating to enable the charger.
VIN is the input power source. Connect to a wall adapter.
V2P8 (Pin 8 for 4x4; Pin 7 for 3x3)
Fault (Pin 2)
This is a 2.8V reference voltage output. This pin outputs a
2.8V voltage source when the input voltage is above POR
threshold and outputs zero otherwise. The V2P8 pin can be
used as an indication for adapter presence.
FAULT is an open-drain output indicating fault status. This
pin is pulled to LOW under any fault conditions.
Status (Pin 3)
STATUS is an open-drain output indicating charging and
inhibit states. The STATUS pin is pulled LOW when the
charger is charging a battery.
IREF (Pin 9 for 4x4; Pin 8 for 3x3)
Time (Pin 4)
IMIN (Pin 10 for 4x4; N/A for 3x3)
The TIME pin determines the oscillation period by
connecting a timing capacitor between this pin and GND.
The oscillator also provides a time reference for the charger.
IMIN is the programmable input for the end-of-charge
current. For the 3x3 DFN package, this pin is shorted to the
V2P8 pin internally.
GND (Pin 5)
TEMP (Pin 11 for 4x4; Pin 9 for 3x3)
GND is the connection to system ground.
TEMP is the input for an external NTC thermistor. The TEMP
pin is also used for battery removal detection.
This is the programming input for the constant charging
current.
TOEN (Pin 6 for 4x4; N/A for 3x3)
TOEN is the TIMEOUT enable input pin. Pulling this pin to
LOW disables the TIMEOUT function. Leaving this pin HIGH
or floating enables the TIMEOUT limit. For the 3x3 DFN
package, this pin is left floating internally.
VBAT (Pin 12, 13, 14 for 4x4; Pin 10 for 3x3)
VBAT is the connection to the battery. Typically a 10µF
Tantalum capacitor is needed for stability when there is no
battery attached. When a battery is attached, only a 1µF
ceramic capacitor is required.
Typical Applications
4x4 QFN Package Options
5V Wall
Adapter
VIN
1µF
C1
500 Ω
R1
500 Ω
R2
D1
D2
VBAT
1µ F
C2
TOEN
ISL6298
FAULT
STATUS
EN
1µF
C3
Battery
Pack
RU
RT
T
TEMP
IREF
IMIN
V2P8
TIME
V2P8
GND
R IMIN
80kΩ
RIREF
80 kΩ
CTIME
15nF
FIGURE 16. TYPICAL APPLICATION CIRCUIT FOR THE 4x4 QFN PACKAGE OPTIONS
7
FN9173.3
July 20, 2005
ISL6298
Typical Applications (Continued)
3x3 DFN Package Option
5V Wall
Adapter
VIN
1µF
C1
500 Ω
R1
500 Ω
R2
D1
D2
VBAT
1µ F
C2
Battery
Pack
ISL6298
(3X3 DFN)
FAULT
RT
T
TEMP
RU
STATUS
V2P8
EN
TIME
IREF
GND
CTIME
15nF
1µF
RIREF C3
80 kΩ
FIGURE 17. TYPICAL APPLICATION CIRCUIT FOR THE 3x3 DFN PACKAGE OPTION
3x3 DFN Package Option
5V Wall
Adapter
VIN
1µF
C1
VBAT
ISL6298
(3X3 DFN)
1µ F
C2
Battery
Pack
V2P8
1µF
C3
10kΩ
R1
10kΩ
R2
To µC
EN
FAULT
STATUS
TIME
CTIME
15nF
TEMP
IREF
GND
RIREF
80 kΩ
FIGURE 18. TYPICAL APPLICATION CIRCUIT FOR NOT USING AN NTC THERMISTOR AND INTERFACING TO A MICRO-COMPUTER.
THE TEMP PIN IS SHORT-CIRCUITED TO IREF PIN. THE INDICATIONS USES V2P8 PIN OUTPUT AS THE PULL-UP
VOLTAGE.
8
FN9173.3
July 20, 2005
ISL6298
Block Diagram
QMAIN
VIN
ISEN
Input_OK
VMIN
IT
25000:1
Current
Mirror
+
CA
-
IMIN
+
+
VA
-
IMIN
RIMIN
-
CHRG
Current
References
VBAT
VPOR
-
IR
RIREF
VIN
+
-
IREF
V2P8
VRECHRG
QSEN
VCH
References
Temperature
Monitoring
VPOR
C1
VBAT
+
100mV
VCH
+
Minbat
Trickle/Fast
ISEN
+
+
-
MIN_I
Recharge
Under Temp
NTC
Interface
VMIN
VRECHRG
ESD
Diodes
V2P8
TEMP
-
LOGIC
VIN
STATUS
STATUS
VIN
Over Temp
Batt Removal
FAULT
TOEN
OSC
TIME
COUNTER
GND
FAULT
Input_OK
EN
NOTE: For the 3x3 DFN package, the TOEN pin is left floating and the IMIN pin is connected to the V2P8 pin internally.
FIGURE 19. BLOCK PROGRAM
9
FN9173.3
July 20, 2005
ISL6298
Theory of Operation
The ISL6298 is an integrated charger optimized for lowcapacity single-cell Li-ion or Li-polymer batteries. It charges
a battery with the constant current (CC) and constant voltage
(CV) profile. The charge current is trimmed to have better
than 10% accuracy at 250mA and is programmable up to
450mA. The charge voltage has 1% accuracy.
Figure 20 shows the typical operating waveforms after
power on. The power is applied at t0. When the input voltage
reaches the power-on reset (POR) threshold at t1, the V2P8
pin starts to output a 2.8V supply. This supply also powers
the internal control circuit. The POR initiates a charge cycle.
Six different ways can initiate a charge cycle, as listed in
Table 1.
TABLE 1. EVENTS THAT LEADS TO A NEW CHARGE CYCLE
#
EVENT
1
Power on Reset
2
The VIN pin voltage drops below the VBAT pin voltage and
then rises back above the VBAT pin voltage
3
A new battery being inserted (detected by TEMP pin)
4
The battery voltage drops below a recharge threshold after
completing a charge cycle
5
recovery from a battery over-temperature fault
6
the EN pin is toggled from GND to floating
at the STATUS pin at the beginning of a charge cycle. When
the EOC condition is reached, the STATUS rises to high, as
shown at t4.
After termination, if the battery voltage drops below a
recharge threshold (t6 in Figure 20), a re-charge cycle will
take place. The total time for the recharge cycle is the total
fast charge time (t7 to t8). The trickle charge time is
negligible in a recharge cycle. More detailed description for
the operation is given below.
Power on Reset (POR)
The ISL6298 resets itself as the input voltage rises above
the POR rising threshold. The V2P8 pin outputs a 2.8V
voltage, the internal oscillator starts to oscillate, the internal
timer is reset, and the charger begins to charge the battery.
The two indication pins, STATUS and FAULT, indicate a
LOW and a HIGH logic signal respectively. Figure 20
illustrates the startup of the charger between t0 to t2.
The ISL6298 has a typical rising POR threshold of 3.4V and
a falling POR threshold of 2.4V. The 2.4V falling threshold
guarantees charger operation with a current-limited adapter
to minimize the thermal dissipation. See more details on
using a current-limited adapter in the ISL6292 datasheet,
available at http://www.intersil.com.
Internal Oscillator
A charge cycle goes through a trickle mode (t1 to t2), a
constant current (CC) mode (t2 to t3) and a constant voltage
(CV) mode (t3 to t5). The total fast charge (CC and CV) time
(t2 to t5) is programmed by users to prevent charging a faulty
battery for an excessively long time. At the end of the fast
charge time (t5), the charger is terminated. The charger
must reach an end-of-charge (EOC) condition before the
termination; otherwise, the charger issues a fault indication
through the FAULT pin. The charger issues a logic low signal
The internal oscillator (see the Block Diagram) establishes a
timing reference. The oscillation period is programmable
with an external timing capacitor, CTIME, as shown in Typical
Applications. The oscillator charges the timing capacitor to
1.5V and then discharges it to 0.5V in one period, both with
10µA current. The period TOSC is:
6
T OSC = 0.2 ⋅ 10 ⋅ C TIME
( sec onds )
(EQ. 1)
A 1nF capacitor results in a 0.2ms oscillation period.
Total Fast Charge Time
The total fast charge time TIMEOUT is also programmed by
the CTIME. A 22-stage binary counter increments each
oscillation period to set the TIMEOUT, thus,
VIN
POR Threshold
V2P8
Charge Cycle
Charge Cycle
TIMEOUT = 2
15 Cycles to
1/8 TIMEOUT
VRECHRG
VBAT
IMIN
ICHARGE
t1 t2
t3
t4
t5
t6 t7
FIGURE 20. TYPICAL OPERATING WAVEFORMS
10
( minutes )
(EQ. 2)
Trickle Charge Time
15 Cycles
2.8V VMIN
t0
C TIME
⋅ T OSC = 14 ⋅ -----------------1nF
A 1nF capacitor leads to 14 minutes of TIMEOUT. If a user
needs to set the TIMEOUT to 3.5 hours, a 15nF capacitor is
required. The charger must reach EOC before the charger
terminates, otherwise, a TIMEOUT fault will be issued.
STATUS
FAULT
22
t8
The trickle charge time is limited to 1/8 of TIMEOUT. If the
trickle charge time (t1 to t2) exceeds the limit, a TIMEOUT
fault will be issued. The end of trickle charger is determined
by the battery voltage staying above the trickle charge
threshold (given in the Electrical Specification) for 15
consecutive cycles of TOSC; therefore, the minimum time
FN9173.3
July 20, 2005
ISL6298
the charger stays in the trickle mode is 15 cycles. Usually for
a recharge cycle, the trickle charge time is 15 cycles (t6 to t7
in Figure 20). If the battery voltage falls below the trickle
charge threshold during the 15 cycles, the 15-cycle counter
is reset (not the total-trickle-charge-time counter) and the
charger remains in the trickle mode.
Disabling TIMEOUT Limit
CC Mode Current Programming
The charge current is programmed by the IREF pin. There
are three ways to program the charge current:
1. driving the IREF pin above 1.3V
1. By connecting a resistor between the IMIN pin and
ground,
When programming with the resistor, the IEOC is set in the
equation below:
V REF
0.8V
I EOC = 2500 ⋅ ---------------- = 2500 ⋅ ---------------- ( A )
R IMIN
R IMIN
(EQ. 5)
where RIMIN is the resistor connected between the IMIN pin
and the ground, as shown in the Typical Application Circuit.
When connected to the V2P8 pin, the IEOC is set to 1/10 of
ICHARGE given in EQ. 3, except when the IREF pin is
shorted to GND. Under this exception, IEOC is 5mA. For the
ISL6298 in the 3x3 DFN package, the IMIN pin is connected
internally to the V2P8 pin.
EOC Conditions
The EOC indication is asserted when the following
conditions are satisfied simultaneously:
1. The battery voltage is above the recharge threshold, and
2. driving the IREF pin below 0.4V,
3. or using the RIREF as shown in the Typical Applications.
The voltage of IREF is regulated to a 0.8V reference voltage
when not driven by any external source. The charging
current during the CC mode is 25,000 times that of the
current in the RIREF resistor. Hence, depending on how the
IREF pin is used, the charge current is,
V IREF > 1.3V
R IREF
(EQ. 3)
V IREF < 0.4V
The actual charge current may be affected by the thermal
foldback function. See the Thermal Foldback section for
more details.
Trickle Mode Current
The charge current in the trickle mode is 20% of the
programmed CC mode charge current, that is:
I TRICKLE = 0.2 ⋅ I CHARGE
(EQ. 4)
where ICHARGE is the charge current given in EQ. 3.
2. The charge current is lower than the EOC current.
The two conditions can prevent prematurely indicating EOC
due to thermal foldback or other transient events.
Recharge
After a charge cycle is completed, charging is prohibited until
the battery voltage drops to a recharge threshold, VRECHRG
(see Electrical Specifications). Then a new charge cycle
starts at point t6 and ends at point t8, as shown in Figure 20.
The safety timer is reset at t6.
2.8V Voltage Regulator
The internal reference voltage at the IREF pin is capable of
sourcing less than 100µA current. When pulling down the
IREF pin with a logic circuit, the logic circuit needs to be able
to sink at least 100µA current.
11
The EOC current IEOC sets the level at which the charger
starts to indicate the end of the charge with the STATUS pin,
as shown in Figure 20. The IEOC is set in two ways:
2. Or by connecting the IMIN pin to the V2P8 pin.
The TOEN pin allows the user to disable the fast charge
TIMEOUT limit by pulling the TOEN pin to LOW or shorting it
to GND. When this happens, the charger never terminates.
The STATUS pin still issues the EOC indication when the
EOC condition is reached. The EOC indication is latched
and does not change until a new charge cycle starts,
initiated by the events listed in Table 1. Leaving the TOEN
pin floating is recommended to enable the TIMEOUT. Driving
the TOEN pin above 3.0V is not recommended. The trickle
charge time limit can never be disabled. For the 3x3 DFN
package option, the TOEN pin is left floating internally and,
therefore, the TIMEOUT cannot be disabled.
 255mA

 0.8V
I CHARGE =  ----------------- × 25000 ( A )
 R IREF

 100mA
End-of-Charge (EOC) Current
The V2P8 pin is the output of an internal 2.8V linear regulator.
The 2.8V is the voltage supply for the internal control circuit
and can also be used by external circuits, such as the NTC
thermistor circuit. The external load is not recommended to
exceed 2mA. The V2P8 pin is recommended to be decoupled
with a 1µF ceramic capacitor.
NTC Thermistor Interface
The TEMP pin offers an interface to an external NTC
thermistor. This pin has two functions: to monitor the battery
ambient temperature or to monitor the insertion of the battery.
The ISL6298 assumes that the NTC thermistor is inside the
battery pack. The battery and the NTC thermistor are inserted
or removed together. Removing the NTC thermistor disables
the charger.
Figure 21 shows the implementation of the TEMP pin. The
comparator CP1 monitors the existence of the NTC thermistor.
When the thermistor is removed, the TEMP pin voltage is
FN9173.3
July 20, 2005
ISL6298
pulled up to the V2P8 pin voltage, higher than the Battery
Removal Threshold VRMV, and the charger is disabled.
Comparators CP2 and CP3 form a window comparator and
the two transistors, Q1 and Q2, create hysteresis for the two
window thresholds respectively. When the TEMP pin voltage
is “out of the window,” determined by the VTMIN and VTMAX,
the ISL6298 stops charging and indicates a fault condition.
When the temperature returns to within the window, the
charger re-starts a charge cycle. See the Application
Information for more details on the NTC thermistor selection.
Thermal Foldback
Over-heating is always a concern in a linear charger. The
maximum power dissipation usually occurs at the beginning
2.8V
V2P8
ISL6298
Battery
Removal
CP1
-
R1
40K
VRMV
R2
60K
+
Under
Temp
CP2
-
RU
VTMIN
+
To TEMP Pin
Usually the charge current should not drop below the EOC
current because of the thermal foldback. For some extreme
cases if that does happen, the charger does not indicate
end-of-charge unless the battery voltage is already above
the recharge threshold.
The ISL6298 has three indications: the input presence, the
charge status, and the fault indication. The input presence is
indicated by the V2P8 pin while the other two indications are
presented by the STATUS pin and FAULT pin respectively.
Q1
CP3 -
+
Figure 22 shows the typical charge curves in a charge cycle,
using a constant voltage input. Once the internal
temperature reaches 100°C, the ISL6298 starts to reduce
the charge current to prevent further temperature rise. The
power dissipation is directly related to the thermal
impedance, which is related to the layout of the printedcircuit board, and the ambient temperature. The dotted lines
show the power limit and the current waveforms in two cases
that the thermal foldback occurs. The current is reduced and
gradually increases to the constant charge current as the
battery voltage rises.
Indications
R3
75K
TEMP
Over
Temp
of a charge cycle when the battery voltage is at its minimum
but the charge current is at its maximum. The charge current
thermal foldback function in the ISL6298 frees users from
the over-heating concern.
RT
R4
25K
VTMAX
Q2
R5
4K
GND
Figure 23 shows the V2P8 pin voltage vs. the input voltage.
The V2P8 pin outputs a 2.8V voltage (blue waveform) when
the input voltage (yellow waveform) rises above 3.4V rising
POR threshold and falls to zero volt when the input voltage
falls below the 2.4V falling POR threshold. The V2P8 pin can
be used as a logic signal for the input presence.
FIGURE 21. THE INTERNAL AND EXTERNAL CIRCUIT FOR
THE NTC INTERFACE
Trickle
Mode
VIN
VCH
Constant Current
Mode
Constant Voltage
Mode
Inhibit
3.4V
2.4V
Input Voltage
Battery Voltage
VMIN
VIN
2.8V
IREF
Charge Current
V2P8
IREF/5
P1
P2
P3
Power Dissipation
FIGURE 23. THE V2P8 PIN OUTPUT vs THE INPUT VOLTAGE
AT THE VIN PIN. VERTICAL: 1V/DIV,
HORIZONTAL: 100ms/DIV
TIMEOUT
FIGURE 22. TYPICAL CHARGE CURVES USING A
CONSTANT-VOLTAGE INPUT
12
FN9173.3
July 20, 2005
ISL6298
Three types of events will result in the FAULT pin to indicate
a logic low signal. The following explains the causes and
consequences.
1. TEMP pin voltage out of window. This is caused by the
ambient temperature being out of the user-set window.
When this fault occurs, the charging is halted until the
temperature returns within the window.
2. TEMP pin voltage higher than the battery removal
threshold. This is caused by the removal of the battery
pack. The charger is disabled when the battery is
removed and enabled when the battery is re-inserted.
3. TIMEOUT fault during trickle mode or CC mode. The
charger is latched when this error occurs. This fault can
only be cleared by cycling the input power or the EN
input.
The STATUS pin indicates a logic low when a charge cycle
starts and indicates a high when the EOC conditions are
met. Once the EOC conditions are met, the STATUS signal
is latched to high until a new charge cycle.
Both the STATUS and the FAULT pin need be pulled up with
external resistors to the 2.8V from the V2P8 pin or the input
voltage. Table 2 summarizes the STATUS and FAULT pins.
TABLE 2. INDICATION PINS
FAULT STATUS
INDICATION
High
High
Charge completed with no fault (Inhibit) or
Standby
High
Low
Charging in one of the three modes
Low
High
Fault
*Both outputs are pulled up with external resistors.
Shutdown
The ISL6298 can be shutdown by pulling the EN pin to
ground. When shut down, the charger draws typically less
than 30µA current from the input power and less than 3µA
current from the battery. The 2.8V output at the V2P8 pin is
also turned off. The EN pin needs be driven with an opendrain or open-collector logic output, so that the EN pin is
floating when the charger is enabled.
Battery Leakage Current
Capacitor Selection
Typically any type of capacitors can be used for the input
and the output. A minimum 1µF ceramic capacitor is
recommended to be placed very close to the charger input.
Higher value input decoupling capacitance helps the stable
operation of the charger.
The output capacitor selection is dependent on the
availability of the battery during operation. When the battery
is attached to the charger, the output capacitor can be any
ceramic type with the value higher than 1µF. However, if
there is a chance the charger will be used as a linear
regulator, a 10µF tantalum capacitor is recommended.
The V2P8 pin supplies power to the internal control circuit as
well as external circuits. A good decoupling to this pin is very
important to a reliable operation of the charger. It is
recommended to use a 1µF ceramic capacitor for this pin.
FAULT and STATUS Pull-Up Resistors
Both FAULT and STATUS pins are open-drain outputs that
need an external pull-up resistor. It is recommended that
both pins be pulled up to the input voltage or the 2.8V from
the V2P8 pin, as shown in the Typical Application Circuits. If
the indication pins have to be pulled up to other voltages, the
user needs to examine carefully whether or not the ESD
diodes will form a leakage current path to the battery when
the input power is removed. If the leakage path does exist,
an external transistor is required to break the path.
Figure 24 shows the implementation. If the FAULT pin is
directly pulled up to the VCC voltage (not shown in Figure
24), a current will flow from the VCC to the FAULT pin, then
through the ESD diode to the VIN pin. Any leakage on the
VIN pin, caused by an external or internal current path, will
result in a current path from VCC to ground.
VIN
VCC
ESD Diode
EN
STATUS
RLKG
VIN or
V2P8
Control
The leakage current from the battery is different when the IC
is enabled and disabled. When the IC is disabled, due to
removing input power or pulling the EN pin to low, the
leakage current is less than 3µA. When the IC is enabled but
not charging (due to a fault condition, the battery removal, or
after termination), the leakage current is caused mainly by
an internal 75kΩ voltage divider for the output voltage feedback. The leakage current is approximately 56µA when the
battery voltage is 4.2V.
Applications Information
R1
VIN
Q1
FAULT
GND
Note:
RLKG is approximately 240kΩ when EN is floating and is
approximately 140kΩ when the EN is grounded.
FIGURE 24. PULL-UP CIRCUIT TO AVOID BATTERY LEAKAGE
CURRENT IN THE ESD DIODES.
13
FN9173.3
July 20, 2005
ISL6298
The N-channel MOSFET Q1 buffers the FAULT pin. The
gate of Q1 is connected to VIN or the V2P8 pin. When the
FAULT pin outputs a logic low signal, Q1 is turned on and its
drain outputs a low signal as well. When FAULT is high
impedance, R1 pulls the Q1 drain to high. When the input
power is removed, the Q1 gate voltage is also removed, thus
the Q1 drain stays high.
where RCOLD and RHOT are the NTC thermistor resistance
values at the cold and hot temperature limits respectively.
It is usually difficult to find an NTC thermistor that has the
exact ratio given in EQ. 7. A thermistor with a ratio larger
than 7.08, that is:
R COLD
-------------------- ≥ 7.08
R HOT
NTC Thermistor Circuit Design
As shown in Figure 21, the thresholds for the NTC circuit are
formed by the internal voltage divider. Since the external
circuit is also a voltage divider, the accuracy of the bias
voltage, that is, the V2P8 pin voltage, becomes not critical.
Figure 25 shows the typical values of the thresholds as
percentages of the V2P8 pin voltage.
The NTC thermistor resistance is dependent on the ambient
temperature. Reducing temperature leads to the increase of
the resistance as well as the TEMP pin voltage. When the
TEMP pin voltage exceeds 50.3% of the bias voltage, an
under-temperature fault is triggered. On the other hand, if
the TEMP pin voltage is lower than 12.5%, an over
temperature fault occurs. The TEMP pin voltage has to fall
back to the 14.5% to 42.9% range for the fault be cleared, as
shown in Figure 25.
The ratio, K, of the TEMP pin voltage to the bias voltage is:
RT
K = --------------------RT + RU
(EQ. 6)
Using the ratios at cold and hot temperature limits, as shown
in Figure 25, resulting in:
R COLD
-------------------- = 7.08
R HOT
(EQ. 7)
and
R U = 1.012 ⋅ R COLD
(EQ. 8)
(EQ. 9)
can be used in series with a regular resistor to form an
effective thermistor that has the right ratio, as shown in
Figure 26. With the series resistor RS, EQ. 7 can be rewritten as:
RS + R
COLD
---------------------------------= 7.08
RS + R
(EQ. 10)
HOT
Once the thermistor and the temperature limits are selected,
RS and RU can be calculated using
R COLD – 7.08R HOT
R S = -----------------------------------------------------6.08
(EQ. 11)
and
R U = 1.012 ⋅ ( R S + R COLD )
(EQ. 12)
To summarize, the NTC thermistor circuit design requires
three steps:
1. Find an NTC thermistor that satisfies EQ. 9. The
temperature limits are determined by the application
requirement.
2. Calculate the series resistance according to EQ. 11.
3. Calculate the pull-up resistance according to EQ. 12.
The following is a design example. The charger is designed
to charge the battery with the temperature range from 0°C to
55°C. The 10kΩ NTC thermistor NCP15XH103F03RC from
Murata (http://www.murata.com) satisfies EQ. 9. The
resistance table is given in Table 3. The typical resistance at
100%
V2P8
VTMIN (50.3%)
RU
TEMP
Pin
Voltage
TEMP
ISL6298
RS
VTMAX+ (14.5%)
VTMAX (12.5%)
RT
0
Under
Temp
Effective NTC
Thermistor
VTMIN- (42.9%)
GND
Over
Temp
FIGURE 25. CRITICAL VOLTAGE LEVELS FOR TEMP PIN
14
FIGURE 26. EFFECTIVE NTC THERMISTOR CIRCUIT
FN9173.3
July 20, 2005
ISL6298
0°C and 55°C are RCOLD = 27.2186kΩ and RHOT = 3.535kΩ
respectively. Using EQ. 11 and EQ. 12 result in RS = 360Ω
and RU = 27.9kΩ.
Hysteresis Temperature Calculation
Using EQ. 6 is re-arranged as:
K
R T = ------------- ⋅ R U – R S
1–K
(EQ. 13)
Working with Current-Limited Adapter
The ISL6298 minimizes the thermal dissipation when
powered by a current-limited ac adapter. The thermal
dissipation can be further reduced when the adapter is
properly designed. For more information regarding working
with current-limited adapters, please refer to the ISL6292
datasheet available at http://www.intersil.com.
Board Layout Recommendations
Substituting the ratio at the hysteresis threshold results in
the NTC thermistor resistance at the threshold. Continuing
the example above, the thermistor values are found to be
20.64kΩ and 4.37kΩ respectively at the low and high
hysteresis temperatures. The corresponding temperatures
are found from the Table 3 to be 7°C and 49°C respectively.
In other words, the hysteresis temperatures for the low and
high temperature limits are approximately 7°C and 6°C
respectively.
Temperature Tolerance Calculation
The temperature accuracy is affected by the accuracy of the
thresholds, RS, RU, and the NTC thermistor. Using the
maximum ratio K, maximum possible RU, and minimum RS
results in the maximum value of RT from EQ. 13, that is:
K MAX
R T, MAX = ------------------------- ⋅ R U, MAX – R S, MIN
1 – K MAX
The ISL6298 internal thermal foldback function limits the
charge current when the internal temperature reaches
approximately 100°C. In order to maximize the current
capability, it is very important that the exposed pad under the
package is properly soldered to the board and is connected
to other layers through thermal vias. More thermal vias and
more copper attached to the exposed pad usually result in
better thermal performance. On the other hand, the number
of vias is limited by the size of the pad. The exposed pad for
the 4x4 QFN package is able to have 5 vias. The 3x3 DFN
package allows 8 vias be placed in two rows. Since the pins
on the 3x3 DFN package are on only two sides, as much top
layer copper as possible should be connected to the
exposed pad to minimize the thermal impedance. Refer to
the ISL6298 evaluation boards for layout examples.
(EQ. 14)
From the Electrical Specification table, the maximum K is
found to be 52.3%. Assuming the resistors have 1%
accuracy, the maximum RU is 28.2kΩ and the minimum RS
is 356Ω. The resultant maximum RT is then found to be
30.6kΩ and the corresponding temperature is -3°C. Hence
the temperature tolerance is 3°C. Similarly, the high
temperature maximum thermistor value is 3.98kΩ. Hence,
the lowest temperature is 51°C and the tolerance is 4°C.
TABLE 3. RESISTANCE TABLE OF NCP15XH103F03RC
TEMP (°C)
R-Low (kΩ)
R-Center (kΩ)
R-High (kΩ)
-3
30.3641
31.0200
31.6869
0
26.6780
27.2186
27.7675
6
20.7560
21.1230
21.4944
7
19.9227
20.2666
20.6143
50
4.0833
4.1609
4.2395
51
4.9498
4.0262
4.1036
55
3.4634
3.5350
3.6076
15
FN9173.3
July 20, 2005
ISL6298
Dual Flat No-Lead Plastic Package (DFN)
2X
0.15 C A
D
A
L10.3x3
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
2X
0.15 C B
E
6
INDEX
AREA
SYMBOL
MIN
0.80
0.90
1.00
-
-
-
0.05
-
0.28
5,8
2.05
7,8
1.65
7,8
0.20 REF
0.18
D
1.95
E
SIDE VIEW
C
SEATING
PLANE
A3
1
e
1.60
-
0.50 BSC
-
k
0.25
-
-
L
0.30
0.35
0.40
N
10
Nd
5
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
NX b
5
(Nd-1)Xe
REF.
3
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
E2/2
N-1
8
2
2. N is the number of terminals.
E2
e
-
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k
8
1.55
NOTES:
D2/2
2
N
-
Rev. 3 6/04
D2
(DATUM B)
2.00
8
7
6
INDEX
AREA
(DATUM A)
0.08 C
-
3.00 BSC
E2
0.10 C
0.23
3.00 BSC
D2
A
NOTES
A
A3
B
MAX
A1
b
TOP VIEW
NOMINAL
0.10 M C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
C
L
0.415
NX (b)
(A1)
0.200
5
L
NX L
e
SECTION "C-C"
C
NX b
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
16
FN9173.3
July 20, 2005
ISL6298
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
A3
b
0.23
D
0.28
9
0.35
5, 8
4.00 BSC
D1
D2
9
0.20 REF
-
3.75 BSC
1.95
2.10
9
2.25
7, 8
E
4.00 BSC
-
E1
3.75 BSC
9
E2
1.95
e
2.10
2.25
7, 8
0.65 BSC
-
k
0.25
-
-
-
L
0.50
0.60
0.75
8
L1
-
-
0.15
10
N
16
2
Nd
4
3
Ne
4
3
P
-
-
0.60
9
θ
-
-
12
9
Rev. 5 5/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
FN9173.3
July 20, 2005