Anpec APW7068 Synchronous buck pwm and linear controller with 0.8v reference out voltage Datasheet

APW7068
Synchronous Buck PWM and Linear Controller
with 0.8V Reference Out Voltage
Features
General Description
•
The APW7068 integrates synchronous buck PWM, linear
controller, and 0.8V Reference Out Voltage, as well as
Two Regulated Voltages and REF_OUT
- Synchronous Buck Converter
- Linear Regulator
the monitoring and protection functions into a single
package. The fixed 300kHz switching frequency synchro-
- REF_OUT = 0.8V±1% with 3mA Source Current
•
Single 12V Power Supply Required
•
Excellent Both Output Voltage Regulation
nous PWM controller drives dual N-channel MOSFETs,
which provides one controlled power output with overvoltage and over-current protections. Linear controller
drives an external N-channel MOSFET with under-volt-
- 0.8V Internal Reference
- ±1% Over Line Voltage and Temperature
•
Integrated Soft-Start for PWM and Linear Outputs
•
300KHz Fixed Switching Frequency
•
Voltage Mode PWM Control Design and Up to 89%
age protection.
The APW7068 provides excellent regulation for output load
variation. An internal 0.8V temperature-compensated reference voltage is designed to meet the requirement of
(Typ.) Duty Cycle
•
low output voltage applications.
The APW7068 with excellent protection functions: POR,
Under-Voltage Protection Monitoring Linear Output
•
Over-Voltage Protection Monitoring PWM Output
•
Over-Current Protection for PWM Output
OCP, OVP and UVP. The Power-On-Reset (POR) circuit
can monitor VCC12 supply voltage exceeds its threshold
voltage while the controller is running, and a built-in digital soft-start provides both outputs with controlled rising
- Sense Low-side MOSFET’s RDS(ON)
•
voltage. The Over-Current Protection (OCP) monitors the
output current by using the voltage drop across the lower
SOP-14, SSOP-16 and Compact QFN4x4-16 packages
•
MOSFET’s RDS(ON), comparing with the voltage of OCSET
pin, VOCSET. The maximum VOCSET voltage is limited to the
Lead Free and Green Devices Available
(RoHS Compliant)
internal default value 0.25V. In addition, when OCSET pin
is floating (no ROCSET resistor), the over current threshold
Applications
•
will also be internal default value, 0.25V. When the output
current reaches the trip point, the controller will shutdown
the IC directly, and latch the converter’s output. The Under-Voltage Protection (UVP) monitors the voltage of FBL
Graphic Cards
pin for short-circuit protection. When the VFBL is less than
50% of VREF, the controller will shutdown the IC directly.
Simplified Application Circuit
12V
The Over-Voltage Protection (OVP) monitors the voltage
of FB. When the VFB is over 135% of VREF, the controller will
VIN1
VIN2
make Low-side gate signal fully turn on until the fault
events are removed.
Q1
Q3
VOUT2
L
PWM
Linear
Controller
Controller
VOUT1
Q2
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
1
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APW7068
Ordering and Marking Information
APW7068
Package Code
K : SOP-14 N : SSOP-16 QA : QFN4x4-16
Temperature Range
E : -20 to 70 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Assembly Material
Handling Code
Temperature Range
Package Code
APW7068 K :
APW7068
XXXXX
XXXXX - Date Code
APW7068 N :
APW7068
XXXXX
XXXXX - Date Code
XXXXX - Date Code
APW7068
XXXXX
APW7068 QA :
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
BOOT
FS_DIS
COMP
FB
DRIVE
FBL
GND
GND
1
2
3
4
5
6
7
8
SSOP-16
TOP VIEW
SOP-14
TOP VIEW
Absolute Maximum Ratings
Symbol
16
15
14
13
12
11
10
9
UGATE
PHASE
COMP
PGND
FB
LGATE
DRIVE
OCSET
REF_OUT FBL
VCC12
VCC12
PHASE
UGATE
16 15 14 13
1
12 PGND
Metal
GND Pad
(Bottom)
2
3
11 LGATE
10 OCSET
4
9
5
6
7
8
VCC12
UGATE
PHASE
PGND
LGATE
OCSET
REF_OUT
VCC12
VCC12
14
13
12
11
10
9
8
AGND
1
2
3
4
5
6
7
DGND
BOOT
FS_DIS
COMP
FB
DRIVE
FBL
GND
BOOT
FS_DIS
Pin Configuration
REF_OUT
QFN 4x4-16
TOP VIEW
(Note 1)
Rating
Unit
VCC12
VCC12 to GND
Parameter
-0.3 to +16
V
VBOOT
BOOT to PHASE
-0.3 to +16
V
<400ns Pulse Width
>400ns Pulse Width
-5 to VBOOT +5
-0.3 to VBOOT +0.3
V
<400ns Pulse Width
>400ns Pulse Width
-5 to VCC12+5
-0.3 to VCC12+0.3
V
UGATE to PHASE
VUGATE
LGATE to PGND
VLGATE
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
2
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APW7068
Absolute Maximum Ratings (Cont.) (Note 1)
Symbol
Parameter
Rating
Unit
-10 to +30
-0.3 to 16
V
12
V
-0.3 to 7
V
PHASE to GND
VPHASE
VDRIVE
<200ns Pulse Width
>200ns Pulse Width
DRIVE to GND
VFB, VFBL,
FB, FBL, COMP, FS_DIS to GND
VCOMP, VFS_DIS
VPGND
TJ
PGND to GND
-0.3 to +0.3
V
Junction Temperature Range
-20 to +150
°C
-65 ~ 150
°C
260
°C
TSTG
Storage Temperature
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Symbol
Parameter
Rating
Unit
VCC12
IC Supply Voltage
10.8 to 13.2
V
VIN1
Converter Input Voltage
2.9 to 13.2
V
VOUT1
Converter Output Voltage
0.9 to 5
V
IOUT1
Converter Output Current
0 to 30
A
IOUT2
Linear Output Current
0 to 3
A
TA
Ambient Temperature Range
-20 to 70
°C
TJ
Junction Temperature Range
-20 to 125
°C
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC12 = 12V, and TA =-20 ~ 70°C. Typical values are at TA = 25°C.
Symbol
Parameter
APW7068
Test Conditions
Unit
Min.
Typ.
Max.
INPUT SUPPLY CURRENT
ICC12
VCC12 Supply Current (Shutdown
Mode)
UGATE, LGATE and DRIVE open;
FS_DIS = GND
-
4
6
mA
VCC12 Supply Current
UGATE, LGATE and DRIVE open
-
8
12
mA
Rising VCC12 Threshold
7.7
7.9
8.1
V
Falling VCC12 Threshold
7.2
7.4
7.6
V
Accuracy
-15
-
+15
%
255
300
345
kHz
-
1.5
-
V
-
89
-
%
POWER-ON-RESET
OSCILLATOR
FOSC
Oscillator Frequency
VOSC
Ramp Amplitude
Duty
Maximum Duty Cycle
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
(Nominal 1.2V to 2.7V)
3
(Note 2)
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APW7068
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC12 = 12V, and TA =-20 ~ 70°C. Typical values are at TA = 25°C.
Symbol
Parameter
Test Conditions
APW7068
Unit
Min.
Typ.
Max.
0.792
0.80
0.808
V
-1
-
+1
%
REFERENCE
VREF
Reference Voltage
for Error Amp1 and Amp2
Reference Voltage Tolerance
PWM Load Regulation
IOUT1 = 0 to 10A
-
-
1
%
Linear Load Regulation
IOUT2 = 0 to 3A
-
-
1
%
RL = 10k, CL = 10pF (Note 2)
-
93
-
dB
Open Loop Bandwidth
RL = 10k, CL = 10pF
(Note 2)
-
20
-
MHz
Slew Rate
RL = 10k, CL = 10pF (Note 2)
-
8
-
V/µs
FB Input Current
VFB = 0.8V
-
0.1
1
µA
PWM ERROR AMPLIFIER
Gain
GBWP
SR
Open Loop Gain
VCOMP
COMP High Voltage
-
5
-
V
VCOMP
COMP Low Voltage
-
0
-
V
ICOMP
COMP Source Current
VCOMP = 2V
-
12
-
mA
ICOMP
COMP Sink Current
VCOMP = 2V
-
12
-
mA
VBOOT = 12V,
VUGATE - VPHASE = 2V
-
2.5
-
A
-
2
-
A
GATE DRIVERS
IUGATE
Upper Gate Source Current
IUGATE
Upper Gate Sink Current
ILGATE
Lower Gate Source Current
ILGATE
Lower Gate Sink Current
RUGATE
Upper Gate Source Impedance
RUGATE
RLGATE
RLGATE
TD
-
2.5
-
A
-
3.5
-
A
VBOOT = 12V, IUGATE = 0.1A
-
2.25
3.375
Ω
Upper Gate Sink Impedance
VBOOT = 12V, IUGATE = 0.1A
-
0.7
1.05
Ω
Lower Gate Source Impedance
VCC12 = 12V, ILGATE = 0.1A
-
2.25
3.375
Ω
Lower Gate Sink Impedance
VCC12 = 12V, ILGATE = 0.1A
-
0.4
0.6
Ω
-
20
-
ns
RL = 10k, CL = 10pF (Note 2)
-
70
-
dB
Open Loop Bandwidth
RL = 10k, CL = 10pF
(Note 2)
-
19
-
MHz
Slew Rate
RL = 10k, CL = 10pF (Note 2)
-
6
-
V/µs
FBL Input Current
VFBL= 0.8V
-
0.1
1
µA
VCC12 = 12V, VLGATE = 2V
Dead Time
LINEAR REGULATOR
Gain
GBWP
SR
Open Loop Gain
VDRIVE
DRIVE High Voltage
-
10
-
V
VDRIVE
DRIVE Low Voltage
-
0
-
V
IDRIVE
DRIVE Source Current
VDRIVE = 5V
-
4
-
mA
IDRIVE
DRIVE Sink Current
VDRIVE = 5V
-
3
-
mA
PROTECTION
VFB-OV
FB Over Voltage Protection Trip Point Percent of VREF
-
135
-
%
VFBL-UV
FBL Under Voltage Protection Trip
Point
-
50
-
%
IOCSET
OCSET Current Source
36
40
44
µA
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
Percent of VREF
4
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APW7068
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC12 = 12V, and TA =-20 ~ 70°C. Typical values are at TA = 25°C.
Symbol
Parameter
APW7068
Test Conditions
Unit
Min.
Typ.
Max.
-
8.5
-
ms
Output Voltage
0.792
0.800
0.808
V
Offset Voltage
-8
-
+8
mV
SOFT-START
TSS
Internal Soft-Start Interval (Note 2)
FOSC=300kHz
REF_OUT
VREF_OUT
IREF_OUT
Source Current
1.5
3
-
mA
Sink Current
0.25
0.5
-
mA
Output Capacitance
0.4
1
2.2
µF
Note 2: Guaranteed by design.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
5
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APW7068
Typical Operating Characteristics
UGATE Source Current vs. UGATE Voltage
UGATE Sink Current vs. UGATE Voltage
3.5
VBOOT =12V
VPHASE=0V
2.5
VBOOT =12V
VPHASE=0V
3
UGATE Sink Current (A)
UGATE Source Current (A)
3
2
1.5
1
0.5
2.5
2
1.5
1
0.5
0
0
0
2
4
6
8
10
0
12
0.5
1
UGATE Voltage (V)
LGATE Source Current vs. LGATE Voltage
2
2.5
3
LGATE Sink Current vs. LGATE Voltage
7
3
VCC12=12V
VCC12=12V
6
2.5
LGATE Sink Current (A)
LGATE Source Current (A)
1.5
UGATE Voltage (V)
2
1.5
1
0.5
5
4
3
2
1
0
0
0
2
4
6
8
10
0
12
LGATE Voltage (V)
1
2
3
4
LGATE Voltage(V)
VREF vs. Junction Temperature
0.804
Reference Voltage(V)
0.8035
0.803
0.8025
VREF
0.802
0.8015
0.801
0.8005
-40
-20
0
20
40
60
80
100
120
Junction Temperature (°C)
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
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APW7068
Operating Waveforms
Power On
Power Off
VCC12=12V, VIN1=12V, VIN2=3.3V
VOUT1=1.2V, VOUT2=2.5V, L=1µH
VCC12=12V, VIN1=12V, VIN2=3.3V
VOUT1=1.2V, VOUT2=2.5V, L=1µH
1
1
2
2
3
3
CH1: VCC12 (10V/div)
CH2: VOUT1 (1V/div)
CH3: VOUT2 (2V/div)
Time: 10ms/div
CH1: VCC12 (10V/div)
CH2: VOUT1 (1V/div)
CH3: VOUT2 (2V/div)
Time: 10ms/div
EN
Shutdown
VCC12=12V, L=1µH
VIN1=12V, VIN2=3.3V
VOUT1=1.2V, VOUT2=2.5V
VCC12=12V, L=1µH
VIN1=12V, VIN2=3.3V
VOUT1=1.2V, VOUT2=2.5V
1
1
2
2
3
3
4
4
CH1: VFS_DIS (1V/div)
CH2: VDRIVE (5V/div)
CH3: VOUT1 (1V/div)
CH4: VOUT2 (2V/div)
CH1: VFS_DIS (1V/div)
CH2: VDRIVE (5V/div)
CH3: VOUT1 (1V/div)
CH4: VOUT2 (2V/div)
Time: 10ms/div
Time: 10ms/div
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
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APW7068
Operating Waveforms (Cont.)
UGATE Rising
UGATE Falling
VCC12=12V, VIN1=12V, VOUT1=1.2V
VCC12=12V, VIN1=12V, VOUT1=1.2V
1
1
2
2
3
3
CH1: VUGATE (20V/div)
CH2: VPHASE (10V/div)
CH3: VLGATE (10V/div)
Time: 50ns/div
CH1: VUGATE (20V/div)
CH2: VPHASE (10V/div)
CH3: VLGATE (10V/div)
Time: 50ns/div
OVP_PWM Controller (VFB > 135% VREF)
UVP_Linear Regulator (VFBL< 50% VREF)
VCC12=12V, VIN1=12V
VOUT1=1.2V, VOUT2=2.5V, L=1µH
VCC12=12V, VIN2=3.3V
VOUT2=2.5V, IOUT2=3A
1
1
2
2
3
3
4
CH1: VCC12 (1V/div)
CH2: VLGATE (1V/div)
CH3: VOUT1 (500mV/div)
CH4: VOUT2 (2V/div)
Time: 10ms/div
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
CH1: VFBL (1V/div)
CH2: VDRIVE (5V/div)
CH3: VOUT2 (2V/div)
Time: 100µs/div
8
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APW7068
Operating Waveforms (Cont.)
Load Transient Response (PWM Controller)
- VCC12=12V, VIN1=12V, VOUT1=2V, FOSC=300kHz
- IOUT1 slew rate=±10 A/µs
IOUT1=0Aà10A
IOUT1=0Aà10Aà0A
IOUT1=10Aà0A
1
1
1
2
2
2
3
3
3
CH1: VOUT1 (100mV/div,AC)
CH2: VUGATE (20V/div)
CH3: IOUT1 (10A/div)
Time: 20µs/div
CH1: VOUT1 (100mV/div,AC)
CH2: VUGATE (20V/div)
CH3: IOUT1(10A/div)
Time: 50µs/div
CH1: VOUT1 (100mV/div,AC)
CH2: VUGATE (20V/div)
CH3: IOUT1(10A/div)
Time: 20µs/div
Load Transient Response (Linear Regulator)
- VCC12=12V, VIN2=3.3V, VOUT2=2.5V
- IOUT2 slew rate=±3A/µs
IOUT2=0Aà3A
IOUT2=0Aà3Aà0A
1
1
2
2
IOUT2=3Aà0A
1
CH1: VOUT2 (100mV/div,AC)
CH2: IOUT2 (2A/div)
Time: 1µs/div
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
2
CH1: VOUT2 (100mV/div,AC)
CH2: IOUT2 (2A/div)
Time: 10µs/div
9
CH1: VOUT2 (100mV/div,AC)
CH2: IOUT2 (2A/div)
Time: 1µs/div
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APW7068
Operating Waveforms (Cont.)
Over Current Protection
1
VCC12=12V, VIN1=12V,
VOUT1=1.2V, VIN2=3.3V,
VOUT2=2.5V, L=1µH
Short Test after Power Ready
VCC12=12V, VIN1=12V,
VOUT1=1.2V, VIN2=3.3V,
VOUT2=2.5V, L=1µH
1
COUT=470µHx2,
ROCSET=1kΩ, RDS(ON)=4mΩ
COUT=470µHx2,
ROCSET=1kΩ, RDS(ON)=4mΩ
2
2
3
3
4
4
CH1: VOUT1 (1V/div)
CH2: VDRIVE (5V/div)
CH3: VUGATE (20V/div)
CH4: IL (10A/div)
Time: 50µs/div
CH1: VOUT1 (1V/div)
CH2: VDRIVE (5V/div)
CH3: VUGATE (20V/div)
CH4: IL (10A/div)
Time: 50µs/div
Short Test before Power On
VCC12=12V, VIN1=12V,
VOUT1=1.2V, VIN2=3.3V,
VOUT2=2.5V, L=1µH
1
2
3
4
CH1: VCC12 (10V/div)
CH2: VOUT1 (1V/div)
CH3: VUGATE (20V/div)
CH4: IL (10A/div)
Time: 2ms/div
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
10
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APW7068
Pin Description
PIN
NO.
FUNCTION
NAME
SOP-14
SSOP-16
QFN4x4-16
1
1
15
BOOT
This pin provides the bootstrap voltage to the upper gate driver for driving the
N-channel MOSFET. An external capacitor from PHASE to BOOT, an internal
diode, and the power supply voltage VCC12, generates the bootstrap voltage
for the upper gate diver (UGATE).
2
2
16
FS_DIS
This pin provides shutdown function. When pulling low the FS_DIS pin near
GND will shutdown both regulators; almost any NFET or other pull-down
device (< 1k. impedance) should work. Upon release of the FS_DIS pin, it will
enable both outputs back into regulation.
3
3
1
COMP
This pin is the output of PWM error amplifier. It is used to set the
compensation components.
4
4
2
FB
This pin is the inverting input of the PWM error amplifier. It is used to set the
output voltage and the compensation components. This pin is also monitored
for under-voltage protection, when the FB voltage is under 50% of reference
voltage (0.4V), both outputs will be shutdowned immediately.
5
5
3
DRIVE
This pin drives the gate of an external N-channel MOSFET for linear regulator.
It is also used to set the compensation for some specific applications, for
example, with low values of output capacitance and ESR.
6
6
4
FBL
This pin is the inverting input of the linear regulator error amplifier. It is used to
set the output voltage. This pin is also monitored for under-voltage protection,
when the FBL voltage is under 50% of reference voltage
(0.4V), both outputs will be shutdown immediately.
7
7,8
5,6
GND
This pin is the signal ground pin. Connect the GND pin to a good ground
plane.
8
9,10
7,8
VCC12
Power supply input pin. Connect a nominal 12V power supply to this pin. The
power-on reset function monitors the input voltage at this pin. It is
recommended that a decoupling capacitor (1 to 10µF) be connected to GND
for noise decoupling.
9
11
9
REF_OUT
This pin provides a buffed voltage, which is from internal reference voltage. It
is recommended that a 1mF capacitor is connected to ground for stability.
When VOCSET is above 1V, the REF_OUT buffer will be closed, the
VREF_OUT is 0V.
10
12
10
OCSET
Connect a resistor (ROCSET) from this pin to GND, an internal 40mA current
source will flow through this resistor and create a voltage drop. When VCC12
reaches the POR rising threshold voltage, the voltage drop of ROCSET will be
memoried and compared with the voltage across the lower MOSFET. The
threshold of the over current limit is therefore given by:
I
× R OCSET
ILIMIT = OCSET
R DS(ON)(LOW − Side)
The APW7068 has a internal OCP voltage source, and the value is around
0.25V. When the ROCSET x IOCSET is bigger than 0.25V or the OCSET PIN
is floating (no ROCSET resistor), the over current threshold will be the internal
default value 0.25V.
11
13
11
LGATE
This pin is the gate driver for the lower MOSFET of PWM output.
12
14
12
PGND
This pin is the power ground pin for the lower gate driver. It should be tied to
GND pin on the board.
13
15
13
PHASE
This pin is the return path for the upper gate driver. Connect this pin to the
upper MOSFET source, and connect a capacitor to BOOT for the bootstrap
voltage. This pin is also used to monitor the voltage drop across the lower
MOSFET for over-current protection.
14
16
14
UGATE
This pin is the gate driver for the upper MOSFET of PWM output.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
11
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APW7068
Block Diagram
OCSET
VCC12
IOCSET
40µA
REF_OUT
Reference
Buffer
PowerOn-Reset
Regulator
GND
VREF
(0.8V)
135%VREF
X1.35
UGATE
O.C.P
Comparator
10V
O.V.P
Comparator
BOOT
VOCSET
Soft Start
and
Fault
Logic
PHASE
Sense Low Side
Gate Control
LGATE
PGND
Error
Amp 1
PWM
Comparator
U.V.P
Comparator
FBL
10V
:2
50%VREF
DRIVE
VREF
Oscillator
COMP
FB
Error
Amp 2
VREF
Sawtooth Wave
(300KHz)
FS_DIS
Typical Application Circuits
C1
VIN1
2.2nF
C2
3.9K
0.01uF
VOUT1
1uH
1.2V
1.5K
22
VIN2
3.3V
C3
22nF
BOOT
UGATE 14
2
FS_DIS
PHASE
3
COMP
PGND
4
FB
LGATE 11
5
DRIVE
OCSET
10
REF_OUT
9
VCC12
8
1
RGND1
3K
Q4
APM3055
C5
VOUT2
2.5V
Q1
APM2509
L
C4
0.1uF
R1
R3
CIN2
470uF
ON/OFF
2N7002
R2
VOUT1
12V
CIN1
470uFx2
Q3
R5
R4
2.5K
COUT2
470uF
6
FBL
7
GND
APW7068
RGND2
1.17K
13
12
Q2
APM2506
C6
2.2nF
C OUT1
470uFx2
R6
2.2
C8
1uF
R7
12V
R8
2.2
C7
1uF
*C5,R5forspecificapplication
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
12
www.anpec.com.tw
APW7068
Function Description
Voltage(V)
Power-On-Reset (POR)
VFB
The Power-On-Reset (POR) function of APW7068 continually monitors the input supply voltage (VCC12), ensures
the supply voltage exceed its rising POR threshold
voltage. The POR function initiates soft-start interval op-
VFBL
20mV
32/FOSC
eration while VCC12 voltage exceeds its POR threshold
and inhibits operation under disabled status.
32/FOSC
20mV
Soft-Start
Figure 1. shows the soft-start interval. When VCC12 reaches
the rising POR threshold voltage, the internal reference
t3
Figure 2. The Controlled Stepped FB and FBL Voltage
During Soft-Start
voltage is controlled to follow a voltage proportional to the
soft-start voltage. The soft-start interval is variable by the
Over-Current Protection
oscillator frequency. The formulation is given by:
TSS = ∆( t 2 − t1) =
1
FOSC
Time
t4
× 2560
Connect a resistor (ROCSET) from this pin to GND, an internal 40µA current source will flow through this resistor
Figure 2. shows more detail of the FB and FBL voltage
ramps. The FB and FBL voltage soft-start ramps are formed
and create a voltage drop, which will be compared with
the voltage across the lower MOSFET. When the voltage
with many small steps of voltage. The voltage of one step
is about 20mV in VFB and VFBL, and the period of one step
across the lower MOSFET exceeds the voltage drop
across the ROCSET, an over-current condition is detected
is about 32/FOSC. This method provides a controlled
voltage rise and prevents the large peak current to charge
and the controller will shutdown the IC directly, and the
converter's output is latched.
The APW7068 has a internal OCP voltage source, and
the output capacitors. The FB voltage compares the FBL
voltage to shift to an earlier time the establishment as
the value is around 0.25V. When the ROCSET x IOCSET is
bigger than 0.25V or the OCSET PIN is floating (no ROCSET
Figure2. The voltage estabilishment time difference for
VFB and VFBL is variable by the oscillator. The formulation
resistor), the over current threshold will be the internal
default value 0.25V.
is given by:
∆( t 4 − t 3 ) =
1
1
× 640 = × TSS
FOSC
4
The threshold of the over current limit is therefore given
by:
IOCSET × R OCSET
ILIMIT =
RDS(ON) (LOW − Side)
Voltage (V)
For the over-current is never occurred in the normal operating load range; the variation of all parameters in the
VCC12
above equation should be determined.
- The MOSFET’s RDS(ON) is varied by temperature and gate
POR
to source voltage, the user should determine the maximum RDS(ON) in manufacturer’s datasheet.
- The minimum IOCSET (36µA) and minimum ROCSET should
be used in the above equation.
VOUT1
VOUT2
- Note that the ILIMIT is the current flow through the lower
MOSFET; ILIMIT must be greater than maximum output
current add the half of inductor ripple current.
t0
t1
t2
Time
Figure 1. Soft-Start Interval
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
13
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APW7068
Function Description (Cont.)
Over-Current Protection (Cont.)
When OCSET PIN is floating, the VOCSET will be pulled
high and the over current threshold will be the internal
default value 0.25V. When the voltage drop across the
lower MOSFET’s RDS(ON) is larger than 0.25V, an over-current condition is detected, the controller will shutdown
the IC directly, and latch the converter’s output.
Over Voltage Protection
The FB pin is monitored during converter operation by its
own Over Voltage(OV) comparator. If the FB voltage is
over 135% of the reference voltage, the controller will
make Low-Side gate signal fully turn on until the fault
events are removed.
Under Voltage Protection
The FBL pin is monitored during converter operation by
its own Under Voltage (UV) comparator. If the FBL voltage
drop below 50% of the reference voltage (50% of 0.8V =
0.4V), a fault signal is internally generated, and the device turns off both high-side and low-side MOSFET and
the converter’s output is latched to be floating. The controller will shutdown the IC directly.
Shutdown and Enable
Pulling low the FS_DIS pin near GND by an open drain
transistor or other pull-down device (<1k. impedance)
will shutdown both regulators. Upon release of the FS_DIS
pin, it will enable both outputs back into regulation. In
shutdown mode, the UGATE and LGATE turn off and pull
to PHASE and GND respectively.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
14
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APW7068
Application Information
Output Voltage Selection
Linear Regulator Compensation Selection
The output voltage of PWM converter can be programmed
with a resistive divider. Use 1% or better resistors for the
The linear regulator is stable over all loads current.
However, the transient response can be further enhanced
resistive divider is recommended. The FB pin is the
inverter input of the error amplifier, and the reference
by connecting a RC network between the FBL and DRIVE
pin. Depending on the output capacitance and load cur-
voltage is 0.8V. The output voltage is determined by:
rent of the application, the value of this RC network is
then varied.

R1 

VOUT1 = 0.8 × 1 +

 RGND1 
PWM Compensation
Where R1 is the resistor connected from VOUT1 to FB and
RGND1 is the resistor connected from FB to GND.
The output LC filter of a step down converter introduces a
double pole, which contributes with -40dB/decade gain
The linear regulator output voltage VOUT2 is also set by
means of an external resistor divider. The FBL pin is the
slope and 180 degrees phase shift in the control loop. A
compensation network among COMP, FB and V OUT1
inverter input of the error amplifier, and the reference voltage is 0.8V. The output voltage is determined by:
should be added. The compensation network is shown
in Figure 6. The output LC filter consists of the output

R4 

VOUT2 = 0.8 × 1 +

R
GND2 

inductor and output capacitors. The transfer function of
the LC filter is given by:
1 + s × ESR × COUT1
GAINLC = 2
s × L × COUT1 + s × ESR × COUT1 + 1
Where R4 is the resistor connected from VOUT2 to FBL
and RGND2 is the resistor connected from FBL to GND.
The poles and zero of this transfer functions are:
Linear Regulator Input/Output Capacitor Selection
FLC =
The input capacitor is chosen based on its voltage rating.
Under load transient condition, the input capacitor will
momentarily supply the required transient current. The
1
2 × π × L × COUT1
FESR =
output capacitor for the linear regulator is chosen to minimize any droop during load transient condition. In addition,
1
2 × π × ESR × COUT1
The FLC is the double poles of the LC filter, and FESR is the
zero introduced by the ESR of the output capacitor.
the capacitor is chosen based on its voltage rating.
VPHASE
Linear Regulator Input/Output MOSFET Selection
L
VOUT1
The maximum DRIVE voltage is about 10V when VCC12 is
equal 12V. Since this pin drives an external N-channel
MOSFET, therefore the maximum output voltage of the
COUT1
linear regulator is dependent upon the VGS.
ESR
VOUT2MAX = 10 - VGS
Another criterion is its efficiency of heat removal. The
Figure 3. The Output LC Filter
power dissipated by the MOSFET is given by:
PD = IOUT2 x (VIN2 – V OUT2)
Where IOUT2 is the maximum load current, VOUT2 is the
nominal output voltage.
In some applications, heatsink might be required to help
maintain the junction temperature of the MOSFET below
its maximum rating.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
15
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APW7068
Application Information (Cont.)
PWM Compensation (Cont.)
The poles and zeros of the transfer function are:
1
2 × π × R2 × C2
1
FZ2 =
2 × π × (R1 + R3) × C3
1
FP1 =
 C1× C2 
2 × π × R2 × 

 C1 + C2 
FZ1 =
FLC
GAIN (dB)
-40dB/dec
FP2 =
FESR
1
2 × π × R3 × C3
C1
-20dB/dec
R3
C3
R2
C2
VOUT1
R1
FB
VCOMP
Frequency(Hz)
VREF
Figure 4. The LC Filter GAIN and Frequency
Figure 6. Compensation Network
The PWM modulator is shown in Figure 5. The input is
the output of the error amplifier and the output is the
PHASE node. The transfer function of the PWM modula-
The closed loop gain of the converter can be written as:
tor is given by:
Figure 7. shows the asymptotic plot of the closed loop
converter gain, and the following guidelines will help to
GAINPWM =
VIN
∆VOSC
GAINLC X GAINPWM X GAINAMP
design the compensation network. Using the below
guidelines should give a compensation similar to the
VIN1
Driver
curve plotted. A stable closed loop has a -20dB/ decade
slope and a phase margin greater than 45 degree.
OSC
PWM
Comparator
ΔVOSC
PHASE
Output of
Error Amplifier
1. Choose a value for R1, usually between 1K and 5K.
2. Select the desired zero crossover frequency
FO: (1/5 ~ 1/10) X FS >FO>FESR
Use the following equation to calculate R2:
Driver
R2 =
Figure 5. The PWM Modulator
∆VOSC FO
×
× R1
VIN
FLC
The compensation network is shown in Figure 6. It pro-
3. Place the first zero FZ1 before the output LC filter double
vides a close loop transfer function with the highest zero
crossover frequency and sufficient phase margin.
pole frequency FLC.
The transfer function of error amplifier is given by:
Calculate the C2 by the equation:
GAINAMP =
VCOMP
VOUT1
FZ1 = 0.75 X FLC
1
2 × π × R2 × FLC × 0.75
4. Set the pole at the ESR zero frequency FESR:
1 
1 
// R2 +

sC1 
sC2 
=
1 

R1//  R3 +

sC3 

C2 =
FP1 = FESR

1
1

 

s +
 × s +
R2 × C2  
R1 + R3) × C3 
(
R1 + R3

=
×
R1× R3 × C1
C1 + C2  
1


s s +
 × s +

R2 × C1× C2  
R3 × C3 

Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
Calculate the C1 by the equation:
C2
C1 =
2 × π × R2 × C2 × FESR − 1
16
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APW7068
Application Information (Cont.)
PWM Compensation (Cont.)
where FS is the switching frequency of the regulator.
5. Set the second pole FP2 at the half of the switching
Although increase of the inductor value and frequency
reduces the ripple current and voltage, a tradeoff will ex-
frequency and also set the second zero FZ2 at the output
LC filter double pole FLC. The compensation gain should
ist between the inductor’s ripple current and the regulator load transient response time.
not exceed the error amplifier open loop gain, check the
compensation gain at FP2 with the capabilities of the error
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple current.
amplifier.
Increasing the switching frequency (FS) also reduces the
ripple current and voltage, but it will increase the switch-
FP2 = 0.5 X FS
FZ2 = FLC
ing loss of the MOSFET and the power dissipation of the
converter. The maximum ripple current occurs at the
Combine the two equations will get the following compo-
maximum input voltage. A good starting point is to choose
the ripple current to be approximately 30% of the maxi-
nent calculations:
R3 =
R1
FS
−1
2 × FLC
C3 =
1
π × R3 × FS
FZ1
FZ2
mum output current. Once the inductance value has been
chosen, select an inductor that is capable of carrying the
required peak current without going into saturation. In
some types of inductors, especially core that is made of
FP1
ferrite, the ripple current will increase abruptly when it
saturates. This will result in a larger output ripple voltage.
FP2
GAIN (dB)
Output Capacitor Selection
Higher capacitor value and lower ESR reduce the output
ripple and the load transient drop. Therefore, selecting
Compensation Gain
20log
(R2/R1)
20log
(VIN/ΔVOSC)
high performance low ESR capacitors is intended for
switching regulator applications. In some applications,
multiple capacitors have to be parallel to achieve the desired ESR value. A small decoupling capacitor in parallel
FLC
FESR
for bypassing the noise is also recommended, and the
voltage rating of the output capacitors also must be
Converter Gain
PWM & Filter
Gain
considered. If tantalum capacitors are used, make sure
they are surge tested by the manufactures. If in doubt,
Frequency(Hz)
consult the capacitors manufacturer.
Figure 7. Converter Gain and Frequency
Input Capacitor Selection
Output Inductor Selection
The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation,
The inductor value determines the inductor ripple current
and affects the load transient response. Higher inductor
value reduces the inductor’s ripple current and induces
select the capacitor voltage rating to be at least 1.3 times
higher than the maximum input voltage. The maximum
lower output ripple voltage. The ripple current and ripple
voltage can be approximated by:
IRIPPLE =
RMS current rating requirement is approximately IOUT1/2,
where IOUT1 is the load current. During power up, the input
VIN1 − VOUT1 VOUT1
×
FS × L
VIN1
capacitors have to handle large amount of surge current.
If tantalum capacitors are used, make sure they are surge
∆VOUT1 = IRIPPLE × ESR
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
tested by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a
17
www.anpec.com.tw
APW7068
Application Information (Cont.)
Input Capacitor Selection (Cont.)
combined using ground plane construction or single point
grounding. Figure 8. illustrates the layout, with bold lines
ceramic capacitor 1µF can be connected between the
drain of upper MOSFET and the source of lower MOSFET.
indicating high current paths; these traces must be short
and wide. Components along the bold lines should be
MOSFET Selection
placed lose together. Below is a checklist for your layout:
- The metal plate of the bottom of the packages (QFN-16)
The selection of the N-channel power MOSFETs are de-
must be soldered to the PCB and connected to the GND
plane on the backside through several thermal vias.
termined by the R DS(ON), reverse transfer capacitance (CRSS)
and maximum output current requirement. There are two
- Keep the switching nodes (UGATE, LGATE and PHASE)
away from sensitive small signal nodes since these
components of loss in the MOSFETs: conduction loss
and transition loss. For the upper and lower MOSFET,
nodes are fast moving signals. Therefore, keep traces
to these nodes as short as possible.
the losses are approximately given by the following:
2
PUPPER = IOUT1 (1+ TC)(RDS(ON))D + (0.5)( IOUT1)(VIN1)( tSW)
FS
- The traces from the gate drivers to the MOSFETs (UG,
LG, DRIVE) should be short and wide.
2
PLOWER = IOUT1 (1+ TC)(RDS(ON))(1-D)
- Place the source of the high-side MOSFET and the drain
of the low-side MOSFET as close as possible. Minimiz-
Where IOUT1 is the load current
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
ing the impedance with wide layout plane between the
two pads reduces the voltage bounce of the node.
tSW is the switching interval
D is the duty cycle
- Decoupling capacitor, compensation component, the
resistor dividers and boot capacitors should be close
Note that both MOSFETs have conduction loss while the
upper MOSFET include an additional transition loss. The
their pins. (For example, place the decoupling ceramic
capacitor near the drain of the high-side MOSFET as
switching internal, tSW, is a function of the reverse transfer
capacitance CRSS. The (1+TC) term is to factor in the
close as possible. The bulk capacitors are also placed
near the drain).
temperature dependency of the RDS(ON) and can be extracted
from the “RDS(ON) vs Temperature” curve of the power
- The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near the
MOSFET.
loads. The input capacitor GND should be close to the
output capacitor GND and the lower MOSFET GND.
Layout Consideration
- The drain of the MOSFETs (VIN1 and PHASE nodes)
should be a large plane for heat sinking.
In any high switching frequency converter, a correct layout is important to ensure proper operation of the
regulator. With power devices switching at 300kHz or
APW7068
VIN1
above, the resulting current transient will cause voltage
spike across the interconnecting impedance and para-
VCC12
VIN2
sitic circuit elements. As an example, consider the turnoff transition of the PWM MOSFET. Before turn-off, the
BOOT
MOSFET is carrying the full load current. During turn-off,
current stops flowing in the MOSFET and is free-wheel-
DRIVE
VOUT2
L
O
A
D
ing by the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage
FBL
L
O
A
D
UGATE
PHASE
LGATE
REF_OUT
VOUT1
spike during the switching interval. In general, using short,
wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. And
signal and power grounds are to be kept separate till
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
Figure 8. Layout Guidelines
18
www.anpec.com.tw
APW7068
Package Information
SOP-14
D
E
E1
SEE VIEW A
h X 45
°
e
c
0.25
A
GAUGE PLANE
SEATING PLANE
A1
A2
b
L
VIEW A
S
Y
M
B
O
L
SOP-14
INCHES
MILLIMETERS
MIN.
MAX.
A
MIN.
MAX.
1.75
0.069
0.010
0.004
0.25
A1
0.10
A2
1.25
b
0.31
0.51
0.012
0.020
c
0.17
0.25
0.007
0.010
D
8.55
8.75
0.337
0.344
5.80
6.20
0.228
0.244
3.80
4.00
0.150
0.157
0.020
0.050
E
E1
e
0.049
1.27 BSC
0.050 BSC
h
0.25
0.50
0.010
L
0.40
1.27
0.016
0
0°
8°
0°
8°
Note: 1. Follow JEDEC MS-012 AB.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
19
www.anpec.com.tw
APW7068
Package Information
SSOP-16
D
h X 45
E
E1
SEE VIEW A
c
A
0.25
b
A2
A1
GAUGE PLANE
SEATING PLANE
L
0
e
VIEW A
S
Y
M
B
O
L
SSOP-16
MILLIMETERS
MIN.
INCHES
MAX.
MIN.
MAX.
A
1.75
A1
0.10
0.25
0.069
A2
1.24
b
0.20
0.30
0.008
0.012
c
0.15
0.25
0.006
0.010
D
0.004
0.010
0.049
4.80
5.00
0.189
0.197
E
5.80
6.20
0.228
0.244
E1
3.80
4.00
0.150
0.157
e
0.635 BSC
0.025 BSC
L
0.40
1.27
0.016
0.050
h
0.25
0.50
0.010
0.020
0
0°
8°
0°
8°
Note : 1. Follow JEDEC MO-137 AB.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
20
www.anpec.com.tw
APW7068
Package Information
QFN4x4-16A
D
b
E
A
Pin 1
A1
D2
A3
L K
E2
Pin 1 Corner
e
S
Y
M
B
O
L
QFN4x4-16A
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.80
1.00
0.031
0.039
A1
0.00
0.05
0.000
0.002
0.35
0.010
0.014
A3
0.20 REF
0.008 REF
b
0.25
D
3.90
4.10
0.154
0.161
D2
2.10
2.50
0.083
0.098
E
3.90
4.10
0.154
0.161
E2
2.10
2.50
0.083
0.098
0.50
0.012
e
0.65 BSC
L
0.30
K
0.20
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
0.026 BSC
0.020
0.008
21
www.anpec.com.tw
APW7068
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
SOP-14
Application
SSOP-16
Application
QFN4x4-16
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
16.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
16.0±0.30
1.75±0.10
7.50±0.10
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±0.10
8.0±0.10
2.0±0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
9.00±0.20
2.10±0.20
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.50±0.10
P0
P1
P2
D0
D1
T
A0
B0
K0
2.00±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
5.20±0.20
2.10±0.20
4.00±0.10
8.00±0.10
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
4.30±0.20
4.30±0.20
1.30±0.20
4.0±0.10
8.0±0.10
(mm)
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
22
www.anpec.com.tw
APW7068
Devices Per Unit
Package Type
SOP- 14
SSOP- 16
QFN4x4-16
Unit
Tape & Reel
Tape & Reel
Tape & Reel
Quantity
2500
2500
3000
Taping Direction Information
SOP-14
USER DIRECTION OF FEED
SSOP-16
USER DIRECTION OF FEED
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
23
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APW7068
Taping Direction Information
QFN4x4-16A
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
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APW7068
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
25
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APW7068
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2009
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