1999.1.15 MITSUBISHI LSIs Ver. 0.1 M5M5W816WG -85L, 10L, 85H, 10H -85LI, 10LI, 85HI, 10HI PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM Those are summarized in the part name table below. DESCRIPTION FEATURES The M5M5W816 is a family of low voltage 8-Mbit static RAMs organized as 524288-words by 16-bit, fabricated by Mitsubishi's high-performance 0.18µm CMOS technology. The M5M5W816 is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. M5M5W816WG is packaged in a CSP (chip scale package), with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48ball) and ball pitch of 0.75mm. It gives the best solution for a compaction of mounting area as well as flexibility of wiring pattern of printed circuit boards. From the point of operating temperature, the family is divided into two versions; "Standard" and "I-version". Version, Power Supply Part name Operating temperature M5M5W816WG -85L Standard M5M5W816WG -10L 0 ~ +70°C M5M5W816WG -85H -40 ~ +85°C M5M5W816WG -85HI 85ns 100ns 85ns 100ns 85ns 100ns 85ns 100ns 1.8 ~ 2.7V M5M5W816WG -85LI M5M5W816WG -10LI max. 1.8 ~ 2.7V M5M5W816WG -10H I-version Access time 1.8 ~ 2.7V 1.8 ~ 2.7V M5M5W816WG -10HI - Single 1.8~2.7V power supply - Small stand-by current: 0.1µA (2.7V, typ.) - No clocks, No refresh - Data retention supply voltage =1.0V - All inputs and outputs are TTL compatible. - Easy memory expansion by S1, S2, BC1 and BC2 - Common Data I/O - Three-state outputs: OR-tie capability - OE prevents data contention in the I/O bus - Process technology: 0.18µm CMOS - Package: 48ball 7.0mm x 8.5mm CSP Stand-by current (Vcc=2.7V) Ratings (max.) * Typical 25°C 40°C 25°C 40°C 70°C 85°C 0.1 0.2 --- --- 16 --- 0.1 0.2 1 2 8 --- 0.1 0.2 --- --- 16 30 0.1 0.2 1 2 8 15 Active current Icc1 (2.7V, typ.) 40mA (10MHz) 5mA (1MHz) * Typical parameter indicates the value for the center of distribution, and not 100% tested. PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 BC1 OE A0 A1 A2 S2 DQ9 BC2 A3 A4 S1 DQ1 C DQ10 DQ11 A5 A6 DQ2 DQ3 D GND DQ12 A17 A7 DQ4 VCC E VCC DQ13 GND A16 DQ5 F DQ15 DQ14 A14 A15 G DQ16 N.C. A12 H A18 A8 A9 A B Pin Function A0 ~ A18 Address input DQ1 ~ DQ16 Data input / output Chip select input 1 GND S1 S2 DQ7 W OE Write control input DQ6 A13 W DQ8 A10 A11 N.C. Chip select input 2 Output enable input BC1 Lower Byte (DQ1 ~ 8) BC2 Upper Byte (DQ9 ~ 16) Vcc Power supply GND Ground supply Outline: 48FHA NC: No Connection MITSUBISHI ELECTRIC 1 1999.1.15 MITSUBISHI LSIs Ver. 0.1 M5M5W816WG -85L, 10L, 85H, 10H -85LI, 10LI, 85HI, 10HI PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM FUNCTION The M5M5W816WG is organized as 524288-words by 16bit. These devices operate on a single +1.8~2.7V power supply, and are directly TTL compatible to both input and output. Its fully static circuit needs no clocks and no refresh, and makes it useful. The operation mode are determined by a combination of the device control inputs BC1 , BC2 , S1, S2 , W and OE. Each mode is summarized in the function table. A write operation is executed whenever the low level W overlaps with the low level BC1 and/or BC2 and the low level S1 and the high level S2. The address(A0~A18) must be set up before the write cycle and must be stable during the entire cycle. A read operation is executed by setting W at a high level and OE at a low level while BC1 and/or BC2 and S1 and S2 are in an active state(S1=L,S2=H). When setting BC1 at the high level and other pins are in an active stage , upper-byte are in a selectable mode in which both reading and writing are enabled, and lower-byte are in a non-selectable mode. And when setting BC2 at a high level and other pins are in an active stage, lower-byte are in a selectable mode and upper-byte are in a non-selectable mode. When setting BC1 and BC2 at a high level or S1 at a high level or S2 at a low level, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and S1, S2. The power supply current is reduced as low as 0.1µA(25°C, typical), and the memory data can be held at +1V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode. FUNCTION TABLE BLOCK DIAGRAM S1 H L H X L L L L L L L L L S2 BC1 BC2 L X X L X X H X X X H H H L H H L H H L H H H L H H L H H L H L L H L L H L L W OE X X X X X X X X L X H L H H L X H L H H L X H L H H A0 Mode Non selection Non selection Non selection Non selection Write Read Write Read Write Read DQ1~8 DQ9~16 High-Z High-Z High-Z High-Z Din Dout High-Z High-Z High-Z High-Z Din Dout High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Din Dout High-Z Din Dout High-Z Icc Standby Standby Standby Standby Active Active Active Active Active Active Active Active Active DQ 1 A1 MEMORY ARRAY DQ 8 524288 WORDS x 16 BITS A17 - DQ 9 A18 S1 CLOCK GENERATOR DQ 16 S2 BC1 Vcc BC2 W GND OE MITSUBISHI ELECTRIC 2 1999.1.15 MITSUBISHI LSIs Ver. 0.1 M5M5W816WG -85L, 10L, 85H, 10H -85LI, 10LI, 85HI, 10HI PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI VO Pd Ta Tstg Parameter Conditions Units Ratings Supply voltage Input voltage With respect to GND Output voltage With respect to GND -0.5* ~ +4.6 -0.2* ~ Vcc + 0.2 (max. 4.6V) 0 ~ Vcc 700 0 ~ +70 - 40 ~ +85 With respect to GND Power dissipation Ta=25∞C Operating temperature Standard (-L, -H) I-version (-LI, -HI) Storage temperature V mW °C - 65 ~ +150 °C * -3.0V in case of AC (Pulse width < = 30ns) DC ELECTRICAL CHARACTERISTICS Symbol Parameter VIH VIL VOH VOL II IO High-level input voltage ( Vcc=1.8 ~ 2.7V, unless otherwise noted) Limits Conditions Min Low-level input voltage High-level output voltage Low-level output voltage Input leakage current Output leakage current IOH= -0.1mA IOL=0.1mA VI =0 ~ Vcc BC1 and BC2< = 0.2V, S1< = 0.2V, S2 Vcc-0.2V > other inputs < = 0.2V or = Vcc-0.2V Output - open (duty 100%) f= 10MHz Active supply current Icc2 ( AC,TTL level ) BC1 and BC2=VIL , S=VIL ,S2=VIH other pins =VIH or VIL Output - open (duty 100%) f= 10MHz other inputs = 0 ~ Vcc Icc3 Stand by supply current ( AC,MOS level ) -H, -HI (2) S2 => 0.2V, -0.2 * 1.6 0.4 - 40 5 40 5 0.1 0.2 - 0.2 ±1 ±1 50 10 50 10 1 2 8 15 16 30 (3) BC1 and BC2 => Vcc - 0.2V - - 0.5 - f= 1MHz - ~ +40°C ~ +70°C other inputs = 0 ~ Vcc >Vcc - 0.2V S1 < = 0.2V, S2 = other inputs = 0 ~ Vcc -HI -L, -LI -LI Stand by supply current Icc4 ( AC,TTL level ) Vcc+0.2V f= 1MHz ~ +25°C (1) S1 => Vcc - 0.2V, Max 0.7 x Vcc BC1 and BC2=VIHor S1=VIHor S2=VIL or OE=VIH, VI/O=0 ~ Vcc Icc1 Active supply current ( AC,MOS level ) Typ ~ +85°C ~ +70°C ~ +85°C BC1 and BC2=VIH or S1=VIH or S2=VIL Other inputs= 0 ~ Vcc Units V µA mA µA mA < 30ns) Note 1: Direction for current flowing into IC is indicated as positive (no mark) * -1.0V in case of AC (Pulse width = Note 2: Typical parameter indicates the value for the center of distribution at 2.7V, and not 100% tested. CAPACITANCE Symbol CI CO Parameter (Vcc=1.8 ~ 2.7V, unless otherwise noted) Conditions Min Input capacitance VI=GND, VI=25mVrms, f=1MHz Output capacitance VO=GND,VO=25mVrms, f=1MHz MITSUBISHI ELECTRIC Limits Typ Max 10 10 Units pF 3 1999.1.15 MITSUBISHI LSIs Ver. 0.1 M5M5W816WG -85L, 10L, 85H, 10H -85LI, 10LI, 85HI, 10HI PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS Supply voltage Input pulse Input rise time and fall time Reference level (Vcc=1.8 ~ 2.7V, unless otherwise noted) 1TTL 1.8~2.7V VIH=0.7 x Vcc, VIL=0.2V 5ns VOH=VOL=0.9V DQ CL Transition is measured ±200mV from steady state voltage.(for ten,tdis) Including scope and jig capacitance Fig.1,CL=30pF CL=5pF (for ten,tdis) Output loads Fig.1 Output load (2) READ CYCLE Limits Parameter Symbol tCR ta(A) ta(S1) ta(S2) ta(BC1) ta(BC2) ta(OE) tdis(S1) tdis(S2) tdis(BC1) tdis(BC2) tdis(OE) ten(S1) ten(S2) tdis(BC1) tdis(BC2) ten(OE) tV(A) 85L, 85H, 85LI, 85HI Read cycle time Address access time Chip select 1 access time Chip select 2 access time Byte control 1 access time Byte control 2 access time Output enable access time Output disable time after S1 high Output disable time after S2 low Output disable time after BC1 high Output disable time after BC2 high Output disable time after OE high Output enable time after S1 low Output enable time after S2 high Output enable time after BC1 low Output enable time after BC2 low Output enable time after OE low Data valid time after address Min 85 10L, 10H, 10LI, 10HI Max Min 100 85 85 85 85 85 45 30 30 30 30 30 100 100 100 100 100 50 35 35 35 35 35 10 10 10 10 5 10 Units Max 10 10 10 10 5 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Limits Symbol tCW tw(W) tsu(A) tsu(A-WH) tsu(BC1) tsu(BC2) tsu(S1) tsu(S2) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) 85L, 85H, 85LI, 85HI Parameter Write cycle time Write pulse width Address setup time Address setup time with respect to W Byte control 1 setup time Byte control 2 setup time Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recovery time Output disable time from W low Output disable time from OE high Output enable time from W high Output enable time from OE low Min 85 60 0 70 70 70 70 70 45 0 0 10L, 10H, 10LI, 10HI Max Min 100 75 0 85 85 85 85 85 50 0 0 30 30 35 35 5 5 5 5 MITSUBISHI ELECTRIC Units Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 1999.1.15 MITSUBISHI LSIs Ver. 0.1 M5M5W816WG -85L, 10L, 85H, 10H -85LI, 10LI, 85HI, 10HI PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle tCR A0~18 tv (A) ta(A) ta(BC1) or ta(BC2) BC1,BC2 (Note3) tdis (BC1) or tdis (BC1) (Note3) ta(S1) S1 (Note3) tdis (S1) (Note3) tdis (S2) (Note3) ta(S2) S2 (Note3) ta (OE) OE (Note3) ten (OE) W = "H" level DQ1~16 Write cycle ( W control mode ) tdis (OE) ten (BC1) ten (BC2) ten (S1) ten (S2) (Note3) VALID DATA tCW A0~18 tsu (BC1) or tsu(BC2) BC1,BC2 (Note3) (Note3) tsu (S1) S1 (Note3) (Note3) S2 tsu (S2) (Note3) (Note3) OE tsu (A) tsu (A-WH) tw (W) trec (W) tdis (W) W ten(OE) ten (W) tdis(OE) DQ1~16 DATA IN STABLE tsu (D) th (D) MITSUBISHI ELECTRIC 5 1999.1.15 MITSUBISHI LSIs Ver. 0.1 M5M5W816WG -85L, 10L, 85H, 10H -85LI, 10LI, 85HI, 10HI PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM Write cycle (BC control mode) tCW A0~18 tsu (A) tsu (BC1) or tsu (BC2) trec (W) BC1,BC2 S1 (Note3) (Note3) S2 (Note3) W (Note3) (Note5) (Note4) (Note3) (Note3) tsu (D) DQ1~16 th (D) DATA IN STABLE Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S1 low, S2 high overlaps BC1 and/or BC2 low and W low. Note 5: When the falling edge of W is simultaneously or prior to the falling edge of BC1 and/or BC2 or the falling edge of S1 or rising edge of S2, the outputs are maintained in the high impedance state. Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode. MITSUBISHI ELECTRIC 6 1999.1.15 MITSUBISHI LSIs Ver. 0.1 M5M5W816WG -85L, 10L, 85H, 10H -85LI, 10LI, 85HI, 10HI PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM Write cycle (S1 control mode) tCW A0~18 BC1,BC2 (Note3) tsu (S1) tsu (A) trec (W) (Note3) S1 S2 (Note3) (Note3) (Note5) W (Note4) (Note3) tsu (D) DQ1~16 th (D) (Note3) DATA IN STABLE Write cycle (S2 control mode) tCW A0~18 BC1,BC2 (Note3) tsu (A) tsu (S2) trec (W) (Note3) S1 S2 (Note3) (Note3) (Note5) W (Note4) (Note3) DQ1~16 tsu (D) th (D) (Note3) DATA IN STABLE MITSUBISHI ELECTRIC 7 1999.1.15 MITSUBISHI LSIs Ver. 0.1 M5M5W816WG -85L, 10L, 85H, 10H -85LI, 10LI, 85HI, 10HI PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Parameter Test conditions Min Vcc (PD) Power down supply voltage VI (BC) VI (S1) VI (S2) Byte control input BC1 & BC2 Chip select input S1 1.8V Vcc(PD) 1.0V Vcc(PD) 1.8V 1.8V Vcc(PD) 1.0V Vcc(PD) 1.8V 0.7xVcc V Vcc(PD) 0.7xVcc V Vcc(PD) (1) S1 => Vcc - 0.2V, -H, -HI other inputs = 0 ~ Vcc other inputs = 0 ~ Vcc -HI -L, -LI -LI (3) BC1 and BC2 => Vcc - 0.2V > Vcc - 0.2V S1 < = 0.2V, S2 = other inputs = 0 ~ Vcc - ~ +25°C ~ +40°C ~ +70°C ~ +85°C ~ +70°C ~ +85°C (2) S2 => 0.2V, 0.02 0.05 - 0.2 0.5 1 4 7.5 8 15 Limits Parameter tsu (PD) trec (PD) Power down set up time Power down recovery time µA Note 2: Typical parameter of Icc(PD) indicates the value for the center of distribution at 1.0V, and not 100% tested. (2) TIMING REQUIREMENTS Symbol Units V Chip select input S2 Power down supply current Max 1.0 Vcc=1.0V Icc (PD) Limits Typ Test conditions Min Typ Max 0 5 Units ns ms (3) TIMING DIAGRAM BC control mode Vcc tsu (PD) 1.8V 1.8V trec (PD) 0.7 x Vcc 0.7 x Vcc BC1 BC2 BC1 , BC2 > =Vcc-0.2V S1 control mode Vcc tsu (PD) 1.8V 1.8V trec (PD) 0.7 x Vcc 0.7 x Vcc S1 > = Vcc-0.2V S1 S2 control mode Vcc S2 Vcc-0.2V tsu (PD) 1.8V 1.8V trec (PD) 0.7 x Vcc S2 0.2V MITSUBISHI ELECTRIC 8