LINER LT3023 Dual 100ma, low dropout, low noise, micropower regulator Datasheet

LT3023
Dual 100mA,
Low Dropout, Low Noise,
Micropower Regulator
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FEATURES
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DESCRIPTIO
Low Noise: 20µVRMS (10Hz to 100kHz)
Low Quiescent Current: 20µA/Channel
Wide Input Voltage Range: 1.8V to 20V
Output Current: 100mA/Channel
Very Low Shutdown Current: <0.1µA
Low Dropout Voltage: 300mV at 100mA
Adjustable Output from 1.22V to 20V
Stable with 1µF Output Capacitor
Stable with Aluminum, Tantalum or
Ceramic Capacitors
Reverse Battery Protected
No Reverse Current
No Protection Diodes Needed
Overcurrent and Overtemperature Protected
Thermally Enhanced 10-Lead MSOP and DFN
Packages
The LT ®3023 is a dual, micropower, low noise, low dropout regulator. With an external 0.01µF bypass capacitor,
output noise drops to 20µVRMS over a 10Hz to 100kHz
bandwidth. Designed for use in battery-powered systems,
the low 20µA quiescent current per channel makes it an
ideal choice. In shutdown, quiescent current drops to less
than 0.1µA. Shutdown control is independent for each
channel, allowing for flexibility in power management. The
device is capable of operating over an input voltage from
1.8V to 20V, and can supply 100mA of output current from
each channel with a dropout voltage of 300mV. Quiescent
current is well controlled in dropout.
The LT3023 regulator is stable with output capacitors as
low as 1µF. Small ceramic capacitors can be used without
the series resistance required by other regulators.
Internal protection circuitry includes reverse battery protection, current limiting, thermal limiting and reverse
current protection. The device is available as an adjustable
device with a 1.22V reference voltage. The LT3023 regulator is available in the thermally enhanced 10-lead MSOP
and DFN packages.
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APPLICATIO S
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Cellular Phones
Pagers
Battery-Powered Systems
Frequency Synthesizers
Wireless Modems
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
3.3V/2.5V Low Noise Regulators
10Hz to 100kHz Output Noise
VIN
3.7V TO
20V
IN
1µF
3.3V AT100mA
20µVRMS NOISE
OUT1
0.01µF
SHDN1
SHDN2
422k
10µF
BYP1
ADJ1
249k
LT3023
OUT2
0.01µF
261k
VOUT
100µV/DIV
20µVRMS
2.5V AT100mA
20µVRMS NOISE
10µF
BYP2
ADJ2
GND
3023 TA01b
249k
3023 TA01
3023f
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LT3023
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AXI U
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ABSOLUTE
RATI GS
(Note 1)
IN Pin Voltage ........................................................ ±20V
OUT1, OUT2 Pin Voltage ....................................... ±20V
Input to Output Differential Voltage ....................... ±20V
ADJ1, ADJ2 Pin Voltage ......................................... ±7V
BYP1, BYP2 Pin Voltage ....................................... ±0.6V
SHDN1, SHDN2 Pin Voltage ................................. ±20V
Output Short-Circut Duration .......................... Indefinite
Operating Junction Temperature Range
(Note 2) ............................................ – 40°C to 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
BYP2
1
10 OUT2
ADJ2
2
9 SHDN2
11
GND
3
ADJ1
4
7 SHDN1
BYP1
5
6 OUT1
LT3023EDD
8 IN
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 40°C/ W, θJC = 10°C/ W
DD PART
MARKING
LAJA
ORDER PART
NUMBER
TOP VIEW
BYP2
ADJ2
GND
ADJ1
BYP1
1
2
3
4
5
11
10
9
8
7
6
OUT2
SHDN2
IN
SHDN1
OUT1
LT3023EMSE
MSE PART
MARKING
MSE PACKAGE
10-LEAD PLASTIC MSOP
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
TJMAX = 150°C, θJA = 40°C/ W, θJC = 10°C/ W
LTAHZ
Consult factory for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
Minimum Input Voltage
(Notes 3, 11)
ILOAD = 100mA
●
MIN
ADJ1, ADJ2 Pin Voltage
(Note 3, 4)
VIN = 2V, ILOAD = 1mA
2.3V < VIN < 20V, 1mA < ILOAD < 100mA
●
Line Regulation (Note 3)
∆VIN = 2V to 20V, ILOAD = 1mA
●
Load Regulation (Note 3)
VIN = 2.3V, ∆ILOAD = 1mA to 100mA
VIN = 2.3V, ∆ILOAD = 1mA to 100mA
●
Dropout Voltage
VIN = VOUT(NOMINAL)
ILOAD = 1mA
ILOAD = 1mA
●
(Notes 5, 6, 11)
ILOAD = 10mA
ILOAD = 10mA
●
ILOAD = 50mA
ILOAD = 50mA
●
ILOAD = 100mA
ILOAD = 100mA
●
1.205
1.190
TYP
MAX
UNITS
1.8
2.3
V
1.220
1.220
1.235
1.250
V
V
1
10
mV
1
12
25
mV
mV
0.10
0.15
0.19
V
V
0.17
0.22
0.29
V
V
0.24
0.28
0.38
V
V
0.30
0.35
0.45
V
V
3023f
2
LT3023
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
MIN
GND Pin Current (Per Channel)
VIN = VOUT(NOMINAL)
(Notes 5, 7)
ILOAD = 0mA
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 50mA
ILOAD = 100mA
Output Voltage Noise
COUT = 10µF, CBYP = 0.01µF, ILOAD = 100mA, BW = 10Hz to 100kHz
●
●
●
●
●
(Notes 3, 8)
Shutdown Threshold
VOUT = Off to On
VOUT = On to Off
●
●
SHDN1/SHDN2 Pin Current
(Note 9)
VSHDN = 0V
VSHDN = 20V
●
●
Quiescent Current in Shutdown
VIN = 6V, VSHDN = 0V (Both SHDN Pins)
Ripple Rejection (Note 3)
VIN = 2.72V (Avg), VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz,
ILOAD = 50mA
Current Limit
VIN = 7V, VOUT = 0V
VIN = 2.3V, ∆VOUT = – 5%
●
VIN = – 20V, VOUT = 0V
●
Reverse Output Current (Notes 3,10) VOUT = 1.22V, VIN < 1.22V
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT3023 regulator is tested and specified under pulse load
conditions such that TJ ≈ TA. The LT3023 is 100% production tested at
TA = 25°C. Performance at – 40°C and 125°C is assured by design,
characterization and correlation with statistical process controls.
Note 3: The LT3023 is tested and specified for these conditions with the
ADJ1/ADJ2 pin connected to the corresponding OUT1/OUT2 pin.
Note 4: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification will not apply for
all possible combinations of input voltage and output current. When
operating at maximum input voltage, the output current range must be
limited. When operating at maximum output current, the input voltage
range must be limited.
Note 5: To satisfy requirements for minimum input voltage, the LT3023 is
tested and specified for these conditions with an external resistor divider
(two 250k resistors) for an output voltage of 2.44V. The external resistor
divider will add a 5µA DC load on the output.
MAX
UNITS
20
55
230
1
2.2
45
100
400
2
4
µA
µA
µA
mA
mA
µVRMS
20
ADJ1/ADJ2 Pin Bias Current
Input Reverse Leakage Current
TYP
0.25
55
30
100
nA
0.8
0.65
1.4
V
V
0
1
0.5
3
µA
µA
0.01
0.1
µA
65
dB
200
mA
mA
110
5
1
mA
10
µA
Note 6: Dropout voltage is the minimum input to output voltage differential
needed to maintain regulation at a specified output current. In dropout, the
output voltage will be equal to: VIN – VDROPOUT.
Note 7: GND pin current is tested with VIN = 2.44V and a current source
load. This means the device is tested while operating in its dropout region
or at the minimum input voltage specification. This is the worst-case GND
pin current. The GND pin current will decrease slightly at higher input
voltages.
Note 8: ADJ1 and ADJ2 pin bias current flows into the pin.
Note 9: SHDN1 and SHDN2 pin current flows into the pin.
Note 10: Reverse output current is tested with the IN pin grounded and the
OUT pin forced to the rated output voltage. This current flows into the OUT
pin and out the GND pin.
Note 11: For the LT3023 dropout voltage will be limited by the minimum
input voltage specification under some output voltage/load conditions. See
the curve of Minimum Input Voltage in the Typical Performance
Characteristics.
3023f
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LT3023
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TYPICAL PERFOR A CE CHARACTERISTICS
500
450
450
400
400
TJ = 125°C
300
250
TJ = 25°C
200
150
500
= TEST POINTS
450
DROPOUT VOLTAGE (mV)
500
350
Dropout Voltage
Guaranteed Dropout Voltage
DROPOUT VOLTAGE (mV)
DROPOUT VOLTAGE (mV)
Typical Dropout Voltage
TJ ≤ 125°C
350
300
TJ ≤ 25°C
250
200
150
250
150
50
50
50
10 20 30 40 50 60 70 80 90 100
OUTPUT CURRENT (mA)
3023 G01
VIN = 6V
RL = 250k
IL = 5µA
15
1.230
1.225
1.220
1.215
10
1.210
5
1.205
VSHDN = 0V
0
–50 –25
0
25
50
75
100
125
1.200
–50 –25
25
50
75
100
0
125
RL = 24.4Ω
IL = 50mA*
0.75
0.25
0.9
2.00
SHDN PIN THRESHOLD (V)
GND PIN CURRENT (mA)
1.50
1.75
1.50
1.25
1.00
0.75
0.50
RL = 122Ω
IL = 10mA*
0.25
0
1
2
3 4 5 6 7
INPUT VOLTAGE (V)
8
9
10
3023 G07
IL = 1mA
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)
1.0
VIN = VOUT(NOMINAL) + 1V
2.25
RL = 12.2Ω
IL = 100mA*
RL = 1.22k
IL = 1mA*
4
SHDN1 or SHDN2 Pin Threshold
(On-to-Off)
2.50
0.50
2
3023 G06
GND Pin Current vs ILOAD
TJ = 25°C
*FOR VOUT = 1.22V
1.00
0
3023 G05
2.50
1.25
10
TEMPERATURE (°C)
GND Pin Current
1.75
15
VSHDN = 0V
0
3023 G03
2.00
VSHDN = VIN
20
5
TEMPERATURE (°C)
2.25
TJ = 25°C
RL = 250k
IL = 5µA
25
QUIESCENT CURRENT (µA)
ADJ PIN VOLTAGE (V)
VSHDN = VIN
125
Quiescent Current
IL = 1mA
1.235
20
100
30
1.240
25
50
25
0
75
TEMPERATURE (°C)
3023 G03
ADJ1 or ADJ2 Pin Voltage
Quiescent Current
30
IL = 1mA
3023 G02
40
35
IL = 10mA
0
–50 –25
0
0
IL = 50mA
200
100
10 20 30 40 50 60 70 80 90 100
OUTPUT CURRENT (mA)
IL = 100mA
300
100
0
QUIESCENT CURRENT (µA)
350
100
0
GND PIN CURRENT (mA)
400
0
10 20 30 40 50 60 70 80 90 100
OUTPUT CURRENT (mA)
3023 G08
0
–50 –25
50
0
75
25
TEMPERATURE (°C)
100
125
3023 G09
3023f
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LT3023
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TYPICAL PERFOR A CE CHARACTERISTICS
0.9
IL = 100mA
0.7
0.6
IL = 1mA
0.5
0.4
0.3
0.2
0.1
1.4
VSHDN = 20V
SHDN PIN INPUT CURRENT (µA)
1.0
0.9
SHDN PIN INPUT CURRENT (µA)
SHDN PIN THRESHOLD (V)
1.0
0.8
SHDN1 or SHDN2 Pin Input
Current
SHDN1 or SHDN2 Pin Input
Current
SHDN1 or SHDN2 Pin Threshold
(Off-to-On)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–50 –25
50
0
75
25
TEMPERATURE (°C)
100
0
1
2
3 4 5 6 7 8
SHDN PIN VOLTAGE (V)
9
3023 G10
80
70
60
50
40
30
20
10
250
200
150
100
50
150
100
1
4
3
2
5
INPUT VOLTAGE (V)
0
–50 –25
7
6
40
30
20
15
Input Ripple Rejection
VIN = 0V
VOUT = VADJ = 1.22V
70
12
9
6
3
10
0
9
10
3023 G16
0
–50 –25
50
25
75
0
TEMPERATURE (°C)
125
100
80
RIPPLE REJECTION (dB)
REVERSE OUTPUT CURRENT (µA)
50
50
25
0
75
TEMPERATURE (°C)
3023 G15
Reverse Output Current
60
3 4 5 6 7 8
OUTPUT VOLTAGE (V)
200
3023 G14
18
2
250
50
0
Reverse Output Current
125
100
VIN = 7V
VOUT = 0V
300
0
TA = 25°C
90 VIN = 0V
= VADJ
V
80 OUT
CURRENT FLOWS
70 INTO OUTPUT PIN
50
25
0
75
TEMPERATURE (°C)
Current Limit
VOUT = 0V
TJ = 25°C
300
125
100
1
0.2
350
3023 G13
0
0.4
3023 G12
CURRENT LIMIT (mA)
SHORT-CIRCUIT CURRENT (mA)
ADJ PIN BIAS CURRENT (nA)
90
REVERSE OUTPUT CURRENT (µA)
10
350
100
0.6
Current Limit
100
50
0
75
25
TEMPERATURE (°C)
0.8
3023 G11
ADJ1 or ADJ2 Pin Bias Current
0
–50 –25
1.0
0
–50 –25
0
125
1.2
100
125
3023 G17
60
50
40
COUT = 10µF
30
20
I = 100mA
10 VL = 2.3V + 50mV
IN
RMS RIPPLE COUT = 1µF
CBYP = 0
0
0.1
100
0.01
1
10
1000
FREQUENCY (kHz)
LTXXXX GXX
3023f
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LT3023
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TYPICAL PERFOR A CE CHARACTERISTICS
Input Ripple Rejection
Input Ripple Rejection
80
70
60
CBYP = 1000pF
50
CBYP = 100pF
40
30
20
I = 100mA
10 VL = 2.3V + 50mV
IN
RMS RIPPLE
COUT = 10µF
0
0.1
0.01
1
10
FREQUENCY (kHz)
RIPPLE REJECTION (dB)
CBYP = 0.01µF
70
50
40
VOUT2
20mV/DIV
30
20
10
100
VOUT1
20mV/DIV
60
VIN = VOUT (NOMINAL) +
1V + 0.5VP-P RIPPLE
AT f = 120Hz
IL = 50mA
0
–50 –25
1000
0
25
50
75
100
3023 G20
Minimum Input Voltage
Channel-to-Channel Isolation
–1
80
70
60
50
40
30
20
–2
2.0
LOAD REGULATION (mV)
MINIMUM INPUT VOLTAGE (V)
CHANNEL-TO-CHANNEL ISOLATION (dB)
Load Regulation
0
2.5
ILOAD = 100mA PER CHANNEL
90
IL = 100mA
1.5
IL = 50mA
1.0
0.1
1
10
FREQUENCY (kHz)
100
0
–50 –25
1000
50
0
75
25
TEMPERATURE (°C)
100
3023 G21b
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
VOUT SET FOR 5V
VOUT =VADJ
0.1
0.01
0.01
0.1
1
10
FREQUENCY (kHz)
–5
–6
–7
–9
∆IL = 1mA TO 100mA
–10
0
50
75
25
–50 –25
TEMPERATURE (°C)
125
100
3023 G24
10
125
RMS Output Noise vs
Bypass Capacitor
160
COUT = 10µF
IL = 100mA
COUT = 10µF
IL = 100mA
f = 10Hz TO 100kHz
140
VOUT SET FOR 5V
100
3023 G23
Output Noise Spectral Density
COUT = 10µF
CBYP = 0
IL = 100mA
1
–4
3023 G22
Output Noise Spectral Density
10
–3
–8
0.5
10
0
0.01
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
125
TEMPERATURE (°C)
3023 G19
100
3023 G21a
50µs/DIV
COUT1, COUT2 = 10µF
CBYP1, CBYP2 = 0.01µF
∆IL1 = 10mA to 100mA
∆IL2 = 10mA to 100mA
VIN = 6V, VOUT1 = VOUT2 = 5V
OUTPUT NOISE (µVRMS)
RIPPLE REJECTION (dB)
Channel-to-Channel Isolation
80
CBYP = 1000pF
1
CBYP = 100pF
VOUT =VADJ
0.1
CBYP = 0.01pF
120
VOUT SET FOR 5V
100
80
60
40
VOUT =VADJ
20
0.01
0.01
0
0.1
1
10
FREQUENCY (kHz)
100
10
100
1k
10k
CBYP (pF)
3023 G25
3023 G26
3023f
6
LT3023
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TYPICAL PERFOR A CE CHARACTERISTICS
RMS Output Noise vs
Load Current (10Hz to 100kHz)
160
COUT = 10µF
CBYP = 0µF
CBYP = 0.01µF
120
VOUT SET FOR 5V
VOUT
100µV/DIV
VOUT
100µV/DIV
100
80
VOUT =VADJ
60
40
VOUT SET FOR 5V
20
0.1
1
10
LOAD CURRENT (mA)
3023 G28
1ms/DIV
COUT = 10µF
IL = 100mA
VOUT SET FOR 5V OUT
VOUT =VADJ
100
1ms/DIV
COUT = 10µF
IL = 100mA
VOUT SET FOR 5V OUT
3023 G29
3023 G27
10Hz to 100kHz Output Noise
CBYP = 1000pF
10Hz to 100kHz Output Noise
CBYP = 0.01µF
VOUT
100µV/DIV
VOUT
100µV/DIV
3023 G30
1ms/DIV
COUT = 10µF
IL = 100mA
VOUT SET FOR 5V OUT
1ms/DIV
COUT = 10µF
IL = 100mA
VOUT SET FOR 5V OUT
OUTPUT VOLTAGE
DEVIATION (V)
0.2
0.1
0
–0.1
100
LOAD CURRENT
(mA)
VIN = 6V
CIN = 10µF
COUT = 10µF
VOUT SET FOR 5V OUT
–0.2
50
0
0
400
800
1200
TIME (µs)
3023 G31
Transient Response
CBYP = 0.01µF
Transient Response
CBYP = 0
OUTPUT VOLTAGE
DEVIATION (V)
0
0.01
LOAD CURRENT
(mA)
OUTPUT NOISE (µVRMS)
140
10Hz to 100kHz Output Noise
CBYP = 100pF
10Hz to 100kHz Output Noise
CBYP = 0
1600
2000
3023 G32
0.04
0.02
0
–0.02
VIN = 6V
CIN = 10µF
COUT = 10µF
VOUT SET FOR 5V OUT
–0.04
100
50
0
0
20 40 60 80 100 120 140 160 180 200
TIME (µs)
3023 G33
3023f
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LT3023
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PI FU CTIO S
GND (Pin 3): Ground.
ADJ1/ADJ2 (Pins 4/2): Adjust Pin. These are the inputs to
the error amplifiers. These pins are internally clamped to
±7V. They have a bias current of 30nA which flows into the
pin (see curve of ADJ1/ADJ2 Pin Bias Current vs Temperature in the Typical Performance Characteristics section).
The ADJ1 and ADJ2 pin voltage is 1.22V referenced to
ground and the output voltage range is 1.22V to 20V.
BYP1/BYP2 (Pins 5/1): Bypass. The BYP1/BYP2 pins are
used to bypass the reference of the LT3023 regulator to
achieve low noise performance from the regulator. The
BYP1/BYP2 pins are clamped internally to ±0.6V (one
VBE) from ground. A small capacitor from the corresponding output to this pin will bypass the reference to lower the
output voltage noise. A maximum value of 0.01µF can be
used for reducing output voltage noise to a typical 20µVRMS
over a 10Hz to 100kHz bandwidth. If not used, this pin
must be left unconnected.
OUT1/OUT2 (Pins 6/10): Output. The outputs supply
power to the loads. A minimum output capacitor of 1µF is
required to prevent oscillations. Larger output capacitors
will be required for applications with large transient loads
to limit peak voltage transients. See the Applications
Information section for more information on output capacitance and reverse output characteristics.
SHDN1/SHDN2 (Pins 7/9): Shutdown. The SHDN1/SHDN2
pins are used to put the corresponding channel of the
LT3023 regulator into a low power shutdown state. The
output will be off when the pin is pulled low. The
SHDN1/SHDN2 pins can be driven either by 5V logic or
open-collector logic with pull-up resistors. The pull-up
resistors are required to supply the pull-up current of the
open-collector gates, normally several microamperes,
and the SHDN1/SHDN2 pin current, typically 1µA. If
unused, the pin must be connected to VIN. The device will
not function if the SHDN1/SHDN2 pins are not connected.
IN (Pin 8): Input. Power is supplied to the device through
the IN pin. A bypass capacitor is required on this pin if the
device is more than six inches away from the main input
filter capacitor. In general, the output impedance of a
battery rises with frequency, so it is advisable to include a
bypass capacitor in battery-powered circuits. A bypass
capacitor in the range of 1µF to 10µF is sufficient. The
LT3023 regulator is designed to withstand reverse voltages on the IN pin with respect to ground and the OUT pin.
In the case of a reverse input, which can happen if a battery
is plugged in backwards, the device will act as if there is a
diode in series with its input. There will be no reverse
current flow into the regulator and no reverse voltage will
appear at the load. The device will protect both itself and
the load.
Exposed Pad (Pin 11): Ground. This pin must be soldered
to the PCB and electrically connected to ground.
3023f
8
LT3023
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APPLICATIO S I FOR ATIO
The LT3023 is a dual 100mA low dropout regulator with
micropower quiescent current and shutdown. The device
is capable of supplying 100mA per channel at a dropout
voltage of 300mV. Output voltage noise can be lowered to
20µVRMS over a 10Hz to 100kHz bandwidth with the
addition of a 0.01µF reference bypass capacitor. Additionally, the reference bypass capacitor will improve transient
response of the regulator, lowering the settling time for
transient load conditions. The low operating quiescent
current (20µA per channel) drops to less than 1µA in
shutdown. In addition to the low quiescent current, the
LT3023 regulator incorporates several protection features
which make it ideal for use in battery-powered systems.
The device is protected against both reverse input and
reverse output voltages. In battery backup applications
where the output can be held up by a backup battery when
the input is pulled to ground, the LT3023 acts like it has a
diode in series with its output and prevents reverse current
flow. Additionally, in dual supply applications where the
regulator load isreturned to a negative supply, the output
can be pulled below ground by as much as 20V and still
allow the device to start and operate.
Adjustable Operation
The LT3023 has an output voltage range of 1.22V to 20V.
The output voltage is set by the ratio of two external resistors as shown in Figure 1. The device servos the output to
maintain the corresponding ADJ1/ADJ2 pin voltage at
1.22V referenced to ground. The current in R1 is then equal
to 1.22V/R1 and the current in R2 is the current in R1 plus
the ADJ1/ADJ2 pin bias current. The ADJ1/ADJ2 pin bias
current, 30nA at 25°C, flows through R2 into the ADJ1/ADJ2
pin. The output voltage can be calculated using the formula
in Figure 1. The value of R1 should be no greater than 250k
to minimize errors in the output voltage caused by the ADJ1/
ADJ2 pin bias current. Note that in shutdown the output is
turned off and the divider current will be zero. Curves of
ADJ1/ADJ2 Pin Voltage vs Temperature and ADJ1/ADJ2 Pin
Bias Current vs Temperature appear in the Typical Performance Characteristics.
IN
VIN
OUT1/OUT2
VOUT
+
LT3023
R2
 R2 
VOUT = 1.22V  1 +  + IADJ R2
 R1
( )( )
VADJ = 1.22V
ADJ1/ADJ2
GND
R1
IADJ = 30nA AT 25°C
OUTPUT RANGE = 1.22V TO 20V
3023 F01
Figure 1. Adjustable Operation
The device is tested and specified with the ADJ1/ADJ2 pin
tied to the corresponding OUT1/OUT2 pin for an output
voltage of 1.22V. Specifications for output voltages greater
than 1.22V will be proportional to the ratio of the desired
output voltage to 1.22V: VOUT/1.22V. For example, load
regulation for an output current change of 1mA to 100mA
is –1mV typical at VOUT = 1.22V. At VOUT = 12V, load
regulation is:
(12V/1.22V)(–1mV) = – 9.8mV
Bypass Capacitance and Low Noise Performance
The LT3023 regulator may be used with the addition of a
bypass capacitor from VOUT to the corresponding BYP1/
BYP2 pin to lower output voltage noise. A good quality low
leakage capacitor is recommended. This capacitor will
bypass the reference of the regulator, providing a low frequency noise pole. The noise pole provided by this bypass
capacitor will lower the output voltage noise to as low as
20µVRMS with the addition of a 0.01µF bypass capacitor.
Using a bypass capacitor has the added benefit of improving transient response. With no bypass capacitor and a
10µF output capacitor, a 10mA to 100mA load step will
settle to within 1% of its final value in less than 100µs. With
the addition of a 0.01µF bypass capacitor, the output will
stay within 1% for a 10mA to 100mA load step (see Transient Reponse in Typical Performance Characteristics section). However, regulator start-up time is inversely proportional to the size of the bypass capacitor, slowing to
15ms with a 0.01µF bypass capacitor and 10µF output
capacitor.
3023f
9
LT3023
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APPLICATIO S I FOR ATIO
The LT3023 regulator is designed to be stable with a wide
range of output capacitors. The ESR of the output capacitor affects stability, most notably with small
capacitors. A minimum output capacitor of 1µF with an
ESR of 3Ω or less is recommended to prevent oscillations. The LT3023 is a micropower device and output
transient response will be a function of output capacitance. Larger values of output capacitance decrease the
peak deviations and provide improved transient response
for larger load current changes. Bypass capacitors, used
to decouple individual components powered by the
LT3023, will increase the effective output capacitor value.
With larger capacitors used to bypass the reference (for
low noise operation), larger values of output capacitors
are needed. For 100pF of bypass capacitance, 2.2µF of
output capacitor is recommended. With a 330pF bypass
capacitor or larger, a 3.3µF output capacitor is recommended. The shaded region of Figure 2 defines the region
over which the LT3023 regulator is stable. The minimum
ESR needed is defined by the amount of bypass capacitance used, while the maximum ESR is 3Ω.
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common
dielectrics used are Z5U, Y5V, X5R and X7R. The Z5U and
Y5V dielectrics are good for providing high capacitances
in a small package, but exhibit strong voltage and temperature coefficients as shown in Figures 3 and 4. When
used with a 5V regulator, a 10µF Y5V capacitor can exhibit
an effective value as low as 1µF to 2µF over the operating
temperature range. The X5R and X7R dielectrics result in
more stable characteristics and are more suitable for use
as the output capacitor. The X7R type has better stability
across temperature, while the X5R is less expensive and
is available in higher values.
20
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
0
X5R
CHANGE IN VALUE (%)
Output Capacitance and Transient Response
–20
–40
–60
Y5V
–80
–100
0
2
4
14
8
6
10 12
DC BIAS VOLTAGE (V)
16
3023 F03
Figure 3. Ceramic Capacitor DC Bias Characteristics
40
4.0
20
CHANGE IN VALUE (%)
3.5
3.0
STABLE REGION
ESR (Ω)
2.5
2.0
CBYP = 0
CBYP = 100pF
CBYP = 330pF
CBYP > 3300pF
1.5
1.0
0.5
X5R
0
–20
–40
Y5V
–60
–80
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
–100
–50 –25
0
1
3
2
4 5 6 7 8 9 10
OUTPUT CAPACITANCE (µF)
50
25
75
0
TEMPERATURE (°C)
100
125
3023 F04
3023 F02
Figure 2. Stability
Figure 4. Ceramic Capacitor Temperature Characteristics
3023f
10
LT3023
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APPLICATIO S I FOR ATIO
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or
microphone works. For a ceramic capacitor the stress
can be induced by vibrations in the system or thermal
transients. The resulting voltages produced can cause
appreciable amounts of noise, especially when a ceramic
capacitor is used for noise bypassing. A ceramic capacitor produced Figure 5’s trace in response to light tapping
from a pencil. Similar vibration induced behavior can
masquerade as increased output voltage noise.
COUT = 10µF
CBYP = 0.01µF
ILOAD = 100mA
dissipation from both channels must be considered during thermal analysis.
The LT3023 regulator has internal thermal limiting designed to protect the device during overload conditions.
For continuous normal conditions, the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat generated by power devices.
The following tables list thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 3/32" FR-4 board with one ounce
copper.
VOUT
500µV/DIV
Table 1. MSE Package, 10-Lead MSOP
100ms/DIV
3023 F05
Figure 5. Noise Resulting from Tapping on a Ceramic Capacitor
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C). The
power dissipated by the device will be made up of two
components (for each channel):
1. Output current multiplied by the input/output voltage
differential: (IOUT)(VIN – VOUT), and
2. GND pin current multiplied by the input voltage:
(IGND)(VIN).
The ground pin current can be found by examining the
GND Pin Current curves in the Typical Performance
Characteristics section. Power dissipation will be equal to
the sum of the two components listed above. Power
COPPER AREA
TOPSIDE*
BACKSIDE
BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
2500mm2
2500mm2
2500mm2
40°C/W
2
2
2
1000mm
2500mm
2500mm
45°C/W
225mm2
2500mm2
2500mm2
50°C/W
2
2
2
62°C/W
100mm
2500mm
2500mm
*Device is mounted on topside.
Table 2. DD Package, 10-Lead DFN
COPPER AREA
TOPSIDE*
BACKSIDE
BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
2500mm2
2500mm2
2500mm2
40°C/W
2
2500mm
2
2500mm2
45°C/W
2500mm
2
2
50°C/W
2500mm
2
2
62°C/W
1000mm
225mm
2
100mm
2
2500mm
2500mm
*Device is mounted on topside.
The thermal resistance juncton-to-case (θJC), measured
at the Exposed Pad on the back of the die is 10°C/W.
3023f
11
LT3023
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APPLICATIONS INFORMATION
Calculating Junction Temperature
Example: Given an output voltage on the first channel of
3.3V, an output voltage of 2.5V on the second channel, an
input voltage range of 4V to 6V, output current ranges of
0mA to 100mA for the first channel and 0mA to 50mA for
the second channel, with a maximum ambient temperature of 50°C, what will the maximum junction temperature
be?
The power dissipated by each channel of the device will be
equal to:
IOUT(MAX)(VIN(MAX) – VOUT) + IGND(VIN(MAX))
where (for the first channel):
IOUT(MAX) = 100mA
VIN(MAX) = 6V
IGND at (IOUT = 100mA, VIN = 6V) = 2mA
so:
P1 = 100mA(6V – 3.3V) + 2mA(6V) = 0.28W
and (for the second channel):
IOUT(MAX) = 50mA
VIN(MAX) = 6V
IGND at (IOUT = 50mA, VIN = 6V) = 1mA
so:
P2 = 50mA(6V – 2.5V) + 1mA(6V) = 0.18W
The thermal resistance will be in the range of 40°C/W to
60°C/W depending on the copper area. So the junction
temperature rise above ambient will be approximately
equal to:
(0.28W + 018W)(60°C/W) = 27.8°C
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
TJMAX = 50°C + 27.8°C = 77.8°C
Protection Features
The LT3023 regulator incorporates several protection
features which makes it ideal for use in battery-powered
circuits. In addition to the normal protection features
associated with monolithic regulators, such as current
limiting and thermal limiting, the devices are protected
against reverse input voltages, reverse output voltages
and reverse voltages from output to input.
Current limit protection and thermal overload protection
are intended to protect the device against current overload
conditions at the output of the device. For normal operation, the junction temperature should not exceed 125°C.
The input of the device will withstand reverse voltages of
20V. Current flow into the device will be limited to less than
1mA (typically less than 100µA) and no negative voltage
will appear at the output. The device will protect both itself
and the load. This provides protection against batteries
which can be plugged in backward.
The output of the LT3023 can be pulled below ground
without damaging the device. If the input is left open circuit
or grounded, the output can be pulled below ground by
20V. The output will act like an open circuit; no current will
flow out of the pin. If the input is powered by a voltage
source, the output will source the short-circuit current of
the device and will protect itself by thermal limiting. In this
case, grounding the SHDN1/SHDN2 pins will turn off the
device and stop the output from sourcing the short-circuit
current.
The ADJ1 and ADJ2 pins can be pulled above or below
ground by as much as 7V without damaging the device. If
the input is left open circuit or grounded, the ADJ1 and
ADJ2 pins will act like an open circuit when pulled below
ground and like a large resistor (typically 100k) in series
with a diode when pulled above ground.
In situations where the ADJ1 and ADJ2 pins are connected
to a resistor divider that would pull the pins above their 7V
clamp voltage if the output is pulled high, the ADJ1/ADJ2
pin input current must be limited to less than 5mA. For
example, a resistor divider is used to provide a regulated
1.5V output from the 1.22V reference when the output is
forced to 20V. The top resistor of the resistor divider must
be chosen to limit the current into the ADJ pin to less than
5mA when the ADJ1/ADJ2 pin is at 7V. The 13V difference
between output and ADJ1/ADJ2 pin divided by the 5mA
maximum current into the ADJ1/ADJ2 pin yields a minimum top resistor value of 2.6k.
3023f
12
LT3023
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APPLICATIO S I FOR ATIO
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled to
ground, pulled to some intermediate voltage or is left open
circuit. Current flow back into the output will follow the
curve shown in Figure 6.
REVERSE OUTPUT CURRENT (µA)
100
When the IN pin of the LT3023 is forced below the OUT1
or OUT2 pins or the OUT1/OUT2 pins are pulled above the
IN pin, input current will typically drop to less than 2µA.
This can happen if the input of the device is connected to
a discharged (low voltage) battery and the output is held
up by either a backup battery or a second regulator circuit.
The state of the SHDN1/SHDN2 pins will have no effect on
the reverse output current when the output is pulled above
the input.
TA = 25°C
90 VIN = 0V
V
= VADJ
80 OUT
CURRENT FLOWS
760 INTO OUTPUT PIN
60
50
40
30
20
10
0
0
1
2
3 4 5 6 7 8
OUTPUT VOLTAGE (V)
9
10
3023 F06
Figure 6. Reverse Output Current
U
TYPICAL APPLICATIO S
Noise Bypassing Slows Startup, Allows Outputs to Track
VSHDN1/SHDN2
1V/DIV
VIN
3.7V TO 20V
VOUT1
1V/DIV
VOUT2
1V/DIV
OUT1
IN
0.01µF
1µF
10µF
3.3V
AT 100mA
422k
BYP1
3023 TA02b
2ms/DIV
ADJ1
249k
LT3023
Startup Time
SHDN1
OUT2
0.01µF
SHDN2
BYP2
GND
10µF
2.5V
AT 100mA
100
261k
ADJ2
249k
3023 TA02a
STARTUP TIME (ms)
OFF ON
10
1
0.1
10
100
1000
10000
CBYP (pF)
3023 TA02c
3023f
13
LT3023
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PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
0.675 ±0.05
3.50 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
R = 0.115
TYP
6
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10
(4 SIDES)
0.38 ± 0.10
10
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 5)
(DD10) DFN 0403
5
0.200 REF
1
0.75 ±0.05
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3023f
14
LT3023
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PACKAGE DESCRIPTIO
MSE Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1663)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.794 ± 0.102
(.110 ± .004)
5.23
(.206)
MIN
0.889 ± 0.127
(.035 ± .005)
1
2.06 ± 0.102
(.081 ± .004)
1.83 ± 0.102
(.072 ± .004)
2.083 ± 0.102 3.20 – 3.45
(.082 ± .004) (.126 – .136)
10
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
0.254
(.010)
DETAIL “A”
0° – 6° TYP
1 2 3 4 5
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
0.18
(.007)
0.497 ± 0.076
(.0196 ± .003)
REF
10 9 8 7 6
SEATING
PLANE
0.86
(.034)
REF
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
0.127 ± 0.076
(.005 ± .003)
MSOP (MSE) 0603
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3023f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT3023
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TYPICAL APPLICATIO S
Startup Sequencing
Turn-On Waveforms
VSHDN1
1V/DIV
VIN
3.7V TO 20V
1µF
OUT1
IN
10µF
0.01µF
LT3023
BYP1
422k
35.7k
249k
28k
3.3V
AT
100mA
VOUT1
1V/DIV
VOUT2
1V/DIV
ADJ1
OFF ON
SHDN1
OUT2
10µF
0.01µF
SHDN2
3023 TA03b
Turn-Off Waveforms
261k
BYP2
GND
0.47µF
2ms/DIV
2.5V
AT
100mA
ADJ2
VSHDN1
1V/DIV
249k
3023 TA03a
VOUT1
1V/DIV
VOUT2
1V/DIV
2ms/DIV
3023 TA03c
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COMMENTS
VIN: 4.2V to 30V, VOUT(MIN): 3.75V, IQ: 50µA, ISD: 16µA,
DD, SOT-223, S8,TO220, TSSOP20 Packages
Guaranteed Voltage Tolerance and Line/Load Regulation
VIN: –20V to –4.3V, VOUT(MIN): –3.8V, IQ: 45µA, ISD: 10µA,
DD,SOT-223, S8 Packages
Accurate Programmable Current Limit, Remote Sense
VIN: –35V to –4.2V, VOUT(MIN): –2.40V, IQ: 2.5mA, ISD: <1µA, TO220-5 Package
Low Noise < 20µVRMS, Stable with 1µF Ceramic Capacitors,
VIN: 1.8V to 20V, VOUT(MIN): 1.22V, IQ: 20µA, ISD: <1µA, ThinSOT Package
Low Noise < 20µVRMS,
VIN: 1.8V to 20V, VOUT(MIN): 1.22V, IQ: 25µA, ISD: <1µA, MS8 Package
Low Noise < 20µVRMS,
VIN: 1.8V to 20V, VOUT(MIN): 1.22V, IQ: 30µA, ISD: <1µA, S8 Package
Low Noise < 40µVRMS, "A" Version Stable with Ceramic Capacitors,
VIN: 2.7V to 20V, VOUT(MIN): 1.21V, IQ: 1mA, ISD: <1µA, DD, TO220 Packages
Low Noise < 30µVRMS, Stable with 1µF Ceramic Capacitors,
VIN: 1.6V to 6.5V, VOUT(MIN): 1.25V, IQ: 40µA, ISD: <1µA, ThinSOT Package
Low Noise < 20µVRMS,
VIN: 1.8V to 20V, VOUT(MIN): 1.22V, IQ: 30µA, ISD: <1µA, MS8 Package
Low Noise < 40µVRMS, "A" Version Stable with Ceramic Capacitors,
VIN: 2.1V to 20V, VOUT(MIN): 1.21V, IQ: 1mA, ISD: <1µA,
DD, TO220, SOT-223, S8 Packages
Low Noise < 30µVRMS, Stable with Ceramic Capacitors,
VIN: –0.9V to –20V, VOUT(MIN): –1.21V, IQ: 30µA, ISD: 3µA, ThinSOT Package
VIN: 2.5V to 5.5V, VOUT(MIN): 0.6 V, IQ: 40µA, ISD: <1µA, MSE Package
3023f
16
Linear Technology Corporation
LT/TP 1103 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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 LINEAR TECHNOLOGY CORPORATION 2003