Sony CXD1913AQ Digital video encoder Datasheet

CXD1913AQ
Digital Video Encoder
Description
The CXD1913AQ is a digital video encoder designed
for video CD, car navigation system and other digital
video applications. The device accepts ITU-R601
compatible Y, Cb, Cr data and also accepts ITUR656-format Y, Cb, Cr data, and the data are
encoded to composite video and separate Y/C video
(S-Video) signal.
Features
• NTSC and PAL encoding mode
• Composite video and separate Y/C video (S-Video)
signal outputs
• 8/16-bit pixel data input mode
• 13.5 Mpps pixel rate
• Interlace and non-interlace supported
• On-chip 100% color bar generator
• 10-bit 3 channels DACs
• Supports I2C bus (400kHz) and SONY SIO
• Closed Caption (Line 21, Line 284) encoding
• VBID encoding
• Monolithic CMOS single 3.3V ± 5% and 5.0V ± 5%
power supplies
• 64-pin plastic QFP package
64 pin QFP (Plastic)
Absolute Maximum Ratings
–0.3 to +7.0
• Supply voltage
VDD
• Input voltage
VI
–0.3 to +7.0
• Output voltage
VO
–0.3 to +7.0
• Operating temperature Topr
–20 to +75
• Storage temperature Tstg
–40 to +125
(Vss = 0V)
V
V
V
°C
°C
Recommended Operating Conditions
• Logic supply voltage
DVDD
3.3V ± 5%
DVDD
• Analog supply voltage AVDD
AVDD
• Input voltage
VIN
• Operating temperature Topr
5.0V ± 5%
3.3V ± 5%
5.0V ± 5%
Vss to VDD
0 to +70
V
°C
I/O Capacitance
• Input pin
• Output pin
11 (Max.)
11 (Max.)
pF
pF
CI
CO
Note) Test conditions: VDD = VI = 0V
fM = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97918-PS
1 to 4,
6 to 9
37 to 39,
54
–2–
XRST 55
XIICEN 64
SO 61
XCS/SA 50
SCK/SCL 49
SI/SDA 48
F1/XTEST4 52
XVRST 51
FID 62
SIO
Controller
Sub Carrier
Gen.
LPF
LPF
Delay
VBID Encoder
(for NTSC)
Closed Caption Encoder
(for NTSC)
CSYNC
SYNC Gen.
and
Timing Controller
HSYNC 60
V
U
Y
BURST FLAG
1/2
Demultiplex,
Level
Translator
and
interpolator
4:2:2 to
4:4:4
VSYNC 59
SYSCLK 56
PDCLK 57
PD8 to 15 11 to 18
PD0 to 7
XTEST1 to 3
XTEST
Block Diagram
Modulator
SYNC Slope
Gen.
CHROMA
Interpolator
10bit
DAC
10bit
DAC
10bit
DAC
41 TRST
45 TCK
44 TMS
43 TDI
46 TDO
21 VREF
20 IREF
26 VG
32 C-OUT
24 COMP-O
29 Y-OUT
25 VB
CXD1913AQ
CXD1913AQ
Pin Description
Pin
No.
Symbol
I/O
Description
1
PD7
I
2
PD6
I
3
PD5
I
4
PD4
I
5
VSS
—
6
PD3
I
7
PD2
I
8
PD1
I
9
PD0
I
10
VDD
—
11
PD15/TD7
I/O
12
PD14/TD6
I/O
13
PD13/TD5
I/O
14
PD12/TD4
I/O
15
PD11/TD3
I/O
16
PD10/TD2
I/O
17
PD9/TD1
I/O
18
PD8/TD0
I/O
19
VSS
—
Digital ground
20
IREF
O
Reference current output.
Connect resistance “16R” which is 16 times output resistance “R”.
21
VREF
I
Voltage reference input.
Sets output full scale value.
22
AVDD1
—
Analog power supply
23
AVSS1
—
Analog ground
24
COMP-O
O
10-bit D/A converter output.
This pin outputs composite signal.
25
VB
O
Connect to VSS with a capacitor of approximately 0.1µF.
26
VG
O
Connect to AVDD with a capacitor of approximately 0.1µF.
27
AVDD2
—
Analog power supply
28
AVSS2
—
Analog ground
29
Y-OUT
O
10-bit D/A converter output.
This pin outputs luminance (Y) signal.
30
AVDD3
—
Analog power supply
31
AVSS3
—
Analog ground
8-bit pixel data input pins (PD0 to 7).
When control register bit “PIF MODE” = “0”:
These are inputs for multiplexed Y, Cb, and Cr signal.
When control register bit “PIF MODE” = “1”:
These are inputs for Y signal.
Digital ground
8-bit pixel data input pins (PD0 to 7).
When control register bit “PIF MODE” = “0”:
These are inputs for multiplexed Y, Cb, and Cr signal.
When control register bit “PIF MODE” = “1”
These are inputs for Y signal.
Digital power supply
8-bit pixel data input pins / Test data bus.
When control register bit “PIF MODE” = “0”:
These inputs are not used.
When control register bit “PIF MODE” = “1”:
These are inputs for multiplexed Cb and Cr signal.
For test mode, it's used for internal circuit test data bus.
Test mode is available only for device bender.
–3–
CXD1913AQ
Pin
No.
32
Symbol
C-OUT
I/O
Description
O
10-bit D/A converter output. This pin outputs chroma (C) signal.
33
TD10
I/O
Test data bus.
This pin should be open.
For test mode, it’s used for internal circuit test data bus.
Test mode is available only for device bender.
34
VDD
—
Digital power supply
35
TD9
I/O
36
TD8
I/O
Test data bus.
These pins should be open.
For test mode, it’s used for internal circuit test data bus.
Test mode is available only for device bender.
37
XTEST1
I
38
XTEST2
I
39
XTEST3
I
40
VSS
41
TRST
42
VDD
—
43
TDI
I
Test mode control input. This pin is pulled up.
44
TMS
I
Test mode control input. This pin is pulled up.
45
TCK
I
Test mode control input. This pin should be “H” input.
46
TDO
O
Test data bus output. This pin should be open.
47
VSS
—
Digital ground
48
SI/SDA
I
This pin's function is selected by XIICEN (Pin 64).
When XIICEN = “H”, this pin is SONY SIO mode; SI serial data input.
When XIICEN = “L”, this pin is I2C bus mode; SDA input/output.
49
SCK/SCL
I
This pin's function is selected by XIICEN (Pin 64).
When XIICEN = “H”, this pin is SONY SIO mode; SCK serial clock input.
When XIICEN = “L”, this pin is I2C bus mode; SCL input.
I
This pin's function is selected by XIICEN (Pin 64). This pin is pulled up.
When XIICEN = “H”, this pin is SONY SIO mode; XCS chip select input.
When XIICEN = “L”, this pin is I2C bus mode; SA slave address select input
signal which selects I2C bus slave address.
I
Vertical sync reset input in active low. This pin is pulled up.
This is used to synchronize external vertical sync and internal vertical sync.
When XVRST is “L”, internal digital sync generator is reset according to F1 status.
Valid only for 8-bit mode (control register address 01H bit 4 "PF MODE" = "0").
I
This pin's function is selected by XTEST (Pin 54).
When XTEST = "H", this pin is F1; field ID input.
Field ID during vertical sync reset is indicated.
“H” indicates 1st field. “L” indicates 2nd field.
When XTEST = "L", XTEST4 input.
50
51
52
XCS/SA
XVRST
F1/
XTEST4
—
I
Test mode control inputs. These pins are pulled up.
Normally, these pins should be open.
Digital ground
Test mode reset input. This pin is pulled up.
For power on reset, set “L” for more than 40 clocks (SYSCLK).
Digital power supply
–4–
CXD1913AQ
Pin
No.
Symbol
I/O
—
Function
Digital power supply
53
VDD
54
XTEST
I
Test mode control input. This pin is pulled up.
Normally, this pin should be open.
55
XRST
I
System reset input in active low.
For power on reset, set “L” for more than 40 clocks (SYSCLK).
56
SYSCLK
I
System clock input.
To generate correct subcarrier frequency, precise 27MHz is required.
57
PDCLK
O
Pixel data clock output.
This clock is divided in half from SYSCLK.
This is used when 16-bit pixel data mode.
58
VSS
—
Digital ground
59
VSYNC
O
Vertical sync signal output.
60
HSYNC
O
Horizontal sync signal output.
61
SO
O
This pin's function is selected by XIICEN (Pin 64).
When XIICEN = “H”, this pin is SONY SIO mode; SO serial out output.
When XIICEN = “L”, this pin is not used and output is high impedance.
62
FID
O
Field ID output.
When control register bit “FIDS” = “1”:
“L” indicates 1st field, “H” indicates 2nd field.
When control register bit “FIDS” = “0”:
“H” indicates 1st field, “L” indicates 2nd field.
63
VDD
—
Digital power supply
64
XIICEN
I
Serial interface mode select input. This pin is pulled up.
When XIICEN = “L”, Pins 48 to 50 and 61 are I2C bus mode.
When XIICEN = “H”, Pins 48 to 50 and 61 are SONY SIO mode.
–5–
CXD1913AQ
Electrical Characteristics
DC characteristics
Item
(Ta = 0 to +70°C, Vss = 0V)
Symbol Measurement conditionsConditions
Input high voltage
VIH1
VDD = 5.0V ± 5%
VDD = 3.3V ± 5%
Input low voltage
VIL1
VDD = 5.0V ± 5%
VDD = 3.3V ± 5%
Input high voltage
VIH2
VDD = 5.0V ± 5%
VDD = 3.3V ± 5%
Input low voltage
VIL2
VDD = 5.0V ± 5%
VDD = 3.3V ± 5%
Input high voltage
VIH3
VDD = 5.0V ± 5%
VDD = 3.3V ± 5%
Input low voltage
VIL3
VDD = 5.0V ± 5%
VDD = 3.3V ± 5%
Output high voltage
VOH1
IOH = –2.4mA
VDD = 5.0V ± 5%
VDD = 3.3V ± 5%
Output low voltage
VOL1
IOL = 4.8mA
VDD = 5.0V ± 5%
VDD = 3.3V ± 5%
Output high voltage
VOH2
IOH = –1.2mA
VDD = 5.0V ± 5%
VDD = 3.3V ± 5%
Output low voltage
VOL2
IOL = 2.4mA
VDD = 5.0V ± 5%
VDD = 3.3V ± 5%
Input leak current
IIL1
VI = 0 to 5.25V
VDD = 5.0V ± 5%
VDD = 3.3V ± 5%
Input leak current
IIL2
VI = 0V
VDD = 5.0V ± 5%
VDD = 3.3V ± 5%
Supply current
IDD
VDD = 5.0V ± 5%
VDD = 3.3V ± 5%
∗1
∗2
∗3
∗4
∗5
∗6
∗7
∗8
Min.
Typ.
Max.
2.2
1.8
V
∗1
V
∗1
V
∗2
V
∗2
V
∗3
V
∗3
V
∗4
V
∗4
V
∗5
0.4
V
∗5
10
µA
∗6
–240
–75
70 ∗8
40 ∗8
µA
∗7
0.8
0.5
2.4
1.8
0.8
0.5
0.7VDD
0.3VDD
VDD – 0.8
0.4
VDD – 0.8
–10
–40
–12
–100
–30
Unit Pins
mA
PD0 to 15, TD8 to 10, XTEST1 to 3, TRST, TDI, TCK, XCS/SA, XVRST, F1/XTEST4, XTEST, XRST, XIICEN
SYSCLK
SI/SDA, SCK/SCL
PDCLK, VSYNC, HSYNC, FID, SO
TDO, TD0 to 10
PD0 to 15, TD8 to 10, TCK, SI/SDA, SCK/SCL, F1/XTEST4, XRST, SYSCLK
XTEST1 to 3, TRST, TDI, TMS, XCS/SA, XVRST, XTEST, XIICEN
Not include analog current
–6–
CXD1913AQ
DAC characteristics 1
Item
(AVDD = 5.0V, R = 200Ω, VREF = 2.0V, Ta = 25°C)
Symbol
Measurement conditions
Min.
Typ.
Max.
Unit
Resolution
n
Linearity error
EL
–2.0
2.0
LSB
Differential linearity error
ED
–1.0
1.0
LSB
Output full-scale current
IFS
9.5
10.5
mA
Output offset voltage
VOS
1
mV
Output full-scale voltage
VFS
1.9
2.0
2.1
V
Precision guaranteed output
voltage range
VOC
1.9
2.0
2.1
V
10
DAC characteristics 2
Item
10.0
bit
(AVDD = 3.3V, R = 200Ω, VREF = 1.35V, Ta = 25°C)
Symbol
Measurement conditions
Min.
Typ.
Max.
10
Unit
bit
Resolution
n
Linearity error
EL
–3.0
3.0
LSB
Differential linearity error
ED
–1.5
1.5
LSB
Output full-scale current
IFS
6.25
7.25
mA
Output offset voltage
VOS
1
mV
Output full-scale voltage
VFS
1.25
1.35
1.45
V
Precision guaranteed output
voltage range
VOC
1.25
1.35
1.45
V
–7–
6.75
CXD1913AQ
AC characteristics
1. Pixel Data Interface
(1) 8-bit mode
SYSCLK
tPDS
tPDH
PD0 to 7
(Ta = 0 to +70°C, VDD = 3.3V ± 5%, 5.0V ± 5%, Vss = 0V)
Item
Pixel data setup time to SYSCLK
Pixel data hold time to SYSCLK
Symbol
tPDS
tPDH
Min.
Typ.
Max.
Unit
10
ns
3
ns
(2) 16-bit mode
PDCLK
tPDS
tPDH
PD0 to 15
(Ta = 0 to +70°C, VDD = 3.3V ± 5%, 5.0V ± 5%, Vss = 0V)
Item
Pixel data setup time to PDCLK
Pixel data hold time to PDCLK
Symbol
tPDS
tPDH
–8–
Min.
Typ.
Max.
Unit
20
ns
0
ns
CXD1913AQ
2. Serial Port Interface
fSCK
tPWLSCK
tPWHSCK
SCK
tCSS
tCSH
XCS
tSIS
tSIH
SI
tSOH
tSOD
SO
(Ta = 0 to +70°C, VDD = 5.0V ± 5%, Vss = 0V)
Item
Symbol
Min.
Typ.
Max.
Unit
3
MHz
SCK clock rate
fSCK
DC
SCK pulse width Low
tPWLSCK
tPWHSCK
tCSS
tCSH
tSIS
tSIH
tSOD ∗
tSOH ∗
100
ns
100
ns
150
ns
150
ns
50
ns
10
ns
SCK pulse width High
Chip select setup time to SCK
Chip select hold time to SCK
Serial input setup time to SCK
Serial input hold time to SCK
Serial output delay time from SCK
Serial output hold time from SCK
30
3
ns
ns
∗ CL = 35pF
(Ta = 0 to +70°C, VDD = 3.3V ± 5%, Vss = 0V)
Item
Symbol
Min.
Typ.
Max.
Unit
3
MHz
SCK clock rate
fSCK
DC
SCK pulse width Low
tPWLSCK
tPWHSCK
tCSS
tCSH
tSIS
tSIH
tSOD ∗
tSOH ∗
100
ns
100
ns
150
ns
150
ns
50
ns
10
ns
SCK pulse width High
Chip select setup time to SCK
Chip select hold time to SCK
Serial input setup time to SCK
Serial input hold time to SCK
Serial output delay time from SCK
Serial output hold time from SCK
50
3
ns
ns
∗ CL = 35pF
–9–
CXD1913AQ
3. XVRST, F1
SYSCLK
tVS
tVH
XVRST
F1
(Ta = 0 to +70°C, VDD = 3.3V ± 5%, 5.0V ± 5%, Vss = 0V)
Item
Symbol
Min.
tVS
tVH
XVRST setup time to SYSCLK
XVRST hold time to SYSCLK
Typ.
Max.
Unit
20
ns
0
ns
4. SYSCLK, PDCLK, VSYNC, HSYNC, FID
fSYSCLK
tPWHCLK
tPWLCLK
SYSCLK
tPDCLKD
tPDCLKD
PDCLK
tCOD
VSYNC,
HSYNC,
FID
tCOH
(Ta = 0 to +70°C, VDD = 5.0V ± 5%, Vss = 0V)
Item
Symbol
SYSCLK clock rate
fSYSCLK
SYSCLK pulse width Low
tPWLCLK
tPWHCLK
tPDCLKD ∗
tCOD ∗
tCOH ∗
SYSCLK pulse width High
PDCLK delay time from SYSCLK
Control output delay time from SYSCLK
Control output hold time from SYSCLK
Min.
Typ.
Max.
27
Unit
MHz
11
ns
11
ns
3
15
ns
20
ns
ns
∗ CL = 35pF
– 10 –
CXD1913AQ
(Ta = 0 to +70°C, VDD = 3.3V ± 5%, Vss = 0V)
Item
Symbol
SYSCLK clock rate
fSYSCLK
SYSCLK pulse width Low
tPWLCLK
tPWHCLK
tPDCLKD ∗
tCOD ∗
tCOH ∗
SYSCLK pulse width High
PDCLK delay time from SYSCLK
Control output delay time from SYSCLK
Control output hold time from SYSCLK
Min.
Typ.
Max.
27
Unit
MHz
11
ns
11
ns
3
23
ns
25
ns
ns
∗ CL = 35pF
– 11 –
CXD1913AQ
Description of Functions
The CXD1913AQ converts digital parallel data (ITU-R601 Y, Cb, Cr) into analog TV signals in NTSC (RS170A)
or PAL (ITU-R624; B, G, H, I) format.
The CXD1913AQ first receives image data in 8-bit parallel form (multiplexed Y, Cb, and Cr data), or in 16-bit
parallel form (8-bit Y and 8-bit multiplexed Cb and Cr data). After demultiplexing, it converts Cb and Cr signals
into U and V signals respectively, interpolates 4:2:2 to 4:4:4, and modulates the signals with the subcarrier
generated by digital subcarrier generator.
Y signal and modulated chroma signal are oversampled (at double) to reduce sin (x)/(x) rolloff.
10-bit DACs are used for converting digital composite and Y/C signals into analog signals.
1. Pixel Input Format
Pixel input format is determined by Bit 4 (PIF MODE) of control register address 01H as shown in Table 1-1.
When PIF MODE is “0”, the image data (Y, Cb, Cr) input from PD0 to PD7 is sampled at the rising edge of
SYSCLK.
When PIF MODE is “1”, Y data is input into PD0 to 7, multiplexed Cb and Cr data are input into PD8 to 15, and
these respective data are sampled at the rising edge of PDCLK.
Table 1-1
PIF MODE
PD15 to 8
PD7 to 0
0 (8-bit mode)
NA
Y/Cb/Cr
1 (16-bit mode)
Cb/Cr
Y
Also, pixel input data sampling point is determined by Bits 3 and 2 (PIX TIM) of control register address 01H as
shown in Table 1-2.
During 8-bit mode, the data, which is sampled at the timing phase (Fig 1-1: 8-bit mode #0 to #3) set at PIX TIM
from the falling edge of HSYNC, is recognized as Cb0.
(in the default, the data, which is sampled at the rising edge of second SYSCLK from the falling edge of
HSYNC), is recognized as Cb0.
During 16-bit mode, the data, which is sampled at the timing phase (Fig 1-1: 16-bit mode #0 to #3) set at PIX
TIM from the falling edge of HSYNC, is recognized as Cb0.
(In the default, the data, which is sampled at the rising edge of second PDCLK from the falling edge of
HSYNC), is recognized as Cb0.
Table 1-2
PIX TIM
Timing phase
0
0
#0 (default)
0
1
#1
1
0
#2
1
1
#3
– 12 –
CXD1913AQ
Pixel Data Input Timing
1
2
3
5
4
SYSCLK
1
2
3
PDCLK
HSYNC
[16-bit mode]
PD0 to 7
#0
PD8 to 15
#2
Y0
Y1
Y2
Y3
Y4
Y5
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
Y0
Y1
Y2
Y3
Y4
Cb0
Cr0
Cb2
Cr2
Cb4
#1
#3
[8-bit mode]
PD0 to 7
Cb0
#0
Y0
Y1
Cb2
Y2
Cr2
Y3
Cb4
Y4
Cr4
Y5
Cb6
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Cb4
Y4
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Cb4
Y4
Cr4
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Cb4
Y4
Cr4
Y5
Cr0
#1
#2
Cb0
#3
PD0
PD1
:
PD7
Pixel data 0 (LSB)
Pixel data 1
:
Pixel data 7 (MSB)
PD8
PD9
:
PD15
Fig 1-1
– 13 –
Pixel data 0 (LSB)
Pixel data 1
:
Pixel data 7 (MSB)
CXD1913AQ
2. Serial Interface
The CXD1913AQ supports both I2C bus (high-speed mode) and Sony serial interface. These modes can be
selected by XIICEN input pin as shown in Table 2-1 below.
Table 2-1
H
XIICEN
L
I2C
Sony SIO mode
SI/SDA
mode
SI
SDA
SCK/SCL
SCK
SCL
XCS/SA
XCS
SA
SO
Hi-Z
SO
2-1. I2C bus interface
The CXD1913AQ becomes a slave transceiver of I2C bus, and supports the 7-bit slave address and the highspeed mode (400K bit/s).
2-1-1. Slave address
Two kinds of slave addresses (88H, 8CH) can be selected by the SA signal, as shown in Table 2-2 below.
Table 2-2
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
0
0
1
SA
0
X
AA
AAAAAA
AAAA
A
AAA
AAAA
AAAA
AA
AAAAAA
AA
AAAA
AAA
A
AAA
AAAA
AAAA
AA
AA
AA
AA
2-1-2. Write cycle
S
slave address
W
A
start address
A
write data
A
write data
A
P
"0"
from master to slave
from slave to master
D7
D6
D5
D4
start address
D3
D2
D1
D0
ADR [4 : 0]
After the slave address is supplied from the master, the data in the next transfer cycle is set up inside the start
address register of this IC as start address of the control register. In subsequent cycles, the data supplied from
the master is written in the addresses indicated by the control register address. The set control register
address is automatically incremented with the completed transfer of each byte of data.
– 14 –
CXD1913AQ
2-1-3. Read cycle
AA
AAAAAA
AAAA
A
AAA
AA
AAA
AAA
AA
AAAAAA
AA
AAAA
AAA
A
AAA
AA
AAA
AAA
AA
AA
AA
AA
S
slave address
R
A
read data
A
read data
A
P
"1"
from master to slave
from slave to master
After the slave address is supplied from the master, subsequent cycles change immediately to read cycles and
only ID code (addresses 09H, 0AH) is read out. During the read cycle, the start address is automatically set to
09H.
Note) In the Sony SIO mode, addresses from 00H to 0AH can be read out.
2-1-4. Handling of general call address (00H)
General call address is neglected and there is no ACK response.
– 15 –
CXD1913AQ
2-2. Sony serial interface
Sony serial interface uses SCK, XCS, SI and SO signals.
Serial interface is activated when XCS signal is “Low”, and samples serial input data at the rising edge of SCK.
The first one byte after XCS activation is set up as a serial control command. The data includes a start control
register address and direction of the serial interface. The control register address is automatically incremented
with the transfer of each byte of data. In the write mode, the data of second byte and after are written in the
addresses indicated by the address generated by the address generator of the CXD1913AQ. In the read
mode, the serial input data is neglected and writing is not done.
Serial Interface Timing
SCK
XCS
SI
D0
D1
LSB
D2
D3
D4
D5
D6
Serial control command
D7
D0
MSB
LSB
SO
D0
D1
D2
D1
D2
D3
D4
D5
D6
D7
D5
D6
D7
Serial data
D3
D4
MSB
Serial Interface Sequence
SCK
XCS
SI
00H
Internl address generator
FFH
11H
00H
01H
Start control register address set Control register address
auto-increment
Control register address
00H
01H
02H
CEH
02H
Control register address
auto-increment
Control register data
FFH
11H
CEH
2-1. Serial control command format
D7
D6
D5
D4
D3
WR
WR
D2
D1
D0
ADR [4 : 0]
: Direction for serial interface
When this bit is “1”:
The serial interface is write mode.
Incoming serial data is set up inside the control register according to the control register
address.
When this bit is “0”:
The serial interface is read mode.
The control register data is output to SO according to the control register address.
ADR [4 : 0] : Start control register address
– 16 –
CXD1913AQ
3. XVRST, F1
XVRST and F1 signals are used to synchronize with external V sync.
XVRST and F1 signals are sampled at the rising edge of SYSCLK in 8-bit mode.
F1 signal is sampled when XVRST is Low. When F1 is High, the internal sync generator is reset to the 1st
field, and when F1 is Low, it is reset to the 2nd field. When XVRST is set at High, digital sync generator starts
operation, and the sequence of 1st or 2nd field starts.
In 8bit mode
XVRST Timing (1st Field)
SYSCLK
XVRST
F1 "H"
Start of 1st field (NTSC: 4H)
(PAL: 1H)
VSYNC
F-ID
HSYNC
XVRST Timing (2nd Field)
SYSCLK
XVRST
F1 "L"
Start of 2nd field (NTSC: 266H)
(PAL: 313H)
VSYNC
F-ID
1/2H
HSYNC
– 17 –
CXD1913AQ
4. Closed Caption
The CXD1913AQ supports closed caption encoding.
ASCII data for closed caption encodes line 21 and line 284 by adding parity bit to ASCII data (data #1 and data
#2 for line 21, data #1 and data #2 for line 284) which is set up for control registers 03H, 04H, 05H and 06H.
Control registers 03H to 06H are double-buffered and ASCII data which is set up by serial interface is
synchronized with VSYNC.
ASCII data reset ON/OFF can be selected in synchronized with VSYNC by setting control register address
02H bit (OOEN).
When OOEN = "1", the first stage buffer ASCII data is cleared at the rising edge of the field in the next VSYNC
where data renewed.
When OOEN = "0" (default), closed caption data is maintained.
Closed Caption Data Renewal Timing
OOEN = "1"
Field
4 FIELD
1 FIELD
VSYNC
Control resisters 03H and 04H set
NEW DATA
SI/SDA
Data 21H
first stage buffer
Data 21H
last stage buffer
Data 284H
first stage buffer
OLD DATA
DATA A
(7'h00)
NEW DATA
OLD DATA
NEW DATA
DATA RESET (7'h00)
Data 284H
last stage buffer
(7'h00)
DATA A
Field
2 FIELD
1 FIELD
VSYNC
Control resisters 05H and 06H set
NEW DATA
SI/SDA
Data 284H
first stage buffer
Data 284H
last stage buffer
Data 21H
first stage buffer
Data 21H
last stage bufer
OLD DATA
DATA A
(7'h00)
NEW DATA
OLD DATA
NEW DATA
DATA RESET (7'h00)
DATA A
– 18 –
(7'h00)
CXD1913AQ
OOEN = "0"
Field
1 FIELD
4 FIELD
VSYNC
Control register 03H and 04H set
SI/SDA
NEW DATA
Data 21H
first stage buffer
NEW DATA
OLD DATA
Data 21H
last stage buffer
OLD DATA
Data 284H
first stage buffer
DATA A
Data 284H
last stage buffer
DATA A
Field
NEW DATA
2 FIELD
1 FIELD
VSYNC
Control register 05H and 06H set
NEW DATA
SI/SDA
Data 284H
first stage buffer
NEW DATA
OLD DATA
Data 284H
last stage buffer
OLD DATA
Data 21H
first stage buffer
DATA A
Data 21H
last stage buffer
DATA A
NEW DATA
Double Buffer for Closed Caption
SI/SDA
03H
ASCII data #1
Load
VSYNC
Closed Caption Signal Waveform
HSYNC
Color
burst
Clock run-in
Start
bits
ASCII data #1
ASCII data #2
S1 S2 S3 b0 b1 b2 b3 b4 b5 b6 P1 b0 b1 b2 b3 b4 b5 b6 P2
50 IRE
– 19 –
CXD1913AQ
5. VBID (Video ID)
The CXD1913AQ supports Video ID (Provisional standard of EIAJ, CPX-1204) encording to perform aspect
ratio identification. VBID is 14-bit data as shown in Table 5-1, and adding 6-bit CRCC results total 20 bits. This
data is put on 20H and 283H in the vertical blanking period of NTSC video signal.
Encordes by adding CRCC to the VBID data which is set up for control registers 07H and 08H by serial
interface. Control registers 07H and 08H are double-buffered and data which is set up by serial interface is
synchronized with VSYNC.
Table 5-1
bit-No.
Contents
A
1
2
3
Transmission aspect ratio
Image display format
Undefined
B
4
5
6
Identification information for video and other signals (aural signal, etc.) which
is propagated at the same with video
WORD 0
"0"
"1"
Full mode (16:9)
Letter box
4:3
Normal
WORD 1
4-bit width
Identification signal subordinated to WORD 0
WORD 2
4-bit width
Identification signal and information subordinated to WORD 0
(Provisional standard of EIAJ, CPX-1204)
VBID Double Buffer
SI/SDA
VSYNC
07H
Load
WORD 0
VBID Data Renewal Timing
VSYNC
Control register 07H set
SI/SDA
NEW DATA
Data #1
OLD DATA
– 20 –
NEW DATA
CXD1913AQ
VBID Code Layout
20-bit data is configured with WORD 0 = 6 bits; its contents are WORD 0-A = 3 bits and WORD 0-B = 3 bits.
And 20-bit data, with WORD 1 = 4 bits, WORD 2 = 4 bits and CRC = 6 bits.
bit 1 ···
··· bit 20
DATA
0-A
0-B
WORD 0
6 bit
WORD 1
4 bit
WORD 2
4 bit
CRC
6 bit
VBID Signal Waveform
IRE
100
Ref.
bit 1 bit 2 bit 3
···
bit 20
70 IRE
0 IRE
0
2.235µs ± 20ns
–40
11.2µs ± 0.6µs
49.1µs ± 0.5µs
1H
6. Interlace and Non interlace Supported
The CXD1913AQ can select interlace output or non interlace output by the set of Bit 1 (INTERLS) of control
register address 01H.
Number of lines/field
Register set value
INTERLS
Scan mode
0
1
NTSC
PAL
Non interlace
262
312
Interlace
262.5
312.5
– 21 –
– 22 –
FID
VSYNC
HSYNC
FID
VSYNC
HSYNC
261
524
262
525
NTSC Vertical Interval (Interlace)
263
2
264
265
Fields 2 and 4
1
3
Pre-equalization
3H
Fields 1 and 3
266
4
267
5
268
Vertical SYNC
3H
6
Vertical blanking
269
7
270
8
271
9
Post-equalization
3H
272
10
273
11
274
19
282
20
283
21
284
22
285
23
CXD1913AQ
– 23 –
FID
VSYNC
HSYNC
FID
VSYNC
HSYNC
620
308
623
310
(3)
622
(4)
309
(3)
(1)
621
(4)
(2)
PAL Vertical Interval (Interlace)
311
624
625
312
2.5H
313
2
3
314
315
Fields 2 and 4
1
2.5H
Fields 1 and 3
316
4
317
2.5H
5
318
7
(3)
(1)
319
(2)
6
(3)
320
(2)
(4)
8
321
20
333
21
334
22
335
23
336
24
CXD1913AQ
– 24 –
FID
VSYNC
HSYNC
FID
VSYNC
HSYNC
261
523
263
264
Field 2 ∗1
2
265
3
266
4
267
5
6
268
3H
1
Vertical SYNC
3H
Vertical blanking
Pre-equalization
Field 1 ∗1
269
7
270
8
3H
271
9
Post-equalization
272
10
∗1 "Field 1" or "Field 2" is used for the convenience of the description of frame.
262
524
NTSC Vertical Interval (Non interlace)
273
11
281
19
282
20
283
21
284
22
285
23
CXD1913AQ
– 25 –
FID
VSYNC
HSYNC
FID
VSYNC
HSYNC
308
620
309
621
PAL Vertical Interval (Non interlace)
311
2H
623
312
624
313
1
314
2.5H
Field 2 ∗1
2
2.5H
315
3
316
2.5H
4
2.5H
317
5
318
6
319
7
8
320
∗1 "Field 1" or "Field 2" is used for the convenience of the description of frame.
310
622
2H
Field 1 ∗1
332
20
333
21
334
22
335
23
336
24
CXD1913AQ
CXD1913AQ
Vertical Synchronization Timing
0.148µs
2.3µs
29.5µs
0.148µs
4.67µs
27.1µs
1/2H
63.555µs
NTSC Equalizing & Synchronizing Pulses
0.296µs
2.37µs
29.63µs
0.296µs
27.3µs
4.67µs
1/2H
64µs
PAL Equalizing & Synchronizing Pulses
– 26 –
CXD1913AQ
Control Register Map
In case "0" or "1" is indicated on the map below, fix that value.
BIT
Function Selection #1
Address
00H
7
6
5
4
3
2
1
0
FIDS
MASK
EN
PIX
EN
1
CBAR
SET UP
0
ENC
MODE
ENC MODE
Encoding mode
0 : PAL encoding mode
1 : NTSC encoding mode (Default)
SET UP
Set up enable
0 : Non set-up level, black = blanking level
1 : 7.5 IRE set-up level insertion (Default)
CBAR
Color bar enable
0 : on-chip color bar output enable (ITU-R100% color bar)
1 : on-chip color bar output disable (Default)
R/W
When CBAR = "0", on-chip color bar generator is valid, and output is ITU-R100%
color bar output.
When CBAR = "1", input pixel data is valid, and output obeys input pixel data.
PIX EN
Pixel data enable
0 : Disable input pixel data
1 : Enable input pixel data (Default)
When input pixel data is disabled, output becomes blanking level or black level
regardless of input PD0 to PD15.
MASK EN
Mask enable
0 : When V-blanking, pixel data through
1 : When V-blanking, pixel data reject (Default)
When MASK EN = “0”, input pixel data during V-blanking interval are valid, and
output obeys input pixel data.
When MASK EN = “1”, input pixel data during V-blanking interval are all invalid,
and output becomes blanking level.
FIDS
FID polarity select
0 : 1st field “H”, 2nd field “L”
1 : 1st field ”L“, 2nd field “H” (Default)
– 27 –
CXD1913AQ
BIT
Function Selection #2
7
Address
01H
6
5
4
3
DAC MODE
0
PIF
MODE
2
PIX TIME
1
0
INTERLS
FREE
RUN
R/W
FREE RUN
Free run
0 : SCH timing is reset every 4 fields for NTSC and every 8 fields for PAL (Default)
1 : No SCH timing reset
INTERLS
Interlace
0 : Interlace (Default)
1 : Non interlace
PIX TIME
Pixel input timing (See the diagram on Page 13.)
0 0 : #0 (Default)
0 1 : #1
1 0 : #2
1 1 : #3
PIF MODE
Pixel input format
0 : 8-bit mode
Multiplexed Y, Cb, Cr (4:2:2) (Default)
1 : 16-bit mode Y and multiplexed Cb, Cr (4:2:2)
DAC MODE
DAC output activity
0 0 : Non-active
0 1 : Y-OUT and C-OUT active
1 0 : Comp-out active
1 1 : Both active (Default)
– 28 –
CXD1913AQ
BIT
Function Selection #3
Address
02H
7
6
5
4
3
2
0
0
0
0
VBID
OOEN
CC MODE
Closed caption encoding mode
0 0 : Disable closed caption encoding (Default)
0 1 : Enable encoding in 1st field (Line 21)
1 0 : Enable encoding in 2nd field (Line 284)
1 1 : Enable encoding in both fields
OOEN
Closed caption data reset
0 : Non reset (Default)
1 : Data reset synchronized with VSYNC
VBID
VBID encode mode
0 : Disable encoding of VBID (Default)
1 : Enable encoding of VBID
– 29 –
1
0
CC MODE
R/W
CXD1913AQ
BIT
Closed Caption Character #1 for 21H
7
6
5
Address
03H
4
3
2
ASCII data #1
1
0
R/W
(Default: 0H)
Closed Caption Character #2 for 21H
7
6
5
Address
04H
4
3
2
ASCII data #2
1
0
R/W
(Default: 0H)
Closed Caption Character #1 for 284H
7
6
5
Address
05H
4
3
2
ASCII data #1
1
0
R/W
(Default: 0H)
Closed Caption Character #2 for 284H
7
6
5
Address
06H
4
3
2
ASCII data #2
1
0
R/W
(Default: 0H)
VBID#1
7
6
5
4
3
2
1
0
WORD 0
Address
07H
WORD 0-B
WORD 0-A
WORD 0-B
WORD 0-A
R/W
VBID#2
7
Address
08H
6
5
4
3
WORD 2
2
1
0
R/W
WORD 1
Device ID#1
7
6
5
4
Address
09H
3
ID Code
2
1
(Lower)
13H
2
1
(Upper)
19H
0
RO
Identification Code: 13H
ID code
Device ID#2
7
Address
0AH
6
5
4
3
ID Code
ID code
Identification Code: 19H
– 30 –
0
RO
CXD1913AQ
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Video Timing
806
806
WHITE LEVEL
748
655
597
506
100 IRE
448
7.5 IRE
355
297
BLACK LEVEL
BLANK LEVEL
256
40 IRE
36
SYNC LEVEL
NTSC Y (Luminance) Video Output Waveform
BLACK
BLUE (±227)
RED (±320)
MAGENTA (±299)
GREEN (±299)
CYAN (±320)
YELLOW (±227)
WHITE
7.5 IRE SETUP
832
622
20 IRE
BLANK LEVEL
512
402
COLOR BURST
192
NTSC C (Chroma) Video Output Waveform
7.5 IRE SETUP
– 31 –
CXD1913AQ
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Video Timing
806
806
WHITE LEVEL
744
643
580
100 IRE
482
419
318
BLANK LEVEL
256
40 IRE
36
SYNC LEVEL
BLACK
BLUE (±245)
RED (±347)
MAGENTA (±324)
GREEN (±324)
CYAN (±347)
YELLOW (±245)
WHITE
NTSC Y (Luminance) Video Output Waveform
No SETUP
859
622
20 IRE
BLANK LEVEL
512
402
COLOR BURST
165
NTSC C (Chroma) Video Output Waveform
No SETUP
– 32 –
CXD1913AQ
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Video Timing
806
806
WHITE LEVEL
744
643
580
100 IRE
482
419
318
BLANK LEVEL
256
43 IRE
SYNC LEVEL
20
BLACK
BLUE (±245)
RED (±347)
MAGENTA (±324)
GREEN (±324)
CYAN (±347)
YELLOW (±245)
WHITE
PAL Y (Luminance) Video Output Waveform
859
630
21.5 IRE
BLANK LEVEL
512
394
COLOR BURST
165
PAL C (Chroma) Video Output Waveform
– 33 –
CXD1913AQ
Interpolation Filter Characteristics
0
Attenuation [dB]
–10
–20
–30
–40
–50
0
1
2
3
4
5
6
7
9
8
10 11 12 13 14
Frequency [MHz]
Chrominance Filter Characteristics
0
Attenuation [dB]
–20
–40
–60
–80
–100
0
1
2
3
4
5
6
Frequency [MHz]
– 34 –
7
8
9
10
CXD1913AQ
Application Circuit 1
CXD1913AQ
AVDD
VG
0.1µF
1kΩ
VREF
3.3kΩ
IREF
AVSS
Buff AMP
0.1µF
Video output
LPF
COMP-O
Y-OUT
C-OUT
75Ω
200Ω
VB
VSS
Application Circuit 2
CXD1856Q
(MPEG1 decoder)
CXD1913AQ
(Video encoder)
8
Y
PD0 to 7
8
C
PD8 to 15
FID
FID
HSYNC
HSYNC
VSYNC
VSYNC
DCLK
13.5MHz
PDCLK
SYSCLK
27MHz
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 35 –
CXD1913AQ
Package Outline
Unit: mm
64PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
51
0.15
20
1
1.0
+ 0.15
0.4 – 0.1
19
16.3
64
+ 0.2
0.1 – 0.05
+ 0.35
2.75 – 0.15
0.8 ± 0.2
32
+ 0.4
14.0 – 0.1
52
17.9 ± 0.4
33
± 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY / PHENOL RESIN
SONY CODE
QFP-64P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP064-P-1420-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
1.5g
JEDEC CODE
– 36 –