Cypress CY29973 3.3v 125-mhz multi-output zero delay buffer Datasheet

CY29973
3.3V 125-MHz Multi-Output Zero Delay Buffer
Features
■
Output Frequency up to 125 MHz
■
Spread Spectrum Compatible
■
12 Clock Outputs: Frequency Configurable
■
Glitch-free Output Clocks Transitioning
■
350 ps max. Output to Output Skew
■
3.3V Power Supply
■
Configurable Output Disable
■
Pin Compatible with MPC973
■
Two Reference Clock Inputs for Dynamic Toggling
■
Industrial Temperature Range: - 40°C to +85°C
■
Oscillator or PECL Reference Input
■
52-Pin TQFP Package
Table 1. Frequency Table[1]
VC0_SEL
FB_SEL2
FB_SEL1
FB_SEL0
FVC0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8x
12x
16x
20x
16x
24x
32x
40x
4x
6x
8x
10x
8x
12x
16x
20x
Note
1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz.
Cypress Semiconductor Corporation
Document #: 38-07291 Rev. *C
•
198 Champion Court
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San Jose, CA 95134-1709
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Revised September 09, 2008
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CY29973
Logic Block Diagram
PECL_CLK
PECL_CLK#
VCO_SEL
PLL_EN
REF_SEL
D Q
TCLK0
TCLK1
Phase
Detector
0
1
0
1
VCO
Sync
Frz
QA1
LPF
TCLK_SEL
QA0
QA2
QA3
FB_IN
D Q
Sync
Frz
QB0
QB1
QB2
FB_SEL2
QB3
MR#/OE
Power-On
Reset
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
FB_OUT
D Q
Sync
Frz
SYNC
/4, /6, /8, /12
SELA(0,1)
2
SELB(0,1)
2
QC1
/4, /6, /8, /10
/2, /4, /6, /8
SELC(0,1)
2
FB_SEL(0,1)
2
QC0
QC2
QC3
/4, /6, /8, /10
/2
0
1
Sync Pulse
Data Generator
SCLK
Output Disable
Circuitry
SDATA
12
INV_CLK
Pinouts
SELB1
SELB0
SELA1
SELA0
QA3
VDDC
QA2
VSS
QA1
VDDC
QA0
VSS
VCO_SEL
52 51 50 49 48 47 46 45 44 43 42 41 40
VSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
CY29973
39
38
37
36
35
34
33
32
31
30
29
28
27
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
QB3
FB_IN
VSS
FB_OUT
VDDC
FB_SEL0
14 15 16 17 18 19 20 21 22 23 24 25 26
FB_SEL1
SYNC
VSS
QC0
VDDC
QC1
SELC0
SELC1
QC2
VDDC
QC3
VSS
INV_CLK
Document #: 38-07291 Rev. *C
Page 2 of 9
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CY29973
Pin Definitions[2]
Pin
Name
PWR
IO
Type
Description
11
PECL_CLK
I
PU
PECL Clock Input.
12
PECL_CLK#
I
PD
PECL Clock Input.
9
TCLK0
I
PU
External Reference or Test Clock Input.
10
TCLK1
I
PU
External Reference or Test Clock Input.
44, 46, 48, 50 QA(3:0)
VDDC
O
Clock Outputs. See Table 2 on page 4 for frequency selections.
32, 34, 36, 38 QB(3:0)
VDDC
O
Clock Outputs. See Table 2 on page 4 for frequency selections.
16, 18, 21, 23 QC(3:0)
VDDC
O
Clock Outputs. See Table 2 on page 4 for frequency selections.
29
FB_OUT
VDDC
O
Feedback Clock Output. Connect to FB_IN for normal operation. The
divider ratio for this output is set by FB_SEL(0:2). See Table 1 on page 1.
A bypass delay capacitor at this output control Input Reference or Output
Banks phase relationships.
25
SYNC
VDDC
O
Synchronous Pulse Output. This output is used for system
synchronization. The rising edge of the output pulse is in sync with both
the rising edges of QA (0:3) and QC(0:3) output clocks regardless of the
divider ratios selected.
42, 43
SELA(1,0)
I
PU
Frequency Select Inputs. These inputs select the divider ratio at QA(0:3)
outputs. See Table 2 on page 4.
40, 41
SELB(1,0)
I
PU
Frequency Select Inputs. These inputs select the divider ratio at QB(0:3)
outputs. See Table 2 on page 4.
19, 20
SELC(1,0)
I
PU
Frequency Select Inputs. These inputs select the divider ratio at QC(0:3)
outputs. See Table 2 on page 4.
5, 26, 27
FB_SEL(2:0)
I
PU
Feedback Select Inputs. These inputs select the divide ratio at FB_OUT
output. See Table 1 on page 1.
52
VCO_SEL
I
PU
VCO Divider Select Input. When set LOW, the VCO output is divided by 2.
When set HIGH, the divider is bypassed. See Table 1 on page 1.
31
FB_IN
I
PU
Feedback Clock Input. Connect to FB_OUT for accessing the PLL.
6
PLL_EN
I
PU
PLL Enable Input. When asserted HIGH, PLL is enabled. When LOW, PLL
is bypassed.
7
REF_SEL
I
PU
Reference Select Input. When HIGH, the PECL inputs are selected. When
LOW, TCLK[0:1] are selected.
8
TCLK_SEL
I
PU
TCLK Select Input. When LOW, TCLK0 is selected. When HIGH TCLK1
is selected.
2
MR#/OE
I
PU
Master Reset or Output Enable Input. When asserted LOW, resets all of
the internal flip-flops and also disables all of the outputs. When pulled
HIGH, releases the internal flip-flops from reset and enables all of the
outputs.
14
INV_CLK
I
PU
Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted. When
set LOW, the inverter is bypassed.
3
SCLK
I
PU
Serial Clock Input. Clocks data at SDATA into the internal register.
4
SDATA
I
PU
Serial Data Input. Input data is clocked to the internal register to enable or
disable individual outputs. This provides flexibility in power management.
17, 22, 28,
33,37, 45, 49
VDDC
3.3V Power Supply for Output Clock Buffers.
13
VDD
3.3V Supply for PLL.
1, 15, 24, 30, VSS
35, 39, 47, 51
Common Ground.
Note
2. A bypass capacitor (0.1μF) must be placed as close as possible to each positive power (<0.2”). If these bypass capacitors are not close to the pins their high frequency
filtering characteristics is cancelled by the lead inductance of the traces.
Document #: 38-07291 Rev. *C
Page 3 of 9
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CY29973
Description
Zero Delay Buffer
The CY29973 has an integrated PLL that provides low-skew and
low-jitter clock outputs for high-performance microprocessors.
Three independent banks of four outputs and an independent
PLL feedback output, FB_OUT, provide exceptional flexibility for
possible output configurations. The PLL is ensured stable
operation given that the VCO is configured to run between 200
MHz to 480 MHz. This allows a wide range of output frequencies
up to125 MHz.
When used as a zero delay buffer the CY29973 is likely to be in
a nested clock tree application. For these applications the
CY29973 offers a low voltage PECL clock input as a PLL
reference. This allows the user to use LVPECL as the primary
clock distribution device to take advantage of its far superior
skew performance. The CY29973 then can lock onto the
LVPECL reference and translate with near zero delay to low
skew outputs.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the input
reference clock set by FB_SEL(0:2) and VCO_SEL select inputs,
refer to Table 1 on page 1. The VCO frequency is then divided
down to provide the required output frequencies. These dividers
are set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs, see
Table 2. For situations were the VCO needs to run at relatively
low frequencies and hence might not be stable, assert VCO_SEL
LOW to divide the VCO frequency by 2. This maintains the
desired output relationships, but provides an enhanced PLL lock
range.
By using one of the outputs as a feedback to the PLL the propagation delay through the device is eliminated. The PLL works to
align the output edge with the input reference edge thus
producing a near zero delay. The reference frequency affects the
static phase offset of the PLL and thus the relative delay between
the inputs and outputs. Because the static phase offset is a
function of the reference clock the Tpd of the CY29973 is a
function of the configuration used.
The CY29973 is also capable of providing inverted output clocks.
When INV_CLK is asserted high, QC2 and QC3 output clocks
are inverted. These clocks could be used as feedback outputs to
the CY29973 or a second PLL device to generate early or late
clocks for a specific design. This inversion does not affect the
output to output skew.
Glitch-Free Output Frequency Transitions
Customarily when output buffers have their internal counter’s
changed “on the fly’ their output clock periods will:
1. Contain short or “runt” clock periods. These are clock cycles
in which the cycle(s) are shorter in period than either the old
or new frequency that is being transitioned to.
2. Contain stretched clock periods. These are clock cycles in
which the cycle(s) are longer in period than either the old or
new frequency that is being transitioned to.
This device specifically includes logic to guarantee that runt and
stretched clock pulses do not occur if the device logic levels of
any or all of the following pins changed “on the fly” while it is
operating: SELA, SELB, SELC, and VCO_SEL.
Table 2. Divider Table
VCO_SEL
SELA1
0
0
0
0
0
1
0
1
1
1
1
1
1
1
SELA0
QA
SELB1
SELB0
0
VCO/8
0
0
VCO/8
0
0
VCO/4
1
VCO/12
0
1
VCO/12
0
1
VCO/8
0
VCO/16
1
0
VCO/16
1
0
VCO/12
1
VCO/24
1
1
VCO/20
1
1
VCO/16
0
0
VCO/4
0
0
VCO/4
0
0
VCO/2
0
1
VCO/6
0
1
VCO/6
0
1
VCO/4
0
VCO/8
1
0
VCO/8
1
0
VCO/6
1
VCO/12
1
1
VCO/10
1
1
VCO/8
Document #: 38-07291 Rev. *C
QB
SELC1
SELC0
QC
Page 4 of 9
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CY29973
SYNC Output
In situations were output frequency relationships are not integer multiples of each other the SYNC output provides a signal for system
synchronization. The CY29973 monitors the relationship between the QA and the QC output clocks. It provides a low going pulse,
one period in duration, one period prior to the coincident rising edges of the QA and QC outputs. The duration and the placement of
the pulse depend on the higher of the QA and QC output frequencies. The following timing diagram illustrates various waveforms for
the SYNC output. Note that the SYNC output is defined for all possible combinations of the QA and QC outputs even though under
some relationships the lower frequency clock could be used as a synchronizing signal.
Figure 1. SYNC Output for Different Input and Out Ratio
VCO
1:1 Mode
QA
QC
SYNC
2:1 Mode
QA
QC
SYNC
3:1 Mode
QC
QA
SYNC
3:2 Mode
QA
QC
SYNC
4:1 Mode
QC
QA
SYNC
4:3 Mode
QA
QC
SYNC
6:1 Mode
QA
QC
SYNC
Document #: 38-07291 Rev. *C
Page 5 of 9
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CY29973
Power Management
The individual output enable or freeze control of the CY29973 allows the user to implement unique power management schemes into
the design. The outputs are stopped in the logic ‘0’ state when the freeze control bits are activated. The serial input register contains
one programmable freeze enable bit for 12 of the 14 output clocks. The QC0 and FB_OUT outputs can not be frozen with the serial
port, this avoids any potential lock up situation must an error occur in the loading of the serial data. An output is frozen when a logic
‘0’ is programmed and enabled when a logic ‘1’ is written. The enabling and freezing of individual outputs is done in such a manner
as to eliminate the possibility of partial “runt” clocks.
The serial input register is programmed through the SDATA input by writing a logic ‘0’ start bit followed by 12 NRZ freeze enable bits.
The period of each SDATA bit equals the period of the free running SCLK signal. The SDATA is sampled on the rising edge of SCLK.
Figure 2. Control Bit Map
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Absolute Maximum Conditions[3]
Operating Temperature:................................ - 40°C to +85°C
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions must be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, Vin and Vout must be constrained to the range:
Maximum ESD protection............................................... 2 kV
VSS < (Vin or Vout) < VDD
Maximum Power Supply:................................................ 5.5V
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
Maximum Input Voltage Relative to VSS:.............. VSS - 0.3V
Maximum Input Voltage Relative to VDD:............. VDD + 0.3V
Storage Temperature: ................................ - 65°C to + 150°C
Maximum Input Current:................................................ ± 20 mA
DC Electrical Specifications VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = - 40°C to +85°C
Min
Typ.
Max
Unit
VIL
Parameter
Input Low Voltage
Description
VSS
–
0.8
V
2.0
–
VDD
VIH
Input High Voltage
VPP
Peak-to-Peak Input Voltage
PECL_CLK
VCMR
Common Mode Range PECL_CLK[4]
IIL
IIH
Input Low
Current[5]
Input High
Current[5]
Conditions
Output Low
Voltage[6]
IOL = 20 mA
VOH
Output High
Voltage[6]
IOH = –20 mA
IDDQ
Quiescent Supply Current
IDDA
PLL Supply Current
VOL
VDD only
V
mV
300
–
1000
VDD – 2.0
–
VDD – 0.6
V
–
–
–120
μA
–
–
120
μA
–
–
0.5
V
2.4
–
–
V
–
10
15
mA
–
15
20
mA
Notes
3. Multiple Supplies: The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range
and the input lies within the VPP specification.
5. Inputs have pull up/pull down resistors that effect input current.
6. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
Document #: 38-07291 Rev. *C
Page 6 of 9
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CY29973
DC Electrical Specifications VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = - 40°C to +85°C
Parameter
IDD
Description
Conditions
Dynamic Supply Current
(continued)
Min
Typ.
Max
Unit
QA and QB at 60 MHz,
QC at 120 MHz, CL=30 pF
–
225
–
mA
QA and QB at 25 MHz,
QC at 50 MHz, CL=30 pF
–
125
–
Cin
Input Pin Capacitance
–
4
–
pF
ZOUT
Output Impedance
15
18
22
Ω
AC Electrical Specifications VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = - 40°C to +85°C [7]
Parameter
Tr/Tf
Description
Conditions
Min
TCLK Input Rise or Fall
Typ.
Max
Unit
–
3.0
ns
Fref
Reference Input Frequency
Note 8
–
Note 8
MHz
FrefDC
Reference Input Duty Cycle
25
–
75
%
Fvco
PLL VCO Lock Range
200
–
480
MHz
Tlock
Maximum PLL lock Time
–
–
10
ms
Time[9]
Tr/Tf
Output Clocks Rise or Fall
Fout
Maximum Output Frequency
0.15
–
1.2
ns
Q (÷2)
0.8V to 2.0V
–
–
125
MHz
Q (÷4)
–
–
120
Q (÷6)
–
–
80
Q (÷8)
FoutDC
Output Duty
tpZL, tpZH
tpLZ, tpHZ
TCCJ
TSKEW
Cycle[9]
–
–
60
TCYCLE/2 - 750
–
TCYCLE/2 + 750
ps
Output Enable
Time[9](all
outputs)
2
–
10
ns
Output Disable
Time[9](all
outputs)
2
–
8
ns
Cycle to Cycle
Jitter[9](peak
to peak)
–
±100
–
ps
Skew[9,10]
–
250
350
ps
- 225
- 25
175
ps
- 70
130
330
- 130
70
270
Any Output to Any Output
Propagation Delay[10,11] PECL_CLK
Tpd
TCLK0
QFB =(³8)
TCLK1
Ordering Information
Part Number
Package Type
Production Flow
CY29973AI[12]
52-pin TQFP
Industrial, – 40°C to +85°C
CY29973AIT[12]
52-pin TQFP– Tape and reel
Industrial, - 40°C to +85°C
CY29973AXI
52-pin TQFP
Industrial, - 40°C to +85°C
CY29973AXIT
52-pin TQFP – Tape and reel
Industrial, - 40°C to +85°C
Pb-Free
Notes
7. Parameters are guaranteed by design and characterization. Not 100% tested in production.
8. Maximum and minimum input reference is limited by VC0 lock range.
9. Outputs loaded with 30pF each.
10. 50Ω transmission line terminated into VDD/2.
11. Tpd is specified for a 50MHz input reference. Tpd does not include jitter.
12. Not recommended for new designs.
Document #: 38-07291 Rev. *C
Page 7 of 9
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CY29973
Package Drawing and Dimensions
Figure 3. 52-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A52B
51-85158-**
Document #: 38-07291 Rev. *C
Page 8 of 9
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CY29973
Document History Page
Document Title: CY29973 3.3V 125-MHz Multi-Output Zero Delay Buffer
Document Number: 38-07291
REV.
ECN
Orig. of
Change
Submission
Date
**
111102
BRK
02/07/02
Description of Change
New data sheet
*A
122883
RBI
12/22/02
Added power up requirements to Maximum Ratings
*B
200081
RGL
01/22/04
Added ZOUT specifications in the DC Electrical Specs
Changed the Package Drawing and Dimension to CY standard
*C
2562606
AESA
09/09/08
Updated template. Added Note “Not recommended for new designs.”
Added part number CY29973AXI and CY29973AXIT in ordering information
table.
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07291 Rev. *C
Revised September 09, 2008
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