Freescale Semiconductor, Inc. Data Sheet: Technical Data K21P121M120SF5 Rev 4, 11/2014 Kinetis K21F Sub-Family Data Sheet MK21FX512VMC12 MK21FN1M0VMC12 120 MHz ARM® Cortex®-M4-based Microcontroller with FPU The K21 product family members are optimized for cost-sensitive applications requiring low-power, USB connectivity, processing efficiency with floating point unit and the need for extensive tamper protection, such as Electronic Point of Sales. It shares the comprehensive enablement and scalability of the Kinetis family. This product offers: • Up to 1 MB of flash memory with up to 128 KB of SRAM 121 MAPBGA • DryIce Tamper Detection with active/passive pin, 8 x 8 x 1.4 mm Pitch 0.65 mm temperature, clock, supply voltage monitoring • Run power consumption down to 279 μA/MHz. Static power consumption down to 5.1 μA with full state retention and 5 μs wakeup. Lowest Static mode down to 268 nA • USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO voltage regulator Performance • Up to 120 MHz ARM Cortex-M4-based core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz Memories and memory interfaces • Up to 1 MB program flash memory and 128 KB RAM • Up to 128 KB FlexNVM and 4 KB FlexRAM on FlexMemory devices • FlexBus external bus interface System peripherals • Multiple low-power modes; low leakage wakeup unit • Memory protection unit with multi-master protection • 16-channel DMA controller • External watchdog monitor and software watchdog Security and integrity modules • Hardware CRC module • Tamper detect and secure storage • Hardware random-number generator • Hardware encryption • 128-bit unique identification (ID) number per chip Analog modules • Two 16-bit SAR ADCs • Two 12-bit DACs Communication interfaces • USB full-/low-speed On-the-Go controller • USB Device Charger detect • Controller Area Network (CAN) module • Three SPI modules • Three I2C modules • Six UART modules • Secure Digital host controller (SDHC) • I2S module Timers • Two 8-channel Flex-Timers (PWM/Motor Control) • Two 2-channel Flex-Timers (PWM/Quad Decoder) • Periodic interrupt timers and 16-bit low-power timer • Carrier modulator transmitter • Real-time clock • Programmable delay block Clocks • 3 to 32 MHz and 32 kHz crystal oscillator • PLL, FLL, and multiple internal oscillators Operating Characteristics • Voltage range: 1.71 to 3.6 V • Flash write voltage range: 1.71 to 3.6 V • Temperature range (ambient): –40 to 105°C Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2013–2015 Freescale Semiconductor, Inc. All rights reserved. • Three analog comparators (CMP) • Voltage reference Ordering Information 1 Part Number Memory Maximum number of I\O's Flash (KB) SRAM (KB) MK21FX512VMC12 512 KB 128 81 MK21FN1M0VMC12 1 MB 128 81 1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number search. Related Resources Type Description Resource Selector Guide The Freescale Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. K20PB1 Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. K21P121M50SF5RM1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. K21P121M50SF51 Package drawing Package dimensions are provided in package drawings. • MAPBGA 121-pin: 98ASA00344D1 1. To find the associated resource, go to http://www.freescale.com and perform a search using this term. 2 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Kinetis K21D Family ARM ® Cortex™-M4 Core System Memories and Memory Interfaces Internal and external watchdogs Program flash RAM Clocks Phaselocked loop Debug interfaces DSP DMA FlexMemory Frequencylocked loop Interrupt controller Floating point Low-leakage wakeup Serial programming interface Low/high frequency oscillators Internal reference clocks Security and Integrity CRC Analog 16-bit ADC Timers Communication Interfaces 2 2 FlexTimers I C I S Carrier modulator transmitter UART USB OTG LS/FS/HS SPI USB LS/FS transceiver Random number generator Analog comparator Hardware encryption 6-bit DAC Tamper detect 12-bit DAC Periodic interrupt timers USB charger detect Voltage reference Low power timer USB voltage regulator Programmable delay block Human-Machine Interface (HMI) GPIO Independent real-time clock Figure 1. K20 block diagram Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 3 Freescale Semiconductor, Inc. Table of Contents 1 Ratings.................................................................................... 5 1.1 Thermal handling ratings................................................. 5 1.2 Moisture handling ratings................................................ 5 1.3 ESD handling ratings....................................................... 5 1.4 Voltage and current operating ratings............................. 5 2 General................................................................................... 6 2.1 AC electrical characteristics.............................................6 2.2 Nonswitching electrical specifications..............................7 2.2.1 Voltage and current operating requirements.....7 2.2.2 LVD and POR operating requirements............. 8 2.2.3 Voltage and current operating behaviors.......... 9 2.2.4 Power mode transition operating behaviors......10 2.2.5 Power consumption operating behaviors.......... 11 2.2.6 EMC radiated emissions operating behaviors...15 2.2.7 Designing with radiated emissions in mind....... 16 2.2.8 Capacitance attributes...................................... 16 2.3 Switching specifications...................................................16 2.3.1 Device clock specifications............................... 16 2.3.2 General switching specifications....................... 17 2.4 Thermal specifications..................................................... 18 2.4.1 Thermal operating requirements....................... 18 2.4.2 Thermal attributes............................................. 18 3 Peripheral operating requirements and behaviors.................. 19 3.1 Core modules.................................................................. 20 3.1.1 Debug trace timing specifications..................... 20 3.1.2 JTAG electricals................................................ 20 3.2 System modules.............................................................. 23 3.3 Clock modules................................................................. 23 3.3.1 MCG specifications........................................... 23 3.3.2 Oscillator electrical specifications..................... 26 3.3.3 32 kHz oscillator electrical characteristics.........28 3.4 Memories and memory interfaces................................... 28 4 Freescale Semiconductor, Inc. 4 5 6 7 8 3.4.1 Flash (FTFE) electrical specifications............... 28 3.4.2 EzPort switching specifications......................... 33 3.4.3 Flexbus switching specifications....................... 34 3.5 Security and integrity modules........................................ 37 3.5.1 DryIce Tamper Electrical Specifications............37 3.6 Analog............................................................................. 38 3.6.1 ADC electrical specifications.............................38 3.6.2 CMP and 6-bit DAC electrical specifications.....42 3.6.3 12-bit DAC electrical characteristics................. 44 3.6.4 Voltage reference electrical specifications........ 47 3.7 Timers..............................................................................48 3.8 Communication interfaces............................................... 48 3.8.1 USB electrical specifications............................. 48 3.8.2 USB DCD electrical specifications.................... 49 3.8.3 USB VREG electrical specifications..................49 3.8.4 CAN switching specifications............................ 50 3.8.5 DSPI switching specifications (limited voltage range)................................................................50 3.8.6 DSPI switching specifications (full voltage range)................................................................52 3.8.7 I2C switching specifications.............................. 53 3.8.8 UART switching specifications.......................... 54 3.8.9 SDHC specifications......................................... 54 3.8.10 I2S switching specifications.............................. 55 Dimensions............................................................................. 67 4.1 Obtaining package dimensions....................................... 67 Pinout...................................................................................... 68 5.1 K21 Signal Multiplexing and Pin Assignments.................68 5.2 K21 Pinouts..................................................................... 73 Revision History...................................................................... 74 Copyright................................................................................. 0 Legal....................................................................................... 0 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Ratings 1 Ratings 1.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105°C -100 +100 mA 3 ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 1.4 Voltage and current operating ratings Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 5 Freescale Semiconductor, Inc. General Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V IDD Digital supply current — 185 mA VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V VAIO Analog1, –0.3 VDD + 0.3 V ID VDDA RESET, EXTAL, and XTAL input voltage Maximum current single pin limit (applies to all digital pins) Analog supply voltage –25 25 mA VDD – 0.3 VDD + 0.3 V VUSB0_DP USB0_DP input voltage –0.3 3.63 V VUSB0_DM USB0_DM input voltage –0.3 3.63 V RTC battery supply voltage –0.3 3.8 V VBAT 1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 2 General 2.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. VIH Input Signal High Low 80% 50% 20% Midpoint1 Fall Time VIL Rise Time The midpoint is VIL + (VIH - VIL) / 2 Figure 2. Input signal measurement reference All digital I/O switching characteristics assume: 1. output pins • have CL=30pF loads, • are configured for fast slew rate (PORTx_PCRn[SRE]=0), and • are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins • have their passive filter disabled (PORTx_PCRn[PFE]=0) 6 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. General 2.2 Nonswitching electrical specifications 2.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V 1.71 3.6 V • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.71 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V • 2.7 V ≤ VDD ≤ 3.6 V — 0.35 × VDD V • 1.71 V ≤ VDD ≤ 2.7 V — 0.3 × VDD V 0.06 × VDD — V -5 — mA VBAT VIH VIL RTC battery supply voltage Notes Input high voltage Input low voltage VHYS Input hysteresis IICDIO Digital pin (except Tamper pins) negative DC injection current — single pin 1 • VIN < VSS-0.3V IICAIO IICcont Analog2, EXTAL, and XTAL pin DC injection current — single pin 3 mA • VIN < VSS-0.3V (Negative current injection) -5 — • VIN > VDD+0.3V (Positive current injection) — +5 -25 — — +25 Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins • Negative current injection • Positive current injection mA VODPU Open drain pullup voltage level VDD VDD V VRAM VDD voltage required to retain RAM 1.2 — V VPOR_VBAT — V VRFVBAT VBAT voltage required to retain the VBAT register file 4 1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 7 Freescale Semiconductor, Inc. General 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and XTAL are analog pins. 3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/| IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative injection currents. 4. Open drain outputs must be pulled to VDD. 2.2.2 LVD and POR operating requirements Table 2. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V VLVDH Falling low-voltage detect threshold — high range (LVDV=01) 2.48 2.56 2.64 V Low-voltage warning thresholds — high range 1 VLVW1H • Level 1 falling (LVWV=00) 2.62 2.70 2.78 V VLVW2H • Level 2 falling (LVWV=01) 2.72 2.80 2.88 V VLVW3H • Level 3 falling (LVWV=10) 2.82 2.90 2.98 V VLVW4H • Level 4 falling (LVWV=11) 2.92 3.00 3.08 V — 80 — mV 1.54 1.60 1.66 V VHYSH Low-voltage inhibit reset/recover hysteresis — high range VLVDL Falling low-voltage detect threshold — low range (LVDV=00) Low-voltage warning thresholds — low range 1 VLVW1L • Level 1 falling (LVWV=00) 1.74 1.80 1.86 V VLVW2L • Level 2 falling (LVWV=01) 1.84 1.90 1.96 V VLVW3L • Level 3 falling (LVWV=10) 1.94 2.00 2.06 V VLVW4L • Level 4 falling (LVWV=11) 2.04 2.10 2.16 V — 60 — mV VHYSL Low-voltage inhibit reset/recover hysteresis — low range Notes VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising threshold is the sum of falling threshold and hysteresis voltage Table 3. VBAT power operating requirements Symbol Description VPOR_VBAT Falling VBAT supply POR detect voltage 8 Freescale Semiconductor, Inc. Min. Typ. Max. Unit 0.8 1.1 1.5 V Notes Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. General 2.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol VOH Description Min. Typ Max. Unit • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -8mA VDD – 0.5 — — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA VDD – 0.5 — — V • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA VDD – 0.5 — — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA VDD – 0.5 — — V — — 100 mA Notes Output high voltage — high drive strength Output high voltage — low drive strength IOHT Output high current total for all ports VOH_Tamper Output high voltage — high drive strength • 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -10mA VBAT – 0.5 VBAT – 0.5 • 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -3mA Output high voltage — low drive strength • 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -2mA VOL — — — — VBAT – 0.5 VBAT – 0.5 • 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -0.6mA IOH_Tamper Output high current total for Tamper pins V — V V — — — — — 100 V mA Output low voltage — high drive strength 1 • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA — — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA — — 0.5 V • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA — — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA — — 0.5 V — — 100 mA 0.5 V 0.5 V 0.5 V 0.5 V 100 mA Output low voltage — low drive strength IOLT Output low current total for all ports VOL_Tamper Output low voltage — high drive strength • 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 10mA — — • 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 3mA — — Output low voltage — low drive strength • 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 2mA — — • 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 0.6mA — — — — IOL_Tamper Output low current total for Tamper pins IIND 2, Input leakage current, digital pins • VSS ≤ VIN ≤ VIL • All digital pins — 0.002 0.5 3 μA Table continues on the next page... Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 9 Freescale Semiconductor, Inc. General Table 4. Voltage and current operating behaviors (continued) Symbol Description Min. Typ Max. Unit — 0.002 0.5 μA — 0.004 1 μA Notes • VIN = VDD • All digital pins except PTD7 • PTD7 IIND Input leakage current, digital pins • VIL < VIN < VDD 2 • VDD = 3.6 V — 18 26 μA • VDD = 3.0 V — 12 19 μA • VDD = 2.5 V — 8 13 μA • VDD = 1.7 V — 3 6 μA Input leakage current, digital pins • VDD < VIN < 5.5 V — 1 50 μA IIN_Tamper Input leakage current (per Tamper pin) for full temperature range — — 1 μA IIN_Tamper Input leakage current (per Tamper pin) at 25°C — — 0.025 μA — — 0.25 μA — — 0.25 μA IIND IOZ Hi-Z (off-state) leakage current (per pin) IOZ_Tamper Hi-Z (off-state) leakage current (per Tamper pin) 1. 2. 3. 4. 5. RPU Internal pullup resistors (except Tamper pins) 20 35 50 kΩ 4 RPD Internal pulldown resistors (except Tamper pins) 20 35 50 kΩ 5 Open drain outputs must be pulled to VDD. Measured at VDD=3.6V Internal pull-up/pull-down resistors disabled. Measured at VDD supply voltage = VDD min and Vinput = VSS Measured at VDD supply voltage = VDD min and Vinput = VDD 2.2.4 Power mode transition operating behaviors All specifications except tPOR, and VLLSx→RUN recovery times in the following table assume this clock configuration: • • • • CPU and system clocks = 100 MHz Bus clock = 50 MHz FlexBus clock = 50 MHz Flash clock = 25 MHz 10 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. General Table 5. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. • VLLS0 → RUN • VLLS1 → RUN • VLLS2 → RUN • VLLS3 → RUN • LLS → RUN • VLPS → RUN • STOP → RUN Min. Max. Unit — 300 μs — 183 μs — 183 μs — 105 μs — 105 μs — 5.0 μs — 4.4 μs — 4.4 μs Notes 2.2.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol IDDA IDD_RUN Description Analog supply current Typ. Max. Unit Notes — — See note mA 1 Run mode current — all peripheral clocks disabled, code executing from flash • @ 1.8V • @ 3.0V IDD_RUN Min. 2 — 33.57 36.2 mA — 33.51 36.1 mA Run mode current — all peripheral clocks enabled, code executing from flash • @ 1.8V • @ 3.0V • @ 25°C 3, 4 — 46.36 50.1 mA — 46.31 49.9 mA — 57.4 — mA • @ 125°C IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 18.2 — mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 7.2 — mA 5 Table continues on the next page... Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 11 Freescale Semiconductor, Inc. General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 1.21 — mA 6 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — 1.88 — mA 7 — 0.80 — mA 8 • @ –40 to 25°C — 0.528 2.25 mA • @ 70°C — 1.6 8 mA • @ 105°C — 5.2 20 mA • @ –40 to 25°C — 78 700 μA • @ 70°C — 498 2400 μA • @ 105°C — 1300 3600 μA • @ –40 to 25°C — 5.1 15 μA • @ 70°C — 28 80 μA • @ 105°C — 124 300 μA • @ –40 to 25°C — 3.1 7.5 μA • @ 70°C — 14.5 45 μA • @ 105°C — 63.5 195 μA • @ –40 to 25°C — 2.0 5 μA • @ 70°C — 6.9 32 μA • @ 105°C — 30 112 μA • @ –40 to 25°C — 1.25 2.1 μA • @ 70°C — 6.5 18.5 μA • @ 105°C — 37 108 μA — 0.745 1.65 μA — 6.03 18 μA — 37 108 μA IDD_VLPW Very-low-power wait mode current at 3.0 V — all peripheral clocks disabled IDD_STOP IDD_VLPS IDD_LLS Stop mode current at 3.0 V Very-low-power stop mode current at 3.0 V Low leakage stop mode current at 3.0 V IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit enabled • @ –40 to 25°C • @ 70°C • @ 105°C Table continues on the next page... 12 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit — 0.268 1.25 μA — 3.7 15 μA — 22.9 95 μA — 0.19 0.22 μA — 0.49 0.64 μA — 2.2 3.2 μA Notes IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit disabled • @ –40 to 25°C • @ 70°C • @ 105°C IDD_VBAT Average current with RTC and 32kHz disabled at 3.0 V • @ –40 to 25°C • @ 70°C • @ 105°C IDD_VBAT Average current when CPU is not accessing RTC registers 9 • @ 1.8V • @ –40 to 25°C • @ 70°C • @ 105°C — 0.68 0.8 μA — 1.2 1.56 μA — 3.6 5.3 μA — 0.81 0.96 μA — 1.45 1.89 μA — 4.3 6.33 μA • @ 3.0V • @ –40 to 25°C • @ 70°C • @ 105°C 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 120 MHz core and system clock, 60 MHz bus 40 Mhz and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE mode. All peripheral clocks disabled. 3. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled. 4. Max values are measured with CPU executing DSP instructions. 5. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI mode. 6. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 7. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 9. Includes 32kHz oscillator current and RTC operation. 2.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: • MCG in PEE mode at greater than 100 MHz frequencies Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 13 Freescale Semiconductor, Inc. General • No GPIOs toggled • Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFE Figure 3. Run mode supply current vs. core frequency 14 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. General Figure 4. VLPR mode supply current vs. core frequency 2.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors Symbol Description Frequency band (MHz) Typ. Unit Notes 1, 2 VRE1 Radiated emissions voltage, band 1 0.15–50 23 dBμV VRE2 Radiated emissions voltage, band 2 50–150 27 dBμV VRE3 Radiated emissions voltage, band 3 150–500 28 dBμV VRE4 Radiated emissions voltage, band 4 500–1000 14 dBμV IEC level 0.15–1000 K — VRE_IEC 2, 3 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 15 Freescale Semiconductor, Inc. General application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 2.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for “EMC design.” 2.2.8 Capacitance attributes Table 8. Capacitance attributes Symbol Description Min. Max. Unit CIN_A Input capacitance: analog pins — 7 pF CIN_D Input capacitance: digital pins — 7 pF 2.3 Switching specifications 2.3.1 Device clock specifications Table 9. Device clock specifications Symbol Description Min. Max. Unit System and core clock — 120 MHz System and core clock when Full Speed USB in operation 20 — MHz Bus clock — 60 MHz FlexBus clock — 50 MHz fFLASH Flash clock — 25 MHz fLPTMR LPTMR clock — 25 MHz Notes Normal run mode fSYS fSYS_USB fBUS FB_CLK VLPR mode1 fSYS System and core clock — 4 MHz fBUS Bus clock — 4 MHz Table continues on the next page... 16 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. General Table 9. Device clock specifications (continued) Symbol Description Min. Max. Unit FB_CLK FlexBus clock — 4 MHz fFLASH Flash clock — 0.8 MHz fERCLK External reference clock — 16 MHz LPTMR clock — 25 MHz fLPTMR_ERCLK LPTMR external reference clock fLPTMR_pin — 16 MHz fFlexCAN_ERCLK FlexCAN external reference clock — 8 MHz fI2S_MCLK I2S master clock — 12.5 MHz fI2S_BCLK I2S bit clock — 4 MHz Notes 1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 2.3.2 General switching specifications These general purpose specifications apply to all pins configured for: • GPIO signaling • Other peripheral module signaling not explicitly stated elsewhere Table 10. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.5 — Bus clock cycles 1, 2 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) — Asynchronous path 100 — ns 3 GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) — Asynchronous path 16 — ns 3 External reset pulse width (digital glitch filter disabled) 100 — ns 3 Mode select (EZP_CS) hold time after reset deassertion 2 — Bus clock cycles Port rise and fall time (high drive strength) 4 • Slew disabled • 1.71 ≤ VDD ≤ 2.7V — 12 ns • 2.7 ≤ VDD ≤ 3.6V — 6 ns • 1.71 ≤ VDD ≤ 2.7V — 36 ns • 2.7 ≤ VDD ≤ 3.6V — 24 ns • Slew enabled Table continues on the next page... Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 17 Freescale Semiconductor, Inc. General Table 10. General switching specifications (continued) Symbol Description Min. Max. Unit Notes Port rise and fall time (low drive strength) 5 • Slew disabled • 1.71 ≤ VDD ≤ 2.7V — 12 ns • 2.7 ≤ VDD ≤ 3.6V — 6 ns • 1.71 ≤ VDD ≤ 2.7V — 36 ns • 2.7 ≤ VDD ≤ 3.6V — 24 ns • Slew enabled 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75 pF load 5. 15 pF load 2.4 Thermal specifications 2.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature –40 125 °C TA Ambient temperature –40 105 °C 2.4.2 Thermal attributes Board type Symbol Description 121 MAPBGA Unit Notes Single-layer (1s) RθJA Thermal 65 resistance, junction to ambient (natural convection) °C/W 1 Four-layer (2s2p) RθJA Thermal 36 resistance, junction to ambient °C/W 1 Table continues on the next page... 18 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors Board type Symbol Description 121 MAPBGA Unit Notes (natural convection) Single-layer (1s) RθJMA Thermal 52 resistance, junction to ambient (200 ft./min. air speed) °C/W 1 Four-layer (2s2p) RθJMA Thermal 31 resistance, junction to ambient (200 ft./min. air speed) °C/W 1 — RθJB Thermal resistance, junction to board 17 °C/W 2 — RθJC Thermal resistance, junction to case 13 °C/W 3 — ΨJT Thermal characterization parameter, junction to package top outside center (natural convection) 3 °C/W 4 Notes 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). 3 Peripheral operating requirements and behaviors Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 19 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3.1 Core modules 3.1.1 Debug trace timing specifications Table 12. Debug trace operating behaviors Symbol Description Min. Max. Tcyc Clock period Twl Low pulse width 2 — ns Twh High pulse width 2 — ns Tr Clock and data rise time — 3 ns Tf Clock and data fall time — 3 ns Ts Data setup 3 — ns Th Data hold 2 — ns Frequency dependent (limited to 50 MHz) Unit MHz TRACECLK Tr Tf Twh Twl Tcyc Figure 5. TRACE_CLKOUT specifications TRACE_CLKOUT Ts Th Ts Th TRACE_D[3:0] Figure 6. Trace data specifications 20 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors 3.1.2 JTAG electricals Table 13. JTAG limited voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 2.7 3.6 V TCLK frequency of operation MHz • Boundary Scan 0 10 • JTAG and CJTAG 0 25 • Serial Wire Debug 0 50 1/J1 — ns • Boundary Scan 50 — ns • JTAG and CJTAG 20 — ns • Serial Wire Debug 10 — ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 2.6 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 17 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns Unit J2 TCLK cycle period J3 TCLK clock pulse width Table 14. JTAG full voltage range electricals Symbol J1 Description Min. Max. Operating voltage 1.71 3.6 TCLK frequency of operation V MHz • Boundary Scan 0 10 • JTAG and CJTAG 0 20 • Serial Wire Debug 0 40 1/J1 — ns • Boundary Scan 50 — ns • JTAG and CJTAG 25 — ns • Serial Wire Debug 12.5 — ns J2 TCLK cycle period J3 TCLK clock pulse width Table continues on the next page... Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 21 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 14. JTAG full voltage range electricals (continued) Symbol Description Min. Max. Unit J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns J11 TCLK low to TDO data valid — 22.1 ns J12 TCLK low to TDO high-Z — 22.1 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns J2 J3 J3 TCLK (input) J4 J4 Figure 7. Test clock input timing TCLK J5 Data inputs J6 Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 8. Boundary scan (JTAG) timing 22 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 9. Test Access Port timing TCLK J14 J13 TRST Figure 10. TRST timing 3.2 System modules There are no specifications necessary for the device's system modules. 3.3 Clock modules Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 23 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3.3.1 MCG specifications Table 15. MCG specifications Symbol Description Min. Typ. Max. Unit fints_ft Internal reference frequency (slow clock) — factory trimmed at nominal VDD and 25 °C — 32.768 — kHz fints_t Internal reference frequency (slow clock) — user trimmed 31.25 — 39.0625 kHz Iints Internal reference (slow clock) current Notes — 20 — µA Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM — ± 0.3 ± 0.6 %fdco 1 Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM only — ± 0.2 ± 0.5 %fdco 1 Δfdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature — ± 0.5 ±2 %fdco Δfdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0–70°C — ± 0.3 ±1 %fdco fintf_ft Internal reference frequency (fast clock) — factory trimmed at nominal VDD and 25°C — 4 — MHz fintf_t Internal reference frequency (fast clock) — user trimmed at nominal VDD and 25 °C 3 — 5 MHz Internal reference (fast clock) current — 25 — µA Iintf floc_low Loss of external clock minimum frequency — RANGE = 00 (3/5) x fints_t — — kHz floc_high Loss of external clock minimum frequency — RANGE = 01, 10, or 11 (16/5) x fints_t — — kHz 31.25 — 39.0625 kHz 20 20.97 25 MHz 40 41.94 50 MHz 60 62.91 75 MHz 80 83.89 100 MHz — 23.99 — MHz — 47.97 — MHz — 71.99 — MHz 1 ,2 1 FLL ffll_ref fdco FLL reference frequency range DCO output frequency range Low range (DRS=00) 3, 4 640 × ffll_ref Mid range (DRS=01) 1280 × ffll_ref Mid-high range (DRS=10) 1920 × ffll_ref High range (DRS=11) 2560 × ffll_ref fdco_t_DMX3 DCO output frequency 2 Low range (DRS=00) 5, 6 732 × ffll_ref Mid range (DRS=01) 1464 × ffll_ref Mid-high range (DRS=10) Table continues on the next page... 24 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors Table 15. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit — 95.98 — MHz — 180 — — 150 — — — 1 ms 48.0 — 120 MHz — 1060 — µA — 600 — µA 2.0 — 4.0 MHz Notes 2197 × ffll_ref High range (DRS=11) 2929 × ffll_ref Jcyc_fll FLL period jitter • fDCO = 48 MHz • fDCO = 98 MHz tfll_acquire FLL target frequency acquisition time ps 7 PLL fvco VCO operating frequency Ipll PLL operating current • PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) Ipll PLL operating current • PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) fpll_ref PLL reference frequency range Jcyc_pll PLL period jitter (RMS) Jacc_pll • fvco = 48 MHz — 120 — ps • fvco = 120 MHz — 75 — ps PLL accumulated jitter over 1µs (RMS) 9 • fvco = 48 MHz — 1350 — ps • fvco = 120 MHz — 600 — ps Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % Lock detector detection time 8 9 Dlock tpll_lock 8 — — 10-6 150 × + 1075(1/ fpll_ref) s 10 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. 2 V <= VDD <= 3.6 V. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 25 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3.3.2 Oscillator electrical specifications 3.3.2.1 Oscillator DC electrical specifications Table 16. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDOSC IDDOSC Supply current — low-power mode (HGO=0) Notes 1 • 32 kHz — 600 — nA • 4 MHz — 200 — μA • 8 MHz (RANGE=01) — 300 — μA • 16 MHz — 950 — μA • 24 MHz — 1.2 — mA • 32 MHz — 1.5 — mA Supply current — high gain mode (HGO=1) 1 • 32 kHz — 7.5 — μA • 4 MHz — 500 — μA • 8 MHz (RANGE=01) — 650 — μA • 16 MHz — 2.5 — mA • 24 MHz — 3.25 — mA • 32 MHz — 4 — mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ RS 2, 4 Series resistor — high-frequency, high-gain mode (HGO=1) Table continues on the next page... 26 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors Table 16. Oscillator DC electrical specifications (continued) Symbol Vpp5 1. 2. 3. 4. 5. Description Min. Typ. Max. Unit — 0 — kΩ Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V Notes VDD=3.3 V, Temperature =25 °C, Internal capacitance = 20 pf See crystal or resonator manufacturer's recommendation Cx,Cy can be provided by using either the integrated capacitors or by using external components. When low power mode is selected, RF is integrated and must not be attached externally. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.2.2 Symbol Oscillator frequency specifications Table 17. Oscillator frequency specifications Min. Typ. Max. Unit Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00) 32 — 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency — high-frequency mode (low range) (MCG_C2[RANGE]=01) 3 — 8 MHz fosc_hi_2 Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 — 32 MHz fec_extal Input clock frequency (external clock mode) — — 50 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time — 32 kHz low-frequency, low-power mode (HGO=0) — 750 — ms Crystal startup time — 32 kHz low-frequency, high-gain mode (HGO=1) — 250 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) — 0.6 — ms Crystal startup time — 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) — 1 — ms fosc_lo tcst Description Notes 1, 2 3, 4 1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 27 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. NOTE The 32 kHz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 3.3.3 32 kHz oscillator electrical characteristics 3.3.3.1 32 kHz oscillator DC electrical specifications Table 18. 32kHz oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VBAT Supply voltage 1.71 — 3.6 V Internal feedback resistor — 100 — MΩ Cpara Parasitical capacitance of EXTAL32 and XTAL32 — 5 7 pF Vpp1 Peak-to-peak amplitude of oscillation — 0.6 — V RF 1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.3.2 Symbol fosc_lo tstart 32 kHz oscillator frequency specifications Table 19. 32 kHz oscillator frequency specifications Description Min. Typ. Max. Unit Oscillator crystal — 32.768 — kHz Crystal start-up time — 1000 — ms 1 700 — VBAT mV 2, 3 vec_extal32 Externally provided input clock amplitude Notes 1. Proper PC board layout procedures must be followed to achieve specifications. 2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The oscillator remains enabled and XTAL32 must be left unconnected. 3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied clock must be within the range of VSS to VBAT. 3.4 Memories and memory interfaces 28 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors 3.4.1 Flash (FTFE) electrical specifications This section describes the electrical characteristics of the FTFE module. 3.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 20. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm8 thversscr Notes Program Phrase high-voltage time — 7.5 18 μs Erase Flash Sector high-voltage time — 13 113 ms 1 thversblk128k Erase Flash Block high-voltage time for 128 KB — 104 904 ms 1 thversblk512k Erase Flash Block high-voltage time for 512 KB — 416 3616 ms 1 Notes 1. Maximum time based on expectations at cycling end-of-life. 3.4.1.2 Symbol Flash timing specifications — commands Table 21. Flash command timing specifications Description Min. Typ. Max. Unit Read 1s Block execution time trd1blk128k • 128 KB data flash — — 0.5 ms trd1blk512k • 512 KB program flash — — 1.8 ms trd1sec4k Read 1s Section execution time (4 KB flash) — — 100 μs 1 tpgmchk Program Check execution time — — 95 μs 1 trdrsrc Read Resource execution time — — 40 μs 1 tpgm8 Program Phrase execution time — 90 150 μs Erase Flash Block execution time 2 tersblk128k • 128 KB data flash — 110 925 ms tersblk512k • 512 KB program flash — 435 3700 ms Erase Flash Sector execution time — 15 115 ms Program Section execution time (1KB flash) — 5 — ms tersscr tpgmsec1k 2 Read 1s All Blocks execution time trd1allx • FlexNVM devices — — 2.2 ms trdonce Read Once execution time — — 30 μs tpgmonce 1 Program Once execution time — 90 — μs tersall Erase All Blocks execution time — 870 7400 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 Table continues on the next page... Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 29 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 21. Flash command timing specifications (continued) Symbol Description Min. Typ. Max. Unit Notes Swap Control execution time tswapx01 • control code 0x01 — 200 — μs tswapx02 • control code 0x02 — 90 150 μs tswapx04 • control code 0x04 — 90 150 μs tswapx08 • control code 0x08 — — 30 μs Program Partition for EEPROM execution time tpgmpart32k • 32 KB EEPROM backup — 70 — ms tpgmpart128k • 128 KB EEPROM backup — 75 — ms • Control Code 0xFF — 70 — μs tsetram32k • 32 KB EEPROM backup — 0.8 1.2 ms tsetram64k • 64 KB EEPROM backup — 1.3 1.9 ms tsetram128k • 128 KB EEPROM backup — 2.4 3.1 ms — 175 275 μs Set FlexRAM Function execution time: tsetramff teewr8bers Byte-write to erased FlexRAM location execution time 3 Byte-write to FlexRAM execution time: teewr8b32k • 32 KB EEPROM backup — 385 1700 μs teewr8b64k • 64 KB EEPROM backup — 475 2000 μs teewr8b128k • 128 KB EEPROM backup — 650 2350 μs — 175 275 μs teewr16bers 16-bit write to erased FlexRAM location execution time 16-bit write to FlexRAM execution time: teewr16b32k • 32 KB EEPROM backup — 385 1700 μs teewr16b64k • 64 KB EEPROM backup — 475 2000 μs teewr16b128k • 128 KB EEPROM backup — 650 2350 μs — 360 550 μs teewr32bers 32-bit write to erased FlexRAM location execution time 32-bit write to FlexRAM execution time: teewr32b32k • 32 KB EEPROM backup — 630 2000 μs teewr32b64k • 64 KB EEPROM backup — 810 2250 μs teewr32b128k • 128 KB EEPROM backup — 1200 2650 μs 1. Assumes 25MHz or greater flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. 30 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors 3.4.1.3 Flash high voltage current behaviors Table 22. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 3.4.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation — 3.5 7.5 mA Average current adder during high voltage flash erase operation — 1.5 4.0 mA Reliability specifications Table 23. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles 5 50 — years tnvmretp1k Data retention after up to 1 K cycles 20 100 — years nnvmcycp Cycling endurance 10 K 50 K — cycles tnvmretd10k Data retention after up to 10 K cycles 5 50 — years tnvmretd1k Data retention after up to 1 K cycles 20 100 — years nnvmcycd Cycling endurance 10 K 50 K — cycles 2 Data Flash 2 FlexRAM as EEPROM tnvmretee100 Data retention up to 100% of write endurance 5 50 — years tnvmretee10 Data retention up to 10% of write endurance 20 100 — years 20 K 50 K — cycles nnvmcycee Cycling endurance for EEPROM backup Write endurance 2 3 nnvmwree16 • EEPROM backup to FlexRAM ratio = 16 70 K 175 K — writes nnvmwree128 • EEPROM backup to FlexRAM ratio = 128 630 K 1.6 M — writes nnvmwree512 • EEPROM backup to FlexRAM ratio = 512 2.5 M 6.4 M — writes nnvmwree2k • EEPROM backup to FlexRAM ratio = 2,048 10 M 25 M — writes nnvmwree4k • EEPROM backup to FlexRAM ratio = 4,096 20 M 50 M — writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and typical values assume all byte-writes to FlexRAM. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 31 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3.4.1.5 Write endurance to FlexRAM for EEPROM When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the FTFE to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. Writes_subsystem = EEPROM – 2 × EEESPLIT × EEESIZE EEESPLIT × EEESIZE × Write_efficiency × n nvmcycee where • Writes_subsystem — minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance) • EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with the Program Partition command • EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command • EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command • Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • nnvmcycee — EEPROM-backup cycling endurance 32 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors Figure 11. EEPROM backup writes to FlexRAM 3.4.2 EzPort switching specifications Table 24. EzPort switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V EP1 EZP_CK frequency of operation (all commands except READ) — fSYS/2 MHz EP1a EZP_CK frequency of operation (READ command) — fSYS/8 MHz EP2 EZP_CS negation to next EZP_CS assertion 2 x tEZP_CK — ns EP3 EZP_CS input valid to EZP_CK high (setup) 5 — ns EP4 EZP_CK high to EZP_CS input invalid (hold) 5 — ns EP5 EZP_D input valid to EZP_CK high (setup) 2 — ns EP6 EZP_CK high to EZP_D input invalid (hold) 5 — ns EP7 EZP_CK low to EZP_Q output valid — 18 ns EP8 EZP_CK low to EZP_Q output invalid (hold) 0 — ns EP9 EZP_CS negation to EZP_Q tri-state — 12 ns Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 33 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors EZP_CK EP3 EP2 EP4 EZP_CS EP9 EP7 EP8 EZP_Q (output) EP5 EP6 EZP_D (input) Figure 12. EzPort Timing Diagram 3.4.3 Flexbus switching specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values. Table 25. Flexbus limited voltage range switching specifications Num Description Min. Max. Unit Notes Operating voltage 2.7 3.6 V Frequency of operation — FB_CLK MHz FB1 Clock period 20 — ns FB2 Address, data, and control output valid — 11.5 ns 1 FB3 Address, data, and control output hold 0.5 — ns 1 FB4 Data and FB_TA input setup 8.5 — ns 2 FB5 Data and FB_TA input hold 0.5 — ns 2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 34 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors 2. Specification is valid for all FB_AD[31:0] and FB_TA. Table 26. Flexbus full voltage range switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V — FB_CLK MHz 1/FB_CLK — ns Frequency of operation Notes FB1 Clock period FB2 Address, data, and control output valid — 13.5 ns 1 FB3 Address, data, and control output hold 0 — ns 1 FB4 Data and FB_TA input setup 13.7 — ns 2 FB5 Data and FB_TA input hold 0.5 — ns 2 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 35 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors FB1 FB_CLK FB3 FB5 FB_A[Y] Address FB4 FB2 FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 13. FlexBus read timing diagram 36 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors FB1 FB_CLK FB2 FB3 FB_A[Y] FB_D[X] Address Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 14. FlexBus write timing diagram 3.5 Security and integrity modules 3.5.1 DryIce Tamper Electrical Specifications Information about security-related modules is not included in this document and is available only after a nondisclosure agreement (NDA) has been signed. To request an NDA, please contact your local Freescale sales representative. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 37 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3.6 Analog 3.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on the differential pins ADCx_DP0, ADCx_DM0. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 3.6.1.1 16-bit ADC operating conditions Table 27. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes VDDA Supply voltage Absolute 1.71 — 3.6 V — ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2 ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V VREFL ADC reference voltage low VSSA VSSA VSSA V VADIN Input voltage • 16-bit differential mode VREFL — 31/32 * VREFH V — • All other modes VREFL — • 16-bit mode — 8 10 pF — • 8-bit / 10-bit / 12-bit modes — 4 5 — 2 5 kΩ — CADIN RADIN RAS Input capacitance Input series resistance VREFH Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz — — 5 kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging 3 5 20.000 — 818.330 Ksps Table continues on the next page... 38 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors Table 27. 16-bit ADC operating conditions (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes Continuous conversions enabled, subsequent conversion time Crate ADC conversion rate 16-bit mode 5 No ADC hardware averaging 37.037 — 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input protection ZAS RAS ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE VADIN VAS CAS RADIN INPUT PIN INPUT PIN RADIN RADIN INPUT PIN CADIN Figure 15. ADC input impedance equivalency diagram 3.6.1.2 16-bit ADC electrical characteristics Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 39 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Conditions1 Description Min. Typ.2 Max. Unit Notes 0.215 — 1.7 mA 3 • ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz • ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/fADACK • ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz • ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz LSB4 5 LSB4 5 LSB4 5 LSB4 VADIN = VDDA5 IDDA_ADC Supply current fADACK ADC asynchronous clock source Sample Time TUE DNL INL EFS EQ ENOB See Reference Manual chapter for sample times Total unadjusted error • 12-bit modes — ±4 ±6.8 • <12-bit modes — ±1.4 ±2.1 Differential nonlinearity • 12-bit modes — ±0.7 –1.1 to +1.9 • <12-bit modes — ±0.2 • 12-bit modes — ±1.0 • <12-bit modes — ±0.5 • 12-bit modes — –4 –5.4 • <12-bit modes — –1.4 –1.8 • 16-bit modes — –1 to 0 — • ≤13-bit modes — — ±0.5 Integral nonlinearity Full-scale error Quantization error Effective number of bits –0.3 to 0.5 –2.7 to +1.9 –0.7 to +0.5 16-bit differential mode bits • Avg = 32 12.8 14.5 • Avg = 4 11.9 13.8 • Avg = 4 SINAD THD Signal-to-noise plus distortion See ENOB Total harmonic distortion 16-bit differential mode — bits bits 12.2 13.9 — 11.4 13.1 — 6.02 × ENOB + 1.76 • Avg = 32 6 bits — 16-bit single-ended mode • Avg = 32 LSB4 dB dB — -94 7 — dB 16-bit single-ended mode • Avg = 32 SFDR Spurious free dynamic range — -85 82 95 16-bit differential mode • Avg = 32 16-bit single-ended mode 78 — — dB — dB 7 90 Table continues on the next page... 40 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Conditions1 Description Typ.2 Min. Max. Unit Notes mV IIn = leakage current • Avg = 32 EIL Input leakage error IIn × RAS (refer to the MCU's voltage and current operating ratings) VTEMP25 Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. 8. ADC conversion clock < 3 MHz Typical ADC 16-bit Differential ENOB vs ADC Clock 100Hz, 90% FS Sine Input 15.00 14.70 14.40 14.10 ENOB 13.80 13.50 13.20 12.90 12.60 Hardware Averaging Disabled Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples 12.30 12.00 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 16. Typical ENOB vs. ADC_CLK for 16-bit differential mode Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 41 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Typical ADC 16-bit Single-Ended ENOB vs ADC Clock 100Hz, 90% FS Sine Input 14.00 13.75 13.50 13.25 13.00 ENOB 12.75 12.50 12.25 12.00 11.75 11.50 11.25 11.00 Averaging of 4 samples Averaging of 32 samples 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 17. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 3.6.2 CMP and 6-bit DAC electrical specifications Table 29. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDHS Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA VAIN Analog input voltage VSS – 0.3 — VDD V VAIO Analog input offset voltage — — 20 mV • CR0[HYSTCTR] = 00 — 5 — mV • CR0[HYSTCTR] = 01 — 10 — mV • CR0[HYSTCTR] = 10 — 20 — mV • CR0[HYSTCTR] = 11 — 30 — mV VH Analog comparator hysteresis1 VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns — — 40 μs — 7 — μA Analog comparator initialization IDAC6b delay2 6-bit DAC current adder (enabled) INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 42 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 0.08 0.07 CMP Hystereris (V) 0.06 HYSTCTR Setting 0.05 00 0.04 01 10 11 0.03 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 18. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 43 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP Hysteresis (V) 0.12 HYSTCTR Setting 0.1 00 01 10 11 0.08 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 1.9 Vin level (V) 2.2 2.5 2.8 3.1 Figure 19. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 3.6.3 12-bit DAC electrical characteristics 3.6.3.1 Symbol 12-bit DAC operating requirements Table 30. 12-bit DAC operating requirements Desciption Min. Max. Unit VDDA Supply voltage 1.71 3.6 V VDACR Reference voltage Notes 1.13 3.6 V 1 CL Output load capacitance — 100 pF 2 IL Output load current — 1 mA 1. The DAC reference can be selected to be VDDA or VREFH. 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC. 44 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors 3.6.3.2 Symbol 12-bit DAC operating behaviors Table 31. 12-bit DAC operating behaviors Description IDDA_DACL Supply current — low-power mode Min. Typ. Max. Unit — — 150 μA — — 700 μA Notes P IDDA_DACH Supply current — high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) — low-power mode — 100 200 μs 1 tDACHP Full-scale settling time (0x080 to 0xF7F) — high-power mode — 15 30 μs 1 — 0.7 1 μs 1 tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) — low-power mode and highspeed mode Vdacoutl DAC output voltage range low — highspeed mode, no load, DAC set to 0x000 — — 100 mV Vdacouth DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF VDACR −100 — VDACR mV INL Integral non-linearity error — high speed mode — — ±8 LSB 2 DNL Differential non-linearity error — VDACR > 2 V — — ±1 LSB 3 DNL Differential non-linearity error — VDACR = VREF_OUT — — ±1 LSB 4 — ±0.4 ±0.8 %FSR 5 Gain error — ±0.1 ±0.6 %FSR 5 Power supply rejection ratio, VDDA ≥ 2.4 V 60 — 90 dB TCO Temperature coefficient offset voltage — 3.7 — μV/C TGE Temperature coefficient gain error — 0.000421 — %FSR/C AC Offset aging coefficient — — 100 μV/yr Rop Output resistance (load = 3 kΩ) — — 250 Ω SR Slew rate -80h→ F7Fh→ 80h VOFFSET Offset error EG PSRR 1. 2. 3. 4. 5. V/μs • High power (SPHP) 1.2 1.7 — • Low power (SPLP) 0.05 0.12 — — — -80 CT Channel to channel cross talk BW 3dB bandwidth 6 dB kHz • High power (SPHP) 550 — — • Low power (SPLP) 40 — — Settling within ±1 LSB The INL is measured for 0 + 100 mV to VDACR −100 mV The DNL is measured for 0 + 100 mV to VDACR −100 mV The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 45 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device 8 6 4 DAC12 INL (LSB) 2 0 -2 -4 -6 -8 0 500 1000 1500 2000 2500 3000 3500 4000 Digital Code Figure 20. Typical INL error vs. digital code 46 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors 1.499 DAC12 Mid Level Code Voltage 1.4985 1.498 1.4975 1.497 1.4965 1.496 55 25 -40 85 105 125 Temperature °C Figure 21. Offset at half scale vs. temperature 3.6.4 Voltage reference electrical specifications Table 32. VREF full-range operating requirements Symbol Description Min. Max. Unit Notes VDDA Supply voltage 1.71 3.6 V — Operating temperature range of the device °C — 100 nF 1, 2 TA Temperature CL Output load capacitance 1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external reference. 2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of the device. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 47 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 33. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes Vout Voltage reference output with factory trim at nominal VDDA and temperature=25C 1.1915 1.195 1.1977 V 1 Vout Voltage reference output — factory trim 1.1584 — 1.2376 V 1 Vout Voltage reference output — user trim 1.193 — 1.197 V 1 Vstep Voltage reference trim step — 0.5 — mV 1 Vtdrift Temperature drift (Vmax -Vmin across the full temperature range) — — 80 mV 1 Bandgap only current — — 80 µA 1 µV 1, 2 Ibg ΔVLOAD Load regulation • current = ± 1.0 mA — 200 — Tstup Buffer startup time — — 100 µs — Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load Table 34. VREF limited-range operating requirements Symbol Description Min. Max. Unit Notes TA Temperature 0 50 °C — Table 35. VREF limited-range operating behaviors Symbol Vout Description Voltage reference output with factory trim Min. Max. Unit Notes 1.173 1.225 V — 3.7 Timers See General switching specifications. 3.8 Communication interfaces 48 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors 3.8.1 USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-todate standards, visit usb.org. NOTE The MCGFLLCLK does not meet the USB jitter specifications for certification. 3.8.2 USB DCD electrical specifications Table 36. USB0 DCD electrical specifications Symbol Description Min. Typ. Max. Unit VDP_SRC USB_DP source voltage (up to 250 μA) 0.5 — 0.7 V Threshold voltage for logic high 0.8 — 2.0 V VLGC IDP_SRC USB_DP source current 7 10 13 μA IDM_SINK USB_DM sink current 50 100 150 μA RDM_DWN D- pulldown resistance for data pin contact detect 14.25 — 24.8 kΩ VDAT_REF Data detect voltage 0.25 0.33 0.4 V 3.8.3 USB VREG electrical specifications Table 37. USB VREG electrical specifications Symbol Description Min. Typ.1 Max. Unit VREGIN Input supply voltage 2.7 — 5.5 V IDDon Quiescent current — Run mode, load current equal zero, input supply (VREGIN) > 3.6 V — 125 186 μA IDDstby Quiescent current — Standby mode, load current equal zero — 1.1 10 μA IDDoff Quiescent current — Shutdown mode — 650 — nA — — 4 μA • VREGIN = 5.0 V and temperature=25 °C • Across operating voltage and temperature ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA Notes VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V Table continues on the next page... Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 49 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 37. USB VREG electrical specifications (continued) Symbol Description • Run mode • Standby mode VReg33out Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode Min. Typ.1 Max. Unit 3 3.3 3.6 V 2.1 2.8 3.6 V 2.1 — 3.6 V 1.76 2.2 8.16 μF COUT External output capacitor ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 290 — mA Notes 2 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad. 3.8.4 CAN switching specifications See General switching specifications. 3.8.5 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 38. Master mode DSPI timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation — 30 MHz Notes DS1 DSPI_SCK output cycle time 2 x tBUS — ns DS2 DSPI_SCK output high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) − 2 — ns 1 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) − 2 — ns 2 DS5 DSPI_SCK to DSPI_SOUT valid — 8.5 ns DS6 DSPI_SCK to DSPI_SOUT invalid −2 — ns Table continues on the next page... 50 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors Table 38. Master mode DSPI timing (limited voltage range) (continued) Num Description Min. Max. Unit DS7 DSPI_SIN to DSPI_SCK input setup 15 — ns DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns Notes 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. DSPI_PCSn DS3 DSPI_SCK (CPOL=0) DS7 DSPI_SIN DS1 DS2 DS4 DS8 First data DSPI_SOUT Data Last data DS5 First data DS6 Data Last data Figure 22. DSPI classic SPI timing — master mode Table 39. Slave mode DSPI timing (limited voltage range) Num Description Operating voltage Min. Max. Unit 2.7 3.6 V Frequency of operation 15 MHz 4 x tBUS — ns (tSCK/2) − 2 (tSCK/2) + 2 ns DSPI_SCK to DSPI_SOUT valid — 17.4 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns DS15 DSPI_SS active to DSPI_SOUT driven — 16 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — 16 ns DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 51 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Last data Data DS14 First data Data Last data Figure 23. DSPI classic SPI timing — slave mode 3.8.6 DSPI switching specifications (full voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 40. Master mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit Notes 1.71 3.6 V 1 — 15 MHz 4 x tBUS — ns DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) − 4 — ns 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) − 4 — ns 3 DS5 DSPI_SCK to DSPI_SOUT valid — 10 ns DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 — ns DS7 DSPI_SIN to DSPI_SCK input setup 20.5 — ns DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns 1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. 52 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors DSPI_PCSn DS3 DS4 DS8 DS7 (CPOL=0) DS1 DS2 DSPI_SCK DSPI_SIN Data First data DSPI_SOUT Last data DS5 DS6 First data Data Last data Figure 24. DSPI classic SPI timing — master mode Table 41. Slave mode DSPI timing (full voltage range) Num Description Operating voltage Frequency of operation Min. Max. Unit 1.71 3.6 V — 7.5 MHz 8 x tBUS — ns (tSCK/2) - 4 (tSCK/2) + 4 ns DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid — 20 ns DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns DS15 DSPI_SS active to DSPI_SOUT driven — 19 ns DS16 DSPI_SS inactive to DSPI_SOUT not driven — 19 ns DSPI_SS DS10 DS9 DSPI_SCK (CPOL=0) DS15 DSPI_SOUT First data DS13 DSPI_SIN DS12 DS16 DS11 Data Last data DS14 First data Data Last data Figure 25. DSPI classic SPI timing — slave mode Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 53 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3.8.7 I2C switching specifications See General switching specifications. 3.8.8 UART switching specifications See General switching specifications. 3.8.9 SDHC specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. The following timing specifications assume a load of 50 pF. Table 42. SDHC switching specifications Num Symbol Description Operating voltage Min. Max. Unit 1.71 3.6 V Card input clock SD1 fpp Clock frequency (low speed) 0 400 kHz fpp Clock frequency (SD\SDIO full speed\high speed) 0 25\50 MHz fpp Clock frequency (MMC full speed\high speed) 0 20\50 MHz fOD Clock frequency (identification mode) 0 400 kHz SD2 tWL Clock low time 7 — ns SD3 tWH Clock high time 7 — ns SD4 tTLH Clock rise time — 3 ns SD5 tTHL Clock fall time — 3 ns SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD6 tOD SDHC output delay (output valid) -5 8.3 ns SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD7 tISU SDHC input setup time 5 — ns SD8 tIH SDHC input hold time 0 — ns 54 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors SD3 SD2 SD1 SDHC_CLK SD6 Output SDHC_CMD Output SDHC_DAT[3:0] SD7 SD8 Input SDHC_CMD Input SDHC_DAT[3:0] Figure 26. SDHC timing 3.8.10 I2S switching specifications This section provides the AC timings for the I2S in master (clocks driven) and slave modes (clocks input). All timings are given for non-inverted serial clock polarity (TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0, RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync (I2S_FS) shown in the figures below. Table 43. I2S master mode timing Num Description Min. Max. Unit Operating voltage 2.7 3.6 V S1 I2S_MCLK cycle time 40 — ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_BCLK cycle time S4 I2S_BCLK pulse width high/low S5 80 — ns 45% 55% BCLK period I2S_BCLK to I2S_FS output valid — 15 ns S6 I2S_BCLK to I2S_FS output invalid 0 — ns S7 I2S_BCLK to I2S_TXD valid — 15 ns S8 I2S_BCLK to I2S_TXD invalid 0 — ns S9 I2S_RXD/I2S_FS input setup before I2S_BCLK 15 — ns S10 I2S_RXD/I2S_FS input hold after I2S_BCLK 0 — ns Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 55 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_BCLK (output) S4 S4 S6 S5 I2S_FS (output) S10 S9 I2S_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 27. I2S timing — master mode Table 44. I2S slave mode timing Num Description Min. Max. Unit Operating voltage 2.7 3.6 V S11 I2S_BCLK cycle time (input) 80 — ns S12 I2S_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_FS input setup before I2S_BCLK 4.5 — ns S14 I2S_FS input hold after I2S_BCLK 2 — ns S15 I2S_BCLK to I2S_TXD/I2S_FS output valid — 18 ns S16 I2S_BCLK to I2S_TXD/I2S_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_BCLK 4.5 — ns S18 I2S_RXD hold after I2S_BCLK 2 — ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 21 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear 56 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors S11 S12 I2S_BCLK (input) S12 S15 S16 I2S_FS (output) S13 I2S_FS (input) S14 S15 S19 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 28. I2S timing — slave modes 3.8.10.1 Normal Run, Wait and Stop mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. Table 45. I2S/SAI master mode timing Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 40 — ns S2 I2S_MCLK (as an input) pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 — ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid — 15 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid -1 — ns S7 I2S_TX_BCLK to I2S_TXD valid — 15 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 20.5 — ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 57 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 29. I2S/SAI timing — master modes Table 46. I2S/SAI slave mode timing Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 5.8 — ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 2 — ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 23.5 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK 5.8 — ns S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns — 25 ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear 58 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 30. I2S/SAI timing — slave modes 3.8.10.2 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. Table 47. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 62.5 — ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 — ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid — 45 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid 0 — ns S7 I2S_TX_BCLK to I2S_TXD valid — 45 ns S8 I2S_TX_BCLK to I2S_TXD invalid — ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK — ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK — ns Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 0 59 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 31. I2S/SAI timing — master modes Table 48. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 — ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 30 — ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK — ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK — ns S18 I2S_RXD hold after I2S_RX_BCLK — ns 72 ns S19 I2S_TX_FS input assertion to I2S_TXD output — 30 valid1 — ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear 60 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 32. I2S/SAI timing — slave modes 3.8.10.3 3.8.10.3.1 Ordering parts Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: PK21 and MK21 3.8.10.4 3.8.10.4.1 Part identification Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 3.8.10.4.2 Format Part numbers for this device have the following format: Q K## A M FFF R T PP CC N 3.8.10.4.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 61 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Field Description Values Q Qualification status • M = Fully qualified, general market flow • P = Prequalification K## Kinetis family • K21 A Key attribute • D = Cortex-M4 w/ DSP • F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only • X = Program flash and FlexMemory FFF Program flash memory size • • • • • • • R Silicon revision • Z = Initial • (Blank) = Main • A = Revision after main T Temperature range (°C) • V = –40 to 105 • C = –40 to 85 PP Package identifier • • • • • • • • • • • FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LF = 48 LQFP (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) MP = 64 MAPBGA (5 mm x 5 mm) LK = 80 LQFP (12 mm x 12 mm) LL = 100 LQFP (14 mm x 14 mm) MC = 121 MAPBGA (8 mm x 8 mm) DC = 121 XFBGA (8 mm x 8 mm x 0.5 mm) LQ = 144 LQFP (20 mm x 20 mm) MD = 144 MAPBGA (13 mm x 13 mm) CC Maximum CPU frequency (MHz) • • • • • • • 5 = 50 MHz 7 = 72 MHz 10 = 100 MHz 12 = 120 MHz 15 = 150 MHz 16 = 168 MHz 18 = 180 MHz N Packaging type • R = Tape and reel • (Blank) = Trays 3.8.10.4.4 Example 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB 512 = 512 KB 1M0 = 1 MB 2M0 = 2 MB This is an example part number: MK21FN1M0VMC10 62 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors 3.8.10.4.5 Small package marking In an effort to save space, small package devices use special marking on the chip. These markings have the following format: Q ## C F T PP This table lists the possible values for each field in the part number for small packages (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow • P = Prequalification ## Kinetis family • 2# = K21/K22 C Speed • H = 120 MHz F Flash memory configuration • K = 512 KB + Flex • 1 = 1 MB T Temperature range (°C) • V = –40 to 105 PP Package identifier • • • • • LL = 100 LQFP MC = 121 MAPBGA LQ = 144 LQFP MD = 144 MAPBGA DC = 121 XFBGA This tables lists some examples of small package marking along with the original part numbers: Original part number MK21FX512VMC12 3.8.10.5 3.8.10.5.1 Alternate part number M21HKVMC Terminology and guidelines Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 3.8.10.5.1.1 Example This is an example of an operating requirement: Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 63 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Symbol VDD Description 1.0 V core supply voltage 3.8.10.5.2 Min. 0.9 Max. 1.1 Unit V Definition: Operating behavior Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.8.10.5.2.1 Example This is an example of an operating behavior: Symbol IWP Description Min. Digital I/O weak pullup/ 10 pulldown current 3.8.10.5.3 Max. 130 Unit µA Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.8.10.5.3.1 Example This is an example of an attribute: Symbol CIN_D 3.8.10.5.4 Description Input capacitance: digital pins Min. — Max. 7 Unit pF Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. 64 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Peripheral operating requirements and behaviors 3.8.10.5.4.1 Example This is an example of an operating rating: Symbol Description VDD 1.0 V core supply voltage 3.8.10.5.5 Max. –0.3 Unit 1.2 V Result of exceeding a rating 40 Failures in time (ppm) Min. 30 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 20 10 0 Operating rating Measured characteristic 3.8.10.5.6 Relationship between ratings and operating requirements .) ) e Op ing rat n.) mi ( ing rat rat e Op ing e re ir qu in. t (m ax t (m n me ing rat e Op .) en rem re i qu rat e Op ing g tin ra ax (m Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure –∞ ∞ Operating (power on) g lin nd Ha n.) mi g( in rat g( ng li nd Ha in rat .) x ma Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure –∞ ∞ Handling (power off) 3.8.10.5.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 65 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8.10.5.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.10.5.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol IWP 3.8.10.5.8.2 Description Digital I/O weak pullup/pulldown current Min. 10 Typ. 70 Max. 130 Unit µA Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 66 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Dimensions 5000 4500 4000 TJ IDD_STOP (μA) 3500 150 °C 3000 105 °C 2500 25 °C 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 VDD (V) 3.8.10.5.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V 4 Dimensions 4.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 121-pin MAPBGA 98ASA00344D 169-pin MAPBGA 98ASA00628D Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 67 Freescale Semiconductor, Inc. Pinout 5 Pinout 5.1 K21 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. • • • • • • 121 MAP BGA Pin Name NOTE The analog input signals ADC0_DP2 and ADC0_DM2 on PTE2 and PTE3 are available only for K21 and K22 devices and are not present on K10 and K20 devices. The TRACE signals on PTE0, PTE1, PTE2, PTE3, and PTE4 are available only for K11, K12, K21, and K22 devices and are not present on K10 and K20 devices. If the VBAT pin is not used, the VBAT pin should be left floating. Do not connect VBAT pin to VSS. The FTM_CLKIN signals on PTB16 and PTB17 are available only for K11, K12, K21, and K22 devices and is not present on K10 and K20 devices. For K22D devices this signal is on ALT7, and for K22F devices, this signal is on ALT4. The FTM0_CH2 signal on PTC5/LLWU_P9 is available only for K11, K12, K21, and K22 devices and is not present on K10 and K20 devices. The I2C0_SCL signal on PTD2/LLWU_P13 and I2C0_SDA signal on PTD3 are available only for K11, K12, K21, and K22 devices and are not present on K10 and K20 devices. Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 E4 PTE0 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 TRACE_ CLKOUT I2C1_SDA RTC_ CLKOUT E3 PTE1/ LLWU_P0 ADC1_SE5a ADC1_SE5a PTE1/ LLWU_P0 SPI1_SOUT UART1_RX SDHC0_D0 TRACE_D3 I2C1_SCL SPI1_SIN E2 PTE2/ LLWU_P1 ADC0_DP2/ ADC1_SE6a ADC0_DP2/ ADC1_SE6a PTE2/ LLWU_P1 SPI1_SCK UART1_CTS_ SDHC0_ b DCLK 68 Freescale Semiconductor, Inc. EzPort TRACE_D2 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Pinout 121 MAP BGA Pin Name Default ALT0 F4 PTE3 ADC0_DM2/ ADC1_SE7a ADC0_DM2/ ADC1_SE7a E7 VDD VDD VDD F7 VSS VSS VSS H7 PTE4/ LLWU_P2 G4 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 PTE3 SPI1_SIN UART1_RTS_ SDHC0_CMD TRACE_D1 b DISABLED PTE4/ LLWU_P2 SPI1_PCS0 UART3_TX SDHC0_D3 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 FTM3_CH0 F3 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_ I2S0_MCLK b FTM3_CH1 E6 VDD VDD VDD G7 VSS VSS VSS K3 PTE16 ADC0_SE4a ADC0_SE4a PTE16 SPI0_PCS0 UART2_TX FTM_CLKIN0 FTM0_FLT3 H4 PTE17 ADC0_SE5a ADC0_SE5a PTE17 SPI0_SCK UART2_RX FTM_CLKIN1 LPTMR0_ ALT3 A11 PTE18 ADC0_SE6a ADC0_SE6a PTE18 SPI0_SOUT UART2_CTS_ I2C0_SDA b L6 VSS VSS VSS F1 USB0_DP USB0_DP USB0_DP F2 USB0_DM USB0_DM USB0_DM G1 VOUT33 VOUT33 VOUT33 G2 VREGIN VREGIN VREGIN H1 ADC0_DP1 ADC0_DP1 ADC0_DP1 H2 ADC0_DM1 ADC0_DM1 ADC0_DM1 J1 ADC1_DP1 ADC1_DP1 ADC1_DP1 J2 ADC1_DM1 ADC1_DM1 ADC1_DM1 K1 ADC0_DP0/ ADC1_DP3 ADC0_DP0/ ADC1_DP3 ADC0_DP0/ ADC1_DP3 K2 ADC0_DM0/ ADC1_DM3 ADC0_DM0/ ADC1_DM3 ADC0_DM0/ ADC1_DM3 L1 ADC1_DP0/ ADC0_DP3 ADC1_DP0/ ADC0_DP3 ADC1_DP0/ ADC0_DP3 L2 ADC1_DM0/ ADC0_DM3 ADC1_DM0/ ADC0_DM3 ADC1_DM0/ ADC0_DM3 F5 VDDA VDDA VDDA G5 VREFH VREFH VREFH G6 VREFL VREFL VREFL F6 VSSA VSSA VSSA J3 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 H3 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. ALT7 EzPort SPI1_SOUT TRACE_D0 USB_SOF_ OUT 69 Freescale Semiconductor, Inc. Pinout 121 MAP BGA Pin Name Default ALT0 L3 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 K5 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 K4 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 L7 TAMPER0/ RTC_ WAKEUP_B TAMPER0/ RTC_ WAKEUP_B TAMPER0/ RTC_ WAKEUP_B H5 TAMPER1 TAMPER1 TAMPER1 J5 TAMPER2 TAMPER2 TAMPER2 H6 TAMPER3 TAMPER3 TAMPER3 J9 TAMPER4 TAMPER4 TAMPER4 J4 TAMPER5 TAMPER5 TAMPER5 L4 XTAL32 XTAL32 XTAL32 L5 EXTAL32 EXTAL32 EXTAL32 K6 VBAT VBAT VBAT J6 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK PTA0 UART0_CTS_ FTM0_CH5 b JTAG_TCLK/ SWD_CLK EZP_CLK H8 PTA1 JTAG_TDI/ EZP_DI PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI J7 PTA2 JTAG_TDO/ TRACE_ SWO/ EZP_DO PTA2 UART0_TX FTM0_CH7 JTAG_TDO/ EZP_DO TRACE_SWO H9 PTA3 JTAG_TMS/ SWD_DIO PTA3 UART0_RTS_ FTM0_CH0 b J8 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b PTA4/ LLWU_P3 K7 PTA5 DISABLED PTA5 USB_CLKIN FTM0_CH2 CMP2_OUT I2S0_TX_ BCLK JTAG_TRST_ b E5 VDD VDD VDD G3 VSS VSS VSS K8 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2C2_SCL I2S0_TXD0 FTM1_QD_ PHA L8 PTA13/ LLWU_P4 CMP2_IN1 CMP2_IN1 PTA13/ LLWU_P4 CAN0_RX FTM1_CH1 I2C2_SDA I2S0_TX_FS FTM1_QD_ PHB K9 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX I2C2_SCL I2S0_RX_ BCLK I2S0_TXD1 70 Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort JTAG_TMS/ SWD_DIO FTM0_CH1 NMI_b EZP_CS_b Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Pinout 121 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 L9 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_RXD0 J10 PTA16 DISABLED PTA16 SPI0_SOUT UART0_CTS_ b I2S0_RX_FS PTA17 SPI0_SIN UART0_RTS_ b I2S0_MCLK H10 PTA17 ADC1_SE17 ADC1_SE17 L10 VDD VDD VDD K10 VSS VSS VSS L11 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_CLKIN0 K11 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_CLKIN1 J11 RESET_b RESET_b RESET_b DISABLED PTA29 G11 PTB0/ LLWU_P5 ADC0_SE8/ ADC1_SE8 ADC0_SE8/ ADC1_SE8 PTB0/ LLWU_P5 I2C0_SCL FTM1_CH0 FTM1_QD_ PHA G10 PTB1 ADC0_SE9/ ADC1_SE9 ADC0_SE9/ ADC1_SE9 PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_ PHB G9 PTB2 ADC0_SE12 ADC0_SE12 PTB2 I2C0_SCL UART0_RTS_ b FTM0_FLT3 G8 PTB3 ADC0_SE13 ADC0_SE13 PTB3 I2C0_SDA UART0_CTS_ b FTM0_FLT0 F11 PTB6 ADC1_SE12 ADC1_SE12 PTB6 FB_AD23 E11 PTB7 ADC1_SE13 ADC1_SE13 PTB7 FB_AD22 DISABLED PTB8 E10 DISABLED PTB9 PTB9 EzPort I2S0_RXD1 LPTMR0_ ALT1 H11 PTA29 D11 PTB8 ALT7 FB_A24 UART3_RTS_ b FB_AD21 SPI1_PCS1 UART3_CTS_ b FB_AD20 D10 PTB10 ADC1_SE14 ADC1_SE14 PTB10 SPI1_PCS0 UART3_RX FB_AD19 FTM0_FLT1 C10 PTB11 ADC1_SE15 ADC1_SE15 PTB11 SPI1_SCK UART3_TX FB_AD18 FTM0_FLT2 B11 PTB12 DISABLED PTB12 UART3_RTS_ FTM1_CH0 b FTM0_CH4 FTM1_QD_ PHA C11 PTB13 DISABLED PTB13 UART3_CTS_ FTM1_CH1 b FTM0_CH5 FTM1_QD_ PHB B10 PTB16 DISABLED PTB16 SPI1_SOUT UART0_RX FTM_CLKIN0 FB_AD17 EWM_IN E9 PTB17 DISABLED PTB17 SPI1_SIN UART0_TX FTM_CLKIN1 FB_AD16 EWM_OUT_b D9 PTB18 DISABLED PTB18 CAN0_TX FTM2_CH0 I2S0_TX_ BCLK FB_AD15 FTM2_QD_ PHA C9 PTB19 DISABLED PTB19 CAN0_RX FTM2_CH1 I2S0_TX_FS FB_OE_b FTM2_QD_ PHB F10 PTB20 DISABLED PTB20 SPI2_PCS0 FB_AD31 CMP0_OUT F9 PTB21 DISABLED PTB21 SPI2_SCK FB_AD30 CMP1_OUT F8 PTB22 DISABLED PTB22 SPI2_SOUT FB_AD29 CMP2_OUT E8 PTB23 DISABLED PTB23 SPI2_SIN Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. SPI0_PCS5 FB_AD28 71 Freescale Semiconductor, Inc. Pinout 121 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 B9 PTC0 ADC0_SE14 ADC0_SE14 PTC0 SPI0_PCS4 PDB0_ EXTRG FB_AD14 I2S0_TXD1 D8 PTC1/ LLWU_P6 ADC0_SE15 ADC0_SE15 PTC1/ LLWU_P6 SPI0_PCS3 UART1_RTS_ FTM0_CH0 b FB_AD13 I2S0_TXD0 C8 PTC2 ADC0_SE4b/ CMP1_IN0 ADC0_SE4b/ CMP1_IN0 PTC2 SPI0_PCS2 UART1_CTS_ FTM0_CH1 b FB_AD12 I2S0_TX_FS B8 PTC3/ LLWU_P7 CMP1_IN1 CMP1_IN1 PTC3/ LLWU_P7 SPI0_PCS1 UART1_RX FTM0_CH2 CLKOUT I2S0_TX_ BCLK A8 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11 CMP1_OUT D7 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 I2S0_RXD0 FB_AD10 CMP0_OUT C7 PTC6/ LLWU_P10 CMP0_IN0 CMP0_IN0 PTC6/ LLWU_P10 SPI0_SOUT PDB0_ EXTRG I2S0_RX_ BCLK FB_AD9 I2S0_MCLK B7 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_SOF_ OUT I2S0_RX_FS FB_AD8 A7 PTC8 ADC1_SE4b/ CMP0_IN2 ADC1_SE4b/ CMP0_IN2 PTC8 FTM3_CH4 I2S0_MCLK FB_AD7 D6 PTC9 ADC1_SE5b/ CMP0_IN3 ADC1_SE5b/ CMP0_IN3 PTC9 FTM3_CH5 I2S0_RX_ BCLK FB_AD6 C6 PTC10 ADC1_SE6b ADC1_SE6b PTC10 I2C1_SCL FTM3_CH6 I2S0_RX_FS FB_AD5 C5 PTC11/ LLWU_P11 ADC1_SE7b ADC1_SE7b PTC11/ LLWU_P11 I2C1_SDA FTM3_CH7 I2S0_RXD1 FB_RW_b B6 PTC12 DISABLED PTC12 UART4_RTS_ b FB_AD27 A6 PTC13 DISABLED PTC13 UART4_CTS_ b FB_AD26 A5 PTC14 DISABLED PTC14 UART4_RX FB_AD25 B5 PTC15 DISABLED PTC15 UART4_TX FB_AD24 D5 PTC16 DISABLED PTC16 UART3_RX FB_CS5_b/ FB_TSIZ1/ FB_BE23_ 16_BLS15_8_ b C4 PTC17 DISABLED PTC17 UART3_TX FB_CS4_b/ FB_TSIZ0/ FB_BE31_ 24_BLS7_0_b B4 PTC18 DISABLED PTC18 UART3_RTS_ b FB_TBST_b/ FB_CS2_b/ FB_BE15_8_ BLS23_16_b A4 PTC19 DISABLED PTC19 UART3_CTS_ b FB_CS3_b/ FB_BE7_0_ BLS31_24_b 72 Freescale Semiconductor, Inc. ALT7 EzPort FTM0_CH2 FTM2_FLT0 FTM3_FLT0 FB_TA_b Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Pinout 121 MAP BGA Pin Name Default D4 PTD0/ LLWU_P12 DISABLED D3 PTD1 ADC0_SE5b C3 PTD2/ LLWU_P13 B3 ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 PTD0/ LLWU_P12 SPI0_PCS0 UART2_RTS_ FTM3_CH0 b FB_ALE/ FB_CS1_b/ FB_TS_b PTD1 SPI0_SCK UART2_CTS_ FTM3_CH1 b FB_CS0_b DISABLED PTD2/ LLWU_P13 SPI0_SOUT UART2_RX FTM3_CH2 FB_AD4 I2C0_SCL PTD3 DISABLED PTD3 SPI0_SIN UART2_TX FTM3_CH3 FB_AD3 I2C0_SDA A3 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1 UART0_RTS_ FTM0_CH4 b FB_AD2 EWM_IN A2 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_ FTM0_CH5 b FB_AD1 EWM_OUT_b B2 PTD6/ LLWU_P15 ADC0_SE7b ADC0_SE7b PTD6/ LLWU_P15 SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0 A1 PTD7 DISABLED PTD7 CMT_IRO UART0_TX FTM0_CH7 A10 PTD8 DISABLED PTD8 I2C0_SCL UART5_RX FB_A16 A9 PTD9 DISABLED PTD9 I2C0_SDA UART5_TX FB_A17 B1 PTD10 DISABLED PTD10 UART5_RTS_ b FB_A18 C2 PTD11 DISABLED PTD11 SPI2_PCS0 UART5_CTS_ SDHC0_ b CLKIN FB_A19 C1 PTD12 DISABLED PTD12 SPI2_SCK FTM3_FLT0 SDHC0_D4 FB_A20 D2 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21 D1 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22 E1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23 ADC0_SE5b EzPort FTM0_FLT1 5.2 K21 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 73 Freescale Semiconductor, Inc. Revision History 1 2 3 4 5 6 7 8 9 10 11 A PTD7 PTD5 PTD4/ LLWU_P14 PTC19 PTC14 PTC13 PTC8 PTC4/ LLWU_P8 PTD9 PTD8 PTE18 A B PTD10 PTD6/ LLWU_P15 PTD3 PTC18 PTC15 PTC12 PTC7 PTC3/ LLWU_P7 PTC0 PTB16 PTB12 B C PTD12 PTD11 PTD2/ LLWU_P13 PTC17 PTC11/ LLWU_P11 PTC10 PTC6/ LLWU_P10 PTC2 PTB19 PTB11 PTB13 C D PTD14 PTD13 PTD1 PTD0/ LLWU_P12 PTC16 PTC9 PTC5/ LLWU_P9 PTC1/ LLWU_P6 PTB18 PTB10 PTB8 D E PTD15 PTE2/ LLWU_P1 PTE1/ LLWU_P0 PTE0 VDD VDD VDD PTB23 PTB17 PTB9 PTB7 E F USB0_DP USB0_DM PTE6 PTE3 VDDA VSSA VSS PTB22 PTB21 PTB20 PTB6 F G VOUT33 VREGIN VSS PTE5 VREFH VREFL VSS PTB3 PTB2 PTB1 PTB0/ LLWU_P5 G PTE17 TAMPER1 TAMPER3 PTE4/ LLWU_P2 PTA1 PTA3 PTA17 PTA29 H TAMPER5 TAMPER2 PTA0 PTA2 PTA4/ LLWU_P3 TAMPER4 PTA16 RESET_b J VBAT PTA5 PTA12 PTA14 VSS PTA19 K PTA15 VDD PTA18 L 9 10 11 ADC0_SE16/ H ADC0_DP1 ADC0_DM1 CMP1_IN2/ ADC0_SE21 ADC1_SE16/ J ADC1_DP1 ADC1_DM1 CMP2_IN2/ ADC0_SE22 K ADC0_DP0/ ADC0_DM0/ ADC1_DP3 ADC1_DM3 L ADC1_DP0/ ADC1_DM0/ CMP1_IN5/ ADC0_DP3 ADC0_DM3 CMP0_IN5/ PTE16 DAC1_OUT/ DAC0_OUT/ CMP0_IN4/ CMP1_IN3/ CMP2_IN3/ ADC0_SE23 ADC1_SE23 VREF_OUT/ XTAL32 EXTAL32 VSS 4 5 6 ADC1_SE18 1 2 3 TAMPER0/ PTA13/ RTC_ LLWU_P4 WAKEUP_B 7 8 Figure 33. K21 121 MAPBGA Pinout Diagram 6 Revision History The following table provides a revision history for this document. Table 49. Revision History Rev. No. Date Substantial Changes 1 11/2012 Alpha customer release 2 5/2013 • Updated supported part numbers and document number • Updated section "Voltage and current operating behaviors" Table continues on the next page... 74 Freescale Semiconductor, Inc. Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Revision History Table 49. Revision History (continued) Rev. No. Date Substantial Changes • Added DryIce Tamper Electrical Specifications • Added the following figures: • Run mode supply current vs. core frequency • VLPR mode supply current vs. core frequency • Updated section "Device clock specifications" • Updated section "Power consumption operating behaviors" • Updated section "Power mode transition operating behaviors" • Updated section "JTAG limited voltage range electricals" • Updated section "MCG specifications" • Updated section "Oscillator DC electrical specifications" • Updated section "16-bit ADC operating conditions" • Updated the pinouts • Added section "Alternate part numbers for small packages" 3 08/2013 • Updated section "Power consumption operating behaviors" • Updated the "Run mode supply current vs. core frequency" figure in section "Diagram: Typical IDD_RUN operating behavior 4 11/2014 • Updated the table "Voltage and current operating behavior" • Format changes Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 75 Freescale Semiconductor, Inc. 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