TI CY74FCT373ATQCT 8-bit latches with 3-state output Datasheet

CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B – MAY 1994 – REVISED OCTOBER 2001
D
D
D
D
D
D
D
D
D
D
Function and Pinout Compatible With FCT
and F Logic
Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
Ioff Supports Partial-Power-Down Mode
Operation
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
3-State Outputs
CY54FCT373T
– 32-mA Output Sink Current
– 12-mA Output Source Current
CY74FCT373T
– 64-mA Output Sink Current
– 32-mA Output Source Current
CY54FCT373T . . . D PACKAGE
CY74FCT373T . . . Q OR SO PACKAGE
(TOP VIEW)
OE
O0
D0
D1
O1
O2
D2
D3
O3
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
O7
D7
D6
O6
O5
D5
D4
O4
LE
description
The ’FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the
latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup
times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE)
input is low. When OE is high, the bus output is in the high-impedance state. In this mode, data can be entered
into the latches.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B – MAY 1994 – REVISED OCTOBER 2001
ORDERING INFORMATION
SPEED
(ns)
PACKAGE†
TA
QSOP – Q
SOIC – SO
–40°C
40°C to 85°C
QSOP – Q
SOIC – SO
SOIC – SO
ORDERABLE
PART NUMBER
Tape and reel
4.7
CY74FCT373CTQCT
Tube
4.7
CY74FCT373CTSOC
Tape and reel
4.7
CY74FCT373CTSOCT
Tape and reel
5.2
CY74FCT373ATQCT
Tube
5.2
CY74FCT373ATSOC
Tape and reel
5.2
CY74FCT373ATSOCT
Tube
8
CY74FCT373TSOC
Tape and reel
8
CY74FCT373TSOCT
TOP-SIDE
MARKING
FCT373C
FCT373C
FCT373A
FCT373
FCT373
–55°C to 125°C
CDIP – D
Tube
5.6
CY54FCT373ATDMB
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OE
LE
D
OUTPUT
O
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
H = High logic level, L = Low logic level,
X = Don’t care, Z = High-impedance state,
Qn = Previous state of flip flops (Qn–1)
logic diagram (positive logic)
OE
LE
1
11
CP
D0
3
D
Q
To Seven Other Channels
2
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2
O0
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B – MAY 1994 – REVISED OCTOBER 2001
absolute maximum rating over operating free-air temperature range (unless otherwise noted)†
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θJA (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
CY54FCT373T
CY74FCT373T
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
0.8
V
High-level output current
–12
–32
mA
IOL
TA
Low-level output current
32
64
mA
85
°C
High-level input voltage
2
Operating free-air temperature
–55
2
125
–40
V
V
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
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CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B – MAY 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
CY54FCT373T
TYP† MAX
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.75 V,
IIN = –18 mA
IIN = –18 mA
VCC = 4.5 V,
IOH = –12 mA
IOH = –32 mA
VCC = 4
4.75
75 V
MIN
–0.7
–1.2
–0.7
2.4
2.4
Vhys
All inputs
II
VCC = 5.5 V,
VCC = 5.25 V,
VIN = VCC
VIN = VCC
5
IIH
VCC = 5.5 V,
VCC = 5.25 V,
VIN = 2.7 V
VIN = 2.7 V
±1
IIL
VCC = 5.5 V,
VCC = 5.25 V,
VIN = 0.5 V
VIN = 0.5 V
±1
IOZH
VCC = 5.5 V,
VCC = 5.25 V,
VOUT = 2.7 V
VOUT = 2.7 V
10
IOZL
VCC = 5.5 V,
VCC = 5.25 V,
VOUT = 0.5 V
VOUT = 0.5 V
–10
IOS‡
VCC = 5.5 V,
VCC = 5.25 V,
VOUT = 0 V
VOUT = 0 V
VCC = 0 V,
VCC = 5.5 V,
VOUT = 4.5 V
VIN ≤ 0.2 V,
∆ICC
0.3
3.3
0.55
IOL = 64 mA
0.3
0.2
0.55
0.2
±1
±1
10
–10
–120
–225
–60
–120
±1
VIN ≥ VCC – 0.2 V
VIN ≥ VCC – 0.2 V
VCC = 5.25 V,
VIN ≤ 0.2 V,
VCC = 5.5 V, VIN = 3.4 V§, f1 = 0, Outputs open
VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open
0.1
0.5
V
V
5
–60
V
V
2
IOH = –15 mA
IOL = 32 mA
VCC = 4.5 V,
VCC = 4.75 V,
ICC
–1.2
UNIT
3.3
VOL
Ioff
CY74FCT373T
TYP† MAX
MIN
–225
±1
0.2
0.1
0.2
0.5
2
2
µA
µA
µA
µA
µA
mA
µA
mA
mA
† Typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or
sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, IOS tests should be performed last.
§ Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND
4
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CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B – MAY 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
ICCD¶
CY54FCT373T
TYP† MAX
TEST CONDITIONS
MIN
VCC = 5.5 V, Outputs open,
One input switching at 50% duty cycle, OE = GND,
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
VCC = 5.25 V, Outputs open,
One input switching at 50% duty cycle, OE = GND,
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
5V
VCC = 5
5.5
V,
Outputs open,,
OE = GND,
LE = VCC
IC#
VCC = 5
5.25
25 V
V,
Outputs open,,
OE = GND,
LE = VCC
One bit switching
at f1 = 10 MHz
at 50% duty cycle
Eight bits switching
at f1 = 2.5 MHz
at 50% duty cycle
One bit switching
at f1 = 10 MHz
at 50% duty cycle
Eight bits switching
at f1 = 2.5 MHz
at 50% duty cycle
0.06
CY74FCT373T
TYP† MAX
MIN
UNIT
0.12
mA/
MHz
VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
VIN = 3.4 V or GND
VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
VIN = 3.4 V or GND
VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
0.7
1.4
1
2.4
1.3
2.6||
3.3
10.6||
VIN = 3.4 V or GND
VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
VIN = 3.4 V or GND
0.06
0.12
0.7
1.4
1
2.4
1.3
2.6||
3.3
10.6||
mA
Ci
6
10
6
10
pF
Co
8
12
8
12
pF
† Typical values are at VCC = 5 V, TA = 25°C.
¶ This parameter is derived for use in total power-supply calculations.
# IC
= ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1)
Where:
IC
= Total supply current
ICC = Power-supply current with CMOS input levels
∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V)
DH
= Duty cycle for TTL inputs high
NT
= Number of TTL inputs at DH
ICCD = Dynamic current caused by an input transition pair (HLH or LHL)
f0
= Clock frequency for registered devices, otherwise zero
f1
= Input signal frequency
N1
= Number of inputs changing at f1
All currents are in milliamperes and all frequencies are in megahertz.
|| Values for these conditions are examples of the ICC formula.
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CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B – MAY 1994 – REVISED OCTOBER 2001
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY54FCT373T
MIN
MAX
CY54FCT373AT
MIN
MAX
UNIT
tw
tsu
Pulse duration, LE high
6
6
ns
Setup time, data before LE↑
2
2
ns
th
Hold time, data after LE↑
1.5
1.5
ns
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY74FCT373T
MIN
tw
tsu
Pulse duration, LE high
th
Hold time, data after LE↑
CY74FCT373AT
MAX
MIN
6
Setup time, data before LE↑
MAX
5
CY74FCT373CT
MIN
MAX
UNIT
5
ns
2
2
2
ns
1.5
1.5
1.5
ns
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
O
tPLH
tPHL
LE
O
tPZH
tPZL
OE
O
tPHZ
tPLZ
OE
O
CY54FCT373AT
MIN
MAX
1.5
5.6
1.5
5.6
2
9.8
2
9.8
1.5
7.5
1.5
7.5
1.5
6.5
1.5
6.5
UNIT
ns
ns
ns
ns
switching characteristics over operating free-air temperature range (see Figure 1)
6
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
O
tPLH
tPHL
LE
O
tPZH
tPZL
OE
O
tPHZ
tPLZ
OE
O
POST OFFICE BOX 655303
CY74FCT373T
CY74FCT373AT
CY74FCT373CT
MIN
MAX
MIN
MAX
MIN
MAX
1.5
8
1.5
5.2
1.5
4.7
1.5
8
1.5
5.2
1.5
4.7
2
13
2
8.5
2
5.5
2
13
2
8.5
2
5.5
1.5
12
1.5
6.5
1.5
5.5
1.5
12
1.5
6.5
1.5
5.5
1.5
7.5
1.5
5.5
1.5
5
1.5
7.5
1.5
5.5
1.5
5
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B – MAY 1994 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
7V
From Output
Under Test
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
Open
TEST
GND
CL = 50 pF
(see Note A)
500 Ω
S1
500 Ω
S1
Open
7V
Open
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
LOAD CIRCUIT FOR
3-STATE OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
tsu
3V
1.5 V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
1.5 V
1.5 V
VOL
tPHL
Out-of-Phase
Output
tPLZ
≈3.5 V
1.5 V
tPZH
VOH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
Output
Waveform 1
(see Note B)
tPLH
1.5 V
1.5 V
tPZL
VOH
In-Phase
Output
3V
Output
Control
Output
Waveform 2
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright  2001, Texas Instruments Incorporated
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