TI ADS7949 12/10/8-bit 2msps, dual-channel unipolar pseudo-differential ultralow-power sar analog-to-digital converter Datasheet

ADS7947
ADS7948
ADS7949
www.ti.com
SLAS708 – SEPTEMBER 2010
12/10/8-Bit, 2MSPS, Dual-Channel, Unipolar, Pseudo-Differential, Ultralow-Power
SAR Analog-to-Digital Converters
Check for Samples: ADS7947 , ADS7948, ADS7949
FEATURES
DESCRIPTION
•
•
•
The ADS7947/8/9 are 12-bit, 10-bit, and 8-bit 2MSPS
analog-to-digital converters (ADCs), respectively.
Devices operate at 2MSPS sample rate with a
standard 16 clock data frame. In addition, it is
possible to operate the ADS7947 (12-bit) at
2.1MSPS, the ADS7948 (10-bit) at 2.57MSPS, and
the ADS7949 (8-bit) at 3MSPS with a short data
frame optimized for the number of clocks sufficient for
conversion with no drop in performance. The devices
feature both outstanding dc precision and excellent
dynamic performance, this family of pin-compatible
devices includes a two-channel input multiplexer and
a low-power successive approximation register (SAR)
ADC with an inherent sample-and-hold (S/H) input
stage.
1
23
•
•
•
•
•
Sample Rate: 2MSPS
Pin-Compatible Family: 12/10/8-Bit
Outstanding Performance:
– No Missing Codes
– INL: 1LSB (max)
– SNR: 72dB (min)
Low Power:
– 7.5mW at 2MSPS Operation
– Auto Power-Down at Lower Speeds:
– 3.8mW at 500kSPS
– 0.8mW at 100kSPS
– 0.16mW at 20kSPS
Wide Supply Range:
– Analog: 2.7V to 5.5V
– Digital: 1.65V to AVDD
Simple Serial Interface (SPI)
Fully Specified from –40°C to +125°C
Tiny Footprint: 3mm × 3mm QFN
The ADS7947/8/9 support a wide analog supply
range that allows the full-scale input range to extend
to 5V. A simple SPI™, with a digital supply that can
operate as low as 1.65V, allows for easy interfacing
to a wide variety of digital controllers. Automatic
power-down can be enabled when operating at
slower speeds to dramatically reduce power
consumption.
APPLICATIONS
•
•
•
•
•
Offered in a tiny 3mm × 3mm QFN package, the
ADS7947/8/9 are fully specified over the extended
temperature range of –40°C to +125°C and are
suitable for a wide variety of data acquisition
applications where high performance, low power, and
small size are key.
Communication Systems
Optical Networking
Medical Instrumentation
Battery-Powered Equipment
Data Acquisition Systems
AVDD
REF
REFGND
DVDD
PDEN
AIN0P
AIN0N
CS
MUX
S/H
SAR
ADC
SPI
SCLK
SDO
AIN1P
AIN1N
CH SEL
GND
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
ADS7947
ADS7948
ADS7949
SLAS708 – SEPTEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FAMILY AND ORDERING INFORMATION (1)
(1)
PRODUCT
RESOLUTION (Bits)
INPUT
SAMPLE RATE (MSPS)
ADS7947
12
Unipolar, pseudo-differential
2
ADS7948
10
Unipolar, pseudo-differential
2
ADS7949
8
Unipolar, pseudo-differential
2
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
ADS7947, ADS7948, ADS7949
MIN
MAX
AINxP to GND or AINxN to GND
–0.3
AVDD + 0.3
V
AVDD to GND or DVDD to GND
–0.3
+7
V
Digital input voltage to GND
–0.3
DVDD + 0.3
V
Digital output to GND
–0.3
DVDD + 0.3
V
Operating temperature range
–40
+125
°C
Storage temperature range
–65
+150
°C
(1)
UNIT
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under electrical characteristics is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
ADS7947/48/49
THERMAL METRIC (1)
RTE
UNITS
16 PINS
qJA
Junction-to-ambient thermal resistance
54.3
qJCtop
Junction-to-case (top) thermal resistance
53.7
qJB
Junction-to-board thermal resistance
19.2
yJT
Junction-to-top characterization parameter
0.3
yJB
Junction-to-board characterization parameter
14.5
qJCbot
Junction-to-case (bottom) thermal resistance
5.2
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7947 ADS7948 ADS7949
ADS7947
ADS7948
ADS7949
www.ti.com
SLAS708 – SEPTEMBER 2010
ELECTRICAL CHARACTERISTICS: ADS7947 (12-Bit)
Minimum/maximum specifications at AVDD = 2.7V to 5.5V, DVDD = 1.65V to AVDD, TA = –40°C to +125°C, and
fSAMPLE = 2MSPS, unless otherwise noted. Typical specifications at AVDD = 3V, DVDD = 1.8V, TA = +25°C, and fSAMPLE =
2MSPS.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Full-scale input span (1)
AINxP – AINxN
Absolute input range
0
VREF
V
AIN0P, AIN1P
–0.2
AVDD + 0.2
V
AIN0N, AIN1N
–0.2
Input capacitance (2)
Input leakage current
At +125°C
0.2
V
32
pF
1.5
nA
12
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
12
Integral linearity
–1
±0.3
1
LSB (3)
Bits
Differential linearity
–1
±0.3
1
LSB
Offset error (4)
–1
±0.3
1
LSB
Gain error
–1
±0.3
1
LSB
25
µVRMS
Transition noise
Power-supply rejection
60
dB
SAMPLING DYNAMICS
Conversion time
Acquisition time
13.5
SCLK
2
MSPS
2.1
MSPS
80
Maximum sample rate (throughput rate)
ns
34MHz SCLK with a 16-clock frame
34MHz SCLK and CS low for 13.5 clocks
Aperture delay
5
ns
Aperture jitter
10
ps
Step response
80
ns
Overvoltage recovery
80
ns
–85
dB
DYNAMIC CHARACTERISTICS
Total harmonic distortion (THD) (5)
100kHz
Signal-to-noise ratio (SNR)
100kHz
73
dB
Signal-to-noise and distorion ratio (SINAD)
100kHz
72.75
dB
Spurious-free dynamic range (SFDR)
100kHz
86
dB
Full-power bandwidth
At –3dB
15
MHz
72
DIGITAL INPUT/OUTPUT
Logic family
CMOS
VIH
Logic level
Input leakage current
0.7DVDD
VIL
0.3DVDD
VOH
ISOURCE = 200µA
VOL
ISINK = 200µA
IIH, IIL
0 < VIN < DVDD
DVDD – 0.2
External reference
(1)
(2)
(3)
(4)
(5)
V
V
0.4
V
±20
2.5
V
nA
AVDD
V
Ideal input span; does not include gain or offset error.
Refer to Figure 39 for sampling circuit details.
LSB means Least Significant Bit.
Measured relative to an ideal full-scale input.
Calculated on the first nine harmonics of the input frequency.
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7947 ADS7948 ADS7949
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ADS7947
ADS7948
ADS7949
SLAS708 – SEPTEMBER 2010
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ELECTRICAL CHARACTERISTICS: ADS7947 (12-Bit) (continued)
Minimum/maximum specifications at AVDD = 2.7V to 5.5V, DVDD = 1.65V to AVDD, TA = –40°C to +125°C, and
fSAMPLE = 2MSPS, unless otherwise noted. Typical specifications at AVDD = 3V, DVDD = 1.8V, TA = +25°C, and fSAMPLE =
2MSPS.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
AVDD
2.7
3.3
5.5
V
DVDD
1.65
3.3
AVDD
V
POWER-SUPPLY REQUIREMENTS
IDYNAMIC
AVDD supply current
ISTATIC
DVDD supply current
(6)
Power-down state
AVDD supply current
AVDD = 3.3V, fSAMPLE = 2MSPS
2.5
AVDD = 5V, fSAMPLE = 2MSPS
mA
3
AVDD = 3.3V, SCLK off
3.5
1.8
AVDD = 5V, SCLK off
1.9
DVDD = 3.3V, SCLK = 34MHz,
SDO load 20pF
500
mA
mA
2.5
mA
µA
IPD-DYNAMIC
SCLK = 34MHz
550
µA
IPD-STATIC
SCLK off
2.5
µA
1
µs
+125
°C
Power-up time
TEMPERATURE RANGE
Specified performance
(6)
4
–40
DVDD consumes only dynamic current. IDVDD = CLOAD × DVDD × number of 0→1 transitions in SDO × fSAMPLE. This is a
load-dependent current and there is no DVDD current when the output is not toggling.
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7947 ADS7948 ADS7949
ADS7947
ADS7948
ADS7949
www.ti.com
SLAS708 – SEPTEMBER 2010
ELECTRICAL CHARACTERISTICS: ADS7948 (10-Bit)
Minimum/maximum specifications at AVDD = 2.7V to 5.5V, DVDD = 1.65V to AVDD, TA = –40°C to +125°C, and
fSAMPLE = 2MSPS, unless otherwise noted. Typical specifications at AVDD = 3V, DVDD = 1.8V, TA = +25°C, and fSAMPLE =
2MSPS.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Full-scale input span (1)
AINxP – AINxN
Absolute input range
0
VREF
V
AIN0P, AIN1P
–0.2
AVDD + 0.2
V
AIN0N, AIN1N
–0.2
Input capacitance (2)
Input leakage current
At +125°C
0.2
V
32
pF
1.5
nA
10
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
10
Bits
Integral linearity
–0.5
±0.15
0.5
LSB (3)
Differential linearity
–0.5
±0.15
0.5
LSB
Offset error (4)
–0.5
±0.15
0.5
LSB
Gain error
–0.5
±0.15
0.5
LSB
25
µVRMS
Transition noise
Power-supply rejection
60
dB
SAMPLING DYNAMICS
Conversion time
Acquisition time
10.5
SCLK
2
MSPS
2.57
MSPS
80
Maximum sample rate (throughput rate)
ns
34MHz SCLK in 16-clock frame
34MHz SCLK and CS low for 10.5 clocks
Aperture delay
5
ns
Aperture jitter
10
ps
Step response
80
ns
Overvoltage recovery
80
ns
–80
dB
DYNAMIC CHARACTERISTICS
Total harmonic distortion (THD) (5)
100kHz
Signal-to-noise ratio (SNR)
100kHz
Signal-to-noise and distortion ratio (SINAD)
100kHz
61
Spurious-free dynamic range (SFDR)
100kHz
81
dB
Full-power bandwidth
At –3dB
15
MHz
61
dB
dB
DIGITAL INPUT/OUTPUT
Logic family
CMOS
VIH
Logic level
Input leakage current
0.7DVDD
VIL
0.3DVDD
VOH
ISOURCE = 200µA
VOL
ISINK = 200µA
IIH, IIL
0 < VIN < DVDD
DVDD – 0.2
External reference
(1)
(2)
(3)
(4)
(5)
V
V
0.4
V
±20
2.5
V
nA
AVDD
V
Ideal input span; does not include gain or offset error.
Refer to Figure 39 for sampling circuit details.
LSB means Least Significant Bit.
Measured relative to an ideal full-scale input.
Calculated on the first nine harmonics of the input frequency.
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7947 ADS7948 ADS7949
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5
ADS7947
ADS7948
ADS7949
SLAS708 – SEPTEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: ADS7948 (10-Bit) (continued)
Minimum/maximum specifications at AVDD = 2.7V to 5.5V, DVDD = 1.65V to AVDD, TA = –40°C to +125°C, and
fSAMPLE = 2MSPS, unless otherwise noted. Typical specifications at AVDD = 3V, DVDD = 1.8V, TA = +25°C, and fSAMPLE =
2MSPS.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
AVDD
2.7
3.3
5.5
V
DVDD
1.65
3.3
AVDD
V
POWER-SUPPLY REQUIREMENTS
IDYNAMIC
AVDD supply current
ISTATIC
DVDD supply current
(6)
Power-down state
AVDD supply current
AVDD = 3.3V, fSAMPLE = 2MSPS
2.5
AVDD = 5V, fSAMPLE = 2MSPS
mA
3
AVDD = 3.3V, SCLK off
3.5
1.8
AVDD = 5V, SCLK off
1.9
DVDD = 3.3V, SCLK = 34MHz,
SDO load 20pF
500
mA
mA
2.5
mA
µA
IPD-DYNAMIC
SCLK = 34MHz
550
µA
IPD-STATIC
SCLK off
2.5
µA
1
µs
+125
°C
Power-up time
TEMPERATURE RANGE
Specified performance
(6)
6
–40
DVDD consumes only dynamic current. IDVDD = CLOAD × DVDD × number of 0→1 transitions in SDO × fSAMPLE. This is a
load-dependent current and there is no DVDD current when the output is not toggling.
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7947 ADS7948 ADS7949
ADS7947
ADS7948
ADS7949
www.ti.com
SLAS708 – SEPTEMBER 2010
ELECTRICAL CHARACTERISTICS: ADS7949 (8-Bit)
Minimum/maximum specifications at AVDD = 2.7V to 5.5V, DVDD = 1.65V to AVDD, TA = –40°C to +125°C, and
fSAMPLE = 2MSPS, unless otherwise noted. Typical specifications at AVDD = 3V, DVDD = 1.8V, TA = +25°C, and fSAMPLE =
2MSPS.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Full-scale input span (1)
AINxP – AINxN
Absolute input range
0
VREF
V
AIN0P, AIN1P
–0.2
AVDD + 0.2
V
AIN0N, AIN1N
–0.2
Input capacitance (2)
Input leakage current
At +125°C
0.2
V
32
pF
1.5
nA
8
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
8
Bits
Integral linearity
–0.3
±0.06
0.3
LSB (3)
Differential linearity
–0.3
±0.06
0.3
LSB
Offset error (4)
–0.3
±0.06
0.3
LSB
Gain error
–0.3
±0.06
0.3
LSB
25
µVRMS
Transition noise
Power-supply rejection
60
dB
SAMPLING DYNAMICS
Conversion time
8.5
SCLK
34MHz SCLK in 16-clock frame
2
MSPS
34MHz SCLK and CS low for 8.5 clocks
3
MSPS
5
ns
Acquisition time
80
Maximum sample rate (throughput rate)
ns
Aperture delay
Aperture jitter
10
ps
Step response
80
ns
Overvoltage recovery
80
ns
–80
dB
DYNAMIC CHARACTERISTICS
Total harmonic distortion (THD) (5)
100kHz
Signal-to-noise ratio (SNR)
100kHz
Signal-to-noise and distortion ratio (SINAD)
100kHz
49
Spurious-free dynamic range (SFDR)
100kHz
81
dB
Full-power bandwidth
At –3dB
15
MHz
49
dB
dB
DIGITAL INPUT/OUTPUT
Logic family
CMOS
VIH
Logic level
Input leakage current
0.7DVDD
VIL
0.3DVDD
VOH
ISOURCE = 200µA
VOL
ISINK = 200µA
IIH, IIL
0 <VIN < DVDD
DVDD – 0.2
External reference
(1)
(2)
(3)
(4)
(5)
V
V
0.4
V
±20
2.5
V
nA
AVDD
V
Ideal input span; does not include gain or offset error.
Refer to Figure 39 for sampling circuit details.
LSB means Least Significant Bit.
Measured relative to an ideal full-scale input.
Calculated on the first nine harmonics of the input frequency.
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7947 ADS7948 ADS7949
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ADS7947
ADS7948
ADS7949
SLAS708 – SEPTEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: ADS7949 (8-Bit) (continued)
Minimum/maximum specifications at AVDD = 2.7V to 5.5V, DVDD = 1.65V to AVDD, TA = –40°C to +125°C, and
fSAMPLE = 2MSPS, unless otherwise noted. Typical specifications at AVDD = 3V, DVDD = 1.8V, TA = +25°C, and fSAMPLE =
2MSPS.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
AVDD
2.7
3.3
5.5
V
DVDD
1.65
3.3
AVDD
V
POWER-SUPPLY REQUIREMENTS
IDYNAMIC
AVDD supply current
ISTATIC
DVDD supply current
(6)
Power-down state
AVDD supply current
AVDD = 3.3V, fSAMPLE = 2MSPS
2.5
AVDD = 5V, fSAMPLE = 2MSPS
mA
3
AVDD = 3.3V, SCLK off
3.5
1.8
AVDD = 5V, SCLK off
1.9
DVDD = 3.3V, SCLK = 34MHz,
SDO load 20pF
500
mA
mA
2.5
mA
µA
IPD-DYNAMIC
SCLK = 34MHz
550
µA
IPD-STATIC
SCLK off
2.5
µA
1
µs
+125
°C
Power-up time
TEMPERATURE RANGE
Specified performance
(6)
8
–40
DVDD consumes only dynamic current. IDVDD = CLOAD × DVDD × number of 0→1 transitions in SDO × fSAMPLE. This is a
load-dependent current and there is no DVDD current when the output is not toggling.
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7947 ADS7948 ADS7949
ADS7947
ADS7948
ADS7949
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SLAS708 – SEPTEMBER 2010
TIMING DIAGRAM
Sample
N
Sample
N+1
1/fSAMPLE
tACQ
tCONV
CS
tSU1
SCLK
1
tWH
2
3
tD1
SDO
D11
4
5
6
7
D9
8
9
10
tW1
tD4
11
12
13
14
15
16
tD3
tD2
tH1
D10
tWL
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data from Sample N-1
TIMING REQUIREMENTS
All specifications at DVDD = 1.65V to AVDD and TA = –40°C to +125°C, unless otherwise noted.
TEST CONDITIONS (1)
PARAMETER
tCONV
tACQ
Conversion time
MAX
UNIT
ADS7947 (12-bit)
13.5
SCLK
ADS7948 (10-bit)
10.5
SCLK
ADS7949 (8-bit)
8.5
SCLK
Acquisition time
fSAMPLE
Sample rate (throughput rate)
SCLK = 34MHz
2.1
MSPS
SCLK = 34MHz
2.57
MSPS
ADS7949 (8-bit)
SCLK = 34MHz
3
MSPS
25
ns
DVDD = 1.8V
14.5
ns
DVDD = 3V
12.5
ns
DVDD = 5V
8.5
ns
DVDD = 1.8V
3.5
ns
DVDD = 3V
3.5
ns
DVDD = 5V
3.5
ns
DVDD = 1.8V
tH1
Delay time, SCLK falling to SDO
Hold time, SCLK falling to data valid
11
ns
DVDD = 3V
9
ns
DVDD = 5V
7.1
ns
DVDD = 1.8V
4
ns
DVDD = 3V
3
ns
DVDD = 5V
2
ns
DVDD = 1.8V
tD3
Delay time, CS high to SDO 3-state
15
ns
DVDD = 3V
12.5
ns
DVDD = 5V
8.5
ns
tD4
Delay time CS rising edge from conversion end
(refer to the tCONV specification for conversion time)
10
tWH
Pulse duration, SCLK high
11
tW1
Pulse duration, SCLK low
11
SCLK frequency
0.4
tPDSU
Setup time, PDEN high to CS rising edge
(refer to Figure 50 and Figure 51)
tPDH
Hold time, CS rising edge to PDEN falling edge (refer to Figure 50)
(1)
(2)
MSPS
ADS7948 (10-bit)
Setup time, CS low to first rising edge of SCLK
tD2 (2)
2
ADS7947 (12-bit)
Delay time, CS low to first data (D0-15) out
tSU1
ns
SCLK = 34MHz,
16 clock frame
Pulse width CS high
tD1
TYP
80
fSAMPLE MAX = 1/( tCONV MAX + tACQ MIN)
tW1
MIN
ns
ns
ns
34
40
2
20
MHz
ns
ns
1.8V specifications apply from 1.65V to 2V; 3V specifications apply form 2.7V to 3.6V; 5V specifications apply from 4.75V to 5.25V.
With 50pF load.
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ADS7948
ADS7949
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PIN CONFIGURATION
DVDD
SDO
SCLK
CS
16
15
14
13
RTE PACKAGE
QFN-16
(TOP VIEW)
REF
3
10
NC
REFGND
4
9
NC
8
CH SEL
AIN1P
11
7
2
AIN1N
AVDD
6
PDEN
AIN0N
12
5
1
AIN0P
GND
PIN FUNCTIONS
PIN NO.
PIN NAME
FUNCTION
1
GND
Analog/digital
2
AVDD
Analog
ADC power supply
3
REF
Analog
ADC positive reference input; decouple this pin with REFGND
4
REFGND
Analog
Reference return; short to analog ground plane
5
AIN0P
Analog input
Positive analog input, channel 0
6
AIN0N
Analog input
Negative analog input, channel 0. Note that the allowable signal swing on this pin is
±0.2V; this pin can be grounded.
7
AIN1N
Analog input
Negative analog input, channel 1. Note that the allowable signal swing on this pin is
±0.2V; this pin can be grounded.
8
AIN1P
Analog input
Positive analog input, channel 1
9
NC
—
Not connected internally, it is recommended to externally short this pin to GND
10
NC
—
Not connected internally, it is recommended to externally short this pin to GND
10
DESCRIPTION
Power supply ground; all analog and digital signals are referred with respect to this pin
11
CH SEL
Digital input
This pin selects the analog input channel.
Low = channel 0, high = channel 1.
It is recommended to change the channel within a window of one clock; from half a clock
after the CS falling edge. This change ensures the settling on the multiplexer output
before the sample start.
12
PDEN
Digital input
This pin enables a power-down feature if it is high at the CS rising edge
13
CS
Digital input
Chip select signal; active low
14
SCLK
Digital input
Serial SPI clock
15
SDO
Digital output
Serial data out
16
DVDD
Digital
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Digital I/O supply
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TYPICAL CHARACTERISTICS: ADS7947, ADS7948, ADS7949
At TA = +25°C, DVDD = 1.8V, VREF = 2.5V, and fSAMPLE = 2MSPS, unless otherwise noted.
SUPPLY CURRENT vs ANALOG SUPPLY VOLTAGE
SUPPLY CURRENT vs TEMPERATURE
3.2
2.4
AVDD = 3V
2.38
Supply Current (mA)
Supply Current (mA)
3
2.8
2.6
2.4
2.36
2.34
2.32
2.2
2
2.3
2.7
3.2
3.7
4.2
4.7
5.7
5.2
-40 -25 -10
20
5
AVDD, Analog Supply Voltage (V)
35
50
65
80
95
110 125
Free-Air Temperature (°C)
Figure 1.
Figure 2.
STATIC CURRENT vs ANALOG SUPPLY VOLTAGE
STATIC CURRENT vs FREE-AIR TEMPERATURE
1.9
1.77
1.88
1.765
AVDD = 3V
Static Current (mA)
Static Current (mA)
1.86
1.84
1.82
1.8
1.78
1.76
1.76
1.755
1.75
1.745
1.74
1.74
1.735
1.72
1.73
1.7
2.7
3.2
3.7
4.2
4.7
5.7
5.2
-40 -25 -10
AVDD, Analog Supply Voltage (V)
20
5
35
50
65
80
95
110 125
Free-Air Temperature (°C)
Figure 3.
Figure 4.
SUPPLY CURRENT vs THROUGHPUT
2.5
PDEN Pin High
Supply Current (mA)
2
1.5
AVDD = 5V
1
AVDD = 3V
0.5
0
0
100
200
300
400
500
600
700
Throughput (kSPS)
Figure 5.
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TYPICAL CHARACTERISTICS: ADS7947 (12-Bit)
At TA = +25°C, DVDD = 1.8V, VREF = 2.5V, and fSAMPLE = 2MSPS, unless otherwise noted.
INTEGRAL LINEARITY vs
ANALOG SUPPLY VOLTAGE
1
1
0.8
0.8
0.6
0.6
0.4
Integral Linearity (LSBs)
Differential Linearity (LSBs)
DIFFERENTIAL LINEARITY vs
ANALOG SUPPLY VOLTAGE
Maximum DNL
0.2
0
-0.2
Minimum DNL
-0.4
-0.6
-0.8
-1
Maximum INL
0.4
0.2
0
-0.2
Minimum INL
-0.4
-0.6
-0.8
2.7
3.2
3.7
4.2
4.7
-1
5.7
5.2
2.7
3.2
3.7
AVDD, Analog Supply Voltage (V)
4.2
Figure 6.
DIFFERENTIAL LINEARITY vs TEMPERATURE
INTEGRAL LINEARITY vs TEMPERATURE
1
0.8
0.6
Integral Linearity (LSBs)
Differential Linearity (LSBs)
AVDD = 3V
AVDD = 3V
0.8
0.4
Maximum DNL
0.2
0
-0.2
Minimum DNL
-0.4
-0.6
-0.8
0.6
0.4
0.2
Maximum INL
0
-0.2
Minimum INL
-0.4
-0.6
-0.8
-1
-40 -25 -10
5
20
35
50
65
80
95
-1
110 125
-40 -25 -10
5
Free-Air Temperature (°C)
35
50
65
80
95
110 125
Figure 9.
DIFFERENTIAL LINEARITY vs REFERENCE VOLTAGE
INTEGRAL LINEARITY vs REFERENCE VOLTAGE
1
1
AVDD = 5V
AVDD = 5V
0.8
0.6
0.6
Integral Linearity (LSBs)
0.8
0.4
Maximum DNL
0.2
0
-0.2
Minimum DNL
-0.4
-0.6
-0.8
-1
20
Free-Air Temperature (°C)
Figure 8.
Differential Linearity (LSBs)
5.7
5.2
Figure 7.
1
0.4
Maximum INL
0.2
0
-0.2
Minimum INL
-0.4
-0.6
-0.8
2.5
3
3.5
4
4.5
5
-1
2.5
3.5
3
Reference Voltage (V)
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4
4.5
5
Reference Voltage (V)
Figure 10.
12
4.7
AVDD, Analog Supply Voltage (V)
Figure 11.
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TYPICAL CHARACTERISTICS: ADS7947 (12-Bit) (continued)
At TA = +25°C, DVDD = 1.8V, VREF = 2.5V, and fSAMPLE = 2MSPS, unless otherwise noted.
OFFSET ERROR vs TEMPERATURE
1
0.8
0.8
0.6
0.6
Offset Error (LSBs)
Offset Error (LSBs)
OFFSET ERROR vs ANALOG SUPPLY VOLTAGE
1
0.4
0.2
0
-0.2
-0.4
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1
2.7
3.2
3.7
4.2
4.7
-1
5.7
5.2
AVDD = 3V
-40 -25 -10
5
AVDD, Analog Supply Voltage (V)
20
35
50
65
80
95
110 125
Free-Air Temperature (°C)
Figure 12.
Figure 13.
OFFSET ERROR vs REFERENCE VOLTAGE
GAIN ERROR vs ANALOG SUPPLY VOLTAGE
1
1
0.8
0.6
0.6
Gain Error (LSBs)
Offset Error (LSBs)
AVDD = 5V
0.8
0.4
0.2
0
-0.2
-0.4
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1
2.5
3.5
3
4.5
4
-1
5
2.7
3.2
3.7
Reference Voltage (V)
Figure 14.
4.7
5.2
5.7
Figure 15.
GAIN ERROR vs TEMPERATURE
GAIN ERROR vs REFERENCE VOLTAGE
1
1
AVDD = 5V
AVDD = 3V
0.8
0.8
0.6
0.6
Gain Error (LSBs)
Gain Error (LSBs)
4.2
AVDD, Analog Supply Voltage (V)
0.4
0.2
0
-0.2
-0.4
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1
-40 -25 -10
5
20
35
50
65
80
95
110 125
-1
2.5
3
Free-Air Temperature (°C)
Figure 16.
3.5
4
4.5
5
Reference Voltage (V)
Figure 17.
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TYPICAL CHARACTERISTICS: ADS7947 (12-Bit) (continued)
At TA = +25°C, DVDD = 1.8V, VREF = 2.5V, and fSAMPLE = 2MSPS, unless otherwise noted.
SNR vs ANALOG SUPPLY VOLTAGE
fIN = 2kHz
AVDD = 3V
fIN = 2kHz
73.8
Signal-to-Noise Ratio (dB)
73.8
Signal-to-Noise Ratio (dB)
SNR vs TEMPERATURE
74
74
73.6
73.4
73.2
73
72.8
72.6
72.4
73.6
73.4
73.2
73
72.8
72.6
72.4
72.2
72.2
72
72
2.7
3.2
3.7
4.7
4.2
5.2
5.7
-40 -25 -10
5
20
AVDD, Analog Supply Voltage (V)
Figure 18.
SNR vs REFERENCE VOLTAGE
AVDD = 5V
fIN = 2kHz
95
110 125
AVDD = 3V
Throughput = 2MSPS
73.8
Signal-to-Noise Ratio (dB)
Signal-to-Noise Ratio (dB)
80
SNR vs INPUT FREQUENCY
73.6
73.4
73.2
73
72.8
72.6
72.4
72.2
73.6
73.4
73.2
73
72.8
72.6
72.4
72.2
72
72
2.5
3.5
3
4.5
4
0
5
20
40
Reference Voltage (V)
60
80
100
120
Frequency (kHz)
Figure 20.
Figure 21.
SINAD vs ANALOG SUPPLY VOLTAGE
SINAD vs TEMPERATURE
74
74
fIN = 2kHz
Signal-to-Noise and Distortion (dB)
Signal-to-Noise and Distortion (dB)
65
74
73.8
73.6
73.4
73.2
73
72.8
72.6
72.4
72.2
73.8
AVDD = 3V
fIN = 2kHz
73.6
73.4
73.2
73
72.8
72.6
72.4
72.2
72
72
2.7
3.2
3.7
4.2
4.7
5.2
5.7
-40 -25 -10
5
Figure 22.
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20
35
50
65
80
95
110 125
Free-Air Temperature (°C)
AVDD, Analog Supply Voltage (V)
14
50
Figure 19.
74
73.8
35
Free-Air Temperature (°C)
Figure 23.
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TYPICAL CHARACTERISTICS: ADS7947 (12-Bit) (continued)
At TA = +25°C, DVDD = 1.8V, VREF = 2.5V, and fSAMPLE = 2MSPS, unless otherwise noted.
SINAD vs REFERENCE VOLTAGE
SINAD vs INPUT FREQUENCY
74
AVDD = 5V
fIN = 2kHz
73.8
Signal-to-Noise and Distortion (dB)
Signal-to-Noise and Distortion (dB)
74
73.6
73.4
73.2
73
72.8
72.6
72.4
72.2
72
AVDD = 3V
Throughput = 2MSPS
73.8
73.6
73.4
73.2
73
72.8
72.6
72.4
72.2
72
2.5
3.5
3
4.5
4
0
5
20
40
Reference Voltage (V)
Figure 24.
SFDR vs AVDD
120
100
SFDR vs TEMPERATURE
91.9
fIN = 2kHz
Spurious-Free Dynamic Range (dB)
Spurious-Free Dynamic Range (dB)
80
Figure 25.
92.5
92
91.5
91
90.5
90
89.5
89
91.85
91.8
91.75
91.7
AVDD = 3V
fIN = 2kHz
91.65
2.7
3.7
3.2
4.2
4.7
5.2
5.7
-40 -25 -10
AVDD, Analog Supply Voltage (V)
5
20
50
65
80
95
110 125
Figure 27.
SFDR vs REFERENCE VOLTAGE
SFDR vs INPUT FREQUENCY
94
90.35
AVDD = 5V
fIN = 2kHz
Spurious-Free Dynamic Range (dB)
90.3
35
Free-Air Temperature (°C)
Figure 26.
Spurious-Free Dynamic Range (dB)
60
Frequency (kHz)
90.25
90.2
90.15
90.1
90.05
AVDD = 3V
93.5
93
92.5
92
91.5
91
90.5
90
90
2.5
3
3.5
4
4.5
5
0
20
Measured Reference, VREF (V)
Figure 28.
40
60
80
100
120
Input Frequency (kHz)
Figure 29.
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TYPICAL CHARACTERISTICS: ADS7947 (12-Bit) (continued)
At TA = +25°C, DVDD = 1.8V, VREF = 2.5V, and fSAMPLE = 2MSPS, unless otherwise noted.
SFDR vs AVDD
SFDR vs TEMPERATURE
-87.75
fIN = 2kHz
-87
Total Harmonic Distortion (dB)
Total Harmonic Distortion (dB)
-86.8
-87.2
-87.4
-87.6
-87.8
-88
-88.2
AVDD = 3V
fIN = 2kHz
-87.8
-87.85
-87.9
-87.95
-88
-88.05
-88.1
-88.4
2.7
3.7
3.2
4.2
4.7
5.2
5.7
20
5
-40 -25 -10
AVDD, Analog Supply Voltage (V)
Figure 30.
80
95
110 125
THD vs INPUT FREQUENCY
AVDD = 5V
fIN = 2kHz
-86.2
Total Harmonic Distortion (dB)
Total Harmonic Distortion (dB)
65
-86
-86.4
-86.6
-86.8
-87
-87.2
-86.5
-87
-87.5
-88
-88.5
-89
-89.5
-90
-87.4
2.5
3
3.5
4.5
4
0
5
20
40
0
60
80
100
120
Input Frequency (kHz)
Reference, VREF (V)
Figure 32.
Figure 33.
CROSSTALK vs INPUT FREQUENCY(1)
SPECTRAL RESPONSE
(8192-Point FFT)
0
AVDD = 3V
SNR = 73.1dB
THD = -87.5dB
SINAD = 72.9dB
SFDR = 90.6
fIN = 100kHz
-20
-20
-40
-40
Amplitude (dB)
Crosstalk (dB)
50
Figure 31.
THD vs REFERENCE VOLTAGE
-86
-60
-80
Memory Crosstalk
-100
-60
-80
-100
-120
-120
-140
Isolation Crosstalk
-140
-160
0
50
100
150
200
250
300
350
0
100k 200k 300k 400k 500k 600k 700k 800k 900k 1M
Frequency (Hz)
Input Frequency (kHz)
(1) Memory crosstalk is the effect of the last converted channel on
the current converted channel data. Isolation crosstalk is the effect
on the channel being converted that is coming from the signal on the
channel that is off.
Figure 34.
16
35
Free-Air Temperature (°C)
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Figure 35.
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TYPICAL CHARACTERISTICS: ADS7947 (12-Bit) (continued)
At TA = +25°C, DVDD = 1.8V, VREF = 2.5V, and fSAMPLE = 2MSPS, unless otherwise noted.
TYPICAL DNL
1
0.6
0.6
DNL (LSBs)
INL (LSBs)
TYPICAL INL
1
0.2
-0.2
-0.6
-1
0.2
-0.2
-0.6
0
512
1024
1536
2048
2560
3072
3584
4096
-1
0
512
1024
1536
2048
2560
Output Code
Output Code
Figure 36.
Figure 37.
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3072
3584
4096
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OVERVIEW
The ADS7947 is 12-bit, miniature, dual-channel, low-power SAR ADC. The ADS7948 and ADS7949 are 10-bit
and 8-bit devices, respectively, from the same product family. These devices feature very low power
consumption at rated speed. The PDEN pin enables an auto power-down mode that further reduces power
consumption at lower speeds.
MULTIPLEXER AND ADC INPUT
The devices feature pseudo-differential inputs with a double-pole, double-throw multiplexer. The negative inputs
(AINxN) can accept swings of ±0.2V; the positive inputs (AINxP) allow signals in the range of 0V to VREF over the
negative input. The ADC converts the difference in voltage: VAINxP – VAINxN. This feature can be used in multiple
ways.
Two signals can be connected from different sensors with unequal ground potentials (within ±0.2V) to a single
ADC. The pseudo-differential ADC rejects common-mode offset and noise. This feature also allows the use of a
single-supply op amp. The signal and the AINxN input can be offset by +0.2V, which provides the ground
clearance needed for a single-supply op amp.
Figure 38 shows the electrostatic discharge (ESD) diodes to supply and ground at every analog input. Make sure
that these diodes do not turn on by keeping the supply voltage within the specified input range.
AVDD
AIN0P
GND
AVDD
AIN0N
GND
SAR
ADC
AVDD
AIN1P
GND
AVDD
AIN1N
GND
Figure 38. Analog Inputs
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Figure 39 shows an equivalent circuit of the multiplexer and ADC sampling stage. The positive and negative
inputs are separately sampled on 32pF sampling capacitorss. The multiplexer and sampling switches are
represented by an ideal switch in series with a 12Ω resistance. During sampling, the devices connect the 32pF
sampling capacitor to the ADC driver. This connection creates a glitch at the device input. It is recommended to
connect a capacitor across the AINxP and AINxN terminals to reduce this glitch. A driving circuit must have
sufficient bandwidth to settle this glitch within the acquisition time.
12W
AIN0P
32pF
12W
AIN1P
12W
AIN0N
32pF
12W
AIN1N
Figure 39. Input Sampling Stage Equivalent Circuit
(See the Application Information section for details on the driving circuit.)
Figure 40 shows a timing diagram for the ADC analog input channel selection. As shown in Figure 40, the CH
SEL signal selects the analog input channel to the ADC. CH SEL = 0 selects channel 0 ( AIN0P – AIN0N) and
CH SEL = 1 selects channel 1 ( AIN1P – AIN1N). It is recommended not to toggle the CH SEL signal during an
ADC acquisition phase until the device sees the first valid SCLK rising edge after the device samples the analog
input. If CH SEL is toggled during this period, it can cause erroneous output code as the device might see
unsettled analog input.
CH SEL can be toggled at any time during the window specified in Figure 40; however, it is recommended to
select the desired channel after the first SCLK rising edge and before the second SCLK rising edge. This timing
ensures that the multiplexer output is settled before the ADC starts acquisition of the analog input.
Sample
N (AIN0)
Sample
N+1 (AIN1)
tCONV
Conversion of Sample N
tACQ
Acquisition of AIN1
Sample
N+2 (AIN0)
tCONV
Conversion of Sample N+1
tACQ
Acquisition of AIN0
CS
SCLK
1
2
3
N
(1)
1
2
3
N
(1)
CH SEL
Window for
CH SEL Toggle
Do Not Toggle CH SEL
in This Window
(1) N indicates the 14th SCLK rising edge for the ADS7947 (12-bit) , the 11th rising edge for the ADS7948 (10-bit), and the ninth rising edge
for the ADS7949 (8-bit).
Figure 40. ADC Analog Input Channel Selection
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REFERENCE
The ADS7947/8/9 use an external reference voltage during the conversion of a sampled signal. The devices
switch the capacitors used in the conversion process to the reference terminal during conversion. The switching
frequency is the same as the SCLK frequency. It is necessary to decouple the REF terminal to REFGND with a
1µF ceramic capacitor in order to get the best noise performance from the device. The capacitor must be placed
closest to these pins. The reference input can be driven with the REF50xx series precision references from TI.
Figure 41 shows a typical reference driving circuit.
Sometimes it is convenient to use AVDD as a reference. The ADS794x allow reference ranges up to AVDD.
However, make sure that AVDD is well-bypassed and that there is a separate bypass capacitor between REF
and REFGND.
AVDD
AVDD
REF50xx
(1)
REF
1mF
Ceramic
ADS7947
ADS7948
ADS7949
REFGND
AGND
GND
(1) Select the appropriate device as described by the required reference value. For example, select the REF5040 for a 4V reference, the
REF5030 for a 3V reference, and the REF5025 for a 2.5V reference. Ensure that (AVDD – REF) > 0.2V so that the REF50xx functions
properly.
Figure 41. Typical Reference Driving Circuit
CLOCK
The ADS794x use SCLK for conversions (typically 34MHz). A lower frequency SCLK can be used for
applications requiring sample rates less than 2MSPS. However, it is better to use a 34MHz SCLK and slow down
the device speed by choosing a lower frequency for CS, which allows more acquisition time. This configuration
relaxes constraints on the output impedance of the driving circuit. Refer to the Application Information section for
calculation of the driving circuit output impedance.
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ADC TRANSFER FUNCTION
The ADS7947 (12-bit), ADS7948 (10-bit), and ADS7949 (8-bit) devices are unipolar, pseudo-differential input.
The ADC output is in straight binary format. Figure 42 shows ideal characteristics for this family of devices. Here,
FSR is the full-scale range for the ADC input (AINxP – AINxN) and is equal to the reference input voltage to the
ADC (VREF). 1LSB is equal to (VREF/2N) where N is the resolution of the ADC (for example, N = 12 for the
ADS7947).
ADC Code
111¼111
100¼000
000¼001
1LSB
FSR/2
FSR - 1LSB
Analog Input
Figure 42. ADS7947/8/9 Transfer Characteristics
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DEVICE OPERATION
The ADS7947/8/9 are typically operated with either a 16-clock frame or 32-clock frame for ease of interfacing
with the host processor.
16-CLOCK FRAME
Figure 43 through Figure 45 show the devices operating in 16-clock mode. This mode is the fastest mode for
device operation. In this mode, the devices output data from previous conversions while converting the recently
sampled signal.
As shown in Figure 43, the ADS7947 starts acquisition of the analog input from the 14th rising edge of SCLK.
The device samples the input signal on the CS falling edge. SDO comes out of 3-state and the device outputs
the MSB on the CS falling edge. The device outputs the next lower SDO bits on every SCLK falling edge after it
has first seen the SCLK rising edge. The data correspond to the sample and conversion completed in the
previous frame. During a CS low period, the device converts the recently sampled signal. It uses SCLK for
conversions. The number of clocks needed for a conversion for 12-bit and 8-bit devices are different. For the
ADS7947, conversion is complete on the 14th SCLK rising edge. CS can be high at any time after the 14th
SCLK rising edge. The CS rising edge after the 14th SCLK rising edge and before the 29th SCLK falling edge
keeps the device in the 16-clock data frame. The device output goes to 3-state with CS high.
Sample
N
Sample
N+1
tACQ
tCONV
CS
SCLK
SDO
1
D11
2
3
4
5
6
7
8
9
10
11
12
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
13
14
15
16
Data from Sample N-1
Figure 43. ADS7947 Operating in 16-Clock Mode without Power-Down (PDEN = 0)
It is also permissible to stop SCLK after device has seen the 14th SCLK rising edge.
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Figure 44 and Figure 45 show the 16-clock mode operation for the ADS7948 and ADS7949, respectively. The
operation for these 10-bit and 8-bit devices is identical to the ADS7947 except that the conversion ends on
different edges of SCLK. For the ADS7948, the conversion ends and acquisition starts on the 11th SCLK rising
edge. For the ADS7949, the device uses the ninth SCLK rising edge for the conversion end and acquisition start.
Similar to the ADS7947, CS can go high and SCLK may be stopped once the device enters acquisition.
Sample
N
Sample
N+1
tACQ
tCONV
CS
SCLK
1
2
3
4
5
6
7
8
9
10
SDO
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
11
12
13
14
15
16
Data from Sample N-1
Figure 44. ADS7948 Operating in 16-Clock Mode without Power-Down (PDEN = 0)
Sample
N
Sample
N+1
tACQ
tCONV
CS
SCLK
1
2
3
4
5
6
7
8
SDO
D7
D6
D5
D4
D3
D2
D1
D0
9
10
11
12
13
14
15
16
Data from Sample N-1
Figure 45. ADS7949 Operating in 16-Clock Mode without Power-Down (PDEN = 0)
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32-CLOCK FRAME
Figure 46 through Figure 48 show the devices operating in 32-clock mode. In this mode, the devices convert and
output the data from the most recent sample before taking the next sample.
Sample
N
Sample
N+1
tACQ
tCONV
CS
1
SCLK
2
14
15
16
17
D11
SDO
18
23
24
25
26
27
28
D10
D5
D4
D3
D2
D1
D0
29
30
31
32
Data from Sample N
Figure 46. ADS7947 Operation in 32-Clock Frame without Power-Down (PDEN = 0)
Sample
N
Sample
N+1
tACQ
tCONV
CS
1
SCLK
2
11
12
16
SDO
17
18
23
24
25
26
D9
D8
D3
D2
D1
D0
27
28
29
30
31
32
Data from Sample N
Figure 47. ADS7948 Operating in 32-Clock Frame without Power-Down (PDEN = 0)
Sample
N
Sample
N+1
tACQ
tCONV
CS
SCLK
1
2
9
SDO
10
16
17
18
23
24
D7
D6
D1
D0
25
26
27
28
29
30
31
32
Data from Sample N
Figure 48. ADS7949 Operating in 32-Clock Frame without Power-Down (PDEN = 0)
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CS can be held low past the 16th falling edge of SCLK. The device continues to output recently converted data
starting with the 16th SCLK falling edge. If CS is held low until the 30th SCLK falling edge, then the device
detects 32-clock mode. Note that the device data from recent conversions are already out with no latency before
the 30th SCLK falling edge. Once 32-clock mode is detected, the device outputs 16 zeros during the next
conversion (in fact, for the first 16 clocks), unlike 16-clock mode where the device outputs the previous
conversion result. SCLK can be stopped after the device has seen the 30th falling edge with CS low.
POWER-DOWN
The ADS7947/8/9 family of devices offer an easy-to-use power-down feature available through a dedicated
PDEN pin (pin 12). A high level on PDEN at the CS rising edge enables the power-down mode for that particular
cycle. Figure 49 to Figure 51 illustrate device operation with power-down in both 32-clock and 16-clock mode.
Many applications must slow device operation. For speeds below approximately 500kSPS, it is convenient to use
32-clock mode with power-down. This results in considerable power savings.
As shown in Figure 49, PDEN is held at a logic '1' level. Note that the device looks at the PDEN status only at
the CS rising edge; however, for continuous low-speed operation, it is convenient to continuously hold PDEN = 1.
The devices detect power-down mode on the CS rising edge with PDEN = 1.
tACQ
tCONV
11th and 9th SCLK rising edge for 10- and 8-bit devices, respectively.
CS
SCLK
tACQ (min)+ 1ms
1
2
14
15
16
D11
SDO
18
27
28
29
D10
D2
D1
D0
17
30
31
32
Data from Sample N
Power-Down
State
(Internal)
Active
Power-Down
Active
IDYNAMIC
ISTATIC
IAVDD
Profile
IPD-DYNAMIC
IPD-STATIC if
SCLK is off;
otherwise,
IPD-DYNAMIC.
Figure 49. Operation with a 32-Clock Frame in Power-Down Mode (PDEN = 1)
On the CS falling edge, the devices start normal operation as previously described. The devices complete
conversions on the 14th SCLK rising edge. (Conversions complete on the 11th and ninth SCLK rising edge for
10-bit and 8-bit devices, respectively.) The devices enter the power-down state immediately after conversions
complete. However, the devices can still output data as per the timings described previously. The devices
consume dynamic power-down current (IPD-DYNAMIC) during data out operations. It is recommended to stop the
clock after the 32nd SCLK falling edge to further save power down to the static power-down current level
(IPD-STATIC). The devices power up again on the SCLK rising edge. However, they require an extra 1µs to power
up completely. CS must be high for the 1µs + tACQ (min) period.
In some applications, data collection is accomplished in burst mode. The system powers down after data
collection. 16-clock mode is convenient for these applications. Figure 50 and Figure 51 detail power saving in
16-clock burst mode.
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ADS7948
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tPDSU
tPDH
PDEN
Sample
N-1
Dummy
Sample
Sample
N
CS
SCLK
1
15
2
16
1
2
15
16
1
11
2
12
13
14
15
16
SDO
Data from Sample
N-2
Data from Sample
N-1
Data from Sample
N
Power-Down
State
(Internal)
Active
Power-Down
Figure 50. Entry Into Power-Down with 16-Clock Burst Mode
As shown in Figure 50, the two frames capturing the N–1 and Nth samples are normal 16-clock frames. Keeping
PDEN = 1 prior to the CS rising edge in the next frame ensures that the devices detect the power-down mode.
Data from the Nth sample are read during this frame. It is expected that the Nth sample represents the last data
of interest in the burst of conversions. The devices enter power-down state after the end of conversions. This is
the 14th, 11th, or ninth SCLK rising edge for the 12-, 10-, and 8-bit devices, respectively. The clock may be
stopped after the 14th SCLK falling edge; however, it is recommended to stop the clock after the 16th SCLK
falling edge. Note that it is mandatory not to have more than 29 SCLK falling edges during the CS low period.
This limitation ensures that the devices remain in 16-clock mode.
tPDSU
PDEN
Sample
N+1
CS
Sample
N+3
Sample
N+2
tACQ (min) + 1ms
1
SCLK
2
15
16
1
2
15
16
1
2
SDO
Invalid Data
Power-Down
State
(Internal)
Power-Down
Data from Sample
N+1
Data from Sample
N+2
Active
Figure 51. Exit From Power-Down with 16-Clock Burst Mode
The devices remain in a power-down state as long as CS is low. A CS rising edge with PDEN = 0 brings the
devices out of the power-down state. It is necessary to ensure that the CS high time for the first sample after
power up is more than 1µs + tACQ (min).
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APPLICATION INFORMATION
The device employs a sample-and-hold stage at the input; see Figure 39 for a typical equivalent circuit of a
sample-and-hold stage. The device connects a 32pF sampling capacitor during sampling. This configuration
results in a glitch at the input terminals of the device at the start of the sample. The external circuit must be
designed in such a way that the input can settle to the required accuracy during the sampling time chosen.
Figure 52 shows a typical driving circuit for the analog inputs.
0V to VREF
+VA
+
5W
OPA365
AVDD
AINxP
50W
470pF
ADS7947
ADS7948
ADS7949
AINxN
5W
GND
Figure 52. Typical Input Driving Circuit
The 470pF capacitor across the AINxP and AINxN terminals decouples the driving op amp from the sampling
glitch. It is recommended to split the series resistance of the input filter in two equal values as shown in
Figure 52. It is recommended that both input terminals see the same impedance from the external circuit. The
low-pass filter at the input limits noise bandwidth of the driving op amp. Select the filter bandwidth so that the
full-scale step at the input can settle to the required accuracy during the sampling time. Equation 1, Equation 2,
and Equation 3 are useful for filter component selection.
Sampling Time
Filter Time Constant (tAU) =
Settling Resolution ´ ln(2)
Where:
Settling resolution is the accuracy in LSB to which the input needs to settle. A typical settling resolution
for the 12-bit device is 13 or 14.
(1)
Filter Time Constant (tAU) = R ´ C
(2)
Filter Bandwidth =
1
2 ´ p ´ tAU
(3)
Also, make sure the driving op amp bandwidth does not limit the signal bandwidth below filter bandwidth. In
many applications, signal bandwidth may be much lower than filter bandwidth. In this case, an additional
low-pass filter may be used at the input of the driving op amp. This signal filter bandwidth can be selected in
accordance with the input signal bandwidth.
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DRIVING AN ADC WITHOUT A DRIVING OP AMP
There are some low input signal bandwidth applications, such as battery power monitoring or mains monitoring.
For these applications, it is not required to operate an ADC at high sampling rates and it is desirable to avoid
using a driving op amp from a cost perspective. In this case, the ADC input sees the impedance of the signal
source (such as a battery or mains transformer). This section elaborates the effects of source impedance on
sampling frequency.
Equation 1 can be rewritten as Equation 4:
Sampling Time = Filter Time Constant × Settling Resolution × ln(2)
(4)
As shown in Figure 53, it is recommended to use a bypass capacitor across the positive and negative ADC input
terminals.
+VA
RSOURCE
AVDD
AINxP
ADS7947
ADS7948
ADS7949
CBYPASS
AINxN
Signal
Source
R1
5W
GND
Figure 53. Driving an ADC Without a Driving Op Amp
Source impedance (RSOURCE + R1) with (CBYPASS + CSAMPLE) acts as a low-pass filter with Equation 5:
Filter Time Constant = (RSOURCE + R1) × (CBYPASS + CSAMPLE)
Where:
CSAMPLE is the internal sampling capacitance of the ADC (equal to 32pF).
(5)
Table 1 lists the recommended bypass capacitor values and the filter time constant for different source
resistances. It is recommended to use a 10pF bypass capacitor, at minimum.
Table 1. Filter Time Constant versus Source Resistance
RSOURCE (Ω)
RSOURCE + R1
APPROXIMATE CBYPASS
(pF)
CBYPASS + CSAMPLE (pF)
FILTER TIME
CONSTANT (ns)
15
20
370
400
8
25
30
235
267
8
50
55
115
145
8
100
105
44
76
8
180
185
10
43.2
8
250
255
10
42
10.7
1000
1005
10
42
42.2
5000
5005
10
42
210.2
Typically, settling resolution is selected as (ADC resolution + 2). For the ADS7947 (12-bit) the ideal settling
resolution is 14. Using equations Equation 2 and Equation 3, the sampling time can be easily determined for a
given source impedance. This allows 80ns of sampling time for a 12-bit ADC with 8ns of filter time constant,
which matches the ADS7947 specifications. For source impedance above 180Ω, the filter time constant
continues to increase beyond the 8ns required for an 80ns sampling time. This increases the minimum
permissible sampling time for 12-bit settling and the device must be operated at a lower sampling rate.
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SLAS708 – SEPTEMBER 2010
The device sampling rate can be maximized by using a 34MHz clock even for lower throughputs. Table 2 shows
typical calculations for the ADS7947(12-bit).
Table 2. Sampling Frequency versus Source Impedance for the ADS7947 (12-Bit)
RSOURCE (Ω)
CBYPASS (pF)
SAMPLING TIME,
tACQ (ns)
CONVERSION TIME, CYCLE TIME, tACQ +
tCONV (ns)
tCONV (ns)
SAMPLING RATE
(MSPS)
180
10
80
397
(with 34MHz clock)
477
2
250
10
107
397
(with 34MHz clock)
504
1.98
1000
10
422
397
(with 34MHz clock)
819
1.2
5000
10
2102
397
(with 34MHz clock)
2499
0.4
It is necessary to allow 1000ns additional sampling time over what is shown in Table 2 if PDEN (pin 12) is set
high.
PCB LAYOUT/SCHEMATIC GUIDELINES
ADCs are mixed-signal devices. For maximum performance, proper decoupling, grounding, and proper
termination of digital signals is essential. Figure 54 shows the essential components around the ADC. All
capacitors shown are ceramic. These decoupling capacitors must be placed close to the respective signal pins.
There is a 47Ω source series termination resistor shown on the SDO signal. This resistor must be placed as
close to pin 15 as possible. Series terminations for SCLK and CS must be placed close to the host.
Analog
Supply
1mF
C3
4
5W
AIN0P
470pF
C2
AIN0N
5W
AIN1N
470pF
C1
AIN1P
GND
1
5
0.1mF
C5
16
6
15
ADS7947
ADS7948
ADS7949
U0
7
14
8
13
NC
9
10
11
DVDD
1mF
C6
Digital
Supply
SDO
SCLK
CS
12
47W
R1
Digital Signals from Host
5W
Input
Signal
2
PDEN
Input
Signal
3
NC
5W
AVDD
Common Analog/
Digital Ground Plane
REF
REFGND
1mF
C4
CH SEL
Reference
Input
Figure 54. Recommended ADC Schematic
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A common ground plane for both analog and digital often gives better results. Typically, the second PCB layer is
the ground plane. The ADC ground pins are returned to the ground plane through multiple vias (PTH). It is a
good practice to place analog components on one side and digital components on other side of the ADC (or
ADCs). All signals must be routed, assuming there is a split ground plane for analog and digital. Furthermore, it
is better to split the ground initially during layout. Route all analog and digital traces so that the traces see the
respective ground all along the second layer. Then short both grounds to form a common ground plane.
Figure 55 shows a typical layout around the ADC.
Figure 55. Recommended ADC Layout
(Only top layer is shown, second layer is common ground for analog and digital.)
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Sep-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
ADS7947SRTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
ADS7947SRTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
ADS7948SRTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
ADS7948SRTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
ADS7949SRTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
ADS7949SRTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Sep-2010
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADS7947SRTER
WQFN
RTE
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS7947SRTET
WQFN
RTE
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS7948SRTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS7948SRTET
WQFN
RTE
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS7949SRTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS7949SRTET
WQFN
RTE
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS7947SRTER
WQFN
RTE
16
3000
346.0
346.0
29.0
ADS7947SRTET
WQFN
RTE
16
250
190.5
212.7
31.8
ADS7948SRTER
WQFN
RTE
16
3000
346.0
346.0
29.0
ADS7948SRTET
WQFN
RTE
16
250
190.5
212.7
31.8
ADS7949SRTER
WQFN
RTE
16
3000
346.0
346.0
29.0
ADS7949SRTET
WQFN
RTE
16
250
190.5
212.7
31.8
Pack Materials-Page 2
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