NSC CLC5957MTD 12-bit, 70msps broadband monolithic a/d converter Datasheet

CLC5957
12-bit, 70MSPS Broadband Monolithic A/D Converter
October 1999
N
CLC5957
12-bit, 70MSPS Broadband Monolithic A/D Converter
General Description
Features
The CLC5957 is a monolithic 12-bit, 70MSPS analog-to-digital
converter. The device has been optimized for use in IF-sampled
digital receivers and other applications where high resolution,
high sampling rate, wide dynamic range, low power dissipation,
and compact size are required. The CLC5957 features differential
analog inputs, low jitter differential universal clock inputs, a low
distortion track-and-hold with 0-300MHz input bandwidth, a bandgap voltage reference, data valid clock output, TTL compatible
CMOS (3.3V or 2.5V) programmable output logic, and a proprietary 12-bit multi-stage quantizer. The CLC5957 is fabricated on
the ABIC-V 0.8 micron BiCMOS process.
• 70MSPS
• Wide dynamic range
SFDR: 74dBc
SFDR w/dither: 85dBFS
SNR: 67dB
• IF sampling capability
• Input bandwidth = 0-300MHz
• Low power dissipation: 640mW
• Very small package: 48-pin TSSOP
• Single +5V supply
• Data valid clock output
• Programmable output levels:
3.3V or 2.5V
The CLC5957 features a 74dBc spurious free dynamic range
(SFDR) and a 67dB signal to noise ratio (SNR). The wideband
track-and-hold allows sampling of IF signals to greater than
250MHz. The part produces two-tone, dithered, SFDR of 83dBFS
at 75MHz input frequency. The differential analog input provides
excellent common mode rejection, while the differential universal
clock inputs minimize jitter. The 48-pin TSSOP package provides
an extremely small footprint for applications where space is a
critical consideration. The CLC5957 operates from a single +5V
power supply. Operation over the industrial temperature range of
-40°C to +85°C is guaranteed. National Semiconductor tests
each part to verify compliance with the guaranteed specifications.
Applications
•
•
•
•
•
•
•
•
Cellular base-stations
Digital communications
Infrared/CCD imaging
IF sampling
Electro-optics
Instrumentation
Medical imaging
High definition video
Actual Size
ME79TG
CLC5957
CL5956
IMTD
N MTD
ADC Block Diagram
First IF Receiver
DAV
Clock
In
IF
Input
AIn
3-bit
Q
T/H
3-bit
Q
3-bit
Q
3-bit
Q
CLC5902
DVGA
(∆G = 42dB)
IF
Saw
CLC5957
12-bit
70MSPS
ADC
~
~
BPF
(150MHz
typ.)
Noise
BPF
12
Dig.
Tuner/
Filter
AGC
20
DAV
3-bit (Gain Control)
3
3
3
3
12
Bit Align/Error Correct
Decimation/filter = 190/0.8
Output BW = 50M/190 X 0.8 = 210KHz
ADC
Out
Receiver SINAD vs. Input Amplitude
Single Tone Output Spectrum w/Dither
90
0
Output Level (dBFS)
-10
SINAD dBc (BW = 216KHz)
Fin = 25.3MHZ
Fsample = 66MHz
-20
-30
-40
-50
-60
-70
-80
-90
-100
60
50
40
30
20
10
0
0
4
8
12
16
20
24
Frequency (MHz)
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
80
70
28
32
-125
-100
-75
-50
-25
0
Input (dBFS)
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CLC5957 Electrical Characteristics (Vcc= +5V, 66MSPS; unless specified) (Tmin = -40°C, Tmax = +85°C)
PARAMETERS
RESOLUTION
DIFF. INPUT VOLTAGE RANGE
MAXIMUM CONVERSION RATE
SNR
SFDR
NO MISSING CODES
CONDITIONS
TEMP
fin = 25MHz, Ain = -1dBFS
fin = 25MHz, Ain = -1dBFS
fin = 5MHz, Ain = -1dBFS
DYNAMIC PERFORMANCE
large-signal bandwidth
overvoltage recovery time
effective aperture delay (Ta)
aperture jitter
Ain = -3dBFS
Ain = 1.5FS (0.01%)
Bits
V
MSPS
dBFS
dBc
300
12
-0.41
0.3
MHz
ns
ns
ps(rms)
67
66
65
66
66
dBFS
dBFS
dBFS
dBFS
dBFS
74
74
72
69
65
dBc
dBc
dBc
dBc
dBc
+25°C
+25°C
68
58
dBFS
dBFS
+25°C
85
dBFS
+25°C
83
dBFS
Full
Full
Full
Full
Full
Full
±0.65
±1.5
Guaranteed
0
1.2
2.37
LSB
LSB
60
60
-30
2.2
Full
Full
Full
Full
ENCODE INPUTS (Universal)
VIH
VIL
differential input swing
logic LOW
logic HIGH
logic HIGH
TIMING (C load < 7pF)
maximum conversion rate
minimum conversion rate
pulse width high
pulse width low
pipeline latency
falling ENCODE to output change (50%) (Tod)
rising ENCODE to DAV change (50%) (Tdv)
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70
63
66
12
2.048
75
66
74
Guaranteed
Full
Full
Full
+25°C
+25°C
+25°C
Full
Full
Full
Full
Full
ANALOG INPUTS
analog differential input voltage range
analog input resistance (single ended)
analog input resistance (differential)
analog input capacitance (single-ended)
DIGITAL OUTPUTS
output voltage
OUTLEV = 1 (open)
OUTLEV = 0 (GND)
TYP
Full
Full
Full
Full
Full
fin = 5MHz, Ain = -1dBFS
fin = 5MHz, Ain = -1dBFS
fin = 5MHz, Ain = -1dBFS
MAX
30
2.6
2.048
500
1000
2
+25°C
+25°C
+25°C
0
0.2
+25°C
+25°C
+25°C
3.2
2.4
Full
+25°C
Full
Full
Full
+25°C
+25°C
2
UNITS
MIN
+25°C
+25°C
+25°C
+25°C
NOISE AND DISTORTION
signal-to-noise ratio (w/o 50 harmonics)
fin = 5.0MHz
Ain = -1dBFS
Ain = -1dBFS
fin = 25MHz
fin = 75MHz
Ain = -3dBFS
fin = 150MHz
Ain = -15dBFS
fin = 250MHz
Ain = -15dBFS
spurious-free dynamic range
Ain = -1dBFS
fin = 5.0MHz
fin = 25MHz
Ain = -1dBFS
Ain = -3dBFS
fin = 75MHz
fin = 150MHz
Ain = -15dBFS
Ain = -15dBFS
fin = 250MHz
intermodulation distortion
fin1 = 149.84MHz, fin2 = 149.7MHz Ain = -10dBFS
fin1 = 249.86MHz, fin2 = 249.69MHz Ain = -10dBFS
dithered performance
spurious-free dynamic range
Ain = -6dBFS
fin = 19MHz
intermodulation distortion
fin1 = 74MHz, fin2 = 75MHz
Ain = -12dBFS
DC ACCURACY AND PERFORMANCE
differential non-linearity
integral non-linearity
no missing codes
offset error
gain error
Vref
RATINGS
70
0.01
3.5
2.7
2
mV
%FS
V
1
1
1
1
1
1
1
1
1
1
Vpp
Ω
Ω
pF
5
V
V
V
3
3
3
0.4
3.8
3.0
V
V
V
1
1
1
MSPS
MSPS
ns
ns
clk cycle
ns
ns
1
75
10
7.2
7.2
3.0
10
9.6
NOTES
CLC5957 Electrical Characteristics (Vcc= +5V, 66MSPS; unless specified) (Tmin = -40°C, Tmax = +85°C)
PARAMETERS
CONDITIONS
TEMP
RATINGS
MIN
POWER REQUIREMENTS
+5V supply current
Power dissipation
VCC power supply rejection ratio
Full
Full
+25°C
UNITS
TYP
MAX
128
640
64
150
750
NOTES
2
mA
mW
dB
1
1
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Notes
1) These parameters are 100% tested at 25°C. Sample tested at full
temperature range.
3) See page 7, Figure 3 for ENCODE Inputs circuit.
2) Typical specifications are based on the mean test values of
deliverable converters from the first three diffusion lots.
Absolute Maximum Ratings
positive supply voltage (Vcc)
differential voltage between any two grounds
analog input voltage range
digital input voltage range
output short circuit duration (one-pin to ground)
junction temperature
storage temperature range
lead solder duration (+300°C)
Recommended Operating Conditions
-0.5V to +6V
<100mV
GND to Vcc
-0.5V to +Vcc
infinite
175°C
-65°C to 150°C
10sec
positive supply voltage (Vcc)
analog input voltage range
operating temperature range
+5V ±5%
2.048Vpp diff.
-40°C to +85°C
Package Thermal Resistance
Note: Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure to
maximum ratings for extended periods may affect device reliability.
Package
θJA
θJC
48-pin TSSOP
56°C/W
16°C/W
Reliability Information
Transistor count
5000
Ordering Information
Model
Temperature Range
CLC5957MTD
CLC5957PCASM
Description
-40°C to +85°C
48-pin TSSOP
Fully loaded evaluation board with CLC5957 … ready for test.
N+1
N+2
N
ANALOG
INPUT
Ta = -410ps
ENCODE
CLOCK
N
N+1
N+2
Tdv = 9.6ns
DAV
CLOCK
Tod = 10ns
DATA
OUTPUT
N-3
N-2
N-1
CLC5957 Timing Diagram
3
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CLC5957 Typical Performance Characteristics (Vcc = +5V)
SNR and SFDR vs. Input Frequency
SNR and SFDR vs. Input Frequency
85
SNR (dBFS) and SFDR (dBc)
SNR (dBFS) and SFDR (dBc)
85
80
75
70
SFDR
65
SNR
60
55
50
Fs = 66MSPS
Ain = -3dBFS
45
40
80
75
70
SFDR
65
SNR
60
55
50
Fs = 52MSPS
Ain = -3dBFS
45
40
0
100
300
200
0
100
Input Frequency (MHz)
SNR and SFDR vs. Input Frequency
SNR and SFDR vs. Sample Rate
90
SNR (dBc) and SFDR (dBc)
SNR (dBFS) and SFDR (dBc)
85
80
75
70
SFDR
SNR
65
60
55
50
Fs = 40.96MSPS
Ain = -3dBFS
45
40
Fin = 24.5MHz
85
SFDR
80
75
70
SNR
65
60
55
50
0
100
40
300
200
50
Single Tone Output Spectrum
70
80
Single Tone Output Spectrum (w/Dither)
0
0
Fs = 66MSPS
Ain = -1dBFS
Fin = 24.5MHz
-20
-30
-40
-50
-60
-70
-80
-20
-30
-40
-50
-60
-80
-90
-100
-100
5
10
15
20
25
30
Dither Signal = 500kHz @ - 28dBFS
-70
-90
0
Fs = 66MSPS
Ain = - 6dBFS
Fin = 24.5MHz
-10
Output Level (dBFS)
-10
Output Level (dBFS)
60
Sample Rate (MSPS)
Input Frequency (MHz)
35
0
Frequency (MHz)
5
10
15
20
25
30
35
Frequency (MHz)
Differential Non-Linearity
Integral Non-Linearity
1.0
2.0
Fs = 66MSPS
Fin = 5MHz
Fs = 66MSPS
Fin = 5MHz
1.5
0.5
1.0
INL (LSBs)
DNL (LSBs)
300
200
Input Frequency (MHz)
0
-0.5
0.5
0
-0.5
-1.0
-1.5
-1.0
-2.0
0
512 1024 1536 2048 2560 3072 3584 4096
0
Output Code
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512 1024 1536 2048 2560 3072 3584 4096
Output Code
4
SNR and SFDR vs.
Input Amplitude (w/o Dither)
SNR (dBc), SFDR (dBc), & THD (dBFS)
SNR (dBc), SFDR (dBc), & THD (dBFS)
CLC5957 Typical Performance Characteristics (Vcc = +5V)
90
80
THD
70
60
50
SFDR
40
30
SNR
Fin = 20MHz
Fs = 66MSPS
20
10
-50
-40
-30
-20
SNR and SFDR vs.
Input Amplitude (w/Dither)
90
THD
80
70
60
50
Fin = 20MHz
Fs = 66MSPS
20
10
-50
-40
SNR (dBc), SFDR (dBc), & THD (dBFS)
SNR (dBc), SFDR (dBc), & THD (dBFS)
SNR and SFDR vs.
Input Amplitude (w/o Dither)
90
80
THD
70
SNR
50
SFDR
40
30
Fin = 75MHz
Fs = 66MSPS
20
10
-50
-40
-30
-20
0
-10
80
THD
60
50
SFDR
SNR
40
30
Fin = 150MHz
Fs = 66MSPS
20
10
-50
-40
-30
-20
-10
0
Input Amplitude (dBFS)
Two Tone Output Spectrum (w/Dither)
90
0
80
-10
THD
Output Level (dBFS)
SNR (dBc), SFDR (dBc), & THD (dBFS)
0
70
70
SFDR
60
SNR
40
30
Fin = 250MHz
Fs = 66MSPS
Fs = 66MSPS
F1 = 74.5MHz
F2 = 75.5MHz
-20
-30
-40
-50
-60
Dither Signal =
300KHz @ -28dBFS
-70
-80
-90
10
-100
-50
-40
-30
-20
0
-10
0
5
Input Amplitude (dBFS)
10
15
20
25
30
Frequency (MHz)
Two Tone Output Spectrum (w/Dither)
Two Tone Output Spectrum (w/Dither)
0
0
Fs = 66MSPS
F1 = 149.5MHz
F2 = 150.5MHz
-20
-30
-40
-50
-60
Dither Signal =
300KHz @ -28dBFS
-70
-80
-20
-30
-40
-50
-60
-80
-90
-100
-100
5
10
15
20
25
Dither Signal =
500KHz @ -28dBFS
-70
-90
0
Fs = 66MSPS
F1 = 249.5MHz
F2 = 251.5MHz
-10
Output Level (dBFS)
-10
Output Level (dBFS)
-10
90
SNR and SFDR vs.
Input Amplitude (w/o Dither)
20
-20
SNR and SFDR vs.
Input Amplitude (w/o Dither)
Input Amplitude (dBFS)
50
-30
Input Amplitude (dBFS)
Input Amplitude (dBFS)
60
SNR
30
0
-10
SFDR
40
0
30
Frequency (MHz)
5
10
15
20
25
30
Frequency (MHz)
5
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Physical Dimensions
Symbol
Min
Max
A
–
1.10
A1
0.05
0.15
A2
0.80
1.05
b
0.17
0.27
b1
0.17
0.23
c
0.09
0.20
c1
0.09
0.16
D
12.40
12.60
E
E1
e
L
L1
R1
Notes
2
8.1 BSC
6.00
6.20
2
0.50 BSC
0.50
0.75
1.00 REF
0.127
Notes:
1. All dimensions are in millimeters.
2. Dimensions D and E1 do not include mold protrusion.
Allowable protrusion is 0.20mm per side.
CLC5957 Pin Definitions
GND
1
48
GND
GND
2
47
GND
GND
3
46
+DVCC
GND
4
45
D11 (MSB)
+AVCC
5
44
D10
+AVCC
6
43
D9
+AVCC
7
42
D8
GND
8
41
D7
ENCODE
9
40
D6
ENCODE
10
39
D5
GND
11
38
+DVCC
GND
12
37
+DVCC
AIN
13
36
GND
AIN
14
35
GND
GND
15
34
D4
+AVCC
16
33
D3
+AVCC
17
32
D2
+AVCC
18
31
D1
GND
19
30
D0 (LSB)
GND
20
29
GND
VCM
21
28
OUTLEV
+AVCC
22
27
DAV
GND
23
26
GND
GND
24
25
GND
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CLC5957
AIN, AIN
(Pin 13, 14) Differential input with a common mode voltage
of +2.4V. The ADC full scale input is 1.024Vpp on each of
the complimentary input signals.
ENCODE,
ENCODE
(Pin 9, 10) Differential clock where ENCODE initiates a new
data conversion cycle on each rising edge. Logic for these
inputs are 50% duty cycle universal differential signal
(>200mV). The clock input is internally biased to VCC/2 with
a termination impedance of 2.5kΩ.
D0-D11
(Pins 30-34, 39-45) Digital data outputs are CMOS and
TTL compatible. D0 is the LSB and D11 is the MSB. MSB
is inverted. Output coding is two’s complement.
DAV
(Pin 27) Data Valid Clock. Data is valid on rising edge.
OUTLEV
(Pin 28) Output Logic 3.3V or 2.5V option.
Open = 3.3V, GND = 2.5V.
VCM
(Pin 21) Internal common mode voltage reference.
Nominally +2.4V. Can be used for the input common
mode voltage. This voltage is derived from an internal
bandgap reference.
GND
(Pins 1-4, 8, 11, 12, 15, 19, 20, 23-26, 29, 35, 36, 47, 48)
circuit ground.
+AVCC
(Pins 5-7, 16-18, 22,) +5V power supply for the analog
section. Bypass to ground with a 0.1µF capacitor.
+DVCC
(Pin 37, 38, 46) +5V power supply for the digital section.
Bypass to ground with a 0.1µF capacitor.
6
CLC5957 Applications
Analog Inputs and Bias
Figure 1 depicts the analog input and bias scheme. Each
of the differential analog inputs are internally biased to a
nominal voltage of 2.40 volts DC through a 500Ω resistor
to a low impedance buffer. This enables a simple
interface to a broadband RF transformer with a centertapped output winding that is decoupled to the analog
ground. If the application requires the inputs to be DC
coupled, the Vcm output can be used to establish the
proper common -mode input voltage for the ADC. The
Vcm voltage reference is generated from an internal
bandgap source that is very accurate and stable.
ENCODE Clock Inputs
The CLC5957’s differential input clock scheme is
compatible with all commonly used clock sources.
Although small differential and single-ended signals are
adequate, for best aperture jitter performance a low noise
differential clock with a high slew rate is preferred. As
depicted in Figure 3, both ENCODE clock inputs are
internally biased to VCC/2 though a pair of 5KΩ resistors.
The clock input buffer operates with any common-mode
voltage between the supply and ground.
VCCA
ADC
Bias Mirror
Ain
5kΩ
5kΩ
5kΩ
To T/H
and ADC
500µΑ
Ain
500Ω
ENC
500Ω
+
1.23V
Bandgap
Reference
5kΩ
ENC
2KΩ
2.4V
–
Vcm
BJT Current Mirror
GNDA
Figure 1: CLC5957 Bias Scheme
The Vcm output may also be used to power down the
ADC. When the Vcm pin is pulled above 3.5V, the internal
bias mirror is disabled and the total current is reduced to
less than 10mA. Figure 2 depicts how this function can
be used. The diode is necessary to prevent the logic gate
from altering the ADC bias value.
Figure 3: CLC5957 ENCODE Clock Inputs
The internal bias resistors simplify the clock interface to
another center-tapped transformer as depicted in Figure
4. A low phase noise, RF synthesizer of moderate amplitude (1 - 4Vpp) can drive the ADC through this interface.
ENC
~
ENC
CLC5957
CLC5957
5V CMOS
"1" = on
"0" = off
Vref
Figure 4: Transfer Coupled Clock Scheme
Figure 2: Power Shutdown Scheme
7
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Figures 5 and 6 show the clock interface schemes to
several other types of clock sources.
VCCD
2.4Vref
ENC
+
-
CML to
CMOS
Digital
Signal
ENC
Controlled Current
Output Buffer
+
-
50Ω
Digital
Output
0.01µF
CLC5957
10kΩ
Output
Level
GNDD
Open = 3.3Vhi
GND = 2.5Vhi
Figure 7: CLC5957 Digital Outputs
The logic high level is slaved to the internal 2.4 voltage
reference. The OUTLEV control pin selects either a 3.3V
or 2.5V logic high level. An internal pullup resistor selects
the 3.3 volt level as the default when the OUTLEV pin is
left open. Grounding the OUTLEV pin selects the 2.5V
logic high level.
Figure 5: 5V CMOS Level Clock Scheme
ENC
ENC
To ease user interface to subsequent digital circuitry, the
CLC5957 has a data valid clock output (DAV). In order to
match delays over IC processing variables, this digital
output also uses the same output buffer as the data bits.
The DAV clock output is simply a delayed version of the
ENCODE input clock. Since the ADC output data change
is slaved to the falling edge of the ENCODE clock, the
rising DAV clock edge occurs near the center of the data
valid window (or eye) regardless of the sampling frequency.
CLC5957
0.01µF
Figure 6: TTL or 3V CMOS Level Clock Scheme
Digital Outputs and Level Select
Figure 7 depicts the digital output buffer and bias used in
the CLC5957. Although each of the twelve output bits
uses a controlled current buffer to limit supply transients,
it is recommended that parasitic loading of the outputs is
minimized. Because these output transients are harmonically related to the analog input signal, excessive loading
will degrade ADC performance at some frequencies.
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8
CLC5957 Evaluation Board
Description
The Evaluation board for the CLC5957 allows for easy
test and evaluation of the product. The part may be
ordered with all components loaded and tested. The
order number is the CLC5957PCASM. The user supplies
an analog input signal, encode signal and power to the
board and is able to take latched 12-bit digital data out of
the board.
ENCODE Input (ENC)
The ENCODE input is an SMA connector with a
termination of 50Ω. The encode signal is converted to an
AC coupled, differential clock signal centered between
VCC and ground. The user should supply a sinusoidal or
square wave signal of >200mVpp and <4Vpp with a 50%
duty cycle. The duty cycle can vary from 50% if the
minimum clock pulse width times are observed. A low
jitter source will be required for IF-sampled analog input
signals to maintain best performance.
CLC5957 Clock Option
The CLC5957 evaluation board is configured for use with
an optional crystal clock oscillator source. The component Y1 may be loaded with a ”Full-sized”, HCMOS type,
crystal oscillator.
Analog Input (AIN)
The analog input is an SMA connector with a 50Ω
termination. The signal is converted from single to
differential by a transformer with a 5 to 260MHz bandwidth and approximately one dB loss. Full scale is approximately 11dBm or 2.2Vpp. It is recommended that the
source for the analog input signal be low jitter, low noise
and low distortion to allow for proper test and evaluation
of the CLC5957.
Supply Voltages (J1 pins 31 A&B and 32 A&B)
The CLC5957PCASM is powered from a single 5V
supply connected from the referenced pins on the Eurocard connector. The recommended supplies are low
noise linear supplies.
Digital Outputs (J1 pins 7B (MSB, D11) through 18B
(LSB) and 20B (Data Valid))
The digital outputs are provided on the Eurocard
connector. The outputs are buffered by 5V CMOS latches
with 50Ω series output resistors. The rising edge of Data
Valid may be used to clock the output data into data
collection cards or logic analyzers. The board has a
location for the HP 01650-63203 termination adapter
for HP 16500 logic analyzers to simplify connection to
the analyzer.
9
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CLC5957 Evaluation Board Schematic
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10
CLC5957 Evaluation Board Layout
CLC5957PCASM Layer 1
CLC5957PCASM Layer 2
CLC5957PCASM Layer 3
CLC5957PCASM Layer 4
11
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CLC5957
12-bit, 70MSPS Broadband Monolithic A/D Converter
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National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
Life Support Policy
National’s products are not authorized for use as critical components in life support devices or systems without the express written approval
of the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
N
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said
circuitry and specifications.
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