19-3771; Rev 0; 7/05 Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors Features The MAX6877/MAX6878/MAX6879 multivoltage power trackers/sequencers/supervisors monitor up to three system voltages and provide proper power-up and power-down control for systems requiring voltage tracking or sequencing. These devices ensure controlled voltage tracking within a specified range or sequencing in the proper order as system power supplies are enabled. The MAX6877/MAX6878/MAX6879 generate all required voltages and timing to control up to three external n-channel pass FETs for the OUT1/OUT2/ OUT3 supply voltages (see the Selector Guide for different features of each device). ♦ Pin-Selectable Tracking or Sequencing Control for Up to Three Supply Voltages ♦ Capacitor-Adjustable Power-Up/Down Tracking Slew Rate ♦ Capacitor-Adjustable Power-Up Sequencing Delay ♦ Internal Charge Pumps to Enhance External n-Channel FETs ♦ Capacitor-Adjustable Timeout Period Power-Good Output (MAX6877/MAX6878) ♦ Adjustable Undervoltage Lockout or Logic-Enable Input ♦ Internal 100Ω Pulldown for Each Output to Discharge Capacitive Load Quickly ♦ 0.5V to 5.5V Nominal IN_/OUT_ Range ♦ 2.7V to 5.5V Operating Voltage Range ♦ Immune to Short Voltage Transients ♦ Small 4mm x 4mm 24-Pin or 16-Pin Thin QFN Packages Applications Multivoltage Systems Networking Systems Telecom PART PINPACKAGE TEMP RANGE MAX6877ETG+ -40°C to +85°C 24 Thin QFN T2444-4 -40°C to +85°C 24 Thin QFN T2444-4 Ordering Information continued at end of data sheet. +Denotes lead-free package. FAULT PG/RST MARGIN TOP VIEW OUT3 Pin Configurations 18 17 16 15 14 13 GATE2 19 12 TRK/SEQ OUT1 20 11 LTCH/RTR GATE1 21 10 TIMEOUT 9 SLEW 8 DELAY 7 GND MAX6877 IN3 22 EP* IN2 23 + 1 2 3 4 5 6 ABP SET3 SET2 SET1 EN/UV Servers/Workstations VCC IN1 24 Storage Equipment PKG CODE MAX6877ETG GATE3 The MAX6877/MAX6878/MAX6879 are available in small 4mm x 4mm 24-pin and 16-pin thin QFN packages and are fully specified over the -40°C to +85°C extended operating temperature range. Ordering Information OUT2 The MAX6877/MAX6878/MAX6879 feature adjustable undervoltage thresholds for each input supply. When all the voltages are above these adjustable thresholds, the devices turn on the external n-channel MOSFETs to either sequence or track the voltages to the system. During voltage-tracking mode, the voltage at the GATE of each MOSFET is increased to slowly bring up all supplies at a controlled slew rate. The MAX6877/ MAX6878/MAX6879 feature an autoretry or latch-off mode with capacitor-adjusted timing. These devices also provide a controlled power-down (tracking mode) when the system shuts off in an orderly manner. When an unexpected fault occurs, the outputs are all pulled down simultaneously with an internal 100Ω pulldown to help discharge capactive loads at the MOSFET’s source. The MAX6877/MAX6878/ MAX6879 feature independent internal charge pumps to fully enhance the external FETs for low-voltage drop at highpass current. The MAX6877 and MAX6878 also feature a power-good output with a selectable timeout period that can be used for system reset. 4mm x 4mm THIN QFN *EXPOSED PADDLE CONNECTED TO GND. Selector Guide appears at end of data sheet. Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX6877/MAX6878/MAX6879 General Description MAX6877/MAX6878/MAX6879 Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND, unless otherwise noted.) IN1, IN2, IN3, VCC ....................................................-0.3V to +6V ABP .....................................-0.3V to the highest of VIN1 - VIN3 or VCC SET1, SET2, SET3 ....................................................-0.3V to +6V GATE1, GATE2, GATE3 .........................................-0.3V to +12V OUT1, OUT2, OUT3 .................................................-0.3V to +6V LTCH/RTR, TRK/SEQ, MARGIN ...............................-0.3V to +6V FAULT, PG/RST, EN/UV ...........................................-0.3V to +6V DELAY, SLEW, TIMEOUT .........................................-0.3V to +6V OUT_ Current....................................................................±50mA GND Current.....................................................................±50mA Input/Output Current (all pins except OUT_ and GND) ...........................................................±20mA Continuous Power Dissipation (TA = +70°C) 16-Pin 4mm x 4mm Thin QFN (derate 16.9mW/°C above +70°C) .............................1349mW 24-Pin 4mm x 4mm Thin QFN (derate 20.8mW/°C above +70°C) .............................1667mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC, IN1, IN2, or IN3 = +2.7V to +5.5V, EN/UV = MARGIN = ABP, TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Operating Voltage Range Supply Current SET_ Threshold Range SET_ Threshold Hysteresis SET_ Input Current EN/UV Input Voltage SYMBOL CONDITIONS MIN 1.4 VCC Voltage on ABP (the highest of VCC or IN_) to ensure that PG/RST and FAULT are valid and GATE_ = 0V Voltage on ABP (the highest of VCC or IN_) to ensure the device is fully operational 2.7 ICC VTH 1.1 1.8 0.4925 0.5 0.5075 SET_ falling, TA = -40oC to +85oC 0.4875 0.5 0.5125 SET_ rising SET_ = 0.5V VEN_R Input rising VEN_F Input falling EN/UV Input Current IEN EN/UV Input Pulse Width tEN EN/UV falling, 100mV overdrive DELAY, TIMEOUT Output Current ID (Notes 2, 3) 0.5 -100 Track/Sequence Slew-Rate Timebase Accuracy SR -5 Slew-Rate Accuracy during PowerUp and Power-Down CSLEW = 200pF, ABP = 5.5V (Note 4) -50 VOUT_ falling 91.5 2 VTH_PG nA V µA 2.88 µA µs 2.5 25 -15 100pF < CSLEW < 1nF (Note 4) V +5 1.25 22.5 CSLEW = 200pF (Note 4) 1.28 7 2.12 Timebase/CSLEW Ratio Power-Good Threshold 1.25 mA % +100 1.286 1.22 VCC = 3.3V IS UNITS 5.5 SET_ falling, TA = +25oC ISET SLEW Output Current (Note 4) MAX V VCC = 5.5V, IN1 = IN2 = IN3 = 3.3V, no load VTH_HYS DELAY, TIMEOUT Threshold Voltage TYP V 27.5 µA +15 % 104 92.5 _______________________________________________________________________________________ kΩ +50 % 93.5 % Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors (VCC, IN1, IN2, or IN3 = +2.7V to +5.5V, EN/UV = MARGIN = ABP, TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL Power-Good Threshold Hysteresis VHYS_PG CONDITIONS % 2.5 4 µA During power-up and power-down, VGATE_ = 5V 2.5 4 µA GATE_ Pullup Current IGUP IGD tD-GATE UNITS During power-up and power-down, VGATE_ = 1V ISOURCE = 0.5µA SET_ to GATE_ Delay MAX 0.5 IN_ + 5.0 VGOH IGDS TYP IN_ + 4.2 GATE_ Output High GATE_ Pulldown Current MIN VOUT_ rising When disabled, VGATE_ = 5V, VIN_ ≥ 2.7V 9.5 When disabled, VGATE_ = 5V, VIN_ ≥ 4V 20 SET falling, 25mV overdrive 6 IN_ + 5.8 V mA µs VIN_ ≥ 2.7V, ISINK = 1mA, output asserted 0.3 VIN_ ≥ 4.0V, ISINK = 4mA, output asserted 0.4 FAULT, PG/RST Output Low VOL Tracking Differential Voltage Stop Ramp VTRK Differential between each of the OUT_ and the ramp voltage during power-up and power-down, Figure 10 (Note 5) 75 125 180 mV Tracking Differential Fault Voltage VTRK_F Differential between each of the OUT_ and the ramp voltage, Figure 10 (Note 5) 200 250 310 mV Tracking Differential Voltage Hysteresis 20 VTH_PL OUT_ falling Power-Low Hysteresis VTH_PLHYS OUT_ rising 10 mV VABP > 2.7V (Note 6) 100 Ω MARGIN, TRK/SEQ, LTCH/RTR Pullup Current MARGIN, TRK/SEQ, LTCH/RTR Input Voltage MARGIN, TRK/SEQ, LTCH/RTR Glitch Rejection IIN 7 142 % Power-Low Threshold OUT to GND Pulldown Impedance 125 V 10 VIL VIH 170 13 0.8 2.0 100 mV µA V ns Note 1: Specifications guaranteed for the stated global conditions. 100% production tested at TA = +25°C and TA = +85°C. Specifications at TA = -40°C to +85°C are guaranteed by design. These devices meet the parameters specified when at least one of VCC, IN1/IN2/IN3 is between 2.7V to 5.5V, while the remaining IN1/IN2/IN3 are between 0 and 5.5V. Note 2: A current ID = 2.5µA ±15% is generated internally and is used to set the DELAY and TIMEOUT periods and used as a reference for tDELAY and tTIMEOUT. Note 3: The total DELAY is tDELAY = 200ms + (500kΩ x CDELAY). Leave DELAY unconnected for 200µs delay. The total TIMEOUT is tTIMEOUT = 200µs + (500kΩ x CTIMEOUT). Leave TIMEOUT unconnected for 200µs timeout. Note 4: A current IS = 25µA ±10% is generated internally and used as a reference for tFAULT, tRETRY, and slew rate. Note 5: During power-up, only the condition OUT_ < ramp - VTRK is checked in order to stop the ramp. However, both conditions OUT_ < ramp - VTRK_F and OUT_ > ramp + VTRK_F cause a fault. During power-down, only the condition OUT > ramp + VTRK is checked in order to stop the ramp. However, both conditions OUT_ < ramp - VTRK_F and OUT_ > ramp + VTRK_F cause a fault (see Figure 10). Therefore, if OUT1, OUT2, and OUT3 (during power-up tracking and power-down) differ by more than 2 x VTRK_F, a fault condition is asserted. Note 6: A 100Ω pulldown to GND activated by a fault condition. See the Internal Pulldown section. _______________________________________________________________________________________ 3 MAX6877/MAX6878/MAX6879 ELECTRICAL CHARACTERISTICS (continued) MAX6877/MAX6878/MAX6879 Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors EN/UV BUS VOLTAGE MONITORED THROUGH EN/UV INPUT EN/UV VEN_F VEN_R EN/UV IN1 = 2.5V IN2 = 1.8V IN_ IN3 = 0.7V MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS CAPACITORADJUSTED SLEW RATE OUT1 = 2.5V OUT2 = 1.8V OUT_ OUT3 = 0.7V tDELAY PG/RST tTIMEOUT Figure 1. Tracking Timing Diagram in Normal Mode 4 _______________________________________________________________________________________ Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors VEN_R MAX6877/MAX6878/MAX6879 BUS VOLTAGE MONITORED THROUGH EN/UV INPUT EN/UV EN/UV VEN_F IN1 GOES BELOW SET1 THRESHOLD IN1 = 2.5V IN2 = 1.8V IN3 = 0.7V IN_ MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS CAPACITORADJUSTED SLEW RATE OUT1 = 2.5V OUT2 = 1.8V OUT3 = 0.7V OUT_ tDELAY tTIMEOUT PG/RST FAULT = HIGH FORCED INTO QUICK SHUTDOWN AFTER NORMAL SHUTDOWN WHEN IN1 GOES BELOW ITS SET VOLTAGE Figure 2. Tracking in Fast Shutdown Mode _______________________________________________________________________________________ 5 MAX6877/MAX6878/MAX6879 Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors EN/UV BUS VOLTAGE MONITORED THROUGH EN/UV INPUT VEN_R EN/UV VEN_F IN1 = 2.5V IN2 = 1.8V IN3 = 0.7V IN_ MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS CAPACITORADJUSTED SLEW RATE OUT1 = 2.5V OUT2 = 1.8V OUT_ OUT3 = 0.7V tDELAY tDELAY tDELAY PG/RST tTIMEOUT Figure 3. Sequencing in Normal Mode 6 _______________________________________________________________________________________ Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors MAX6877/MAX6878/MAX6879 EN/UV EN/UV BUS VOLTAGE MONITORED THROUGH EN/UV INPUT VEN_R IN1 = 2.5V IN2 = 1.8V IN_ IN3 = 0.7V MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS CAPACITORADJUSTED SLEW RATE OUT_ FORCED BELOW VTH_PG OUT1 = 3.3V OUT2 = 1.8V OUT_ OUT3 = 0.7V tDELAY tDELAY PG/RST tDELAY tTIMEOUT FAULT FORCED INTO QUICK SHUTDOWN WHEN OUT1 FALLS BELOW 92.5% of IN1 Figure 4. Sequencing in Fast Shutdown Mode _______________________________________________________________________________________ 7 MAX6877/MAX6878/MAX6879 Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors EN/UV EN/UV BUS VOLTAGE MONITORED THROUGH EN/UV INPUT VEN_F VEN_R IN1 = 2.5V IN2 = 1.8V IN3 = 0.7V IN_ MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS CAPACITORADJUSTED SLEW RATE OUT1 = 2.5V OUT2 = 1.8V OUT_ OUT3 = 0.7V tDELAY *tTIMEOUT PG/RST = LOW *ANY POWER-DOWN CONDITION BEFORE tTIMEOUT (PG/RST ASSERTED) CAUSES A SHUTDOWN. Figure 5. Timing Diagram (Aborted Tracking) 8 _______________________________________________________________________________________ Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors MAX6877/MAX6878/MAX6879 EN/UV EN/UV BUS VOLTAGE MONITORED THROUGH EN/UV INPUT VEN_R VEN_F IN1 = 2.5V IN2 = 1.8V IN3 = 0.7V IN_ MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS CAPACITORADJUSTED SLEW RATE OUT1 = 2.5V OUT2 = 1.8V OUT_ OUT3 = 0.7V tDELAY tDELAY tDELAY *tTIMEOUT PG/RST = LOW *ANY POWER-DOWN CONDITION BEFORE tTIMEOUT (PG/RST ASSERTED) CAUSES A SHUTDOWN. Figure 6. Timing Diagram (Aborted Sequencing) _______________________________________________________________________________________ 9 MAX6877/MAX6878/MAX6879 Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors EN/UV VEN_R OUT2 AND OUT3 ARE WAITING OUT1 IS SLOW OUT_ OUT2 AND OUT3 ARE WAITING 125mV OUT1 IS SLOW tDELAY tDELAY tFAULT tFAULT tRETRY FAULT tFAULT AND tRETRY NOT TO SCALE ALL SET_ > 0.5V AND VCC OR IN_ ≥ 2.7V Figure 7. tFAULT and tRETRY Timing Diagram in Tracking EN/UV OUT1 OUT1 OUT2 OUT2 OUT_ OUT3 IS SLOW OUT3 IS SLOW tDELAY tDELAY tFAULT tDELAY tDELAY tRETRY tFAULT tDELAY tDELAY FAULT tFAULT AND tRETRY NOT TO SCALE ALL SET_ > 0.5V AND VCC OR IN_ ≥ 2.7V Figure 8. tFAULT and tRETRY Timing Diagram in Sequencing 10 ______________________________________________________________________________________ Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors VCC SUPPLY CURRENT vs. INPUT VOLTAGE NORMALIZED POWER-GOOD TIMEOUT vs. TEMPERATURE 1.1 TA = +25°C TA = -40°C 0.9 0.8 1.00 0.95 0.90 0.85 3.0 3.5 4.0 4.5 5.0 5.5 MAX6877 toc03 10 1 -40 -15 10 35 60 0.1 0.0001 85 0.001 0.01 TEMPERATURE (°C) CTIMEOUT (µF) NORMALIZED SET_ THRESHOLD vs. TEMPERATURE NORMALIZED DELAY TIMEOUT vs. TEMPERATURE SLEW RATE vs. CSLEW 1.001 1.000 0.999 0.998 0.997 1.20 0.996 1.15 1.10 10,000 SLEW RATE (V/s) 1.002 MAX6877 toc05 1.003 1.25 NORMALIZED DELAY TIMEOUT MAX6877 toc04 1.004 1.05 1.00 0.95 1 0.1 INPUT VOLTAGE (V) 1.005 0.90 1000 100 0.85 0.80 0.995 0.75 10 35 60 85 10 -40 -15 TEMPERATURE (°C) 10 35 60 85 DELAY TIMEOUT vs. CDELAY 10 1 1.004 1.003 1.002 1.001 1.000 0.999 0.998 0.997 CDELAY (µF) 0.1 1 10,000 30 IN_ = 3.3V 27 24 21 18 15 12 PG/RST GOES LOW ABOVE THE CURVE 9 6 3 0.996 0.01 1000 IN_ TRANSIENT DURATION vs. IN_ THRESHOLD OVERDRIVE MAX6877 toc08 1.005 NORMALIZED EN_/UV THRESHOLD MAX6877 toc07 100 0.001 100 CSLEW (pF) NORMALIZED EN/UV THRESHOLD vs. TEMPERATURE 1000 0.1 0.0001 10 TEMPERATURE (°C) MAX6877 toc09 -15 IN_ TRANSIENT DURATION (µs) -40 DELAY TIMEOUT (ms) 100 0.80 0.75 2.5 NORMALIZED SET_ THRESHOLD 1.05 MAX6877 toc06 1.0 1.10 1000 POWER-GOOD TIMEOUT (ms) TA = +85°C 1.2 MAX6877 toc02 1.3 1.15 NORMALIZED POWER-GOOD TIMEOUT MAX6877 toc01 VCC SUPPLY CURRENT (mA) 1.4 POWER-GOOD TIMEOUT vs. CTIMEOUT 0 0.995 -40 -15 10 35 TEMPERATURE (°C) 60 85 0 50 100 150 200 250 300 IN_ THRESHOLD OVERDRIVE (mV) ______________________________________________________________________________________ 11 MAX6877/MAX6878/MAX6879 Typical Operating Characteristics (VCC_ = 2.7V to 5.5V, CSLEW = 200pF, EN = MARGIN = ABP, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC_ = 2.7V to 5.5V, CSLEW = 200pF, EN = MARGIN = ABP, TA = +25°C, unless otherwise noted.) GATE_ VOLTAGE LOW vs. GATE SINK CURRENT GATE_ OUTPUT VOLTAGE HIGH vs. GATE SOURCE CURRENT 1.2 1.0 0.8 0.6 0.4 MAX6877 toc12 MAX6877 toc11 9 GATE_ VOLTAGE HIGH (V) 1.4 TRACKING MODE 10 MAX6877 toc10 1.6 GATE_ VOLTAGE LOW (V) MAX6877/MAX6878/MAX6879 Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors 8 EN/UV 2V/div 7 OUT1 6 5 OUT2 1V/div OUT3 4 3 2 0.2 1 0 0 0 1 2 3 4 5 6 7 8 9 10 0 GATE SINK CURRENT (mA) 0.5 1.0 1.5 2.0 2.5 3.0 10ms/div GATE SOURCE CURRENT (µA) SEQUENCING MODE FAST SHUTDOWN MAX6877 toc13 MAX6877 toc14 EN/UV 2V/div EN/UV 2V/div OUT1 OUT1 OUT2 1V/div OUT2 1V/div OUT3 OUT3 FAULT 2V/div 20ms/div 40ms/div FAST SHUTDOWN WITH RETRY MAX6877 toc15 OUT1 2V/div THRESHOLD ERROR AT OUT1, OUT1 PULLED BELOW 92.5% OF IN1 OUT2 2V/div OUT3 2V/div FAULT 1V/div 100ms/div 12 ______________________________________________________________________________________ Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors PIN MAX6877 MAX6878 MAX6879 NAME FUNCTION 1 1 — VCC Optional Supply Voltage Input. Connect VCC to an alternate (i.e., always-on) supply if desired. Leave VCC unconnected, if not used. VCC allows IN_ supplies less than UVLO to be tracked. VCC is internally pulled down by a 100kΩ resistor. 2 2 1 ABP Internal Supply Bypass Input. Bypass ABP with a 1µF capacitor to GND. ABP maintains the device supply voltage during rapid power-down conditions. 3 — — SET3 4 4 2 SET2 5 5 3 SET1 — 3, 16, 17, 22 — N.C. 6 6 4 EN/UV 7 7 5 GND Externally Adjusted IN_ Undervoltage Lockout Threshold. Connect SET_ to an external resistor-divider network to set the desired undervoltage threshold for each IN_ supply (see the Typical Application Circuit). All SET_ inputs must be above the internal SET_ threshold (0.5V) to enable tracking or sequencing functionality. No Connection. Not internally connected. Logic-Enable Input or Undervoltage Lockout Monitor Input. EN/UV must be high (EN/UV > VEN_R) to enable voltage tracking or sequencing power-up operation. OUT_ begins tracking down when EN/UV < VEN_F. Connect EN/UV to an external resistor-divider network to set the external UVLO threshold. Ground 8 8 6 DELAY Tracking Startup/Sequence Delay Select Input. Connect a capacitor from DELAY to GND to select the desired delay period before tracking is enabled (after all SET_ inputs and EN/UV are above their respective thresholds) or between supply sequences. Leave DELAY unconnected for the default 200µs delay period. 9 9 7 SLEW Slew-Rate Adjustment Input. Connect a capacitor from SLEW to GND to select the desired OUT_ slew rate. 10 10 — TIMEOUT PG/RST Timeout Period Adjust Input. PG/RST asserts high after the timeout period when all OUT_ exceed their IN_ referenced threshold. Connect a capacitor from TIMEOUT to GND to set the desired timeout period. Leave TIMEOUT unconnected for the default 200µs delay period. 11 11 8 LTCH/RTR Latch/Autoretry Selection Input. Drive LTCH/RTR low to select the latch mode. Connect LTCH/RTR to ABP or leave unconnected to select autoretry mode. LTCH/RTR is internally pulled up to ABP through a 10µA current source. 9 TRK/SEQ Track/Sequence Select Input. Drive TRK/SEQ low to enable supply tracking function. Connect TRK/SEQ to ABP or leave it unconnected to enable supply sequencing. TRK/SEQ is internally pulled to ABP through a 10µA current source. MARGIN Margin Input, Active-Low. Drive MARGIN low to enable margin mode (see the Margin section). The MARGIN functionality is disabled (returns to normal monitoring mode) after MARGIN returns high. MARGIN is internally pulled up to ABP through a 10µA current source. 12 13 12 13 — ______________________________________________________________________________________ 13 MAX6877/MAX6878/MAX6879 Pin Description MAX6877/MAX6878/MAX6879 Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors Pin Description (continued) PIN NAME FUNCTION MAX6877 MAX6878 MAX6879 14 14 — PG/RST Power-Good Output, Open-Drain. PG_RST asserts high tTIMEOUT after all OUT_ voltages exceed the VTH_PG thresholds. 15 15 10 FAULT Tracking Fault Alert Output, Active Low, Open-Drain. FAULT asserts low if a tracking failure is present for longer than the selected fault period or if tracking voltages fail by more than ±250mV. FAULT asserts low if any OUT_ falls below the corresponding IN_ voltage. 16 — — OUT3 Channel 3 Monitored Output Voltage. Connect OUT3 to the source of an nchannel FET. A fault condition activates a 100Ω pulldown to ground. 17 — — GATE3 Gate Drive for External n-Channel FET. An internal charge pump boosts GATE3 to VIN3 + 5V to fully enhance the external n-channel FET when powerup is complete. 18 18 11 OUT2 Channel 2 Monitored Output Voltage. Connect OUT2 to the source of an n-channel FET. A fault condition activates a 100Ω pulldown to ground. 19 19 12 GATE2 Gate Drive for External n-Channel FET. An internal charge pump boosts GATE2 to VIN2 + 5V to fully enhance the external n-channel FET when powerup is complete. 20 20 13 OUT1 Channel 1 Monitored Output Voltage. Connect OUT1 to the source of an n-channel FET. A fault condition activates a 100Ω pulldown to ground. 21 21 14 GATE1 Gate Drive for External n-Channel FET. An internal charge pump boosts GATE1 to VIN1 + 5V to fully enhance the external n-channel FET when powerup is complete. 22 — — IN3 23 23 15 IN2 24 24 16 IN1 Supply Input Voltage. IN1, IN2, or IN3 must be greater than the internal undervoltage lockout (VABP = 2.7V) to enable the tracking or sequencing functionality. Each IN_ input is simultaneously monitored by SET_ inputs to ensure all supplies have stabilized before power-up is enabled. If IN_ is connected to ground or left unconnected and SET_ is above 0.5V, then nosequencing control is performed on that channel. Each IN_ is internally pulled down by a 100kΩ resistor. EP EP EP EP Exposed Paddle. Connect exposed paddle to ground. 14 ______________________________________________________________________________________ Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors IN1 TO LOAD VCC IN2 IN3 IN1 OUT1 GATE1 ABP INTERNAL VCC/UVLO IN1 CHARGE PUMP MAX6877 SET1 RAMP GENERATOR IN2 COMP GATE CONTROLLER SET2 IN3 COMP CONTROL LOGIC IN2 TO OUT2 CONTROL BLOCK SET3 VBUS COMP GATE2 OUT2 OUT1 OUT2 TRACKING MONITORS EN/UVLO COMP OUT3 IN1 IN3 TO OUT3 CONTROL BLOCK GATE3 OUT3 IN2 IN3 VREF PG CIRCUIT MARGIN GND DELAY SLEW TIMEOUT CSLEW CTIMEOUT PG/RST FAULT TRK/SEQ LTCH/RTR ______________________________________________________________________________________ 15 MAX6877/MAX6878/MAX6879 Functional Diagram MAX6877/MAX6878/MAX6879 Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors Detailed Description The MAX6877/MAX6878/MAX6879 multivoltage power trackers/sequencers/supervisors monitor up to three system voltages and provide proper power-up and power-down control for systems requiring voltage tracking or sequencing. These devices ensure controlled voltage tracking with a specified range or sequencing in the proper order as system power supplies are enabled. The MAX6877/MAX6878/MAX6879 generate all required voltages and timing to control up to three external n-channel pass FETs for the OUT1/OUT2/OUT3 supply voltages (see the Selector Guide for different features of each device.) The MAX6877/MAX6878/MAX6879 feature adjustable undervoltage thresholds for each input supply. When all the voltages are above these adjusted thresholds, the devices turn on the external n-channel MOSFETs to either sequence or track the voltages to the system. During the voltage-tracking mode, the voltage at the GATE of each MOSFET is increased to slowly bring up all supplies at a controlled slew rate. The voltage at the source (output) of each MOSFET is internally compared to a control ramp to maintain a low differential between each monitored supply. Tracking is dynamically adjusted to force all outputs to track within 125mV of the reference ramp. If for any reason any supplies fail to track within ±250mV of the reference ramp, the FAULT output is asserted, the power-up mode is terminated, and all outputs are quickly powered off. In sequencing mode, the outputs are turned on one after the other, OUT1 first and OUT3 last. The MAX6877/MAX6878/ MAX6879 feature an autoretry or latch-off mode with capacitor-adjusted timing. These devices also provide a controlled power-down (tracking mode) when the system shuts off in an orderly manner. When an unexpected fault occurs, the outputs are all pulled down simultaneously with an internal 100Ω pulldown to help discharge capacitive loads at the MOSFET’s source. The MAX6877/MAX6878/MAX6879 feature independent internal charge pumps to fully enhance the external FETs for low-voltage drops at highpass currents. The MAX6877/MAX6878 also feature a power-good output with a selectable timeout period that can be used for system reset. The MAX6877/MAX6878/MAX6879 monitor up to three voltages. Devices may be configured to exclude any IN_. To disable the tracking or sequencing operation of any IN_, connect the IN_ to ground (or leave unconnected) and connect SET_ to a voltage greater than 0.5V. The channel exclusion feature adds more flexibili16 ty to the device in a variety of different applications. As an example, the MAX6877 can track or sequence two voltages using IN1 and IN2 while IN3 is left disabled. Powering the MAX6877/MAX6878/MAX6879 These devices derive power from either the IN1, IN2, or IN3 voltage inputs or VCC (see the Functional Diagram). VCC or one of the IN_ inputs must be at least +2.7V to ensure full device operation. The highest input voltage on IN1/IN2/IN3 or VCC supplies power to the devices. Internal hysteresis ensures that the supply input that initially powers these devices continues to power the MAX6877/MAX6878/MAX6879 when multiple input voltages are within 100mV (typ) of each other. ABP ABP powers the analog circuitry. Bypass ABP to GND with a 1µF ceramic capacitor installed as close to the device as possible. ABP takes the highest voltage of IN_ or VCC. Do not use ABP to provide power to external circuitry. ABP maintains the device supply voltage during rapid power-down conditions. Tracking and Sequencing Modes (TRK/SEQ) To enable the power-up/power-down voltage-tracking operation, drive TRK/SEQ low (connect TRK/SEQ to GND). To enable power-up sequencing and powerdown tracking functions, drive TRK/SEQ high (connect TRK/SEQ to ABP) or leave it unconnected. TRK/SEQ is internally pulled to ABP through a 10µA current source (see Figures 1 and 3). Tracking To operate in tracking mode, connect TRK/SEQ to GND. When VEN/UV > 1.25V and all SET_ inputs are above the internal SET_ threshold (0.5V), the tracking process is initiated. The MAX6877/MAX6878/MAX6879 generate an internal reference ramp voltage that drives the control loops for the tracked voltages. The tracking functionality is monitored with a comparator control block for each output (see the Functional Diagram). The comparators monitor each OUT_ voltage with respect to the common reference ramp voltage to ensure the OUT_ voltages stay within 125mV of the reference ramp, monitor each tracked output voltage with respect to its source input voltage, and monitor each output voltage with respect to GND during powerup/retry cycles. If for any reason any supplies fail to track within ±250mV of the reference ramp, the FAULT output is asserted, the power-up mode is terminated, and all outputs are quickly powered off. ______________________________________________________________________________________ Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors The slew rate for the reference ramp voltage is capacitor adjustable. Connect a capacitor from SLEW to ground to select the desired OUT_ slew rate. When all OUT_ voltages have exceeded the VTH_PG percentage of the IN_ voltage (external n-channel FET is saturated), PG/RST asserts high after tTIMEOUT indicating successful tracking. Sequencing The sequencing operation can be initiated after all input conditions for power-up are met VEN/UV > 1.25V and all SET_ inputs are above the internal SET_ threshold (0.5V). In sequencing mode, the outputs are turned on sequentially, OUT1 first and OUT3 last. Before turning on each channel, a delay period occurs as in Figure 3 (programmable by connecting a capacitor from DELAY to ground). The power-up phase for each channel ends when its output voltage exceeds a fixed percentage (VTH_PG) of the corresponding IN_ voltage. When all channels have exceeded these thresholds, PG/RST asserts high after tTIMEOUT, indicating a successful sequence. If there is a fault condition during the initial power-up sequence, the process is aborted. When powering down, all outputs turn off simultaneously, tracking each other. No reverse power-down sequencing occurs. Power-Up and Power-Down During power-up, the OUT_ is forced to follow the internal reference ramp voltage by an internal loop that controls the GATE_ of the external MOSFET. This phase must be completed within the adjustable fault timeout period; otherwise, the part forces a shutdown on all GATE_. Once the power-up is completed, a power-down phase can be initiated by forcing VEN/UV below VEN_F. The reference voltage ramp ramps down at the capacitoradjusted slew rate. The control-loop comparators monitor each OUT_ voltage with respect to the common reference ramp voltage. During ramp down, if an OUT_ voltage is greater than the reference ramp voltage by more than VTRK, the control loop dynamically stops the control ramp voltage from decreasing until the slow OUT_ voltage catches up. If an OUT_ voltage is greater or less than the reference ramp voltage by more than VTRK_F, a fault is signaled and the fast-shutdown mode is initiated. In fast-shutdown mode, a 100Ω pulldown resistor is connected from OUT_ to GND to quickly discharge capacitance at OUT_ and GATE _ is pulled low with a strong IGDS current (see Figures 2 and 4). Figures 5 and 6 show aborted tracking and sequencing modes. When EN/UV goes low before t TIMEOUT expires, all the outputs go low and the device goes into fast shutdown. Internal Pulldown To ensure that the OUT_ voltages are not held high by a large output capacitance after a fault has occurred, there is a 100Ω internal pulldown at OUT_. The pulldown ensures that all OUT_ voltages are below VTH_PL (referenced to GND) before power-up cycling is initiated. The internal pulldown also ensures a fast discharge of the output capacitor during fast shutdown and fault modes. The pulldowns are not present during normal operation. Stability Comment No external compensation is required for tracking or slew-rate control. Inputs IN1/IN2/IN3 The highest voltage on VCC, IN1, IN2, or IN3 supplies power to the device. The undervoltage threshold for each IN_ supply is set with an external resistor-divider from each IN_ to SET_ to ground. Undervoltage Lockout Threshold Inputs (SET_) The MAX6877 features three and the MAX6878/ MAX6879 feature two externally adjustable IN_ undervoltage lockout (UVLO) thresholds (SET1, SET2, SET3) to enable sequencing/tracking functionality. The undervoltage threshold for each IN_ supply is set with an external resistor-divider from each IN_ to SET_ to ground (see Figure 9). All SET_ inputs must be above the internal SET_ threshold (0.5V) to enable tracking/sequencing functionality. Use the following formula to set the UVLO threshold: VIN_ = VTH (R1 + R2) / R2 where VIN_ is the undervoltage lockout threshold and VTH is the 500mV SET threshold. MARGIN) Margin Input (M MARGIN allows system-level testing while power supplies are below the normal ranges as adjusted by the SET_ inputs. Drive MARGIN low before varying system ______________________________________________________________________________________ 17 MAX6877/MAX6878/MAX6879 During ramp up, if an OUT_ voltage is less than the reference ramp voltage by more than 125mV, the control loop dynamically stops the control ramp voltage from rising until the slow OUT_ voltage catches up. If an OUT_ voltage is greater or less than the reference ramp voltage by more than 250mV, a fault is signaled and a power-down phase is initiated. MAX6877/MAX6878/MAX6879 Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors VIN_ Limiting Inrush Current The capacitor connected at SLEW controls the OUT_S slew rate, thus controlling the inrush current required to charge the load capacitor at the outputs (OUT_). Using the programmed slew rate, limit the inrush current by using the following formula: IN_ R1 MAX6877 MAX6878 SET_ MAX6879 IINRUSH = COUT x SR where IINRUSH is in amperes, COUT is in farads, and SR is in V/s. R2 Figure 9. Setting the Undervoltage (UVLO) Thresholds voltages below the adjusted thresholds to avoid signaling an error. The state of PG/RST and FAULT outputs does not change while MARGIN is low. PG/RST, FAULT, and all monitoring functions are disabled while MARGIN is low. MARGIN makes it possible to vary the supplies without a need to adjust the thresholds to prevent tracker/sequencer alerts or faults. Drive MARGIN high or leave it unconnected for normal operating mode. Slew-Rate Control Input (SLEW) The reference ramp voltage slew rate during any controlled power-up/down phase can be programmed in the 90V/s to 950V/s range by connecting a capacitor (CSLEW) from SLEW to ground. Use the following formula to calculate the typical slew rate: Slew Rate = (9.35 x 10-8)/ CSLEW where slew rate is in V/s and CSLEW is in farads. The capacitor at CSLEW also sets the FAULT timeout period (t FAULT ) and FAULT retry timeout period (tRETRY) (see Table 1). For example, if C SLEW = 100pF, we have t RETRY = 350ms, t FAULT = 21.91ms, slew rate = 935V/s. For example, if C SLEW = 1nF, we have t RETRY = 3.5s, tFAULT = 219ms, slew rate = 93.5V/s. CSLEW is the capacitor on the SLEW pad, and must be large enough to make the parasitic capacitance negligible. C SLEW should be in the range of 100pF < CSLEW < 1nF. Table 1. CSLEW Timing Formulas 18 TIME PERIOD FORMULAS Slew Rate (9.35 x 10-8) / CSLEW tRETRY 3.506 x 109 x CSLEW tFAULT 2.191 x 108 x CSLEW Delay Time Input (DELAY) To adjust the desired delay period (t DELAY ) before tracking/sequencing is enabled, connect a capacitor (CDELAY) between DELAY to ground (see Figures 1 to 8). The selected delay time is also enforced when EN/UV rises from low to high when all the input voltages (IN1/IN2/IN3) are present. Use the following formula to calculate the delay time: tDELAY = 200µs + (500kΩ x CDELAY) where tDELAY is in µs and CDELAY is in farads. Leave DELAY unconnected for the default 200µs delay. Timeout Period Input (TIMEOUT) These devices feature a PG/RST timeout period. Connect a capacitor (C TIMEOUT ) from TIMEOUT to ground to program the PG/RST timeout period. After all OUT_ outputs exceed their IN_ referenced thresholds (VTH_PG), PG/RST remains low for the selected timeout period, tTIMEOUT (see Figure 3): tTIMEOUT = 200µs + (500kΩ x CTIMEOUT) where tTIMEOUT is in µs and CTIMEOUT is in farads. Leave TIMEOUT unconnected for the default 200µs timeout delay. Logic-Enable Input (EN/UV) Drive logic EN/UV input above VEN_R to initiate voltage tracking/sequencing during the power-up operation. Drive logic EN/UV below V EN_F to initiate tracking power-down operation. Connect EN/UV to an external resistor-divider network to set the external undervoltage lockout threshold. OUT1/OUT2/OUT3 The MAX6877 monitors three and MAX6878/MAX6879 monitor two OUT_ outputs to control the tracking/ sequencing performance. After the internal supply (ABP) exceeds the minimum voltage (2.7V) requirements, EN/UV > VEN_R, and IN1/IN2/IN3 are all greater than their adjusted SET_ thresholds, OUT1/OUT2/OUT3 begin to track or sequence. ______________________________________________________________________________________ Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors Outputs GATE_ The MAX6877/MAX6878/MAX6879 feature up to three GATE_ outputs to drive up to three external n-channel FET gates. The following conditions must be met before GATE_ begins enhancing the external n-channel FET_: 1) All SET_ inputs (SET1–SET3) are above their 0.5V thresholds. 2) At least one IN_ input or VCC is above the minimum operating voltage (2.7V). 3) EN/UV > 1.25V. At power-up mode, GATE_ voltages are enhanced by control loops so that all OUT_ voltages track together at a capacitor-adjusted slew rate. Each GATE_ is internally pulled up to 5V above its relative IN_ voltage to fully enhance the external n-channel FET when power-up is complete. FAULT The MAX6877/MAX6878/MAX6879 include an opendrain, active-low tracking fault alarm output (FAULT). FAULT asserts low when a power-up phase is not completed within the specified fault period or if OUT_ voltages are more than VTRK_F. The fault time period (tFAULT) is set through the capacitor at SLEW (CSLEW). Use the following formula to estimate the fault timeout period: tFAULT = 2.191 x 108 x CSLEW 125mV DOWN = STOP RAMP THRESHOLD Power-supply tracking operation should be completed within the selected fault timeout period (tFAULT). The total tracking time is extended when the devices must vary the control slew rate to allow slow supplies to catch up. If the external FET is too small (RDS is too high for the selected load current and IN_ source current), the OUT_ voltage may never reach the control ramp voltage. For a slew rate of 935V/s, a fault is signaled if all outputs have not stabilized within 22ms. For a slew rate of 93.5V/s, a fault is signaled if tracking takes too long (more than 219ms). During power-up, only the condition, OUT_ < ramp VTRK, is monitored in order to stop the ramp. However, both conditions OUT < ramp - V TRK_F and OUT_ > ramp + VTRK_F cause a fault. During power-down, only the condition OUT > ramp + VTRK is checked in order to stop the ramp. However, both conditions OUT_ < ramp - VTRK_F and OUT_ > ramp + VTRK_F cause a fault (see Figure 10). OUT1, OUT2, and OUT3 are tracked within V TRK_F (mV) (power-up tracking and power-down), and if they differ by more than 2 x VTRK_F a fault condition is asserted. Retry time period (tRETRY) is defined as 16 x tFAULT. To calculate the retry time period use the following formula: tRETRY = 3.506 x 109 x CSLEW where tRETRY is in µs and CSLEW is in farads. Autoretry and Latch-Off Functions (LTCH/RTR) The MAX6877/MAX6878/MAX6879 feature latch-off or autoretry modes to power-on again after a fault condition has been detected. Connect LTCH/RTR to ground to set the latch-off mode. To select autoretry mode, connect LTCH/RTR to ABP or leave unconnected. 250mV UP = FAULT THRESHOLD 250mV UP = FAULT THRESHOLD 250mV DOWN = FAULT THRESHOLD 250mV DOWN = FAULT THRESHOLD 125mV UP = STOP RAMP THRESHOLD REFERENCE RAMP REFERENCE RAMP POWER-UP POWER-DOWN Figure 10. Stop Ramp FAULT Window During Power-Up and Power-Down ______________________________________________________________________________________ 19 MAX6877/MAX6878/MAX6879 During fault conditions, an internal pulldown resistor (100Ω) on OUT_ is enabled to help discharge load capacitance (100Ω is connected for fast power-down control). MAX6877/MAX6878/MAX6879 Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors When a fault is detected, for a period of tRETRY, GATE_ remains off and the 100Ω pulldowns are turned on. After the tRETRY period, the device waits tDELAY and retries power-up if all power-up conditions are met (see Figure 8). These include all VSET_ > 0.5V, EN/UV > VEN_R, OUT_ voltages < VTH_PL. The autoretry period, tRETRY, is a function of CSLEW; see Table 1. When the device is in latch mode and a fault occurs, FAULT asserts and all outputs are latched off. To unlatch OUT_ after a fault disappears, cycle EN/UV or cycle VCC and the inputs (IN_) below the 2.7V UVLO threshold. After EN/UV goes high, the device waits a tRETRY period then tries to power-up again. If VCC and all IN_ are cycled below 2.7V, the device tries to powerup immediately. Power-Good Output (PG/RST) The MAX6877/MAX6878 include a power-good (PG/RST) output. PG/RST is an open-drain output and requires an external pullup resistor. All the OUT_ outputs must exceed their IN_ referenced thresholds (IN_ x VTH_PG) for the selected reset timeout period tTIMEOUT (see the TIMEOUT Period Input section) before PG/RST asserts high. PG/RST stays low for the selected reset timeout period (tTIMEOUT) after all the OUT_ voltages exceed their IN_ referenced thresholds. PG/RST goes low when VSET_ < VTH or VEN/UV < VEN_R (see Figure 3). Applications Information MOSFET Selection The external pass MOSFET is connected in series with the sequenced power-supply source. Since the load current and the MOSFET drain-to-source impedance (RDS) determine the voltage drop, the on characteristics of the MOSFET affect the load supply accuracy. The MAX6877/MAX6878/MAX6879 fully enhance the external MOSFET out of its linear range to ensure the lowest drain-to-source on-impedance. For highest supply accuracy/lowest voltage drop, select a MOSFET with an appropriate drain-to-source on-impedance with a gate-to-source bias of 4.5V to 6.0V. Layout and Bypassing For better noise immunity, bypass each of the IN_ inputs to GND with 0.1µF capacitors installed as close to the device as possible. Bypass ABP to GND with a 1µF capacitor installed as close to the device as possible. ABP is an internally generated voltage and must not be used to supply power to external circuitry. Selector Guide 20 PART CHANNEL TIMEOUT SELECTABLE PG/RST MARGIN VCC MAX6877 3 Yes Yes Yes Yes MAX6878 2 Yes Yes Yes Yes MAX6879 2 No No No No ______________________________________________________________________________________ Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors IN1 OUT1 IN2 OUT2 IN3 OUT3 0.1µF IN1 IN2 0.1µF 0.1µF IN3 GATE1 GATE2 GATE3 SET1 OUT1 SET2 OUT2 MAX6877 SET3 OUT3 EN/UV FAULT VBUS VCC PG/RST LTCH/RTR MARGIN ABP SLEW GND TRK/SEQ DELAY TIMEOUT 1µF ______________________________________________________________________________________ 21 MAX6877/MAX6878/MAX6879 Typical Application Circuit Ordering Information (continued) PART TEMP RANGE PINPACKAGE PKG CODE MAX6878ETG+* -40°C to +85°C 24 Thin QFN T2444-4 MAX6878ETG* -40°C to +85°C 24 Thin QFN T2444-4 MAX6879ETE+ -40°C to +85°C 16 Thin QFN T1644-4 MAX6879ETE -40°C to +85°C 16 Thin QFN T1644-4 Chip Information PROCESS: BiCMOS *Future product—contact factory for availability. +Denotes lead-free package. Pin Configurations (continued) 12 TRK/SEQ OUT1 20 11 LTCH/RTR GATE1 21 10 TIMEOUT 9 SLEW 8 DELAY 7 GND MAX6878 N.C. 22 EP* IN2 23 + 1 2 3 4 5 6 ABP N.C. SET2 SET1 EN/UV IN1 24 4mm x 4mm THIN QFN TRK/SEQ 12 11 10 9 OUT1 13 8 LTCH/RTR GATE1 14 7 SLEW 6 DELAY 5 GND MAX6879 IN2 15 EP* IN1 16 + 1 2 3 4 EN/UV 13 FAULT MARGIN 14 SET1 PG/RST 15 OUT2 FAULT 16 SET2 N.C. 17 GATE2 N.C. 18 GATE2 19 ABP OUT2 TOP VIEW VCC MAX6877/MAX6878/MAX6879 Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors 4mm x 4mm THIN QFN *EXPOSED PADDLE CONNECTED TO GND. 22 ______________________________________________________________________________________ Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors 24L QFN THIN.EPS PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 D 1 2 ______________________________________________________________________________________ 23 MAX6877/MAX6878/MAX6879 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX6877/MAX6878/MAX6879 Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 D 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products Heaney Printed USA is a registered trademark of Maxim Integrated Products, Inc.