STMicroelectronics L6585D Combo ic for pfc and ballast control Datasheet

L6585D
Combo IC for PFC and ballast control
Features
■
Pre-heating and ignition phases independently
programmable
■
Ignition voltage control
■
Transition mode PFC with over-current
protection
SO-20
■
Programmable and precise End-of-life
protection compliant with all ballast
configurations
■
Auto-adjusting half-bridge over-current control
Applications
■
Automatic re-lamp
■
■
3% oscillator precision
■
1.2µs dead time
■
PFC over-voltage protection and feedback
disconnection
■
Under voltage lock-out
Block diagram
COMP
2.5V
+
_
INV
MULT
E/A
PFCS
1.7V
BOOT
and THD
17V
OPTIMIZER
_
OL
+
1.2V
Vcc
LEB
MULTIPLIER
+
Figure 1.
Electronic ballast
_
S
0.7V
Q
SYNCHRONOUS
BOOTSTRAP DIODE
DEAD
TIME
LEVEL
SHIFTER
DRIVING
R
LATCH
Vcc
HSD
OUT
CHOKE
SAT.
ZCD
STARTER
HVG
DRIVER
UV
DETECTION
PWM
COMP.
Vcc
LVG DRIVER
LOGIC
LSD
OVP
PFG
COMPARATOR
CTR
PFSTOP
DIS
WINDOW
PFSTOP
& REF.
OL
CONTROL
1.6V
GND
HB STOP
LOGIC
EOL
HBCS
OVP
1.9V
3.4V
DIS
2V
2V
0.75V
RELAMP
EOLP
May 2007
Vcc
4.6
1.5
VCO
EOLR
4.63V
0.9V
TIMING
MANAGEMENT
RF
OSC
EOI
Rev 5
Tch
1/25
www.st.com
25
Contents
L6585D
Contents
1
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
2.1
Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1
Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.1
Pre-heating (time interval A Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.2
Ignition (time interval B Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.3
Run mode (time interval C Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
End of life – window comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7
Half-bridge current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8
CTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9
Re–lamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/25
L6585D
1
Device description
Device description
Designed in High-voltage BCD Off-line technology, the L6585D embeds a PFC controller, a
half-bridge controller, the relevant drivers and the logic necessary to build an electronic
ballast.
The advanced and precise logic circuitry, combined with the programmability of the End-ofLife windows comparator threshold, makes the L6585D compliant with either "lamp-toground" or "block capacitor-to ground" configurations.
Another outstanding feature is the possibility of controlling and limiting the lamp voltage
during the ignition phase.
The pre-heating and ignition durations are independently settable as well as the half-bridge
switching frequencies for each operating phases (pre-heating, ignition and normal mode).
Other features (half-bridge over-current with frequency increase, PFC over-voltage) allow
building a reliable and flexible solution with a reduced part count.
The PFC section achieves current mode control operating in Transition Mode; the highly
linear multiplier includes a special circuit, able to reduce AC input current distortion, that
allows wide-range-mains operation with an extremely low THD, even over a large load
range.
The PFC output voltage is controlled by means of a voltage-mode error amplifier and a
precise internal voltage reference.
The driver of the PFC is able to provide 300mA (source) and 600mA (sink) and the drivers of
the half-bridge provide 290mA source and 480mA sink.
Figure 2.
Typical system block diagram
LPFC
HV BUS
R5
R7
R1
Charge
pump
CBULK
R6
R4
R2
AC MAINS
ZCD
PFG
CBOOT
CTR
COMP
INV
11
10
9
Vcc
7
BOOT
17
20
13
CIN
PFCS
R8
CCOMP
L6585D
12
18
16
8
MULT
15
GND
R3
19
1
OSC
RSNSPF
2
3
RF
EOI
RPRE
COSC
4
RRUN
CIGN
RD
Tch
5
6
EOLP
CD
14
EOL-R
RP
HSD
LB
OUT
LSD
CRES
LAMP
HBCS
RSNSHB
CBLOCK
3/25
Pin settings
L6585D
2
Pin settings
2.1
Connection
Figure 3.
Pin sonnection (Top view)
OSC
RF
HSD
EOI
OUT
TCH
VCC
EOLP
LSD
EOL-R
GND
CTR
HBCS
MULT
PFG
COMP
PFCS
INV
4/25
BOOT
ZCD
L6585D
2.2
Pin settings
Functions
Table 1.
Pin functions
Pin num. Name
1
2
3
4
OSC
Function
An external capacitor to GND fixes the half-bridge switching frequency with a
±3% precision.
RF
Voltage reference able to source up to 240µA; the current sunk from this pin fixes
the switching frequency of the half-bridge for each operating state.
A resistor (RRUN) connected to ground sets the half-bridge operating frequency
combined with the capacitor connected to the pin OSC.
A resistor connected to EOI (RPRE) – in parallel with RRUN – sets the maximum
half-bridge switching frequency during pre-heating.
EOI
Connected to ground by a capacitor that, combined with RPRE, determines the
ignition duration
Pre-heating: low impedance to set high switching frequency
Ignition and run mode: high impedance with controlled current sink in case of
HBCS threshold triggering.
Tch
Pin for setting the pre-heating time and the protection intervention.
Connect a RC parallel network (RD and CD) to ground
Pre-heating: the CD is charged by an internal current generator. When the pin
voltage reaches 4.63V the generator is disabled and the capacitor discharges
because of RD; once the voltage drops below 1.52V, the preheating finishes, the
ignition phase starts and the RDCD is discharged to ground.
Run mode: according to the kind of fault (either over-current or EOL) the
internal generator charges the RC parallel network and appropriate actions are
taken to stop the application. During proper behavior of the IC, this pin is low
impedance.
5
Pin to program the EOL comparator.
EOLP It is possible to select both the EOL sensing method and the window comparator
amplitude by connecting a resistor (REOLP) to ground.
6
Input for the window comparator and re-lamp function.
It can be used to detect the lamp ageing for either “lamp to ground” and “block
capacitor to ground” configurations.
According to the EOLP pin setting, it is possible to program:
– the window amplitude (VW)
EOL-R – the center of the window (VSET) either fixed or in tracking with the PFC output
bus.
This function is blanked during the ignition phase.
In case of either lamp disconnection or removal, a second threshold (VSL-UP)
crossing latches the IC and drives the chip in “ready-mode” so that when the
voltage at EOL-R pin is brought below VSL-DOWN (re-lamp) a new preheating/ignition sequence is repeated.
7
CTR
Input pin for:
– PFC over-voltage detection: the PFC driver is stopped until the voltage returns
in the proper operating range
– Feedback disconnection detection
– reference for End-of-life in case tracking reference;
– shut-down: forcing the pin to a voltage lower than 0.75V, the IC shuts down in
unlatched condition.
8
MULT
Main input to the multiplier. This pin is connected to the rectified mains voltage
via a resistor divider and provides the sinusoidal reference to the PFC current
loop.
5/25
Pin settings
L6585D
Table 1.
Pin functions (continued)
Pin num. Name
9
10
11
Output of the error amplifier. A compensation network is placed between this pin
COMP and INV to achieve stability of the PFC voltage control loop and ensure high
power factor and low THD.
INV
Inverting input of the error amplifier. The information on the output voltage of the
PFC pre-regulator is fed into the pin through a resistor divider. Input for the
feedback disconnection comparator
ZCD
Boost inductor’s demagnetization sensing input for PFC transition-mode
operation. A negative-going edge triggers PFC MOSFET turn-on.
During start-up or when the voltage is not high enough to arm the internal
comparator (e.g. AC Mains peak), the PFC driver is triggered by means of an
internal starter.
12
PFCS
13
PFG
Input to the PFC PWM comparator. The current flowing in the PFC mosfet is
sensed by a resistor; the resulting voltage is applied to this pin and compared
with an internal sinusoidal-shaped reference, generated by the multiplier, to
determine the PFC MOSFET’ s turn-off.
A second comparison level detects abnormal currents (e.g. due to boost inductor
saturation) and, on this occurrence, shuts down and latches the IC reducing its
consumption to the start-up.
An internal LEB prevents undesired function triggering.
PFC gate driver output. The totem pole output stage is able to drive power
MOSFET’S with a peak current of 300mA source and 600mA sink.
14
2-levels half-bridge current monitor for current control.
The current flowing in the HB mosfet is sensed by a resistor; the resulting
voltage is applied to this pin.
Low threshold (active during run mode): in case of thresholds crossing, the IC
reacts with self-adjusting frequency increase in order to limit the half-bridge
HBCS (lamp) current.
High threshold:
– ignition: in case of thresholds crossing during the frequency shift, the IC reacts
with self-adjusting frequency increase in order to limit the lamp voltage and
preventing operation below resonance.
– run mode: in case of thresholds crossing because of current spikes (due e. g.
to capacitive mode / cross-conduction), the L6585D latches to avoid
MOSFETs damaging,
15
GND
Ground. Current return for both the signal part of the IC and the gate driver.
16
LSD
Low side driver output: the output stage can deliver 290mA source and 480mA
sink (typ. values).
17
VCC
Supply Voltage of both the signal part of the IC and the gate driver.
Clamped with a Zener inside.
18
OUT
High Side Driver Floating Reference. This pin must be connected close to the
source of the high side power MOS.
19
HSD
High side driver output: the output stage can deliver 290mA source and 480mA
(typ. values).
20
6/25
Function
Bootstrapped Supply Voltage. Between this pin and VCC, the bootstrap capacitor
must be connected.
BOOT
A patented integrated circuitry replaces the external bootstrap diode, by means
of a high voltage DMOS, synchronously driven with the low side power MOSFET.
L6585D
Electrical data
3
Electrical data
3.1
Maximum ratings
Table 2.
Absolute maximum ratings
Symbol
Pin
VBOOT
20
VOUT
dVOUT /dt
VCC
Value
Unit
Floating supply voltage
-1 to 618
V
18
Floating ground voltage
-3 to VBOOT – 18
V
18
Floating ground max. slew rate
50
V/ns
Self-limited
V
-0.3 to 5
V
2, 5
-0.3 to 2.7
V
6
Vcc
7
-0.3 to 7
14
-5 to 5
17
1, 3, 4,
8, 10,
12
9, 11
Parameter
(1)
IC Supply voltage (ICC = 20mA)
Analog input and outputs
ZCD clamp (IZCD < 4mA)
V
Self-limited
IRF
2
Current capability
240
µA
IEOLP
5
Current capability
100
µA
FOSC(MAX)
Maximum operating frequency
250
KHz
PTOT
Power dissipation @TA = 70°C
0.83
W
1. The device has an internal Clamping Zener between GND and the VCC pin, it must not be supplied by a
Low Impedance Voltage Source.
Note:
ESD immunity for pins 18, 19 and 20 is guaranteed up to 900V (Human Body Model)
3.2
Thermal data
Table 3.
Thermal data
Symbol
RthJA
TJ
TSTG
Description
Value
Unit
120
°C/W
Junction operating temperature range
-40 to 150
°C
Storage temperature
-55 to 150
°C
Max. thermal resistance junction to ambient
7/25
Electrical characteristics
4
L6585D
Electrical characteristics
VCC = 15V, TA = 25°C, CL = 1nF, COSC = 470pF, RRUN = 47K, unless otherwise specified
Table 4.
Electrical characteristics
Symbol
Pin
Parameter
Test condition
Min
Typ
Max
Unit
16
V
Supply voltage
Vcc
VCC(on)
VCC
VCC
Operating range
After turn-on
Turn-on threshold
(1)
13.6
14.3
15
V
9.6
10.3
11
V
16.2
17.2
17.7
V
250
370
µA
VCC(OFF)
VCC
Turn-off threshold
(1)
VZ
VCC
Zener Voltage
Icc = 20mA
IST-UP
VCC
Start-up current
Before turn-on @ 13V
ICC
VCC
Operating supply current
Iq
VCC
Residual current
11
Supply current
7
mA
IC latched
370
µA
-1
µA
PFC section – multiplier input
IMULT
MULT
Input bias current
VMULT = 0
VMULT
MULT
Linear operation range
VCOMP = 3V
MULT
Output max. slope
VMULT = 0 to 1V,
VCOMP = Upper clamp
0.75
V/V
MULT
Gain
VMULT = 1V, VCOMP= 3V
0.52
1/V
∆VCS
∆VMULT
KM
0 to 3
V
PFC section – error amplifier
VINV
IINV
Gv
INV
Voltage feedback input
threshold
INV
Line regulation
INV
Input bias current
INV
Gain-bandwidth product
(2)
Source current
60
mV
-1
µA
VCOMP = 4V, VINV = 2.4 V
-2.6
mA
Sink current
VCOMP = 4V, VINV = 2.6 V
4
mA
Upper clamp voltage
ISOURCE = 0.5 mA
4.2
V
Lower clamp voltage
ISINK = 0.5 mA
2.25
V
INV
Open loop detection
threshold
CTR > 3.4
1.2
V
COMP
Static OVP threshold
COMP
Open loop
50
MHz
COMP
Voltage gain
(2)
V
1
ICOMP
8/25
VCC = 10.3V to 16V
2.55
dB
INV
VDIS
2.5
80
GB
VCOMP
2.45
2.1
2.25
2.4
V
L6585D
Table 4.
Symbol
Electrical characteristics
Electrical characteristics (continued)
Pin
Parameter
Test condition
Min
Typ
Max
Unit
CTR pin
DIS
CTR
PFOV
CTR
Disable threshold
Falling edge
0.75
V
120
mV
3.4
V
140
mV
Lower threshold (falling)
1.7
V
Hysteresys
0.12
Higher threshold (rising)
3.4
Hysteresys
0.14
Hysteresys
Dynamic PFC
overvoltage
Rising edge
Hysteresys
Available range as
tracking reference
CTR
V
PFC section – current sense comparator
ICS
PFCS
Input bias current
VCS = 0
(2)
tLEB
PFCS
Leading edge blanking
VCSdis
PFCS
IC disable level
td(H-L)
PFCS
Delay to output
VCSclamp
PFCS
Current sense reference
clamp
-1
µA
100
200
300
ns
1.65
1.75
1.85
V
120
VCOMP = Upper clamp
1.0
1.08
ns
1.16
V
PFC section – zero current detector
VZCDH
ZCD
Upper clamp voltage
IZCD = 2.5 mA
5
VZCDL
ZCD
Lower clamp voltage
IZCD = -2.5 mA
-0.3
VZCDA
ZCD
Arming voltage
(positive-going edge)
(2)
1.4
V
VZCDT
ZCD
Triggering voltage
(negative-going edge)
(2)
0.7
V
IZCDb
ZCD
Input bias current
VZCD = 1 to 4.5 V
IZCDsrc
ZCD
Source current capability
-4
mA
IZCDsnk
ZCD
Sink current capability
4
mA
V
0
0.3
1
V
µA
PFC section – gate driver
ISINK = 10mA
0.2
V
PFG
Output high/low
tf
PFG
Fall time
40
90
ns
tr
PFG
Rise time
90
140
ns
ISINK
PFG
Peak sink current
475
600
mA
ISOURCE
PFG
Peak source current
200
300
mA
PFG
Pull-down resistor
10
kΩ
ISOURCE = 10mA
14.5
V
9/25
Electrical characteristics
Table 4.
Symbol
L6585D
Electrical characteristics (continued)
Pin
Parameter
Test condition
Min
Typ
Max
Unit
Half bridge section – Timing & oscillator
ICH
TCH
Charge current
VTCH = 2.2V
VCHP
TCH
Charge threshold
(positive going-edge)
VCHN
TCH
RTCH
REOI
IEOI
30
µA
(1)
4.63
V
Discharge threshold
(negative going edge)
(1)
1.50
V
TCH
Leakage current
1.5V < VTCH < 4.5V,
falling
TCH
Internal impedance
Run mode
EOI
Open state current
VEOI = 2V
EOI
EOI impedance
During pre-heating
EOI
EOI current generator
during ignition and run
mode
150
Tspike = 200ns
(3)
20
Tspike = 400ns
(3)
100
Tspike = 600ns
(3)
200
Tspike = 1µs (3)
VEOI
EOI
0.1
µA
200
Ω
0.15
µA
150
Ω
µA
270
EOI threshold
(1)
1.83
1.9
1.98
V
(1)
1.92
2
2.08
V
VREF
RF
Reference voltage
IRF
RF
Max current capability
µA
240
Rising threshold
(1)
3.7
V
OSC
Falling threshold
(1)
0.9
V
D
OSC
Output duty cycle
TDEAD
OSC
fRUN
fPRE
OSC
48
50
52
%
Dead time
0.96
1.2
1.44
µs
OSC
Half-bridge oscillation
frequency (run mode)
58.4
60.2
62
KHz
OSC
Half-bridge oscillation
frequency (pre heating)
113.2
116.7
120.2
KHz
RPRE=50K
Half bridge section – End Of Life FUNCTION and re-lamp comparator
VS
VW
10/25
EOLP
Current capability
100
EOLP
Reference voltage
1.92
EOL-R
Operating range
EOL-R
Window comparator
reference
Half window amplitude
EOLP=27K
220K = REOLP = 270K or
22K = REOLP = 27K
µA
2
0.95
2.08
V
4.15
V
tracking with CTR
V
REOLP > 620K or
75K = REOLP = 91K
2.5
220K = REOLP = 270K or
75K = REOLP = 91K
220
mV
REOLP > 620K or
22K = REOLP = 27K
720
mV
L6585D
Table 4.
Symbol
Electrical characteristics
Electrical characteristics (continued)
Pin
Parameter
Test condition
Min
Typ
Max
Unit
EOL-R
Sink/source capability
2.5
µA
EOL-R
Relamp comparator
4.63
V
hysteresys
160
mV
Half bridge section – Half-bridge current sense
HBCSH
HBCS
HBCSL
HBCS
HBCS
Frequency increase
threshold
Latched threshold
VEOI < 1.9V (ignition)
1.53
1.6
1.66
V
VEOI > 1.9V (run mode)
0.85
0.91
0.97
V
Run mode
1.53
1.6
1.66
V
0.3
V
Half bridge section – Low side gate driver
LSD
Output low voltage
ISINK = 10mA
LSD
Output high voltage
ISOURCE = 10mA
LSD
Peak source current
200
290
mA
LSD
Peak sink current
400
480
mA
TRISE
LSD
Rise time
120
ns
TFALL
LSD
Fall time
80
ns
LSD
Pull-down resistor
45
KΩ
14.5
;
V
Half bridge section – High side gate driver (voltages referred to OUT)
VOUT +
0.3
HSD
Output low voltage
ISINK = 10mA
HSD
Output high voltage
ISOURCE = 10mA
HSD
Peak source current
200
290
mA
HSD
Peak sink current
400
480
mA
TRISE
HSD
Rise time
120
ns
TFALL
HSD
Fall time
80
ns
HSD
HSD-OUT pull-down
50
KΩ
V
VBOOT
– 0.5
V
High-side floating gate-drive supply
BOOT
OUT
Leakage current
VBOOT = 600V (2)
Leakage current
VOUT = 600V
Synchronous bootstrap
diode on-resistance
VLSD = HIGH
(2)
5
µA
5
µA
250
Ω
1. Parameter in tracking
2. Specification over the -40°C to 125°C junction temperature range are ensured by design, characterization and statistical
correlation
3. A pulse train has been sent to the HBCS pin with f=6KHz; the pulse duration is the one indicated in the notes as "TON"
11/25
Application information
L6585D
5
Application information
5.1
Start-up sequence
5.1.1
Pre-heating (time interval A Figure 5)
After IC turn-on, unless a lamp absence is detected, the oscillator starts switching at a
frequency (fPRE) set by values of COSC and RRUN and RPRE Figure 4:
Equation 1
1.328
f PRE = ----------------------------------------------------------C OSC ⋅ ( R RUN || R PRE )
The pre-heating time is:
Equation 2
CD
4.63
T PRE = 4.63 ⋅ -------- + R D ⋅ C D ⋅ ln ----------1.52
I CH
where CD and RD are shown in Figure 4 and ICH is typically 34 µA.
Figure 4.
Oscillator, pre-heating and ignition circuitry
IMAX
VREF
RF
RRUN
RPRE
CIGN
EOI
RD
Tch
CD
COSC
12/25
LOGIC
OSC
L6585D
5.1.2
Application information
Ignition (time interval B Figure 5)
When the voltage at pin TCH drops down to 1.50V (typ.), the pin EOI is driven in high
impedance state and CIGN is exponentially charged according to the time constant τ given
by CIGN*RPRE that defines the ignition time and the frequency shift starts.
The ignition time is the time necessary to EOI voltage to reach 1.9V, so, by means of simple
calculation:
Equation 3
T IGN = 3 ⋅ C IGN ⋅ R PRE
During this phase, the half-bridge current control can limit the maximum voltage applied
to the lamp by forcing small frequency increases whenever the half-bridge sense resistor
voltage exceeds the HBCSH threshold (see the “Half-Bridge current control” paragraph).
Figure 5, centre and right, shows the L6585D behavior as the lamp gets older; if it doesn’t
ignite for a time longer than the pre-heating one (counted by a cycle charge/discharge of the
TCH pin), the IC is stopped, enters low consumption and waits for either a re-lamp or an
UVLO.
13/25
Application information
5.1.3
L6585D
Run mode (time interval C Figure 5)
As the voltage at EOI exceeds 1.9V and the lamp has ignited, the L6585D enters Run mode
and remains in this condition unless one of the protections (all enabled in this mode) is
trigged.
The switching frequency reaches the FRUN value set by RRUN and COSC:
Equation 4
1.328 f RUN = ---------------------------------R RUN ⋅ C OSC
Figure 5.
Oscillator, pre-heating and ignition sequence
VCC(on)
VCC(on)
VCC
VCC
VCC(off)
τ = RD x CD
4.63V
Tch
EOI
Tch
2V
EOI
1.9V
fPRE
fHB
VCC(off)
4.63V
Tch
1.5V
2V
EOI
1.9V
fPRE
fHB
fRUN
fRUN
VHBCS
VHBCS
VLAMP
VLAMP
VLAMP
14/25
B
C
A
1.5V
2V
1.9V
fPRE
fHB
VHBCS
A
VCC(off)
4.63V
1.5V
VZ
VCC(on)
VCC
B
C
fRUN
A
B
C
L6585D
End of life – window comparator
6
End of life – window comparator
To detect the ageing of the lamp with particular attention to the effect appearing as
asymmetric rectification, a programmable window comparator has been introduced
(centered around “VREF” with amplitude “VW”) that triggers when the EOL-R voltage is
higher than VREF+ VW/2 or lower than VREF – VW/2.
By means of the resistor connected to the EOLP pin, it is possible to select:
1. the sensing mode:
2.
Figure 6.
–
fixed reference: the centre of the window comparator (VREF) is fixed at 2.5V by an
internal reference;
–
tracking reference: the centre of the window comparator is the voltage at pin CTR
(that is a signal proportional to the PFC output voltage).
the half-window amplitude (VW/2): 220mV or 720mV.
End-of-life detection circuitry and waveforms
RP2
CTR
RP1
HV BUS
HV BUS
CBOOT
CBOOT
BOOT
INTERNAL
FIXED REF.
WINDOW
COMPARATOR INPUT
CTR
HSD
WINDOW
COMPARATOR INPUT
OUT
AMPLITUDE
HSD
OUT
CBLOCK
AMPLITUDE
LSD
EOLP
BOOT
INTERNAL
FIXED REF.
LSD
VLAMP
EOLR
RFL or RFH
EOLR
EOLP
VK
VLAMP
VK
RE1
CBLOCK
RE2
RFL or RFH
VZ2
VZ1
RE1
RE2
HVBUS (100Hz or 120Hz)
PFCOUT
PFCOUT/2
VCB
VLAMP
VREF + W/2 + VZ1 + VR2
CTR
VK
VREF – W/2 – VZ1 – VR2
VREF + W/2
VEOLR
VREF + W/2
VREF
VREF – W/2
VREF – W/2
VEOLR
15/25
End of life – window comparator
L6585D
The four possible configurations are summarized in the following table, together with the
value of resistance to be connected to the EOLP pin in order to obtain the desired setting:
Table 5.
Configuration of the EOLP pin
EOLP resistor
Symbol
Reference
Half–window amplitude
REOLP > 620K
RFH
Fixed 2.5V
± 720mV
220K = REOLP = 270K
RTL
Tracking with CTR
± 220mV
75K = REOLP = 91K
RFL
Fixed 2.5V
± 220mV
22K = REOLP = 27K
RTL
Tracking with CTR
± 720mV
Tracking reference: this setting is suitable for the block capacitor to ground configuration
(Figure 6, left).
In this case the window comparator centre is set by the CTR voltage that is internally
transferred to the EOL structure.
The effect of rectification appears as shifting of the DC voltage component across the block
capacitor, which, under normal conditions, equals one half of the PFC output voltage.
A signal proportional to the DC block capacitor voltage is sent to the EOL-R pin by means of
a resistive divider (RE1 and RE2); the dividers RE1 and RE2 and RP1 and RP2 must be
designed to set the EOL-R voltage equal to CTR under nominal condition.
Fixed reference: this setting is suitable for the lamp to ground configuration (Figure 6, right).
The effect of rectification appears as shifting of the DC lamp voltage.
A resistive divider (RE1 and RE2) senses the voltage across the lamp under normal
condition, that is an AC signal with zero average value whereas in case of asymmetric
rectification the DC value can shift either in positive or negative direction. Two Zener diodes
can be connected back-to-back between the EOL-R pin and the centre of the resistive
divider.
The Zener voltages should differ by an amount as close as possible to the double of the
internal reference to have a symmetrical detection, as it can easily obtained from the
following equations:
●
VUP = VREF + W/2 + VZ1 + VR2
●
VDOWN = VREF – W/2 – VZ2 – VR1
where VUP and VDOWN are the VK values (equal in absolute value) that trigger the window
comparator.
To avoid an immediate intervention of the EOL protection, a filtering is introduced; as long as
the fault condition persists, the Tch internal generator charges the CD up to 4.63V and then
it opens. If this fault condition is still present when the Tch voltage decreases down to 1.5V,
then the half bridge is stopped, otherwise (if the fault disappears) the counting is stopped
and reset.
16/25
L6585D
7
Half-bridge current control
Half-bridge current control
The information about the lamp current can be obtained by reading the voltage across a
sense resistor placed in series to the source of the half-bridge low side MOS.
This circuitry is enabled at the end of the pre-heating phase and it enriches the L6585D with
two features:
●
Controlled lamp voltage/current during ignition (Figure 5): by properly setting the
sense resistor (such that the VHBCS level is crossed in correspondence of a lamp
voltage higher than the ignition voltage) it is possible to limit the maximum lamp voltage
during ignition. In case of this occurrence, then the L6585D would react with a small
frequency increase that allows limiting the lamp voltage (V+IGN). This also prevents the
risk of crossing the resonance frequency of the LBALLAST-CRES circuit. If the lamp
ignites before TCH reaches 1.50V (Figure 5 left) that is EOI has exceeded 1.9V, then:
–
EOI internal switch opens and its voltage moves asymptotically to 2V
–
The switching frequency reaches the operating one;
–
When TCH reaches 1.52, it will be discharged
If instead that the lamp hasn’t ignited after a time equal to the pre-heat time (Figure 5
right) the oscillator stops, the chip enters low consumption mode and this condition is
latched until the mains supply voltage is removed or a re-lamp is detected.
●
Over-current protection during run mode: if the HBCSL threshold is crossed, the TCH
internal generator is turned on as well as the one at pin EOI causing a frequency
increase: this implements a current control structure.
During run mode another protection is active: a second comparator (HBCSH) on the pin
HBCS detects anomalous current flow through the sense resistor such as the spikes
generated by the capacitive mode; the crossing of this second threshold latches the IC.
17/25
CTR
8
L6585D
CTR
This is a multi-function pin, connected to a resistive divider to the PFC output bus:
18/25
●
PFC over-voltage: in case of PFC output overshoot (e.g. at start-up) that causes a
threshold crossing, the PFC section stops switching until the pin voltage falls below
3.26V (typ.); this is helpful because the bandwidth of the PFC error amplifier is narrow
so the control loop is not fast enough to properly reacts
●
Feedback disconnection: The OVP function above described (together with the static
one embedded in the PFC error amplifier) is able to handle “normal” over-voltage
conditions, i.e. those resulting from an abrupt load/line change or occurring at start-up.
In case of over-voltage generated when the upper resistor of the feedback output
divider fails open, the control loop can no longer read the information on the output
voltage and will force the PFC pre-regulator to work at maximum ON time; if this occurs
(i.e. the pin INV falls below 1.2V, typ.) and the CTR detects an OVP, the gate drivers
activity is immediately stopped, the device enters low consumption and the condition is
latched as long as the IC supply voltage is above the UVLO threshold;
●
Reference for EOL in case of tracking reading.
●
Disable: by forcing the pin below 0.75V an immediate unlatched shut-down is activated;
it can be also used as re-lamp in fact after the pin voltage is above 0.8V a preheating/ignition sequence is repeated.
L6585D
9
Re–lamp
Re–lamp
A second comparator has been introduced on the pin EOL-R; a voltage higher than the
internal threshold is read as lamp absence so the chip suddenly stops switching, enters idle
mode (low consumption) and is ready for a new pre-heating/ignition sequence as soon as a
new lamp is inserted.
In this idle mode the consumption of the chip is reduced so that the current flowing through
the resistors (connected to the high voltage bus for the start-up) is enough to keep the VCC
voltage above the UVLO threshold.
After a re-lamp cycle (that is the EOL-R voltage is brought above 4.63V and then released
below), a new pre-heating/ignition sequence starts.
Table 6.
IC configuration
Pre-heating
Ignition
Run mode
EOI charge from 0 to
1.9V (typ.);
Until a fault appears or
It depends on RD and the AC Mains is removed
CD
Time duration
TCH cycle(1);
It depends on RD and CD
Half-bridge switching
frequency
1.328
f PRE = ----------------------------------------------------------C OSC ⋅ ( R RUN || R PRE )
The frequency shifts
from fPRE to fRUN with
exponential trend
1.328 f RUN = ---------------------------------R RUN ⋅ C OSC
RELAMP comparator
ENABLED
ENABLED
ENABLED
CTR: PFC
overvoltage
ENABLED
ENABLED
ENABLED
CTR: disable function
ENABLED
ENABLED
ENABLED
ENABLED
– low threshold ⇒
disabled
– high threshold ⇒
FSW increase
ENABLED
– low threshold ⇒
FSW increase
– high threshold ⇒
latch
Half-bridge current
sense
DISABLED
EOL: window
comparator
DISABLED
DISABLED
ENABLED
PFC choke saturation
ENABLED
ENABLED
ENABLED
1. TCH cycle: charge of the TCH voltage up to 4.63V and discharge down to 1.50V following the RDCD time constant
19/25
Re–lamp
Table 7.
L6585D
Fault conditions
Fault
Lamp absence
(re-lamp comparator)
End of life
Half-bridge current
sense
Shut-down
Choke saturation
Condition
IC behavior
At turn-on: EOL-R
voltage higher than
4.63V
– The TCH charge doesn’t start (no
ignition)
– Drivers stopped
– IC low consumption (Vcc clamped)
Run mode: EOL-R
voltage higher than
4.63V
– All drivers stopped
– IC low consumption (Vcc clamped)
EOL-R voltage outside
the limits of window
comparator
– TCH cycle (1) (reset if the fault
disappears)
– drivers stopped at the end of TCH
cycle
– IC low consumption (VCC clamped)
Re-lamp cycle (2)
Ignition:
HBCS threshold
– TCH cycle (1) with lamp voltage
control
– In case of HBCS at the end of the
TCH cycle, drivers stopped
– IC low consumption (Vcc clamped)
Re-lamp cycle (2)
Run mode:
HBCSL threshold
– TCH cycle (1) with lamp voltage
control (frequency increase)
– In case of HBCS at the end of the
TCH cycle, drivers stopped
– IC low consumption (Vcc clamped)
Re-lamp cycle (2)
Run mode:
HBCSH threshold
– Drivers stopped
– IC low consumption (Vcc clamped)
Re-lamp cycle (2)
CTR voltage lower than
0.8V
– Drivers stopped
– IC low consumption (Vcc clamped)
When the CTR voltage
returns above 0.8V, the
IC driver restart with a
pre-heating sequence
PFCS voltage higher
than 1.6V
– Drivers stopped
– IC low consumption (Vcc clamped)
Re-lamp cycle (2)(3)
Over-voltage of PFC CTR voltage higher than
– PFC driver stopped
output
3.4V
PFC open loop
(feedback
disconnection)
1.
Action required
CTR voltage higher than
– Drivers stopped
3.4V AND INV voltage
– IC low consumption (Vcc clamped)
lower than 1.2
Lamp replacement
(EOL-R below 4.63V)
When the CTR voltage
returns below
3.26V (Typ.), the PFC
driver restarts
Re-lamp cycle (2)(3)
TCH cycle: charge of the TCH voltage up to 4.63V and discharge down to 1.50V following the RDCD time constant;
2. Re-lamp cycle: the voltage at EOL-R pin must be first pulled above 4.63V and then released below it; this typically happens
in case of lamp replacement. After a re-lamp cycle, a new pre-heating sequence will be repeated.
3. This fault actually is a "board" fault so a lamp replacement is not effective to restart the ballast
20/25
L6585D
10
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
21/25
Package mechanical data
Table 8.
L6585D
SO-20 mechanical data
Dimensions
mm.
inch
Ref.
Min.
Typ.
A
a1
Max.
Typ.
2.65
0.1
Max.
0.104
0.2
a2
0.004
0.008
2.45
0.096
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.012
C
0.5
0.020
c1
45° (typ.)
D
12.60
13.00
0.496
0.512
E
10.00
10.65
0.393
0.419
e
1.27
0.050
e3
11.43
0.450
F
7.40
7.60
0.291
0.300
L
0.50
1.27
0.020
0.050
M
0.75
S
Figure 7.
22/25
Min.
0.029
8° (max.)
Package dimensions
L6585D
11
Order codes
Order codes
Table 9.
Order codes
Part Number
Package
Packaging
L6585D
SO-20
Tube
L6585DTR
SO-20
Tape and Reel
23/25
Revision history
12
L6585D
Revision history
Table 10.
24/25
Revision history
Date
Revision
Changes
12-Jan-2006
1
Initial release
25-Oct-2006
2
Final datasheet
21-Dec-2006
3
Updated fRUN value on Table 4: Electrical characteristics on
page 8
12-Apr-2007
4
Updated electrical values on Table 4
23-May-2007
5
Updated Figure 1: Block diagram on page 1 and Eq.1 and 4
L6585D
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25/25