Fairchild FAN2013MPX 2a low-voltage, current-mode synchronous pwm buck regulator Datasheet

FAN2013 — 2A Low-Voltage, Current-Mode
Synchronous PWM Buck Regulator
Features
Description
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95% Efficiency, Synchronous Operation
The FAN2013 is a high-efficiency, low-noise,
synchronous Pulse Width Modulated (PWM) currentmode DC-DC converter designed for low-voltage
applications. It provides up to 2A continuous-load
current from the 4.5V to 5.5V input. The output voltage
is adjustable over a wide range by means of an external
voltage divider.
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3x3mm 6-lead MLP Package
Adjustable Output Voltage from 0.8V to VIN-1
4.5V to 5.5V Input Voltage Range
Up to 2A Output Current
Fixed-Frequency 1.3 MHz PWM Operation
100% Duty Cycle Low-Dropout Operation (LDO)
The FAN2013 is enabled when the input voltage on the
VIN pin exceed the UVLO threshold.
Soft-Start Function
Excellent Load Transient Response
A current-mode control loop with a fast transient
response ensures excellent line and load regulation.
The fixed 1.3MHz switching frequency enables
designers to choose a small, inexpensive external
inductor and capacitor. Filtering can be accomplished
with small components, reducing space and cost.
Power-Good Flag
Over-Voltage, Under-Voltage Lockout, ShortCircuit, and Thermal Shutdown Protections
Protection features include input under-voltage lockout,
short-circuit protection, and thermal shutdown. Softstart limits inrush current during start-up conditions.
Applications
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Hard Disk Drive
The device is available in a 3x3mm 6-lead MLP.
Set-Top Box
Point-of-Load Power
Notebook Computer
Communications Equipment
Typical Application
PG
VIN
R3
10K
6
5
4
CIN
10µF
FB
PG
VIN
PGND
P1
PVIN
SW
U1
1
2
3
R2
10K
R1
L
COUT
40 - 60µF
FAN2013
Figure 1.
VOUT
2.2µH
Typical Application
Ordering Information
Part Number
Output Voltage
Package
Packing Method
FAN2013MPX
0.8V to VIN-1V
3x3mm 6-Lead Molded Leadless Package (MLP)
Tape and Reel
All packages are lead free per JEDEC: J-STD-020B standard.
© 2006 Fairchild Semiconductor Corporation
FAN2013 Rev. 1.0.3
www.fairchildsemi.com
FAN2013 — 2A Low-Voltage, Current-Mode Synchronous PWM Buck Regulator
January 2008
FB
1
PGND
2
SW
3
Figure 2.
P1
(AGND)
6
PG
5
VIN
4
PVIN
Pin Assignments (Top View)
Pin Definitions
Pin #
Name
Description
P1
AGND
1
FB
2
PGND
3
SW
4
PVIN
5
VIN
Supply Voltage Input.
6
PG
Open Drain Power Good.
Analog Ground. P1 must be soldered to the PCB ground.
Feedback Input. Adjustable voltage option; connect this pin to the resistor divider.
Power Ground. This pin is connected to the internal MOSFET switches. This pin must be
externally connected to AGND.
Switching Node. This pin is connected to the internal MOSFET switches.
Supply Voltage Input. This pin is connected to the internal MOSFET switches.
© 2006 Fairchild Semiconductor Corporation
FAN2013 Rev. 1.0.3
FAN2013 — 2A Low-Voltage, Current-Mode Synchronous PWM Buck Regulator
Pin Assignments
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2
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
VIN
Supply Voltage
θJC
Thermal Resistance, Junction-to-Tab
TL
Lead Soldering Temperature (10 Seconds)
Input Voltage on PVIN and Any Other Pin
TSTG
Storage Temperature
TJ
Junction Temperature
ESD
Min.
Max.
Unit
-0.3
6.2
V
-0.3
VIN
V
(1)
Electrostatic Discharge Protection Level
(2)
8
°C/W
260
°C
-65
150
°C
-40
150
°C
HBM
3.5
CDM
2
kV
Notes:
1. Junction-to-ambient thermal resistance, θJA, is a strong function of PCB material, board thickness, thickness and
number of copper planes, number of via used, diameter of via used, available copper surface, and attached heat
sink characteristics.
2. Using Mil Std. 883E, method 3015.7 (Human Body Model) and EIA/JESD22C101-A (Charged Device Model).
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbols
VIN
Parameter
Min.
Typ.
Max.
Unit
Supply Voltage Range
4.5
5.5
V
VOUT
Output Voltage Range, Adjustable Version
0.8
VIN-1
V
IOUT
Output Current
2.0
A
L
CIN
COUT
TA
Inductor
(3)
Input Capacitor
(3)
Output Capacitor
(3)
Operating Ambient Temperature Range
2.2
µH
10
20
µF
20
40
µF
-40
+85
FAN2013 — 2A Low-Voltage, Current-Mode Synchronous PWM Buck Regulator
Absolute Maximum Ratings
°C
Note:
3. Refer to the Applications section for details.
© 2006 Fairchild Semiconductor Corporation
FAN2013 Rev. 1.0.3
www.fairchildsemi.com
3
VIN = 4.5V to 5.5V, VOUT = 1.2V, IOUT = 200mA, CIN = 10µF, COUT = 40µF, L = 2.2µH, TA = -40°C to +85°C, unless
otherwise noted. Typical values are at TA = 25°C.
Symbol
Parameter
VIN
Input Voltage
IQ
Quiescent Current
VUVLO
RON_PMOS
RON_NMOS
Conditions
Typ.
Max.
Units
5.5
V
10
16
mA
3.7
4.0
V
4.5
IOUT = 0mA
VIN Rising
UVLO Threshold
PMOS On Resistance
3.4
Hysteresis
150
mV
VIN = VGS = 5V
90
MΩ
NMOS On Resistance
VIN = VGS = 5V
ILIMIT
P-Channel Current Limit
4.5V < VIN < 5.5V
TOVP
Over-Temperature Protection
fSW
Min.
90
2.8
3.5
mΩ
4.2
Rising Temperature
150
°C
Hysteresis
20
°C
Switching Frequency
1000
1300
RLINE
Line Regulation
VIN = 4.5 to 5.5V, IOUT = 100mA
0.16
RLOAD
Load Regulation
0mA ≤ IOUT ≤ 2000mA
0.2
VOUT
Output Voltage During Load
(4)
Transition
ILEAK
Reverse Leakage Current
into Pin SW
VREF
Reference Voltage
IOUT from 1500mA to 100mA,
COUT = 60µF
IOUT from 100mA to 1500mA,
COUT = 60µF
1600
Output Voltage Accuracy
VPG
Power Good Output
Threshold and Hysteresis
kHz
%/V
0.6
%
5
%
-5
%
VIN = Open, EN = GND, VSW = 5.5V
0.1
1.0
0.8
VOUT
A
µA
V
VIN = 4.5 to 5.5V, 0mA ≤ IOUT
≤ 2000mA, TA= 0°C to +85°C
-2
2
%
VIN = 4.5 to 5.5V, 0mA ≤ IOUT
≤ 2000mA, TA= -40°C to +85°C
-3
3
%
FB Voltage Rising
0.85 xVOUT
%
2
V
Hysteresis
tPG
Power Good Output Delay
VPG_LOW
Power Good Voltage Low
Isink=6mA, Open-Drain Output
100
VOVP
Over-Voltage Protection
Threshold and Hysteresis
FB Voltage Rising
µs
0.4
V
1.07 xVOUT
V
2
%
Hysteresis
FAN2013 — 2A Low-Voltage, Current-Mode Synchronous PWM Buck Regulator
Electrical Characteristics
ILOAD (mA)
Notes:
4. Please refer to the load transient response test waveform shown in Figure 3.
ss
1500
tr = 100ns
100
ss
0
Figure 3.
© 2006 Fairchild Semiconductor Corporation
FAN2013 Rev. 1.0.3
tf = 100ns
ss
ss
0.6
4.6
Time (ms)
Load Transient Response Test Waveform
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4
TA = 25°C, CIN = 10µF, COUT = 40µF, L = 2.2µH, VIN = 5V, VOUT = 1.2V, unless otherwise noted.
Figure 4.
Start-up with 100mA Resistive Load
Figure 5.
Figure 6. Load Transient Response 1.5A to 100mA
Figure 8.
Figure 7. Load Transient Response 100mA to
1.5A
Output Voltage Regulation
© 2006 Fairchild Semiconductor Corporation
FAN2013 Rev. 1.0.3
Start-up with 2A Resistive Load
Figure 9.
FAN2013 — 2A Low-Voltage, Current-Mode Synchronous PWM Buck Regulator
Typical Performance Characteristics
Power Efficiency
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5
VIN
PG
REF
PG
COMP
FB
GND
UNDER VOLTAGE
LOCKOUT
IS
PVIN
CURRENT
SENSE
DIGITAL
SOFT START
FB
ERROR
AMP
LOGIC
CONTROL
COMP
MOSFET
DRIVER
SW
0.8V
GND
IS
OVER
VOLTAGE
COMP
OSC
SLOPE COMPENSATION
REF
FB
GND
Figure 10.
Block Diagram
Detailed Operation Description
The FAN2013 has an internal soft-start circuit that limits
the inrush current during start-up. This prevents
possible voltage drops of the input voltage and
eliminates the output voltage overshoot. The soft-start
is implemented as a digital circuit, increasing the switch
current in four steps to the P-channel current limit
(3.5A). Typical start-up time for a 40µF output capacitor
with a load current of 2.0A is 800µs.
The FAN2013 is a step-down pulse-width modulated
(PWM) current mode converter with a fixed switching
frequency of 1.3MHz. At the rising edge of each clock
cycle, the P-channel transistor is turned on until the
PWM comparator trips or the current limit is reached.
During the ON time, the inductor current ramps up and
is monitored by the internal current-mode control loop.
After a minimum dead time, the N-channel transistor is
turned ON and the inductor current ramps down. As the
clock cycle is completed, the N-channel switch is turned
OFF and the next clock cycle starts. The duty cycle is
given by the ratio of output voltage and input voltage.
The converter runs at minimum duty cycle when output
voltage is at minimum and input voltage is at maximum,
and at 100% duty cycle when the input voltage
approaches the output voltage, as described below.
Output Over-Voltage Protection
When output voltage, VOUT, reaches approximately 7%
above the nominal value, the device turns OFF the Pchannel switch and turns ON part of the N-channel
transistor with a built-in current limit of about 400mA.
When VOUT reaches the hysteresis of about 2%, the
device starts switching normally in closed loop. If output
voltage is pulled up by an external voltage source with a
current limit higher than typical 400mA, the output
voltage stays up at the external voltage source level.
100% Duty Cycle Operation
As the input voltage approaches the output voltage and
the duty cycle exceeds the typical 95%, the converter
turns the P-channel transistor continuously on. In this
mode, the output voltage is equal to the input voltage,
minus the voltage drop across the P-channel transistor:
VOUT = VIN – ILOAD x (RDS_ON + RL)
FAN2013 — 2A Low-Voltage, Current-Mode Synchronous PWM Buck Regulator
Block Diagram
The over-voltage protection is designed to limit the
output voltage excursion in case of a transient response
from full load to a minimum load.
(1)
Output Short-Circuit Protection
where
RDS_ON = P-channel switch on resistance
ILOAD = Output current
RL = Inductor DC resistance
The switch peak current is limited cycle by cycle to a
typical value of 3.5A. In the event of an output voltage
short circuit, the device operates with a frequency of
400kHz and minimum duty cycle, making the average
typical input current .45A.
UVLO and Soft Start
Thermal Shutdown
The internal voltage reference, VREF, and the IC remain
reset until VIN reaches the 3.7V UVLO threshold.
© 2006 Fairchild Semiconductor Corporation
FAN2013 Rev. 1.0.3
When the die temperature exceeds 150°C, a reset
occurs and remains in effect until the die cools to
130°C, when the circuit is allowed to restart.
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Setting the Output Voltage
PCB Layout Recommendations
The internal voltage reference is 0.8V. The output is
divided down by a voltage divider, R1 and R2 to the FB
pin. The output voltage is:
The inherently high peak currents and switching
frequency of power supplies require a careful PCB
layout design. For best results, use wide traces for highcurrent paths and place the input capacitor, the
inductor, and the output capacitor as close as possible
to the integrated circuit terminals. To minimize voltage
stress to the device resulting from ever-present
switching spikes, use an input bypass capacitor with low
ESR. Note that the peak amplitude of the switching
spikes depends upon the load current; the higher the
load current, the higher the switching spikes.
V
O UT
= V
REF
R
1 + -----1R
(2)
2
According to this equation, assuming desired output
voltage of 1.2V, and given R2 = 10KΩ as the
recommended resistance for any output voltage setting,
the calculated value of R1 is 5KΩ.
Inductor Selection
The resistor divider that sets the output voltage should
be routed away from the inductor to avoid RF coupling.
The ground plane at the bottom side of the PCB acts as
an electromagnetic shield to reduce EMI. The
recommended PCB layout is shown below in Figure 11.
The inductor parameters directly related to device
performance are saturation current and DC resistance.
The FAN2013 operates with a typical inductor value of
2.2µH. The lower the DC resistance, the higher the
efficiency. For saturation current, the inductor should be
rated higher than the maximum load current, plus half of
the inductor ripple current, calculated by:
1 – ( VO U T ⁄ VIN)
∆ IL = VO U T × ------------------------------------------L×f
(3)
where:
ΔIL = Inductor Ripple Current
f = Switching Frequency
L = Inductor Value
Recommended inductors are listed in Table1.
Table 1. Recommended Inductors
Inductor
Vendor
Value
Part Number
2.2µH
Coiltronics
SD25 2R2
2.2µH
Murata
LQH66SSN2R2M03
Capacitors Selection
Figure 11.
For best performances, a low-ESR input capacitor is
required. A ceramic capacitor of at least 10µF, placed
as close to the VIN and AGND pins as possible is
recommended.
Recommended PCB Layout
FAN2013 — 2A Low-Voltage, Current-Mode Synchronous PWM Buck Regulator
Applications Information
The output capacitor determines the output ripple and
the transient response. A minimum of 20µF output
capacitor is required for the FAN2013 to operate in
stable conditions.
Table 2. Recommended Capacitors
Capacitor
Value
Vendor
Taiyo Yuden
10µF
TDK
Murata
© 2006 Fairchild Semiconductor Corporation
FAN2013 Rev. 1.0.3
Part Number
JMK212BJ106MG
JMK316BJ106KL
C2012X5ROJ106K
C3216X5ROJ106M
GRM32ER61C106K
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FAN2013 — 2A Low-Voltage, Current-Mode Synchronous PWM Buck Regulator
Physical Dimensions
Figure 12.
3x3mm 6-Lead Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2006 Fairchild Semiconductor Corporation
FAN2013 Rev. 1.0.3
www.fairchildsemi.com
8
FAN2013 — 2A Low-Voltage, Current-Mode Synchronous PWM Buck Regulator
© 2006 Fairchild Semiconductor Corporation
FAN2013 Rev. 1.0.3
www.fairchildsemi.com
9
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