MLX81205/07 Features Microcontroller: MLX16-FX RISC CPU 16bit RISC CPU with 20MIPS and Power-Saving-Modes Co-processor for fast multiplication and division Flash and NVRAM memory with ECC In-circuit debug and emulation support Supported Bus Interfaces: LIN interface with integrated LIN transceiver supporting LIN 2.x, certified LIN protocol software provided by Melexis In-Module programming (Flash and NVRAM) via pin LIN using a special Melexis fast protocol PWM interface Motor Controller Patented algorithms for sensor-less 3-phase sine and trapezoidal motor control Phase voltage integration filter for BEMF voltage sensing at lowest speeds Position dependent phase inductance sensing via shunt current measurements at stand still and low to medium speeds Support of Star and Delta based motor configurations without the need for center star point Support of 3-phase switched reluctance motor control Voltage Regulator Direct powered from 12V board net with low voltage detection Operating voltage VS = 5V to 18V Internal voltage regulator with possibility to use external regulator transistor Very low standby current, < 50µA in sleep mode, wake-up possible via LIN or local sources Pre-Driver Pre-driver (~27 Rdson) for 3 N-FET half bridges with programmable Inter-Lock-Delay and slope control for optimal EMC and thermal performance during N-FET switching Monitoring of Drain-Source voltages of the N-FETs Periphery Full duplex SPI, Master/Slave, double-buffered, programmable speed, DMA access. Full duplex UART 4 independent 16 bit timer modules with capture and compare and additional software timer 3 programmable 12 bit PWM units with programmable frequencies 10 bit ADC converter (2µs conversion time) and DMA access On-chip temperature sensor with ±10K accuracy System-clock-independent fully integrated watchdog 40MHz clock from internal RC oscillator with PLL Optional crystal oscillator Load dump and brown out interrupt function Integrated shunt current amplifier with programmable gain Applications The MLX81205/07 are designed to control BLDC motors via external FET transistors for applications like oil pumps, water pumps, fuel pumps, blowers, compressors, and positioning actuators. 390108120502 Rev. 4.7 Page 1 of 18 Product Abstract 11/2/2015 MLX81205/07 Table of Contents 1. 2. 3. 4. Family Overview and Ordering Information ..................................................................... 3 Functional Diagram ......................................................................................................... 5 Pin Description ................................................................................................................ 6 Electrical Characteristics ................................................................................................. 7 4.1 4.2 Operating Conditions ....................................................................................................................................... 7 Absolute Maximum Ratings ............................................................................................................................. 7 5. Application Examples 5.1 5.2 5.3 Sensor-less BLDC Motor Control on the LIN bus or via PWM-Interface.......................................................... 9 Sensor-less BLDC Motor Control with LIN bus or via PWM Interface with reverse .......................................... polarity protection in the battery path ............................................................................................................ 11 Sensor based BLDC Motor Control ............................................................................................................... 12 6. Mechanical Specification ............................................................................................. 13 6.1 QFN packages .............................................................................................................................................. 13 6.1.1. 6.1.2. .................................................................................................. 9 QFN32_WF 5x5 (32 leads) ......................................................................................................................... 13 QFN48_WF 7x7 (48 leads) ......................................................................................................................... 14 6.2 6.3 TQFP package (48 leads) ............................................................................................................................. 14 Marking MLX81205/07 .................................................................................................................................. 15 7. Standard information regarding manufacturability of Melexis products .............................. with different soldering processes ................................................................................. 17 Disclaimer ..................................................................................................................... 18 8. 390108120502 Rev. 4.7 Page 2 of 18 Product Abstract 11/2/2015 MLX81205/07 1. Family Overview and Ordering Information MLX81205 MLX81207 Flash Memory [kByte] 32 32 RAM [kByte] 4 4 4x128 4x128 QFN32 QFN48 TQFP48 No Yes High side High side SPI No Yes UART Yes Yes 3 6 Support of sensor based BLDC motor control No Yes Bonded pins in package 32 37 NVRAM [Byte] 1 Package Support of active high side reverse polarity protection Current shunt measurement possibility Number of general purpose IO pins Pin compatibility Table 1 – Family Overview Order Code Temperature Range Package Delivery Remark MLX81205 LLW-BAD-000-RE -40 - 150 °C QFN32_WF 5x5 Reel QFN with wettable flanks MLX81207 LLW-BAD-000-RE -40 - 150 °C QFN48_WF 7x7 Reel QFN with wettable flanks MLX81207 LPF-BAD-000-TR -40 - 150 °C TQFP EP 48 7x7 Tray MLX81207 LPF-BAD-000-RE -40 - 150 °C TQFP EP 48 7x7 Reel Table 2 – Ordering Information 1 One page of 128 byte is only writable in test mode and reserved for Melexis calibration and test data 390108120502 Rev. 4.7 Page 3 of 18 Product Abstract 11/2/2015 MLX81205/07 Legend: MLX812xx LLW xxx 000 RE Delivery Form: RE = Reel, TR = Tray Option Code: 000 = Standard Firmware Version: Character [AA...ZZ] Silicon Version: Character [A...Z] Package Code: LW=QFN_WF, PF = TQFP EP Temperature Code: L= -40 to 150°C Product Name: xx = 05 or 07 390108120502 Rev. 4.7 Page 4 of 18 Product Abstract 11/2/2015 MLX81205/07 2. Functional Diagram RTG VDDA CLKO OSC1 RCOSC. Level shifter VS VDDD Supply Regulator XTAL OSC 8 bit DAC ADC Temp Div + MUX 10 Bit ADC fmain Interrrupt Controller IO3 Clock Independent Watchdog IO5 UART ...... Slope controlled Pre-Driver 16bit bitTimer Timer 16 16 bitTimer Timer Units with 16 bit Units with Units with Double Units with Double Double Capture Double Capture Capture Compare Capture Compare Compare Compare VDS monitor 12 Bit 12 Bit PWM Module 12 Bit PWM Module PWM Module ADC Motor Control Unit RAM PWMD Common Timer GNDA LINPHY Melexis Integrated LIN Protocol Boot loader GNDD GNDCAP MLX16-FX Core M M U CPU debugger LS0 U VDS monitor LS1 Slope controlled Pre-Driver VDS monitor Digital Watchdog HS0 CP1 Flash EEPROM CP0 Slope controlled Pre-Driver SPI SPI LIN VBAT_S2 Voltage Monitor IO1 IO4 VBAT_S1 POR ...... I/O Reg Reference Voltage fmain VS VREF ISENSH ISENSL TEMP VBAT_S1 VBAT_S2 GND_S1 GND_S2 U V W T PHASEINT IOHV IO1 ... IO9 IO2 VREF Divider / PLL Aux. Supply IOHV OSC2 HS1 V CP2 HS2 LS2 W T Test controller GNDDRV TI0 TI1 TO Figure 1 – Block Diagram Colour legend: Black: common for MLX81205 and MLX81207 Blue: additional pins or functionality for MLX81207 390108120502 Rev. 4.7 Page 5 of 18 Product Abstract 11/2/2015 MLX81205/07 3. Pin Description Name Type Function VS RTG VDDA VDDD GNDD GNDCAP GNDDRV GNDA LIN IOHV TI0 TI1 TO OSC1 OSC2 IO1 IO2 IO3 IO4 IO5 CLKO T VREF CP2 HS2 W LS2 CP1 HS1 V LS1 CP0 HS0 U LS0 VBAT_S1 VBAT_S2 P O P P GND GND GND GND HVIO HVIO I I O I O LVIO LVIO LVIO LVIO LVIO HVO HVI P HVIO HVIO HVI HVO HVIO HVIO HVI HVO HVIO HVIO HVI HVO HVI HVI Battery Supply 3.3V External MOS Gate Control 3.3V Supply 1.8V Regulator output Digital ground Digital ground Driver ground Analogue ground Connection to LIN bus or PWM interface General purpose IO pin Test input, debug interface Test input, debug interface Test output, debug interface Quartz interface input Quartz interface output General purpose IO pin (Low voltage 3.3V) General purpose IO pin (Low voltage 3.3V) General purpose IO pin (Low voltage 3.3V) General purpose IO pin (Low voltage 3.3V) General purpose IO pin (Low voltage 3.3V) Switch able 250kHz clock output to VREF level Reference input to BEMF sensing blocks Clamped 8V or 12V ref. voltage for bootstrap High side bootstrap capacitor driver 2 N-FET high side gate driver 2 Phase W input to HS2 buffer and BEMF sensing blocks N-FET low side gate driver 2 High side bootstrap capacitor driver 1 N-FET high side gate driver 1 Phase V input to HS1 buffer and BEMF sensing blocks N-FET low side gate driver 1 High side bootstrap capacitor driver 0 N-FET high side gate driver 0 Phase U input to HS0 buffer and BEMF sensing blocks N-FET low side gate driver 0 VS high side input for current sensing VS low side input for current sensing Pin count MLX81205 MLX81207 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 32 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 37 Table 3 – Pin Description MLX81205 / MLX81207 390108120502 Rev. 4.7 Page 6 of 18 Product Abstract 11/2/2015 MLX81205/07 4. Electrical Characteristics All voltages are referenced to ground (GND). Positive currents flow into the IC. The absolute maximum ratings given in table below are limiting values that do not lead to a permanent damage of the device but exceeding any of these limits may do so. Long term exposure to limiting values may affect the reliability of the device. Reliable operation of the MLX81205/07 is only specified within the limits shown in Table 4. 4.1 Operating Conditions Parameter Symbol min max VS 5.0 18 Tamb -40 IC supply voltage Operating ambient temperature +125 (+150) Unit V 2 °C Table 4 – Operating Conditions 4.2 Absolute Maximum Ratings Parameter Symbol T = 2 min VS IC supply voltage on pins VS, VBAT_S1, VBAT_S2 LIN Bus Condition min max -0.3 28 T < 500 ms 3 VS.tr1 ISO 7637-2 pulse 1 4 VS=13.5V, TA=(23 ± 5)°C VS.tr2 ISO 7637-2 pulse 2 4 VS=13.5V, TA=(23 ± 5)°C VS.tr3 ISO 7637-2 pulses 3A, 3B 4 VS=13.5V, TA=(23 ± 5)°C VS.tr5 45 -100 Unit V V +75 V -150 +100 V ISO 7637-2 pulses 5b 4 VS=13.5V, TA=(23 ± 5)°C +65 +87 V VLIN T<500ms -25 40 V VLIN.tr1 ISO 7637-2 pulse 1 5 VS=13.5V, TA=(23 ± 5)°C -100 VLIN.tr2 ISO 7637-2 pulse 2 5 VS=13.5V, TA=(23 ± 5)°C VLIN.tr3 ISO 7637-2 pulses 3A, 3B 6 VS=13.5V, TA=(23 ± 5)°C Maximum reverse current into any pin 7 +75 -150 +100 -10 +10 mA +10 mA Maximum sum of reverse currents into all pins 7 DC voltage on LVIO pins, OSC<2:1> -0.3 VDDA+0.3 V DC voltage on pins HV I/O -0.3 VS+0.3 V 2 3 4 5 6 7 With temperature applications at TA>125°C a reduction of chip internal power dissipation by using an external supply transistor is mandatory. The extended temperature range is only allowed for a limited period of time, a mission profile has to be agreed by Melexis as a mandatory part of the Part Submission Warrant (PSW) Only allowed, if FET drivers are disabled, i.e. the high-side driver must not be stressed with V(CP) > 45V ISO 7637 test pulses are applied to VS via a reverse polarity diode and >22μF blocking capacitor ISO 7637 test pulses are applied to LIN via a coupling capacitance of 1nF ISO 7637 test pulses are applied to LIN via a coupling capacitance of 100pF Excluding pins HS0, HS1, HS2, U, V, W, LS0, LS1, LS2. 390108120502 Rev. 4.7 Page 7 of 18 Product Abstract 11/2/2015 MLX81205/07 Parameter Symbol Condition min max Unit DC voltage on drivers supply pin VREF -0.3 18 V DC voltage on pin CLKO -0.3 VREF+0.3 V -0.5 8 VREF+0.3 V DC voltage on drivers control pins LS<2:0> DC voltage on drivers pins CP<2:0> Voltage on pins CP<2:0> must not exceed 45V. -0.3 V<U,V,W> + 13 V DC voltage on drivers pins HS<2:0> Voltage on pins HS<2:0> must not exceed 45V -0.5 9 10 VS + VREF V DC voltage on phases related pins U,V,W Voltage on pins U,V,W must not exceed 36V -0.5 9 10 VS+1.5 V DC voltage on phases related pin T Voltage on pin T must not exceed 36V -0.3 VS+1.5 V 4.5 V Positive dynamic disturbance on pin VBAT_S1 11 Vpdd Spdd > 2 V/µs ESD capability of pin LIN to GND ESDBUSHB Human body model 12 -6 +6 kV ESD capability of pin VS to GND ESDVSHB Human body model 12 -4 +4 kV ESD capability of any other pins ESDHB Human body model 12 -2 +2 kV ESD capability ay any pin ESDCDM Charge Device Model 13 -500 +500 V Maximum latch–up free current at any pin ILATCH -250 +250 mA Junction temperature Tvj +155 °C +150 °C Storage temperature Rthjc QFN32 14 Rthjc QFN48 14 2 Tstg -55 10 Rthjc 5 Rthjc TQFP48 14 5.5 Table 5 – Absolute Maximum Ratings 8 9 10 11 12 13 14 During short transient pulses smaller than 1us and while the LS driver is fully connecting the LS pin to GND (i.e. LSI_N_DRV[3:0]=0xF), the voltage on any LS<2:0> pin is allowed: -1V ≤ LS<2:0> ≤ -0.5: if the current flowing out of any LS<2:0> pin does not exceed 75mA. The sum of all currents flowing out of the LS pins during these conditions must not exceed 150mA During short transient pulses smaller than 1us, the voltage on any HS<2:0> pin and any U,V or W pin is allowed: -1V ≤ HS<2:0>, U,V,W ≤ -0.5: if the current flowing out of any pin HS<2:0>, U,V,W does not exceed 50mA During short transient pulses smaller than 1us, the sum of all currents flowing out of pins HS<2:0> and U,V,W with -1V < HS<2:0>, U,V,W <-0.5 must not exceed 75mA There might be ripple on the VBAT_S1 pin due to parasitic elements in the supply line. Positive voltage peaks with a slew rate larger than Spdd should be limited to Vpdd (see Datasheet). This only applies if the high side current sensor is switched on Equivalent to discharging a 100pF capacitor through a 1.5kΩ resistor conform to AEC-Q100-002 or ESDA/JEDEC JDS-001 ESD CDM Test confirm to AEC-Q100-011 or JEDEC22-C101 Simulated value for low conductance board (JEDEC) 390108120502 Rev. 4.7 Page 8 of 18 Product Abstract 11/2/2015 MLX81205/07 5. Application Examples 15 The following sections show typical application examples 5.1 Sensor-less BLDC Motor Control on the LIN bus or via PWM-Interface The below application example with MLX81205 realizes a sensor-less control of a BLDC motor via three external power N-FET half bridges, with only a few external components. The high side N-FET driver is built with a bootstrap output stage. Reverse polarity protection of the bridge is realized with an external power N-FET. An external temperature sensor is connected to the 10 bit ADC via pin IO1. The integrated window watchdog is monitoring application integrity. The communication interface can be either LIN or PWM interface. Pins LIN and IOHV can be used as wake-up sources and furthermore pin LIN will be also used to program the Flash memory. 15 All application examples are principal schematics only. Details need to be worked out for each application separately, depending on application requirements 390108120502 Rev. 4.7 Page 9 of 18 Product Abstract 11/2/2015 MLX81205/07 VREF VBAT CP2 CP1 VS CP0 RTG VCC3 VBAT_S1 SHUNT VDDA VBAT_S2 VPROT HS0 VDDD U U LS0 LIN / PWM LIN VPROT VCC3 MLX81205 IO1 IO2 HS1 V V LS1 VPROT IOHV OSC1 OSC2 HS2 W TI0 TI1 TO VBAT GNDA GNDD W LS2 U T GNDDRV V W LOW GND Figure 2 – Sensor-less BLDC Motor Control with MLX81205 The motor currents are measured by a shunt resistor in battery path. In case current exceeds the programmed threshold, the bridge can be switched off automatically without software interaction and in addition a software interrupt can be generated. The motor current can also be measured by the 10 bit ADC. The patented Melexis TruSense technology combines two methods to determine the rotor position: - The measurement of the induced BEMF voltage at medium and high speeds The measurement of position depending on coil inductance variations at stand-still and low speeds 390108120502 Rev. 4.7 Page 10 of 18 Product Abstract 11/2/2015 MLX81205/07 As a result TruSense allows operation of the motor in the widest dynamic speed range. The motor can be driven with block, trapezoidal or sine-wave currents. The motor start-up can be made independent of the load conditions according to the application requirements. In this example application the motor star point is not available. It is modelled with external resistors from the motor phases and connected to T input. Alternatively an artificial IC internal reference point can be chosen as shown in the block diagram of the MLX81205/07. 5.2 Sensor-less BLDC Motor Control with LIN bus or via PWM Interface with reverse polarity protection in the battery path In the following sample application MLX81207 has been selected in order to benefit from the external high side reverse polarity protection possibility. All other remarks from the previous application example remain valid. VBAT CLKO VS RTG VCC3 VBAT_S1 VDDA SHUNT VBAT_S2 VREF VDDD VPROT CP2 GNDCAP CP1 CP0 LIN / PWM HS0 LIN MLX81210 MLX81215 VCC3 U U LS0 VPROT MLX81207 IO1 HS1 IO2 IO3 IO4 IO5 V V LS1 VPROT IOHV OSC1 OSC2 TI0 TI1 TO GNDCAP GND HS2 W W LS2 U T GNDCAP GNDD GNDA GNDDRV V W Figure 3 – Typical Sensor-less BLDC Motor Control Application Example with MLX81207 390108120502 Rev. 4.7 Page 11 of 18 Product Abstract 11/2/2015 MLX81205/07 5.3 Sensor based BLDC Motor Control In sample application below, the chip MLX81207 is driving a BLDC motor with 3 Hall sensors. An external P-FET is used to generate the 3.3V supply with a higher current capability in order to keep the power dissipation outside of the MLX81207 IC. VBAT CLKO VS VHIGH VCC3 RTG VBAT_S1 VDDA VBAT_S2 SHUNT VREF VPROT CP2 VDDD CP1 GNDCAP CP0 VCC3 HS0 IO1 U U LIN / PWM LIN IO2 LS0 MLX81207 IO3 VPROT HS1 V V IOHV OSC1 LS1 VPROT OSC2 HS2 IO4 IO5 W W LS2 TI0 TI1 TO GNDCAP VCC3 T VCCHALL HALL1 HALL2 HALL3 GND GNDCAP GNDD GNDA GNDDRV GND Figure 4 – Typical Sensor based BLDC Motor Control Application Example with MLX81207 390108120502 Rev. 4.7 Page 12 of 18 Product Abstract 11/2/2015 MLX81205/07 6. Mechanical Specification 16 6.1 QFN packages Figure 5 - QFN Package Drawing 6.1.1. QFN32_WF 5x5 (32 leads) Symbol 17 A A1 A3 b D Min 0.80 0.00 Nom 0.90 0.02 0.20 0.25 5.00 3.60 5.00 3.60 0.50 0.40 Max 1.00 0.05 0.18 0.30 D2 E 3.50 3.70 E2 3.50 3.70 e L Tx Ty N 18 Nd 19 Ne 19 0.16 0.10 32 8 8 0.35 0.45 Table 6 – QFN32_WF 5x5 Package Dimensions 16 17 18 19 Dimensions and tolerances conform to ASME Y14.5M-1994 Dimensions in millimetres, angles in degrees N is the total number of terminals ND and NE refer to number of terminals on each D and E side respectively 390108120502 Rev. 4.7 Page 13 of 18 Product Abstract 11/2/2015 MLX81205/07 6.1.2. QFN48_WF 7x7 (48 leads) Symbol 17 A A1 Min 0.80 0 Nom 0.90 0.02 Max 1.00 A3 b D D2 0.18 0.25 0.20 0.05 E 5.00 7.00 0.30 5.10 E2 e 5.00 7.00 5.20 5.10 L Tx Ty N 18 Nd 19 Ne 19 0.165 0.100 48 12 12 0.40 0.50 5.20 0.50 0.60 Table 7 – QFN48_WF 7x7 Package Dimensions 6.2 TQFP package (48 leads) Min Nom Max A A1 A2 b b1 1.2 0 0.05 - 0.95 1.00 0.17 0.22 0.17 0.20 0.15 1.05 0.27 0.23 D 9.00 D1 7.00 D2 5.00 E 9.00 E1 7.00 E2 5.00 e 0.50 L 0.45 0.60 0.75 N 48 ccc ddd - - 0.08 0.08 Notes: 1. All Dimensioning and Tolerances conform to ASME Y14.5M-1994, Δ2. Datum Plane [-|-|-] located at Mould Parting Line and coincident with Lead, where Lead exists, plastic body at bottom of parting line. Δ3. Datum [A-B] and [-D-] to be determined at centreline between leads where leads exist, plastic body at datum plane [-|-|-] Δ4. To be determined at seating plane [-C-] Δ5. Dimensions D1 and E1 do not include Mould protrusion. Dimensions D1 and E1 do not include mould protrusion. Allowable mould protrusion is 0.254 mm on D1 and E1 dimensions. 6. 'N' is the total number of terminals Δ7. These dimensions to be determined at datum plane [-|-|-] 8. Package top dimensions are smaller than bottom dimensions and top of package will not overhang bottom of package. Δ9. Dimension b does not include dam bar protrusion, allowable dam bar protrusion shall be 0.08mm total in excess of the "b" dimension at maximum material condition, dam bar cannot be located on the lower radius of the foot. 10. Controlling dimension millimetre. 11. maximum allowable die thickness to be assembled in this package family is 0.38mm 12. This outline conforms to JEDEC publication 95 Registration MS-026, Variation ABA, ABC & ABD. Δ13. A1 is defined as the distance from the seating plane to the lowest point of the package body. Δ14. Dimension D2 and E2 represent the size of the exposed pad. The actual dimensions are specified in bonding diagram, and are independent from die size. 15. Exposed pad shall be coplanar with bottom of package within 0.05. 390108120502 Rev. 4.7 Page 14 of 18 Product Abstract 11/2/2015 MLX81205/07 Exposed pad need best possible contact to ground for exlectrical and thermal reasons Figure 6 – TQFP 7x7 Drawing 6.3 Marking MLX81205/07 MLX81207x zzzzzz Silicon Revision: Character [A...Z] Lot Number Assembly Date Code: Week number yywwxx Firmware Revision: Characters [AA...ZZ] 1 Assembly Date Code: Year 81205x zzzzzz Silicon Revision: Character [A...Z] Lot Number Assembly Date Code: Week number Firmware Revision: Characters [AA...ZZ] 1 yywwxx Assembly Date Code: Year Figure 7 – Marking Code 390108120502 Rev. 4.7 Page 15 of 18 Product Abstract 11/2/2015 MLX81205/07 HS0 VREF GNDDRV CP1 U VBAT_S2 VBAT_S1 VS CLKO GNDA RTG CP1 TO HS1 TI0 V TI1 N.C. N.C. N.C. U VBAT_S2 VBAT_S1 VS CLKO GNDA VDDA RTG VDDA IO5 N.C. V HS1 CP2 HS2 T W OSC1 GNDCAP VDDD VREF GNDDRV CP2 TO GNDD LIN VDDD IO4 W LS2 TI0 OSC2 LS2 MLX81207 TQFP48 IO3 HS2 LS1 TI1 LS1 IO2 T IO2 IO1 N.C. MLX81205 QFN32 only LS0 N.C. LS0 IOHV N.C. IOHV CP0 N.C. CP0 LIN N.C. LIN HS0 1 OSC2 1 IO1 GNDCAP N.C. N.C. OSC1 32 GNDD GNDD 48 U VBAT_S2 VS VBAT_S1 RTG GNDA VDDD VDDA The exposed pad is connected to IC substrate via conductive glue and must be connected to PCB ground. 48 N.C. HS0 1 N.C. CP0 IOHV LS0 IO1 LS1 IO2 LS2 MLX81207 QFN48 IO3 IO4 VREF GNDDRV W N.C. T N.C. N.C. N.C. N.C. HS2 N.C. CP2 N.C. N.C. V TI1 OSC1 HS1 TI0 OSC2 CP1 TO N.C. IO5 Figure 8 – MLX81205/07 Pins 390108120502 Rev. 4.7 Page 16 of 18 Product Abstract 11/2/2015 MLX81205/07 7. Standard information regarding manufacturability of products with different soldering processes Melexis Our products are classified and qualified regarding soldering technology, solder ability and moisture sensitivity level according to following test methods: Reflow Soldering SMDs (Surface Mount Devices) IPC/JEDEC J-STD-020 Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices (Classification reflow profiles according to table 5-2) EIA/JEDEC JESD22-A113 Preconditioning of Non-hermetic Surface Mount Devices Prior to Reliability Testing (Reflow profiles according to table 2) Wave Soldering SMDs (Surface Mount Devices) and THDs (Through Hole Devices) EN60749-20 Resistance of plastic- encapsulated SMDs to combined effect of moisture and soldering heat EIA/JEDEC JESD22-B106 and EN60749-15 Resistance to soldering temperature for through-hole mounted devices Iron Soldering THDs (Through Hole Devices) EN60749-15 Resistance to soldering temperature for through-hole mounted devices Solderability SMDs (Surface Mount Devices) and THDs (Through Hole Devices) EIA/JEDEC JESD22-B102 and EN60749-21 Solderability For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon with Melexis. The application of Wave Soldering for SMDs is allowed only after consulting Melexis regarding assurance of adhesive strength between device and board. Melexis recommends reviewing on our web site the General Guidelines soldering recommendation (http://www.melexis.com/Quality_soldering.aspx) as well as trim&form recommendations (http://www.melexis.com/Assets/Trim-and-form-recommendations-5565.aspx). Melexis is contributing to global environmental conservation by promoting lead free solutions. For more information on qualifications of RoHS compliant products (RoHS = European directive on the Restriction Of the use of certain Hazardous Substances) please visit the quality page on our website: http://www.melexis.com/quality.aspx 390108120502 Rev. 4.7 Page 17 of 18 Product Abstract 11/2/2015 MLX81205/07 8. Disclaimer Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering of technical or other services. © 2015 Melexis NV. All rights reserved. 390108120502 Rev. 4.7 Page 18 of 18 Product Abstract 11/2/2015