MK1493-01 PCI Clock Generator Description Features The MK1493-01 is a general purpose clock generator part that provides an integrated clocking solution for PCI /networking applications. It provides 8 individually programmable PCI clocks, 2 CPU clocks, additional fixed PCI clocks and a 25 MHz reference clock for LAN support. This part incorporates ICS’s newest clock technology, offering more robust features and functionality. Using a serially programmable SMBus interface, the MK1493-01 can select the output clock frequency, and enabling/disabling each individual output clock. • 8 PCI clocks at 25, 33, 50, 66.66 MHz individually pin selectableand serioal port slectable • • • • • • 2 CPU clocks at 100 MHz • • • • • 25 MHz crystal or clock input required 2 PCI clocks at 66.66 MHz 1 PCI clock @ 50 MHz 25 MHz reference clock SMBus Programming Power-up default frequency can be selected through FS inputs PCICLK cycle to cycle jitter <250ps CPUCLK cycle to cycle jitter <100ps Packaged in 48-pin (240mil) TSSOP Package Operating Voltage 3.3V + - 5% Block Diagram VDD 7 8 SCLK SDATA FS(0:7)_A 8 FS(0:7)_B 8 PLL Divider Buffer Circuits SMBus Programmable 2 2 PCICLK(0:7) Each PCI Output Clock Individually Programmable CPUCLK(100MHz) 66M CLK 50M CLK X1/CLK Clock Buffer/ Crystal Ocsillator 25 MHz REFCLK X2 7 GND MDS 1493-01 B 1 Revision 021204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK1493-01 PCI Clock Generator Pin Assignment FS3_A 1 48 FS4_A FS2_A FS1_A 2 3 47 46 FS5_A FS6_A FS0_A 4 45 FS7_A GND VDD 5 6 44 43 FS0_B FS1_B SCL SDA 7 8 42 41 PCICLK7 GND GND X1 9 10 40 39 VDD PCICLK6 X2 VDD 11 12 38 37 PCICLK5 PCICLK4 REF25 VDD 13 14 36 35 FS2_B VDD GND GND 15 16 34 33 GND CLK66A0 VDD CPUCLK0 17 18 32 31 CLK66A1 FS3_B CPUCLK1 FS7_B 19 20 30 29 VDD GND CLK50 21 28 PCICLK2 FS6_B FS5_B 22 23 27 26 PCICLK1 PCICLK0 FS4_B 24 25 PCICLK3 Pin Descriptions Pin Number Pin Name Pin Type 1 FS3_A Input Frequency select input pin for PCI CLK3 per per table 1. Pull up resistor. 2 FS2_A Input Frequency select input pin for PCI CLK2 per per table 1. Pull up resistor. 3 FS1_A Input Frequency select input pin for PCI CLK1 per per table 1. Pull up resistor. 4 FS0_A Input Frequency select input pin for PCI CLK0 per per table 1. Pull up resistor. 5 GND Power Connect to ground. 6 VDD Power Connect to +3.3 V. 7 SCL Input Clock pin for SMBus circuitry, 5 V tolerant. 8 SDA Input Data pin for SMBus circuitry, 5 V tolerant. 9 GND Power Connect to ground. 10 X1/ICLK Input Crystal connection/input clock. Connect to a 25 MHz fundamental mode crystal. 11 X2 XO 12 VDD Power MDS 1493-01 B Pin Description Crystal connection. Connect to a 25 MHz fundamental mode crystal or leave open. Connect to +3.3 V. 2 Revision 021204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK1493-01 PCI Clock Generator Pin Number Pin Name 13 REF25 14 VDD Power Connect to +3.3 V. 15 GND Power Connect to ground. 16 GND Power Connect to ground. 17 VDD Power Connect to +3.3 V. 18 CPUCLK0 Output 100 MHz CPU clock. 19 CPUCLK1 Output 100 MHz CPU clock. 20 FS7_B 21 CLK50 22 FS6_B Input Frequency select input pin for PCI CLK6 per per table 1. Pull-up resistor. 23 FS5_B Input Frequency select input pin for PCI CLK5 per per table 1. Pull-up resistor. 24 FS4_B Input Frequency select input pin for PCI CLK4 per per table 1. Pull-up resistor. 25 PCICLK3 Output PCI CLK3. 26 PCICLK0 Output PCI CLK0. 27 PCICLK1 Output PCI CLK1. 28 PCICLK2 Output PCI CLK2. 29 GND Power Connect to ground. 30 VDD Power Connect to +3.3 V. 31 FS3_B Input Frequency select input pin for PCI CLK3 per per table 1. Pull-up resistor. 32 CLK66A1 Output Additional PCI Clock (fixed frequency 66 MHz ). 33 CLK66A0 Output Additional PCI Clock (fixed frequency 66 MHz ). 34 GND Power Connect to ground. 35 VDD Power Connect to +3.3 V. 36 FS2_B Input Frequency select input pin for PCI CLK2 per per table 1. Pull-up resistor. 37 PCICLK4 Output PCI CLK4. 38 PCICLK5 Output PCI CLK5. 39 PCICLK6 Output PCI CLK6. 40 VDD Power Connect to +3.3 V. 41 GND Power Connect to ground. 42 PCICLK7 43 FS1_B Input Frequency select input pin for PCI CLK1 per per table 1. Pull-up resistor. 44 FS0_B Input Frequency select input pin for PCI CLK0 per per table 1. Pull-up resistor. 45 FS7_A Input Frequency select input pin for PCI CLK7 per per table 1. Pull-up resistor. 46 FS6_A Input Frequency select input pin for PCI CLK6 per per table 1. Pull-up resistor. 47 FS5_A Input Frequency select input pin for PCI CLK5 per per table 1. Pull-up resistor. 48 FS4_A Input Frequency select input pin for PCI CLK4 per per table 1. Pull-up resistor. MDS 1493-01 B Pin Type Pin Description Output Buffered reference output of 25 MHz crystal input. Input 1 of 4 frequency select input pin for PCI CLK7 per per table 1. Pull-up resistor. Output 50 MHz clock output. Output PCI CLK7. 3 Revision 021204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK1493-01 PCI Clock Generator Table 1. Frequency Select FS(0:7)_B FS(0:7)_A PCICLK(0:7) 0 0 25 MHz 0 1 33.33 MHz 1 0 50 MHz 1 1 66.66 MHz Power Groups Index Block Write Operation Description Pin Number VDD GND 12 9 Ref, Crystal Osc Power supply 30, 40 29, 41 PCICLK 35 34 PCI 66 clocks 6 5 SCLK 17 16 CPU Clocks(100MHz) 14 15 PLL ICS (Slave/Receiver) Controller (Host) T starT bit Slave Address D2 (H) WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK General I2C Serial Interface Information O O • • • • Controller (host) sends a start bit Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the beginning byte location = N ICS clock will acknowldege Controller (host) starts sending Byte N through Byte N+X-1(note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit MDS 1493-01 B O O O How to Write: • • • • X Byte O 4 Byte N + X - 1 ACK P stoP bit Revision 021204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK1493-01 PCI Clock Generator How to Read: • • • • • • • • • • • • • • Controller (host) will send a start bit Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the beginning byte location = N ICS clock will acknowldege Controller (host) will send a separate start bit Controller (host) sends the read address D3 (H) ICS clock will acknowldege ICS clock will send the data byte count = X ICS clock sends Byte N+X-1 ICS clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation ICS (Slave/Receiver) Controller (Host) T starT bit Slave Address D2 (H) WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address D3 (H) RD ReaD ACK Data Byte Count=X ACK Beginning Byte N ACK X Byte O O O O O O Byte N + X - 1 N Not P stoP bit SMBus Table 2: Read-Back Register Name Control Function FS vs. SMBus prog HW/SW select Type 0 1 PWD RW HW SW 0 Byte 0 Pin # Bit 7 - Bit 6 - Bit 5 - RESERVED 0 Bit 4 - RESERVED 0 Bit 3 - RESERVED 0 Bit 2 - Bit 1 - Bit 0 - MDS 1493-01 B RESERVED 0 0 Frequency Selection See Frequency table 3 0 0 5 Revision 021204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK1493-01 PCI Clock Generator SMBus Table 2: Output Control Register Byte 1 Pin # Name Control Function Type 0 1 PWD Bit 7 40 PCICLK7 Output Control RW Disable Enable 1 Bit 6 39 PCICLK6 Output Control RW Disable Enable 1 Bit 5 38 PCICLK5 Output Control RW Disable Enable 1 Bit 4 37 PCICLK4 Output Control RW Disable Enable 1 Bit 3 31 PCICLK3 Output Control RW Disable Enable 1 Bit 2 28 PCICLK2 Output Control RW Disable Enable 1 Bit 1 27 PCICLK1 Output Control RW Disable Enable 1 Bit 0 26 PCICLK0 Output Control RW Disable Enable 1 SMBus Table 2: Output Control Register Name Control Function Type 0 1 PWD Byte 2 Pin # Bit 7 - RESERVED 0 Bit 6 - RESERVED 0 Bit 5 32 CLK66A1 Output Control RW Disable Enable 0 Bit 4 33 CLK66A0 Output Control RW Disable Enable 1 Bit 3 12 REF25 Output Control RW Disable Enable 0 Bit 2 19 CPUCLK1 Output Control RW Disable Enable 1 Bit 1 18 CPUCLK0 Output Control RW Disable Enable 1 Bit 0 20 CLK50 Output Control RW Disable Enable 1 SMBus Table 2: Frequency Control Register Byte 3 Pin # Control Function Type Bit 7 4 FS0_A RW X Bit 6 44 FS0_B RW X Bit 5 3 FS1_A RW X Bit 4 43 FS1_B RW Bit 3 2 FS2_A RW Bit 2 36 FS2_B RW X Bit 1 1 FS3_A RW X Bit 0 31 FS3_B RW X MDS 1493-01 B 0 1 PWD X See Frequency Table 1 6 X Revision 021204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK1493-01 PCI Clock Generator SMBus Table 2: Frequency Control Register Byte 4 Pin # Control Function Type 0 1 PWD Bit 7 48 FS4_A RW X Bit 6 24 FS4_B RW X Bit 5 47 FS5_A RW X Bit 4 23 FS5_B RW X Bit 3 46 FS6_A RW Bit 2 22 FS6_B RW X Bit 1 45 FS7_A RW X Bit 0 20 FS7_B RW X Control Function Type Bit 7 RESERVED - Bit 6 RESERVED - 0 Bit 5 RESERVED - 0 Bit 4 RESERVED - 0 Bit 3 RESERVED - 0 Bit 2 RESERVED - 0 Bit 1 RESERVED - 0 Bit 0 RESERVED - 0 See Frequency Table 1 X SMBus Table 2: Reserved Byte 5 Pin # 0 1 RESERVED PWD 0 SMBus Table 2: Reserved Byte 6 Pin # Control Function Type 0 1 Bit 7 RESERVED - Bit 6 RESERVED - 0 Bit 5 RESERVED - 0 Bit 4 RESERVED - 0 Bit 3 RESERVED - 1 Bit 2 RESERVED - 0 Bit 1 RESERVED - 0 Bit 0 RESERVED - 0 MDS 1493-01 B RESERVED PWD 7 0 Revision 021204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK1493-01 PCI Clock Generator MBus Table 2: Vendor and Revision ID Register Byte 7 Pin # Control Function Type 0 1 PWD Bit 7 RID3 R Bit 6 RID2 R REVISION ID 0 0 Bit 5 RID1 R 0 Bit 4 RID0 R 0 Bit 3 VID3 R Bit 2 VID2 R 0 Bit 1 VID1 R 0 Bit 0 VID0 R 1 VENDOR ID 0 MBus Table 2: Byte Count Register Control Function Type Bit 7 BC7 RW Bit 6 BC6 RW Bit 5 BC5 RW Bit 4 BC4 RW Bit 3 BC3 RW 1 Bit 2 BC2 RW 0 Bit 1 BC1 RW 0 Bit 0 BC0 RW 0 Byte 8 Pin # 0 1 PWD 0 Writing to this Register will confirm how many bytes will be read back, default 08=8 bytes 0 0 0 Tabel 3. Frequency Selection through SMBus (Byte 0) Bit 2 Bit 1 Bit 0 CPUCLK1,0 (MHz) 0 0 0 100.00 50.00 66.66 nominal 0 0 1 105.00 nominal + 5% nominal + 5% nominal + 5% 0 1 0 110.00 nominal + 10% nominal + 10% nominal + 10% 0 1 1 95.00 nominal - 5% nominal - 5% nominal - 5% 1 0 0 90.00 nominal - 10% nominal - 10% nominal - 10% MDS 1493-01 B CLK50 (MHz) 8 CLK66A1,A0 (MHz) PCICLK (MHz) Revision 021204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK1493-01 PCI Clock Generator Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK1493-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Item Rating Supply Voltage, VDD 5.5 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 260°C Parameter Min. Ambient Operating Temperature Typ. 0 Power Supply Voltage (measured in respect to GND) +3.15 3.3 Max. Units +70 °C +3.45 V DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V+-5%, Ambient Temperature 0 to +70°C Parameter Symbol Conditions Min. Typ. Max. Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN=VDD -5 Input Low Current IIL1 VIN=0V, SDA, SCL inputs with no pull-up resistors. -5 µA IIL2 VIN=0V, All other inputs with pull-up resistors -200 µA Operating Supply Current IDD CL = Full load 350 mA Input Frequency FIN Note 3 25 MHz Pin Inductance LPIN Note 1 MDS 1493-01 B 2 Units 9 V 0.8 V 5 µA 7 nH Revision 021204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK1493-01 PCI Clock Generator Parameter Input Capacitance Note 1 CLK Stabilization Symbol Max. Units Logic inputs 5 pF COUT Output pin capacitance 6 pF CINX X1 and X2 pins 5 pF CIN Conditions Min. Typ. TSTAB From VDD Power-up 3 ms Note 2 Note 1: Guaranteed by design, not 100% tested in production. Note 2: See timing diagrams for timing requirements. Note 3: Input frequency should be measured at the REF output pin and tuned to ideal 25 MHz to meet ppm frequency accuracy on PLL outputs. Electrical Characteristics - CPUCLK Unless stated otherwise, VDD = 3.3 V+-5%, CL=20 pf, Ambient Temperature 0 to +70° C Parameter Symbol Conditions Min. Typ. Max. Units Output Frequency FO1 100 Output Impedance RDSP VO = VDD*(0.5) Note 1 12 Output High Voltage VOH IOH = -12 mA, Note 1 2.4 Output Low Voltage VOL IOL = 12 mA, Note 1 Output High Current IOH VOH@MIN = 2.0 V, Note 1 Output Low Current IOL VOL@MAX = 0.8 V Note 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V, Note 1 1.2 1.7 ns Fall Time tf1 VOH = 2.4 V, VOL = 0.8 V, Note 1 1.2 1.7 ns Duty Cycle dt1 VT = 1.5 V 50 55 % Output to Output Skew tsk1 VT = 1.5 V 175 ps 100 ps Cycle to Cycle Jitter MHz 55 V 0.3 0.4 V -19 mA 19 45 VT = 1.5 V Ω mA 50 Note 1: Guaranteed by design, not 100% tested in production Electrical Characteristics - CLK50, CLK66A0 & CLK66A1 Unless stated otherwise, VDD = 3.3 V+-5%, CL= 20 pf, Ambient Temperature 0 to +70° C Parameter Symbol Conditions Min. Output Frequency FO1 Output Impedance RDSP VO = VDD*(0.5) Note 1 12 Output High Voltage VOH IOH = -12 mA, Note 1 2.4 MDS 1493-01 B Typ. Max. Units 50&66 10 MHz 55 Ω V Revision 021204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK1493-01 PCI Clock Generator Parameter Symbol Conditions Min. Typ. Max. Units Output Low Voltage VOL IOL = 12 mA, Note 1 Output High Current IOH VOH@MIN = 2.0 V, Note 1 Output Low Current IOL VOH@MAX = 0.8 V Note 1 Rise Time tr1 VOL = 0.4V, VOH = 2.4 V, Note 1 1.2 1.7 ns Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V, Note 1 1.2 1.7 ns 50 55 % 0.3 0.4 V -19 mA 19 mA Duty Cycle VT = 1.5 V Output to Output Skew (CLK66A0, A1) VT = 1.5 V 175 ps Cycle to Cycle Jitter VT = 1.5 V 250 ps 45 Note 1: Guaranteed by design, not 100% tested in production Electrical Characteristics - PCICLK Unless stated otherwise, VDD = 3.3 V+-5%, CL=30 pf, Ambient Temperature 0 to +70° C Parameter Symbol Conditions Min. FS0 Typ. Max. Units Output Frequency FO1 25 MHz Output Impedance RDSP VO = VDD*(0.5) Note 1 12 Output High Voltage VOH IOH = -1 mA, Note 1 2.4 Output Low Voltage VOL IOL = 1 mA, Note 1 Output High Current IOH VOH@MIN = 2.0 V, Note 1 -33 mA Output Low Current IOL VOL@MAX = 0.8 V Note 1 30 mA Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V, Note 1 1.7 2.4 ns Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V, Note 1 1.7 2.4 ns 50 55 % 55 V 0.55 45 Ω V Duty Cycle VT = 1.5 V Output to Output Skew VT = 1.5 V 250 ps Cycle to Cycle Jitter VT = 1.5 V 250 ps Note 1: Guaranteed by design, not 100% tested in production MDS 1493-01 B 11 Revision 021204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK1493-01 PCI Clock Generator Electrical Characteristics - 25 MHz Reference Unless stated otherwise, VDD = 3.3 V+-5%, CL=20 pf, VDD = 3.3 V, Ambient Temperature 0 to +70° C Parameter Symbol Conditions Min. Typ. Max. Units Output Frequency FO1 25 Output Impedance RDSP VO = VDD*(0.5) Note 1 20 Output High Voltage VOH IOH = -1 mA, Note 1 2.4 Output Low Voltage VOL IOL = 1 mA, Note 1 Output High Current IOH VOH@MIN = 1.0 V, VOH@MAX = 3.135 V Note 1 -29 mA Output Low Current IOL VOL@MAX = 0.8 V Note 1 29 mA Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V, Note 1 1.2 1.7 ns Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V, Note 1 1.2 1.7 ns 50 55 % 500 ps Duty Cycle VT = 1.5 V Jitter Cycle to Cycle VT = 1.5 V MHz 60 V 0.4 45 Ω V Note 1: Guaranteed by design, not 100% tested in production MDS 1493-01 B 12 Revision 021204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK1493-01 PCI Clock Generator Package Outline and Package Dimensions (48-pin TSSOP, 240 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 c N L E1 INDEX AREA E 1 2 α D 6.10 mm. Body, 0.40 mm. Pitch TSSOP (240 mil) (16 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONSCOMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.13 0.23 .005 .009 c 0.09 0.20 .0035 .008 D 12.40 12.60 0.488 0.496 E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 0.5 BASIC 0.02 BASIC e A A2 A1 -Ce SEATING PLANE b aaa C Ordering Information Part / Order Number Marking Shipping packaging Package Temperature MK1493-01G MK1493-01GTR MK1493-01G MK1493-01G Tubes Tape and Reel 48-pin TSSOP 48-pin TSSOP 0 to +70° C 0 to +70° C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 1493-01 B 13 Revision 021204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com