AD AD9430BSV-170 12-bit, 170 msps 3.3v a/d converter Datasheet

PRELIMINARY TECHNICAL DATA
a
12-Bit, 170 MSPS
3.3V A/D Converter
Preliminary Technical Data
AD9430
PRODUCT DESCRIPTION
The AD9430 is a 12-bit monolithic sampling analog–to–
digital converter with an on–chip track–and–hold circuit and
is optimized for low cost, low power, small size and ease of
use. The product operates up to 170 Msps conversion rate
and is optimized for outstanding dynamic performance in
wideband carrier systems.
FEATURES
SNR = 65dB @ Fin up to 65MHz at 170Msps
ENOB of 10.3 @ Fin up to 65MHz at 170 Msps (-1dBFs)
SFDR = -80dBc @ Fin up to 65MHz at 170Msps (-1dBFs)
Excellent Linearity:
- DNL = +/- 1 lsb (typ)
- INL = +/- 1.5 lsb (typ)
Two Output Data options
- Demultiplexed 3.3V CMOS outputs each at 85 Msps
- LVDS at 170Msps
700 MHz Full Power Analog Bandwidth
On–chip reference and track/hol d
Power dissipation = 1.25W typical at 170Msps
1.5V Input voltage range
+3.3V Supply Operation
Output data format option
Data Sync input and Data Clock output provided
Interleaved or parallel data output option (CMOS)
Clock Duty Cycle Stabilizer.
The ADC requires a +3.3V power supply and a differential
encode clock for full performance operation. No external
reference or driver components are required for many
applications. The digital outputs are TTL/CMOS or LVDS
compatible. Separate output power supply pins support
interfacing with 3.3V CMOS logic.
An output data format select option of two’s complement or
offset binary is supported. In CMOS mode two output buses
support demultiplexed data up to 85 Msps rates. A data sync
input is supported for proper output data port alignment and
a data clock output is available for proper output data timing.
Fabricated on an advanced BiCMOS process, the AD9430 is
available in a 100 pin surface mount plastic package (100
TQFP ePAD) specified over the industrial temperature range
(–40°C to +85°C).
APPLICATIONS
Wireless and Wired Broadband Communications
- Wideband carrier frequency systems
- Cable Reverse Path
Communications Test Equipment
Radar and Satellite sub-systems
Power Amplifier Linearization
SENSE
AGND
DrGND
DrVDD AV DD
Scaleable
Reference
AD9430
AIN+
Track &
Hold
AIN-
VREF
ADC
12-bit
Pipeline
Core
Data(24), OR(2)
LVDS
Outputs
12
CMOS
Outputs
DS+
A port
Data(12), OR(1)
B port
Data(12), OR(1)
DS-
ENC+
Clock
Management
ENC-
Select CMOS or LVDS
DCO+
DCOS1
S2
S4
S5
AD9430 FUNCTIONAL BLOCK DIAGRAM
REV. PrG 4/01/2002
Information furnished by Analog Devices is believed to be accurate and
reliable.However,no responsibility is assumed by Analog Devices for its use,nor
for any infringements of patents or other rights of third parties that may result from
its use.No license is granted by implication or otherwise under any patent or
patent rights of Analog Devices.
One Technology Way,P.O.Box 9106,Norwood,MA 02062-9106,U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703
© Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
AD9430
DC SPECIFICATIONS (AVDD=
DrVDD = 3.3V; TMIN = -40°C, TMAX = +85°C, Fin = -0.5dBFS, 1.235V External
reference, LVDS Output Mode)
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
POWER SUPPLY REJECTION
REFERENCE OUT (VREF)
ANALOG INPUTS (AIN, AIN )
Input Voltage Range (AIN– AIN )1
Input Common Mode Voltage
Input Resistance
Input Capacitance
POWER SUPPLY
Supply Voltages
AVDD
DrVDD
Supply Current
I ANALOG (AVDD= 3.3V) 2
I DIGITAL (DrVDD = 3.3V) 2
POWER CONSUMPTION3
Temp
Test
Level
AD9430BSV-170
Min
Typ
Max
12
Units
Bits
Full
25°C
25°C
25°C
25°C
I
I
I
I
I
Guaranteed
tbd
tbd
+/- .3
+/- .5
mV
% FS
LSB
LSB
Full
Full
Full
Full
V
V
V
V
tbd
tbd
± tbd
1.235
ppm/°C
ppm/°C
mV/V
V
Full
Full
Full
Full
V
V
V
V
± .768
2.8
3
5
V
V
kΩ
pF
Full
Full
V
V
Full
Full
Full
V
V
V
3.0
3.0
3.3
3.3
V
V
3.6
3.6
mA
mA
W
335
55
1.29
NOTES
1
Nominal Differential Full Scale = .766 V * 2 = 1.53 Vp-p differential for S5 = 0; Nominal Differential Full Scale = .766 Vp-p d ifferential for S5 = 1 (see Fig. X)
2 IAVDD and IDrVDD are measured with an analog input of 10.3MHz, -0.5dBFs, sine wave, rated Encode rate and in LVDS output mode. See Typical Performance
Characteristics and Applications section for IDrVDD. 3 Power Consumption is measured with a DC input at rated Encode rate in LVDS output mode
(AVDD= 3.3V, DrVDD = 3.3V; TMIN = -40°°C, TMAX = +85°°C)
Test
AD9430BSV-170
Temp Level
Min
Typ
Max
Units
DIGITAL SPECIFICATIONS
Parameter (Conditions)
ENCODE AND DATA SYNC
INPUTS (ENC, ENC , DS, DS/ )
Differential Input Voltage 1
Encode Common Mode Voltage
Input Resistance
Input Capacitance
LOGIC INPUTS ( S1,S2,S4,S5 )
Logic ‘1’ Voltage
Logic ‘0’ Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUTS (Demux Mode)
Logic “1” Voltage2
Logic “0” Voltage2
LOGIC OUTPUTS (LVDS Mode)2,3
VOD Differential Output Voltage
VOS Output Offset Voltage
Output Coding
NOTES
1.5
V
V
5.5
4
kΩ
pF
0.2
Full
Full
IV
IV
Full
Full
IV
IV
Full
Full
Full
Full
IV
IV
IV
IV
2.0
Full
Full
IV
IV
DrVDD-0.05
Full
Full
Full
IV
IV
IV
247
454
1.125
1.375
Two’s Comp or Binary
.8
30
4
0.05
1All AC specifications tested by driving ENCODE and ENCODE differentially
Digital Output Logic Levels: DrVDD=
2
3.3V, CLOAD = 5pF.
3
V
V
mV
V
| ENCODE - ENCODE |
LVDS Rl=100 ohms,
-2-
V
V
kΩ
pF
> 200mV
LVDS Output Swing Set Resistor = 3.7K
4/01/2002 REV. PrG
PRELIMINARY TECHNICAL DATA
AD9430
AC SPECIFICATIONS1
(AVDD= 3.3 V, DrVDD = 3.3V; ENCODE = Maximum Conversion Rate ; TMIN = -40°C, TMAX
= +85°C, Internal voltage reference, LVDS Output Mode )
Test
AD9430BSV-170
Parameter (Conditions)
Temp
Level
Min
Typ
Max
Units
SNR
dB
65
Analog Input
10 MHz
I
25°C
dB
65
@ -0.5dBFS
65 MHz
I
25°C
dB
65
100 MHz
V
25°C
dB
64
240 MHz
V
25°C
SINAD
dB
65
Analog Input
10 MHz
I
25°C
dB
65
@ -0.5dBFS
65 MHz
I
25°C
dB
64.5
100 MHz
V
25°C
dB
60
240 MHz
V
25°C
nd
rd
Worst Harmonic (2 or 3 )
dBc
-85
Analog Input
10 MHz
I
25°C
dBc
-80
@ -0.5dBFS
65 MHz
I
25°C
dBc
-77
100 MHz
V
25°C
dBc
-63
240 MHz
V
25°C
th
Worst Harmonic (4 or higher)
dBc
-87
Analog Input
10 MHz
I
25°C
dBc
-87
@ -0.5dBFS
65 MHz
I
25°C
dBc
-77
100 MHz
V
25°C
dBc
-63
240 MHz
V
25°C
2
Two-tone IMD
F1, F2 @ -7 dBFS
Full
V
-75
dBc
Analog Input Bandwidth
V
700
MHz
25°C
NOTES
1
All AC specifications tested by driving ENCODE and ENCODE differentially.
2 F1 = 31.5 MHz, F2 = 32.5 MHz
SWITCHING SPECIFICATIONS (AVDD= 3.3 V, DrVDD = 3.3V; ENCODE = Maximum Conversion Rate ;
TMIN = -40°C, TMAX = +85°C )
Test
AD9430BSV-170
Parameter (Conditions)
Temp
Level
Min
Typ
Max
Units
MSPS
170
I
Maximum Conversion Rate1
Full
MSPS
40
V
Minimum Conversion Rate1
Full
nS
2
V
Encode Pulse Width High (tEH)1
Full
nS
2
V
Encode Pulse Width Low (tEL)1
Full
nS
.5
IV
Full
DS Input Setup Time (tSDS) 2
nS
1.5
IV
Full
DS Input Hold Time (tHDS) 2
NOTES
1
All AC specifications tested by driving ENCODE and ENCODE differentially, LVDS Mode.
2 DS inputs used in CMOS Mode only.
REV. PrG 4/01/2002
-3-
PRELIMINARY TECHNICAL DATA
AD9430
SWITCHING SPECIFICATIONS (cont’d)
Parameter
OUTPUT Parameters in Demux Mode
Valid Time (tV)
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DCO Propagation Delay (tCPD)
Data to DCO Skew (tPD – tCPD)
Interleaved Mode (A, B Latency)
Parallel Mode (A, B Latency)
OUTPUT Parameters in LVDS Mode
Valid Time (tV)
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DCO Propagation Delay (tCPD)
Data to DCO Skew (tPD – tCPD)
Pipeline Latency
Aperture Delay (tA)
Aperture Uncertainty (Jitter, t J)
Temp
Test
Level
AD9430BSV-170
Min
Typ Max
Units
Full
Full
25°C
25°C
Full
Full
Full
Full
IV
IV
V
V
VI
IV
VI
VI
tbd
3.8
1
1
3.8
0
14/14
14/15
ns
ns
ns
ns
ns
ns
Cycles
Cycles
Full
Full
25°C
25°C
Full
Full
Full
25°C
25°C
IV
I
V
V
VI
IV
VI
2.0
1.8
V
V
3.2
.5
.5
2.7
.5
14
1.2
0.25
4.3
3.8
ns
ns
ns
ns
ns
ns
Cycles
ps
ps rms
Measured Preliminary Performance : FFT 65MHz Ain at 170MSPS
-4-
4/01/2002 REV. PrG
PRELIMINARY TECHNICAL DATA
AD9430
AD9430 Timing Diagram
REV. PrG 4/01/2002
-5-
PRELIMINARY TECHNICAL DATA
AD9430
EXPLANATION OF TEST LEVELS
Test Level
I 100% production tested.
II 100% production tested at 25C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI 100% production tested at 25C; guaranteed by design
and characterization testing for industrial temperature
range; 100% production tested at temperature extremes
for military devices.
ABSOLUTE MAXIMUM RATINGS
AVDD, DRVDD.. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
Analog Inputs . . . . . . . . . . .. . .. . . –0.5 V to AVDD + 0.5 V
Digital Inputs . . .. . . . . . . . .. . . .. –0.5 V to DRVDD + 0.5 V
REFIN Inputs . . . . . . . . . . . . . . . . –0.5 V to AVDD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . ... . . . . . –55C to +125C
Storage Temperature . . . . . . . . . . . . . ... . . . . –65C to +150C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . ..150C
θJA2 . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . 25C/W, 32C/W
NOTES
1 Stresses above those listed under Absolute Maximum Ratings may
cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions outside of those
indicated in the operation sections of this specification is not implied.
Exposure to absolute maximum ratings for extended periods may affect
device reliability.
2 Typical θJA = 32C/W (heat slug not soldered), Typical θJA =
25C/W (heat slug soldered), for multilayer board in still air.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9430 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality .
ORDERING GUIDE
Model
AD9430BSV-170
AD9430/PCB-CMOS
S1
(Data
Format
Select) 1
1
0
X
X
X
X
X
S2
(LVDS/CMOS
Output Mode
Select )
X
X
0
0
1
X
X
Temperature Range
–40°C to +85°C
Package Option
TQFP–100
+25°C
Evaluatio n Board
(CMOS Mode)
Table 1. AD9430 Output Select Coding
S4
S5
Mode
(Select
(Full Scale
Interleaved or
Adjust)
Parallel Mode) 2
X
X
2’s Complement
X
X
Offset Binary
1
X
Dual Mode CMOS Interleaved
0
X
Dual Mode CMOS Parallel
X
X
LVDS Mode
X
1
Full Scale -> .766 Vpp differential
1.533 Vpp Single- Ended
X
0
Full Scale -> 1.533 Vpp differential
Notes:
1
X = Don’t Care
S1-S5 all have 30K resistive pulldowns on chip
2
In interleaved mode output data on port A is offset from output data changes on port B by ½ output clock cycle.
Interleaved mode
Parallel Mode
-6-
4/01/2002 REV. PrG
PRELIMINARY TECHNICAL DATA
AD9430
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
AGND
AGND
AVDD
AVDD
AVDD
AGND
AGND
OR_T
OR_C
DRVDD
DRGND
D11_T
D11_C
D10_T
D10_C
D9_T
D9_C
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AGND
(MSB)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
S5
DNC
S4
AGND
S2
S1
LVDSBIAS
AVDD
AGND
SENSE
AD9430
LVDS PINOUT
TOP VIEW
(Not to Scale)
DNC
DRVDD
DRGND
D0_C
D0_T
DNC
DNC
DNC
AGND
AVDD
AVDD
AVDD
AGND
AGND
GND
AVDD
AVDD
AGND
ENC
ENC
AGND
AVDD
AVDD
AGND
DNC
42
43
44
45
46
47
48
49
50
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
VREF
AGND
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
AIN
AIN
AGND
AVDD
AGND
75 DRVDD
74 DRGND
73 D8_T
72 D8_C
71 D7_T
70 D7_C
69 D6_T
68 D6_C
67 DRGND
66 D5_T
65 D5_C
64 DCO
63 DCO
62 DRVDD
61 DRGND
60 D4_T
59 D4_C
58 D3_T
57 D3_C
56 D2_T
55 D2_C
54 DRVDD
53 DRGND
52 D1_T
51 D1_C
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
AGND
AGND
AVDD
AVDD
AVDD
AGND
AGND
OR_A
DA11 (MSB)
DRVDD
DRGND
DA10
DA9
DA8
DA7
DA6
DA5
AD9430 LVDS Mode Pinout
AD9430
CMOS PINOUT
TOP VIEW
(Not to Scale)
17
18
19
20
21
22
23
24
25
AGND
AVDD
AVDD
AVDD
AGND
AGND
DS
DS
AVDD
AGND
ENC
ENC
AGND
AVDD
AVDD
AGND
DNC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
VREF
AGND
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
AIN
AIN
AGND
AVDD
AGND
75 DRVDD
74 DRGND
73 DA4
72 DA3
71 DA2
70 DA1
69 DA0
68 DNC
67 DRGND
66 DNC
65 DNC
64 DCO
63 DCO
62 DRVDD
61 DRGND
60 OR_B
59 DB11 (MSB)
58 DB10
57 DB9
56 DB8
55 DB7
54 DRVDD
53 DRGND
52 DB6
51 DB5
42
43
44
45
DB2 46
DRVDD 47
DRGND 48
DB3 49
DB4 50
DNC
AVDD
AGND
SENSE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DNC
DB0
DB1
S5
DNC
S4
AGND
S2
S1
AD9430 CMOS Dual Mode Pinout
REV. PrG 4/01/2002
-7-
PRELIMINARY TECHNICAL DATA
AD9430
PIN FUNCTION DESCRIPTIONS (CMOS mode)
CMOS Mode
Function in CMOS Mode
Name
Pin Number
2,7,42,43,65,66,68
1
DNC
S5
Do not connect
Full Scale Adjust pin : ‘1’ sets FS =.766 Vpp differential,
3
S4
5
6
8,14,15,18,19,24,27,28,29,34,
39,40,88,89,90,94,95,98,99
4,9,12,13,16,17,20,23,25,26,3
0,31,35,38,41,86,87,91,92,93,
96,97,100
10
11
21
22
32
S2
S1
AVDD
Interlaced or parallel output mode. (only in Dual Port mode
operation) HIGH = data arrives in channel A at falling edge of clock
and data arrives in channel A at rising edge of clock. LOW = data
arrives in channels A and B at rising edge of clock.
Output Mode select. Low = Dual Port, CMOS; High = LVDS
Data format select. Low = Binary, High = Two’s compliment
3.3V analog supply. (3.0V to 3.6V)
AGND
Analog Ground
SENSE
VREF
VIN+
VINDS+
33
36
37
44
45
46
49
50
51
52
55
56
57
58
59
60
48,53,61,67,74,82
47,54,62,75,83
63
64
69
70
71
72
73
76
77
78
79
80
81
84
85
DSENC+
ENCDB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
OR_B
DrGND
DrVDD
DCODCO+
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
OR_A
Control Pin for Reference , Full Scale
1.235 Reference I/O - function dependent on REFSENSE
Analog input – true.
Analog input – compliment.
Data sync (input) – true. Aligns output channels so that data from
channel A represents a sample that is prior from data in channel B,
taking into account the pipeline delay. (See timing diagram). Tie
LOW if not used.
Data sync (input) – compliment. Tie HIGH if not used.
Clock input – true.
Clock input – compliment.
B Port Output Data Bit (LSB)
B Port Output Data Bit
B Port Output Data Bit
B Port Output Data Bit
B Port Output Data Bit
B Port Output Data Bit
B Port Output Data Bit
B Port Output Data Bit
B Port Output Data Bit
B Port Output Data Bit
B Port Output Data Bit
B Port Output Data Bit (MSB)
B Port Overrange
Digital ground.
3.3V digital output supply. (3.0V to 3.6V)
Data Clock output – compliment.
Data Clock output – true.
A port Output Data Bit (LSB)
A port Output Data Bit
A port Output Data Bit
A port Output Data Bit
A port Output Data Bit
A port Output Data Bit
A port Output Data Bit
A port Output Data Bit
A port Output Data Bit
A port Output Data Bit
A port Output Data Bit
A port Output Data Bit (MSB)
A port Overrange
‘0’ sets FS = 1.533 Vpp differential
-8-
4/01/2002 REV. PrG
PRELIMINARY TECHNICAL DATA
AD9430
PIN FUNCTION DESCRIPTIONS (LVDS mode )
Function in LVDS Mode
LVDS Mode
Name
Pin Number
2,42,43,44,45,46
1
DNC
S5
Do not connect
Full Scale Adjust pin : ‘1’ sets FS =.766 Vpp differential,
3
S4
5
6
7
S2
S1
LVDSBIAS
8,14,15,18,19,24,27,28,29,34,
39,40,88,89,90,94,95,98,99
4,9,12,13,16,17,20,23,25,26,3
0,31,35,38,41,86,87,91,92,93,
96,97,100
10
11
21
22
32
33
36
37
47,54,62,75,83
AVDD
Interlaced or parallel output mode. (only in Dual Port mode
operation) HIGH = data arrives in channel A at falling edge of clock
and data arrives in channel A at rising edge of clock. LOW = data
arrives in channels A and B at rising edge of clock.
Output Mode select. Low = Dual Port, CMOS; High = LVDS
Data format select. Low = Binary, High = Two’s compliment
Sets LVDS Output Current = 3.5mA
(Place 3.7K RSET resistor from LVDSBIAS to ground)
3.3V analog supply. (3.0V to 3.6V)
AGND
Analog Ground
SENSE
VREF
VIN+
VINDS+
DSENC+
ENCDrVDD
Control Pin for Reference , Full Scale
1.235 Reference I/O - function dependent on REFSENSE
Analog input – true.
Analog input – compliment.
Data sync (input) – Not used in LVDS mode.Tie LOW .
Data sync (input) – compliment. Not used in LVDS mode.Tie HIGH.
Clock input – true.
(LVPECL levels)
Clock input – compliment. (LVPECL levels)
3.3V digital output supply.
48,53,61,67,74,82
49
50
51
52
55
56
57
58
59
60
63
64
65
66
68
69
70
71
72
73
76
77
78
79
80
81
84
85
DrGND
D0_C
D0_T
D1_C
D1_T
D2_C
D2_T
D3_C
D3_T
D4_C
D4_T
DCODCO+
D5_C
D5_T
D6_C
D6_T
D7_C
D7_T
D8_C
D8_T
D9_C
D9_T
D10_C
D10_T
D11_C
D11_T
OR_C
OR_T
Digital ground.
D0 complement output bit (LSB)
(LVDS Levels)
D0 true output bit (LSB)
(LVDS Levels)
D1 complement output bit
(LVDS Levels)
D1 true output bit
(LVDS Levels)
D2 complement output bit (LVDS Levels)
D2 true output bit (LVDS Levels)
D3 complement output bit (LVDS Levels)
D3 true output bit (LVDS Levels)
D4 complement output bit (LVDS Levels)
D4 true output bit (LVDS Levels)
Data Clock output – compliment. (LVDS Levels)
Data Clock output – true.
(LVDS Levels)
D5 complement output bit (LVDS Levels)
D5 true output bit (LVDS Levels)
D6 complement output bit (LVDS Levels)
D6 true output bit (LVDS Levels)
D7 complement output bit (LVDS Levels)
D7 true output bit (LVDS Levels)
D8 complement output bit (LVDS Levels)
D8 true output bit (LVDS Levels)
D9 complement output bit (LVDS Levels)
D9 true output bit (LVDS Levels)
D10 complement output bit (LVDS Levels)
D10 true output bit (LVDS Levels)
D11 complement output bit (LVDS Levels) MSB
D11 true output bit (LVDS Levels) MSB
Overrange complement output bit (LVDS Levels)
Overrange true output bit (LVDS Levels)
‘0’ sets FS = 1.533 Vpp differential
REV. PrG 4/01/2002
-9-
PRELIMINARY TECHNICAL DATA
AD9430
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of
the fundamental frequency (as determined by the FFT
analysis) is reduced by 3 dB.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
2
 VFullscale

 Z Input
PowerFullscale = 10 log
 .001


rms
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog
input is sampled.







Gain Error
Gain error is the difference between the measured and ideal
full scale input voltage range of the ADC.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Crosstalk
Coupling onto one channel being driven by a low level (–40
dBFS) signal when the adjacent interfering channel is driven
by a full-scale signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance and Differential Analog Input
Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak
differential voltage is computed by observing the voltage on
a single pin and subtracting the voltage from the other pin,
which is 180 degrees out of phase. Peak-to-peak differential
is computed by rotating the inputs phase 180 degrees and
again taking the peak measurement. The difference is then
computed between both peak measurements.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, repo rted in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Effective Number of Bits
The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:
Noise (for Any Range within the ADC)
ENOB =
SNR MEASURED− 1.76 dB
6.02
V noise = Z * .001 * 10
 FSdBm − SNRdBc − SignaldBFS 


10


Where Z is the input impedance, FS is the full scale of the
device for the frequency in question, SNR is the value for the
particular input level, and Signal is the signal level within
the ADC reported in dB below full scale. This value includes
both thermal and quantization noise.
ENCODE Pulsewidth / Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. See timing
implications of changing tENCH in text. At a given clock rate,
these specifica-tions define an acceptable ENCODE duty
cycle.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal -to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full
scale) to the rms value of the sum of all other spectral
components, including harmonics but excluding dc.
-10-
4/01/2002 REV. PrG
PRELIMINARY TECHNICAL DATA
AD9430
Signal -to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious
component may or may not be a harmonic. May be reported
in dBc (i.e., degrades as signal level is lowered), or dBFS
(always related back to converter full scale).
Figure X Analog Inputs
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms
value of the worst third order intermodulation product;
reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms
value of the peak spurious component. The peak spurious
component may or may not be an IMD product. May be
reported in dBc (i.e., degrades as signal level is lowered), or
in dBFS (always related back to converter full scale).
Figure X S1-S5 Inputs
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
Transient Response Time
Transient response is defined as the time it takes for the
ADC to reacquire the analog input after a transient from
10% above negative full scale to 10% below positive full
scale.
Out-of-Range Recovery Time
Out of range recovery time is the time it takes for the ADC
to reacquire the analog input after a transient from 10%
above positive full scale to 10% above negative full scale, or
from 10% below negative full scale to 10% below positive
full scale.
Figure X VREF, SENSE I/O
EQUIVALENT CIRCUITS
Figure X Data Outputs (CMOS Mode)
Figure X Encode and DS Inputs
Figure X Data Outputs (LVDS Mode)
REV. PrG 4/01/2002
-11-
PRELIMINARY TECHNICAL DATA
AD9430
APPLICATION NOTES
THEORY OF OPERATION
The AD9430 architecture is optimized for high speed and
ease of use. The analog inputs drive an integrated high
bandwidth track-and-hold circuit that samples the signal
prior to quantization by the 12-bit core. For ease of use the
part includes an onboard reference and input logic that
accepts TTL, CMOS, or LVPECL levels. The digital outputs
logic levels are user selectable as standard 3V CMOS or
LVDS (ANSI-644 compatible) via pin S2.
differential analog inputs for applications that require a
single-ended-to-differential conversion. Both analog inputs
are self-biased by an on-chip resistor divider to a nominal
2.8 V. (See Equivalent Circuits section TBD.)
Special care was taken in the design of the Analog Input
section of the AD9430 to prevent damage and corruption of
data when the input is overdriven. The nominal input range
is 1.5 V diff p-p. The nominal differential input range is 768
mV p-p × 2.
USING THE AD9430
ENCODE Input
Any high speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A
track/hold circuit is essentially a mixer, and any noise,
distortion, or timing jitter on the clock will be combined
with the desired signal at the A/D output. For that reason,
considerable care has been taken in the design of the
ENCODE input of the AD9430, and the user is advised to
give commensurate thought to the clock source.
The AD9430 has an internal clock duty cycle stabilization
circuit that locks to the rising edge of ENCODE (falling
edge of ENCODE if driven differentially), and optimizes
timing internally. This allows for a wide range of input duty
cycles at the input without degrading performance. Jitter in
the rising edge of the input is still of paramount concern, and
is not reduced by the internal stabilization circuit. This
circuit is always on, and cannot be disabled by the user.
The ENCODE and ENCODE inputs are internally biased to
1.5V (nominal), and support either differential or single –
ended signals. For best dynamic performance, a differential
signal is recommended. Good performance is obtained
using an MC10EL16 in the circuit to drive the
encode inputs , as illustrated in figure below.
Differential Analog Input Range
Single Ended Analog Input Range
Driving Encode with EL16
Analog Input
The analog input to the AD9430 is a differential buffer. For
____
best dynamic performance, impedances at AIN and AIN
should match. The analog input has been optimized to
provide superior wideband performance and requires that the
analog inputs be driven differentially. SNR and SINAD
performance will degrade significantly (~6dB) if the analog
input is driven with a single-ended signal. A wideband
transformer such as Minicircuits ADT1 -1WT can be used to
provide the
-12-
4/01/2002 REV. PrG
PRELIMINARY TECHNICAL DATA
AD9430
Digital Outputs
The off chip drivers on the chip can be configured by the
user to provide CMOS or LVDS compatible output levels
via pin S2.
The CMOS digital outputs (S2=0) are TTL/CMOScompatible for lower power consumption. The outputs are
biased from a separate supply (VDD), allowing easy
interface to external logic. The outputs are CMOS devices
which will swing from ground to VDD (with no dc load). It
is recommended to minimize the capacitive load the ADC
drives by keeping the output traces short (<1 inch, for a total
CLOAD < 5 pF). When operating in cmos mode it is also
recommended to place low value (220 ohm) series damping
resistors on the data lines to reduce switching transient
effects on performance.
LVDS outputs are available when S2=VDD and a 3.7K
RSET resistor is placed at pin 7 ( LVDSBIAS) to ground .
This resistor sets the output current at each output equal to a
nominal 3.5mA ( 10* IRSET ) . A 100 ohm differential
termination resistor placed at the lvds receiver inputs results
in a nominal 350mV voltage swing at the receiver. Note that
when operating in LVDS mode the output supply must be at
a dc potential greater than or equal to the analog supply level
(AVDD). This can be accomplished simply by biasing the
two supplies from the same power plane or by tying the two
supplies on the pcb through an inductor. When operating in
CMOS mode this is not required and separate supplies are
recommended.
Clock Outputs (DCO+, DCO-)
The input ENCODE is divided by two (in CMOS mode) and
available off-chip at DCO+ and DCO-. These clocks can
facilitate latching off-chip, providing a low skew clocking
solution (see timing diagram). The on-chip clock buffers
should not drive more than 5 pF of capacitance to limit
switching transient effects on performance.
Note that the Outputs clocks are CMOS levels when CMOS
mode is selected(S2=0) and are LVDS levels when in LVDS
mode(S2=VDD). (Requiring a 100ohm differential
termination at receiver in LVDS mode). The output clock in
LVDS mode switches at the encode rate.
REV. PrG 4/01/2002
-13-
Voltage Reference
A stable and accurate 1.25 V voltage reference is built into
the AD9430 (VREF). The analog input Full Scale Range is
linearly proportional to the voltage at VREF. VREF (and in
turn input full scale ) can be varied by adding an external
resistor network at VREF, SENSE and GROUND. (See
figure X ) . No appreciable degradation in performance
occurs when VREF is adjusted ±5%. Note that an external
reference can be used by connecting the SENSE pin to VDD
(disabling internal reference) and driving VREF with the
external reference source. A .1uF capacitor to ground is
recommended at VREF pin in internal and external reference
applications.
Simplified Voltage Reference Equivalent Circuit
PRELIMINARY TECHNICAL DATA
AD9430
AD9430 EVALUATION BOARD
The AD9430 evaluation board offers an easy way to test the
AD9430. It requires a clock source, an analog input signal, and
a 3.3 V power supply. The clock source is buffered on the board
to provide the clocks for the ADC, an on-board DAC, latches,
and a data ready signal. The digital outputs and output clocks
are available at two 40-pin connectors, P3 and P4. The board
has several different modes of operation, and is shipped in the
following configuration:
> 0.5 V p-p. Power to the EL16 is set at jumper E47. E47–E45
powers the buffer from AVDD, E47–E46 powers the buffer from
VCLK/V_XTAL.
Voltage Reference
• Full-Scale Adjust = Low
The AD9430 has an internal 1.23 V voltage reference. The
ADC uses the internal reference as the default when jumpers
E24–E27 and E25–E26 are left open. The full scale can be
increased by placing optional resistor R3. The required value
would vary with process and needs to be tuned for the specific
application. Full scale can similarly be reduced by placing R4;
tuning would be required here as well. An external reference can
be used by shorting the SENSE pin to 3.3 V (place jumper
E26–E25). E27–E24 jumper connects the ADC VREF pin to
EXT_VREF pin at the power connector.
Power Connector
Data Format Select
Power is supplied to the board via a detachable 12-lead power
strip (three 4-pin blocks).
Data Format Select sets the output data format of the ADC. Setting DFS (E1–E2) low sets the output format to be offset binary;
setting DFS high (E1–E3) sets the output to two’s complement.
• Offset Binary
• Internal Voltage Reference
• CMOS Parallel Timing
Table II. Power Connector
AVDD 3.3 V
DRVDD 3.3 V
VDL 3.3 V
EXT_VREF*
VCLK/V_XTAL
VAMP
Analog Supply for ADC (~ 350 mA)
Output Supply for ADC (~ 28 mA)
Supply for Support Logic and DAC (~350 mA)
Optional External Reference Input
Supply for Clock Buffer/Optional XTAL
Supply for Optional Amp
I/P
Output timing is set at E11–E13. E12–E11 sets S4 low for
parallel output timing mode. E11–E13 sets S4 high for interleaved
timing mode.
Timing Controls
*LVEL16 clock buffer can be powered from AVDD or VCLK at E47 jumper
(AVDD, DrVDD,VDL are the minimum required power connections).
Flexibility in latch clocking and output timing is accomplished
by allowing for clock inversion at the timing controls section of
the PCB. Each buffered clock is buffered by an XOR and can be
inverted by moving the appropriate jumper for that clock.
Analog Inputs
Data Outputs
The evaluation board accepts a 1.3 V p-p analog input signal
centered at ground at SMB connector J4. This signal is terminated
to ground through 50 Ω by R16. The input can be alternatively
terminated at T1 transformer secondary by R13, R14. T1 is a
wideband RF transformer providing the single-ended to differential
conversion allowing the ADC to be driven differentially, minimizing
even order harmonics. An optional second transformer T2 can be
placed following T1 if desired. This would provide some performance advantage (~1–2 dB) for high analog input frequencies
(>100 MHz). If T2 is placed, two shorting traces at the pads would
need to be cut. The analog signal is low pass filtered by R41,
C12, and R42, C13 at the ADC input.
The ADC digital outputs are latched on the board by four LVT574s;
the latch outputs are available at the two 40-pin connectors at pins
11–33 on P23 (channel A) and pins 11–33 on P3 (channel B).
The latch output clocks (data ready) are available at Pin 37 on
P23 (channel A) and Pin 37 on P3 (channel B). The data ready
clocks can be inverted at the timing controls section if needed.
⌬: 4.6nS
C1 FREQ
84.65608MHz
Gain
1
Full scale is set at E17–E19, E17–E18 sets S5 low, full scale =
1.5 V differential; E17–E19 sets S5 high, full scale = 0.75 V
differential.
2
Encode
The encode clock is terminated to ground through 50 Ω at SMB
connector J5. The input is ac-coupled to a high-speed differential
receiver (LVEL16) which provides the required low-jitter, fast
edge rates needed for optimum performance. J5 input should be
CH1
2.00V⍀
CH2
2.00V⍀ M 5.00nS
CH2
Figure 13. Data Output and Clock @ 80-Pin Connector
-14-
4/01/2002 REV. PrG
PRELIMINARY TECHNICAL DATA
AD9430
DAC Outputs
Optional Amplifier
Each channel is reconstructed by an on-board dual-channel DAC,
an AD9753. This DAC is intended to assist in debug—it should
not be used to measure the performance of the ADC. It is a current
output DAC with on-board 50 Ω termination resistors. The
figure below is representative of the DAC output with a full-scale
analog input. The scope setting is low bandwidth.
The footprint for transformer T2 can be modified to accept a
wideband differential amplifier (AD8350) for low frequency
applications where gain is required. Note that Pin 2 would need
to be lifted and left floating for operation. Input transformer T1
would need to be modified to a 4:1 for impedance matching and
ADC input filtering would enhance performance (see AD8350
data sheet). SNR/SINAD Performance of 61 dB/60 dB is possible and would start to degrade at about 30 MHz.
C1 FREQ
10.33592MHz
CUT TRACE
C1 PK-PK
448mV
1
AD9430
1
2.00mV⍀
CH1
M 25.0nS CH1
248mV
Figure 14. DAC Output
CUT TRACE
Encode Xtal
An optional xtal oscillator can be placed on the board to serve
as a clock source for the PCB. Power to the xtal is through the
VCLK/VXTAL pin at the power connector. If an oscillator is used,
ensure proper termination for best results. The board has been
tested with a Valpey Fisher VF561 and a Vectron JN00158-163.84.
Test results for the VF561 are shown below.
0
ENCODE 163.84MHz
ANALOG 65.02MHz
SNR 63.93dB
SINAD 63.87dB
FUND –0.45dBFS
2ND –85.62dBc
3RD –91.31dBc
4TH –90.54dBc
5TH –90.56dBc
6TH –91.12dBc
THD –82.21dBc
SFDR 83.93dBc
SAMPLES 8k
NOISEFLR –100.44dBFS
WORSTSP –83.93dBc
–10
–20
–30
dB
–40
–50
–60
–70
–80
–90
–100
0
20
40
MHz
60
80
Figure 15. FFT—Using VF561 XTAL as Clock Source
REV. PrG 4/01/2002
-15-
Figure 16. Using the AD8350 on the AD9430 PCB
PRELIMINARY TECHNICAL DATA
AD9430
Table III. Evaluation Board Bill of Materials
No. Qty.
Reference Designator
Device
Package
Value
Comments
1
45
Capacitor
0603
0.1 µF
C43, C47
Not Placed
2
3
4
5
6
7
0
0
1
0
7
9
10 pF
20 pF
0.01 µF
1 µF
10 µF
Not Placed
Not Placed
5
2
3
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
3-Pin Header/Jumper
3-Pin Header/Jumper
3-Pin Header/Jumper
4-Pin Header
3-Pin Header/Jumper
3-Pin Header/Jumper
3-Pin Header/Jumper
3-Pin Header/Jumper
3-Pin Header/Jumper
SMB
40-Pin Header
4-Pin Power Connector
0603
0603
0603
0603
CAPL
8
9
10
C1, C3–C11, C15–C17,
C19–C29, C31–C48,
C58–C62
C2
C12, C13
C14
C18
C30, C49, C63–C67
E3–E1–E2
E19–E17–E18
E13–E11–E12
E26–E25–E27–E24
E46–E47–E45
E35–E33–E34
E32–E30–E31
E29–E23–E28
E22–E16–E21
J1, J2, J3, J4, J5, J6
P3, P23
P4, P21, P22
11
8
R1, R5, R13, R14, R16,
12
1
13
8
14
15
16
17
18
5
4
1
1
7
19
20
4
8
21
1
R21–R24, R33–R36, R38
R12, R30, R37
R17, R18, R19, R20
R26
R29
R31, R32, R39, R40, R43,
R44, R45
RZ1, RZ2, RZ3, RZ4
RZ5, RZ6, RZ7, RZ8, RZ9,
RZ10, RZ11, RZ12
T1, T2
22
23
24
25
26
1
1
1
4
1
U1
U2
U3
U4, U5, U6, U7
U9
SMB
C30 Not Placed
J1 Not Placed
25.531.3425.0
Wieland
Resistor
Post
Detachable
Connector
0603
25.602.5453.0
50 Ω
Wieland
R1, R13, R14
Not Placed
R25, R27, R28, R41, R42
R2, R3, R4
Resistor
0603
3.9 kΩ
R3, R4 Not Placed
R6–R8, R10, R15,
Resistor
0603
100 Ω
R15, R21–R24, R38
Not Placed
Resistor
Resistor
Resistor
Resistor
Resistor
0603
0603
0603
0603
0603
0Ω
510 Ω
2 kΩ
390 Ω
1 kΩ
Resistor Pack 220 Ω
Resistor Pack 22 Ω
SO16RES
SO16RES
742C163221JTR
742C163220JTR
CTS
CTS
Transformer
CD542
T2 Not Placed
AD9430BSV
MC100LVEL16D
74LCX86
74LVT574
AD9753AST
TQFP100
SO8NB
SO14NB
SO20
LQFP48
Minicircuits
ADT1–1WT
ADC
Clock Buffer
Xor/Buffer
Latch
DAC
-16-
4/01/2002 REV. PrG
J4
ANALOG
C6
0.1␮F
GND
GND
VCC
E1
E19
1
4
5
2
3
6
PRI SEC
VDL
R14
29⍀
GND
GND
GND
COUT
E7
E20
ENCODE
J5
R13, R14 OPTIONAL
C2
10pF
C3
0.1␮F
R39
1k⍀
R39
1k⍀
H2
MTHOLES
R4
R3
VCC
E24
R27
50⍀
R17
510⍀
R10
510⍀
D
8
VCC
Q
7
C36
0.1␮F
VEE
5
3 DN
6
QN
4 VBB
2
U2
GND
GND
C13
20pF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
R20
510⍀
GND
DATA SYNC J1
R42
25⍀
GND
GND
VCC
GND
GND
GND
VCC
VCC
GND GND
GND
VCC
VCC
C12
GND
20pF
11
8
6
3
R36
100⍀
R35
100⍀
R34
100⍀
R33
100⍀
DRB
CLKLATB
DRA
CLKLATA
GROUND PAD UNDER PART
PLB
GND
U3
74LCX86
U3
74LCX86
U3
74LCX86
U3
74LCX86
9
10
4
5
1
2
12
13
VCC
GND
R6
100⍀
R41
25⍀
C1
0.1␮F
C8
0.1␮F
E46
E45
C5
0.15␮F MC100LVEL 16
E47
C47
0.1␮F
E21
GND
R41
25⍀
C11 0.1␮F
R7
100⍀
E22 COUTAB
E28
GND
E16
E26
GND
VCC
GND
E29 COUTAB
VCC
R8
100⍀
COUTA
R10
100⍀
E31
E23
E30
E32
E34
GND
VCC
GND
C43
0.1␮F
E29
E27
VCLK
4
1
5
2
3
6
PRI SEC
T2
ADT1-1WT
T2
OPTIONAL
GND
GND
VCC
COUTAB
COUTA
EXT_VREF
GND
R11
R9
R3, R4
OPTIONAL
H2
COUTB
MTHOLES
H3
MTHOLES
H4
MTHOLES
DRVDD
C6 R13
0.1␮F 25⍀
E2
E5
E3
E6
VCC
E4
E9
GND
E8
E10
VCC
E13
E18
E12
E11
E14
E17
E19
GND
GND
DRVDD
GND
AVDD (VCC)
VCLK/ V_XTAL
EXT_VREF
GND
VDL
GND
VCC
GND
T1
ADT1-1WT
P21
P4
P22
PTMICA04 PTMICA04 PTMICA04
R16
50⍀
1
2
3
4
1
2
3
4
VCC
P1
P2
P3
P4
P1
P2
P3
P4
COUTA
R1
50⍀
R19
510⍀
00
R12
U1
AD9430
+
C30
10␮F
GND GND
C4
0.1␮F
VCC
E36
R1 NOT PLACED
J2
GND
GND
R5
50⍀
GND
VCC
VCC
VCC
GND
GND
E35
VCC
GND
E33
GND
VCC
VCC
GND
VCC
VCC
GND
GND
VCC
VCC
GND
GND
GND
VCC
VCC
VCC
GND
GND
CLK+
Figure 17a. Evaluation Board Schematic
-17CLK–
GND
VAMP
GND
1
2
3
4
DRVDD
GND
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
REV. PrG 4/01/2002
DRVDD
GND
P1
P2
P3
P4
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DRVDD
GND
COUT
COUTB
DRVDD
GND
GND
DRVDD
GND
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
R8
R7
R6
R5
R4
R3
R2
R1
RZ4 220
R8
R7
R6
R5
R4
R3
R2
R1
RZ3 220
R8
R7
R6
R5
R4
R3
R2
R1
RZ2 220
R8
R7
R6
R5
R4
R3
R2
R1
RZ1 220
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
GND
GND
GND
GND
GND
GND
GND
GND
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
LVT574
GND
D7
D6
D5
D4
D3
D2
D1
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
VCC
CLOCK
U7
OUT_EN
D0
CLOCK
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
VCC
LVT574
GND
D7
D6
D5
D4
D3
D2
D1
D0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CLOCK
U6
OUT_EN
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
VCC
LVT574
GND
D7
D6
D5
D4
D3
D2
D1
D0
OUT_EN
U5
LVT574
GND
D7
D6
D5
D4
D3
D2
D1
D0
VCC
CLOCK
U4
OUT_EN
VDL
4
3
2
1
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
11
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
R8
R7
R6
R5
R4
R3
R2
R1
RZ5 22
CLKLATB
VDL
R8
R7
R6
R5
R4
R3
R2
R1
RZ6 22
CLKLATA
VDL
R8
R7
R6
R5
R4
R3
R2
R1
RZ7 22
CLKLATA
VDL
R8
R7
R6
R5
R4
R3
R2
R1
RZ8 22
CLKLATA
12 DM5 8
13 DM6 7
14 DM7 6
15 DM8 5
16
17
18
19
20
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
DYB
DYA
DY0
DY1
DY2
DY3
DY4
DY5
DY6
DY7
DY8
DY9
DY10
DY11
DRY
DXB
DXA
DX0
DX1
DX2
DX3
DX4
DX5
DX6
DX7
DX8
DX9
DX10
DX11
DRX
GND
GND
P39
P37
P35
P33
P31
P29
P27
P25
P23
P21
P19
P17
P15
P13
P11
P9
P7
P5
P3
P1
P39
P37
P35
P33
P31
P29
P27
P25
P23
P21
P19
P17
P15
P13
P11
P9
P7
P5
P3
P1
C4OMS
P3
P40
P38
P36
P34
P32
P30
P28
P26
P24
P22
P20
P18
P16
P14
P12
P10
P8
P6
P4
P2
C4OMS
P23
P40
P38
P36
P34
P32
P30
P28
P26
P24
P22
P20
P18
P16
P14
P12
P10
P8
P6
P4
P2
GND
GND
DRB
GND
DY11
DY10
DY9
DY8
DY7
DY6
DY5
DY4
DY3
DY2
DY1
DY0
DYA
DYB
DRY
GND
GND
DRA
GND
DX11
DX10
DX9
DX8
DX7
DX6
DX5
DX4
DX3
DX2
DX1
DX0
DXA
DXB
DRX
PRELIMINARY TECHNICAL DATA
AD9430
PRELIMINARY TECHNICAL DATA
AD9430
VCC
+
C64
10␮F
C16
0.1␮F
C17
0.1␮F
C19
0.1␮F
C21
0.1␮F
C20
0.1␮F
C23
0.1␮F
C24
0.1␮F
C25
0.1␮F
C22
0.1␮F
C27
0.1␮F
C26
0.1␮F
C29
0.1␮F
C28
0.1␮F
C31
0.1␮F
C42
0.1␮F
C41
0.1␮F
C32
0.1␮F
C35
0.1␮F
GND
VDL
+
C67
10␮F
C44
0.1␮F
C15
0.1␮F
C37
0.1␮F
GND
DRVDD
VCLK
C60
0.1␮F
C59
0.1␮F
VREF
C58
0.1␮F
+
GND
GND
+
C63
10␮F
GND
GND
OPIN B
OPIN B
OUT–
P1
GND
R21
100⍀
VCLK
8
7
6
5
R22
100⍀ VCLK
U8
GND
AD9430
R23
100⍀
OPTIONAL AMP
P2
IN+
1
OPTIONAL XTAL
2
OPIN
J6
E4Z
GND
C38
.1U
VOL
E40
J3
R28
50⍀
GND
E41
R44
GND
C18
0.1U
OPIN
GND
GND
GND
GND
C33
GND 0.1U
GND
R29
392⍀
1k⍀
E39
VOL
E37
R26
2k⍀
E38
GND
R43
1k⍀
R37
2
0⍀
3
DRA
R32
1k⍀
GND
VOL
C48
0.1U
C45
0.1U
37
38
39
40
41
42
4
R45
1k⍀
RZ12
9
R8
8
10
R7
7
36
11
R6
6
35
12
R5
5
34
13
R4
4
14
R3
3
15
R2
2
16
R1
1
33
5
32
6
31
GND
GND
43
44
45
46
1
GND
R31
1k⍀
47
48
GND
VOL
U10
C34
VOL 0.1U
R25
50⍀
R30
0⍀
4
GND VAMP
GND
VOL
3
OUT+
VCC 6
5
OUTPUT B
4
OUTPUT
GND
GND
1
E/D
2
NC
3
GND
R24
100⍀
AD9430
R8
8
DX11
1
16
7
29
10
R7
7
DX10
2
R2
15
8
28
R6
6
DX9
3
R3
11
14
9
27
R5
5
DX8
4
R4
12
13
26
R4
4
DX7
R5
13
5
12
10
11
3
DX6
6
R6
14
R3
11
12
2
DX5
7
R7
15
R2
10
1
DX4
8
R8
16
R1
9
30
9
24
23
22
21
20
19
18
17
25
16
DYA
DY0
DY1
DY2
DY3
RZ10
R1
15
DYB
220
RZ9
13
DY4
DY5
DY6
DY7
DY8
DY9
DY10
DY11
220
220
RZ11
DX3
1
R1
16
DX2
2
R2
15
DX1
3
R3
14
DX0
4
R4
13
DXA
5
R5
12
DXB
6
R6
11
7
R7
10
8
R8
9
GND
GND
C48
0.1␮F
GND
VCLK
R38 FOR
VF561 CRYSTAL
C40
0.1U
C49
10␮F
GND GND
R15
100⍀
R38
100⍀
VAMP
C14
0.01␮F
C66
10␮F
VCC
C62
0.1␮F
IN–
C61
0.1␮F
ENBL
C65
10␮F
14
+
VOL
GND
C35
0.1U
220
Figure 17b. Evaluation Board Schematic
-18-
4/01/2002 REV. PrG
PRELIMINARY TECHNICAL DATA
AD9430
Figure 18. PCB Top Side Silkscreen
Figure 21. PCB Split Power Plane
Figure 19. PCB Top Side Copper
Figure 22. PCB Bottom Side Copper
Figure 23. PCB Bottom Side Silkscreen
Figure 20. PCB Ground Layer
REV. PrG 4/01/2002
-19-
PRELIMINARY TECHNICAL DATA
AD9430
The AD9430 Evaluation Board is provided as a design example
for customers of Analog Devices, Inc. ADI makes no warranties,
express, statutory, or implied, regarding merchantability or
fitness for a particular purpose.
Troubleshooting
C02607–0–x/02(0)
If the board does not seem to be working correctly, try the following:
• Verify power at IC pins.
• Check that all jumpers are in the correct position for the
desired mode of operation.
• Verify VREF is at 1.23 V.
• Try running Encode Clock and Analog Inputs at low speeds
(10 MSPS/1 MHz) and monitor 574, DAC, and ADC outputs
for toggling.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
100-Lead TQFP (with Exposed Heat Sink)
(TQFP-100)
0.047 (1.20)
MAX
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
0.630 (16.00) SQ
0.551 (14.00) SQ
100
1
76
76
75
100
1
75
BOTTOM VIEW
SEATING
PLANE
TOP VIEW
(PINS DOWN)
CONDUCTIVE
HEAT SINK
50
25
26
50
49
0.041 (1.05)
0.039 (1.00)
0.037 (0.95)
0.006 (0.15)
0.002 (0.05)
0.0197 (0.50)
BSC
0.011 (0.27)
0.009 (0.22)
0.007 (0.17)
25
49
26
0.260 (6.00) NOM
CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
CENTER FIGURES ARE TYPICAL UNLESS
OTHERWISE NOTED.
7ⴗ
0ⴗ
PRINTED IN U.S.A.
NOTE:
THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE
WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
-20-
4/01/2002 REV. PrG
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