LP62S4096E-T Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Change VCCmax from 3.3V to 3.6V January 25, 2002 Remark Add product family and 55ns specification (January, 2002, Version 2.0) AMIC Technology, Inc. LP62S4096E-T Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Features General Description n Power supply range: 2.7V to 3.6V n Access times: 55ns / 70ns (max.) n Current: Very low power version: Operating: 30mA (max.) Standby: 10µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 2V (min.) n Available in 32-pin TSOP/TSSOP 36-ball CSP package The LP62S4096E-T is a low operating current 4,194,304-bit static random access memory organized as 524,288 words by 8 bits and operates on a low power supply range: 2.7V to 3.3V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. n CE2 pin for CSP package only Product Family Product Family LP62S4096E-T Power Dissipation Data Retention Standby Operating (ICCDR, Typ.) (ISB1, Typ.) (ICC2, Typ.) Operating Temperature VCC Range Speed -25°C ~ +85°C 2.7V~3.6V 55ns / 70ns 0.08µA 5mA 0.3µA Package Type 32L TSOP 32L TSSOP 36B CSP 1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested. 2. Data retention current VCC = 2.0V. Pin Configurations n TSOP/(TSSOP) 16 n CSP (Chip Size Package) 36-pin Top View 1 LP62S4096EV-T (LP62S4096EX-T) 17 Pin No. Pin Name 2 3 4 5 6 A A1 CE2 A3 A6 A8 A2 WE A4 A7 I/O1 NC A5 B I/O5 C I/O6 D GND VCC E VCC GND I/O2 F I/O7 A18 A17 G I/O8 OE CE1 A16 A15 I/O3 I/O4 H A9 A10 A11 A12 A13 A14 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4 Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name A3 A2 A1 A0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE1 A10 OE (January, 2002, Version 2.0) 1 A0 AMIC Technology, Inc. LP62S4096E-T Series Block Diagram A0 VCC GND A16 ROW 1024 X 4096 DECODER MEMORY ARRAY INPUT DATA CIRCUIT COLUMN I/O A17 A18 I/O1 I/O8 CE1 CE2 OE WE CONTROL CIRCUIT Recommended DC Operating Conditions Pin Description Symbol (TA = -25°C to + 85°C) Description A0 - A18 Address Inputs I/O1 - I/O8 Data Input/Outputs Symbol Parameter VCC Supply Voltage GND Ground Min. Typ. Max. Unit 2.7 3.0 3.6 V 0 0 0 V Ground VIH Input High Voltage 2.2 - VCC + 0.3 V Chip Enable VIL Input Low Voltage -0.3 0 +0.6 V OE Output Enable CL Output Load - - 30 pF WE Write Enable TTL Output Load - - 1 - VCC Power Supply GND CE1, CE2 (January, 2002, Version 2.0) 3 AMIC Technology, Inc. LP62S4096E-T Series Absolute Maximum Ratings* *Comments VCC to GND ------------------------------------- -0.5V to + 4.0V IN, IN/OUT Volt to GND--------------- -0.5V to VCC + 0.5V Operating Temperature, Topr -------------- -25°C to + 85°C Storage Temperature, Tstg --------------- -55°C to + 125°C Temperature Under Bias, Tbias ----------- -10°C to + 85°C Power Dissipation, PT --------------------------------------- 0.7W Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Symbol (TA = -25°C to + 85°C, VCC = 2.7V to 3.6V, GND = 0V) Parameter LP62S4096E-55LLT / 70LLT Min. Typ. Max. Unit Conditions ILI Input Leakage Current - - 1 µA VIN = GND to VCC ILO Output Leakage Current - - 1 µA CE1= VIH , CE2= VIL or OE = VIH WE =VIL VI/O = GND to VCC ICC Active Power Supply Current - - 5 mA CE1= VIL, CE2= VIH II/O = 0mA ICC1 Dynamic Operating Current - 20 30 mA Min. Cycle, Duty = 100%, CE1= VIL CE2= VIH, II/O = 0mA ICC2 Dynamic Operating Current - 5 15 mA CE1= VIL, CE2= VIH, VIH = VCC VIL = 0V, f = 1MHZ II/O = 0mA ISB Standby Power - - 1 mA ISB1 Supply Current - 0.3 10 µA VOL Output Low Voltage - - 0.4 V IOL = 2.1mA VOH Output High Voltage 2.2 - - V IOH = -1.0mA (January, 2002, Version 2.0) 4 VCC ≤ 3.3V CE1= VIH, CE2= VIL VCC ≤ 3.3V CE1≥ VCC - 0.2V, or CE2 ≤ 0.2V VIN ≤ 0.2V AMIC Technology, Inc. LP62S4096E-T Series Truth Table Mode I/O Operation Supply Current CE1 CE2 OE WE Standby H X X X High Z ISB, ISB1 Standby X L X X High Z ISB, ISB1 Output Disable L H H H High Z ICC, ICC1, ICC2 Read L H L H DOUT ICC, ICC1, ICC2 Write L H X L DIN ICC, ICC1, ICC2 Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pF VIN = 0V CI/O* Input/Output Capacitance 8 pF VI/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (TA = -25°C to + 85°C, VCC = 2.7V to 3.6V) Symbol LP62S4096E-55LLT Parameter LP62S4096E-70LLT Unit Min. Max. Min. Max. 55 - 70 - ns Read Cycle tRC Read Cycle Time tAA Address Access Time - 55 - 70 ns Chip Enable Access Time - 55 - 70 ns Output Enable to Output Valid - 30 35 ns Chip Enable to Output in Low Z 10 - 10 - ns tOLZ Output Enable to Output in Low Z 5 - 5 - ns tCHZ1, tCHZ2 Chip Disable to Output in High Z 0 20 0 25 ns tOHZ Output Disable to Output in High Z 0 20 0 25 ns tOH Output Hold from Address Change 5 - 5 - ns tACE1, tACE2 tOE tCLZ1, tCLZ2 (January, 2002, Version 2.0) 5 AMIC Technology, Inc. LP62S4096E-T Series AC Characteristics (continued) Symbol LP62S4096E-55LLT Parameter LP62S4096E-70LLT Min. Max. Min. Max. Unit Write Cycle tWC Write Cycle Time 55 - 70 - ns tCW1 Chip Enable to End of Write 50 - 60 - ns tAS Address Setup Time 0 - 0 - ns tAW Address Valid to End of Write 50 - 60 - ns tWP Write Pulse Width 40 - 50 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z 0 25 0 25 ns tDW Data to Write Time Overlap 25 - 30 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. Timing Waveforms Read Cycle 1(1) tRC Address tAA OE tOH tOE CE1 tOLZ5 CE2 tOHZ 5 tCHZ1 , tCHZ2 tACE1 , tACE2 tCLZ1 , tCLZ2 DOUT (January, 2002, Version 2.0) 6 AMIC Technology, Inc. LP62S4096E-T Series Timing Waveforms (continued) Read Cycle 2 (1, 2, 4) tRC Address tAA tOH tOH DOUT Read Cycle 3 (1, 3, 4) CS1 CS2 tACS1 , tACS2 tCLZ1 , tCLZ2 tCHZ1 , tCHZ2 DOUT Notes: 1. 2. 3. 4. 5. WE is high for Read Cycle. Device is continuously enabled, CE1 = VIL or CE2= VIH. Address valid prior to or coincident with CE1 transition low or CE2 transition high. OE = VIL. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. (January, 2002, Version 2.0) 7 AMIC Technology, Inc. LP62S4096E-T Series Timing Waveforms (continued) (6) Write Cycle 1 (Write Enable Controlled) tWC Address tAW tWR3 tcw1 ,tcw2 CE1 (4) CE2 tAS1 tWP2 WE tDW tDH DIN tWHZ7 tOW7 DOUT (January, 2002, Version 2.0) 8 AMIC Technology, Inc. LP62S4096E-T Series (6) Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tAS1 tCW1 , tCW2 tWR3 CE1 (4) CE2 tWP2 WE tDW tDH DIN tWHZ7 DOUT Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP) of a low CE1 or high CE2 , and a low WE . 3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low WE going high to the end of the Write cycle. 4. If the CE1 low or CE2 high transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write. 6. OE level is high or low. 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. (January, 2002, Version 2.0) 9 AMIC Technology, Inc. LP62S4096E-T Series AC Test Conditions Input Pulse Levels 0.4V to 2.4V Input Rise and Fall Time 5 ns Input and Output Timing Reference Levels 1.5V Output Load See Figures 1 and 2 TTL TTL CL CL 5pF 30pF * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ, tOHZ, tOL, tCHZ, tWHZ, and tOW Data Retention Characteristics (TA = -25°C to 85°C) Symbol VDR Parameter VCC for Data Retention Min. Typ. Max. Unit 2.0 - 3.6 V Conditions CE1≥ VCC - 0.2V, or CE2 ≤ 0.2V VCC = 2.0V, * ICCDR Data Retention Current LL-Version tCDR Chip Disable to Data Retention Time tR Operation Recovery Time tVR VCC Rising Time from Data Retention Voltage to Operating Voltage LP62S4096E-55LLT / 70LLT (January, 2002, Version 2.0) ICCDR: max. - 0.08 3* µA 0 - - ns tRC - - ns 5 - - ms CE1≥ VCC - 0.2V, or CE2 ≤ 0.2V VIN ≤ 0V See Retention Waveform 1µA at TA = 0°C to + 40°C 10 AMIC Technology, Inc. LP62S4096E-T Series Low VCC Data Retention Waveform (1) ( CE1 Controlled) DATA RETENTION MODE VCC 2.7V 2.7V tCDR tR VDR ≥ 2V tVR CE1 VIH VIH CE1 ≥ VDR - 0.2V Low VCC Data Retention Waveform (2) (CE2 Controlled) DATA RETENTION MODE VCC 2.7V 2.7V tCDR tR VDR ≥ 2V tVR CE2 VIL VIL CE2 ≤ 0.2V Ordering Information Part No. Access Time(ns) Operating Current Max.(mA) Standby Current Max.(uA) Package LP62S4096EV-55LLT 55 30 10 32L TSOP LP62S4096EX-55LLT 55 30 10 32L TSSOP LP62S4096EU-55LLT 55 30 10 36L CSP LP62S4096EV-70LLT 70 30 10 32L TSOP LP62S4096EX-70LLT 70 30 10 32L TSSOP LP62S4096EU-70LLT 70 30 10 36L CSP (January, 2002, Version 2.0) 11 AMIC Technology, Inc. LP62S4096E-T Series Package Information TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm e D A c E A2 12.0° A1 GAUGE PLANE 0.25 BSC θ L LE HD Detail "A" D Detail "A" y S Symbol Dimensions in inches Dimensions in mm A 0.047 Max. 1.20 Max. A1 0.004±0.002 0.10±0.05 A2 0.039±0.002 1.00±0.05 b 0.008±0.001 0.20±0.03 c 0.006±0.001 0.15±0.02 D 0.724±0.004 18.40±0.10 E 0.315±0.004 8.00±0.10 e 0.020 TYP. 0.50 TYP. HD 0.787±0.007 20.00±0.20 L 0.020±0.004 0.50±0.10 LE 0.031 TYP. 0.80 TYP. S 0.0167 TYP. 0.425 TYP. Y 0.004 Max. 0.10 Max. θ 0° ~ 6° 0° ~ 6° b 0.10(0.004) M Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (January, 2002, Version 2.0) 12 AMIC Technology, Inc. LP62S4096E-T Series Package Information TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions e unit: inches/mm A c E A2 12.0° A1 GAUGE PLANE 0.25 BSC θ L LE D1 D Detail "A" D Detail "A" 0.10MM S b SEATING PLANE Symbol Dimensions in inches Dimensions in mm A 0.049 Max. 1.25 Max. A1 0.002 Min. 0.05 Min. A2 0.039±0.002 1.00±0.05 b 0.008±0.001 0.20±0.03 c 0.006±0.0003 0.15±0.008 E 0.315±0.004 8.00±0.10 e 0.020 TYP. 0.50 TYP. D 0.528±0.008 13.40±0.20 D1 0.465±0.004 11.80±0.10 L 0.02±0.008 0.50±0.20 LE 0.0266 Min. 0.675 Min. S 0.0109 TYP. 0.278 TYP. y 0.004 Max. 0.10 Max. θ 0° ~ 6° 0° ~ 6° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (January, 2002, Version 2.0) 13 AMIC Technology, Inc. LP62S4096E-T Series Package Information 36LD CSP (6 x 8 mm) Outline Dimensions unit: mm BOTTOM VIEW TOP VIEW Ball#A1 CORNER 0.10 S C 0.25 S C A B Ball*A1 CORNER b (36X) 6 5 4 3 2 1 1 2 3 4 5 6 A B A C D E F G H C D E F G H E1 E e B B A 0.10 C SIDE VIEW D 0.20(4X) A2 SEATING PLANE A1 (0.36) C Symbol A A1 A2 D E D1 E1 e b A // 0.25 C e D1 Dimensions in mm MIN. NOM. MAX. 1.00 0.16 0.48 5.80 7.80 ------0.25 1.10 0.21 0.53 6.00 8.00 3.75 5.25 0.75 0.30 1.20 0.26 0.58 6.20 8.20 ------0.35 Note: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 4. BALL PAD OPENING OF SUBSTRATE IS Φ 0.25mm (SMD) SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.25mm (NSMD) (January, 2002, Version 2.0) 14 AMIC Technology, Inc.