LINER LTC2054 Spi/digital or i2c î¼module isolator with adjustable â±12.5v and 5v regulated power Datasheet

LTM2883
SPI/Digital or I2C µModule
Isolator with Adjustable ±12.5V
and 5V Regulated Power
Description
Features
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UL Rated 6-Channel Logic Isolator: 2500VRMS
UL Recognized
File #E151738
Isolated Adjustable DC Power:
3V to 5V at Up to 30mA
±12.5V at Up to 20mA
No External Components Required
SPI (LTM2883-S) or I2C (LTM2883-I) Options
High Common Mode Transient Immunity: 30kV/μs
High Speed Operation:
10MHz Digital Isolation
4MHz/8MHz SPI Isolation
400kHz I2C Isolation
3.3V (LTM2883-3) or 5V (LTM2883-5) Operation
1.62V to 5.5V Logic Supply
±10kV ESD HBM Across the Isolation Barrier
Common Mode Working Voltage: 560VPEAK
Low Current Shutdown Mode (<10µA)
Low Profile (15mm × 11.25mm × 3.42mm)
BGA Package
®
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Applications
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The LTM®2883 is a complete galvanic digital µModule®
isolator. No external components are required. A single 3.3V
or 5V supply powers both sides of the interface through
an integrated, isolated DC/DC converter. A logic supply
pin allows easy interfacing with different logic levels from
1.62V to 5.5V, independent of the main supply.
Available options are compliant with SPI and I2C (master
mode only) specifications.
The isolated side includes ±12.5V and 5V nominal power
supplies, each capable of providing more than 20mA of
load current. Each supply may be adjusted from its nominal
value using a single external resistor.
Coupled inductors and an isolation power transformer
provide 2500VRMS of isolation between the input and output logic interface. This device is ideal for systems where
the ground loop is broken, allowing for a large common
mode voltage range. Communication is uninterrupted for
common mode transients greater than 30kV/μs.
L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks
and Easy Drive, Hot Swap, SoftSpan and TimerBlox are trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners.
Isolated SPI or I2C Interfaces
Industrial Systems
Test and Measurement Equipment
Breaking Ground Loops
Typical Application
Isolated 4MHz SPI Interface
LTM2883-5S
5V
VCC2
VCC
AVCC2
V+
VL
AV+
ON
SDI
SCK
SDO
CS
SDI
SCK
ISOLATION BARRIER
SDOE
CS
V–
AV–
CS2
SDI2
SCK2
DO2
I2
SDO
SDO2
DO1
I1
GND
GND2
5V AT 20mA
LTM2883 Operating Through 35kV/µs CM Transient
SCK
SD0
SCK2 = SD02
12.5V AT 20mA
–12.5V AT 15mA
2V/DIV
2V/DIV
REPETITIVE
COMMON MODE
TRANSIENTS
CS
SDI
SCK
SDO
200V/DIV
20ns/DIV
2883 TA01b
2883 TA01a
2883f
1
LTM2883
Absolute Maximum Ratings
(Note 1)
VCC to GND................................................... –0.3V to 6V
VL to GND..................................................... –0.3V to 6V
VCC2, AVCC2, AV+ to GND2............................ –0.3V to 6V
V+ to GND2................................................. –0.3V to 16V
V–, AV– to GND2..........................................0.3V to –16V
Logic Inputs
DI1, SCK, SDI, CS, SCL, SDA, SDOE,
ON to GND...................................–0.3V to (VL + 0.3V)
I1, I2, SDA2,
SDO2 to GND2......................... –0.3V to (VCC2 + 0.3V)
Logic Outputs
DO1, DO2, SDO to GND...............–0.3V to (VL + 0.3V)
O1, SCK2, SDI2, CS2,
SCL2 to GND2......................... –0.3V to (VCC2 + 0.3V)
Operating Temperature Range (Note 4)
LTM2883C..........................................0°C ≤ TA ≤ 70°C
LTM2883I...................................... –40°C ≤ TA ≤ 85°C
LTM2883H....................................–40°C ≤ TA ≤ 105°C
Maximum Internal Operating Temperature............. 125°C
Storage Temperature Range................... –55°C to 125°C
Peak Body Reflow Temperature............................. 245°C
Pin Configuration
LTM2883-I
LTM2883-S
TOP VIEW
1
2
3
4
DO2 DNC SCL SDA
5
6
7
8
DI1
GND
ON
VL
TOP VIEW
1
A
A
B
B
C
DO1
VCC
GND
C
D
D
E
E
F
F
G
G
H
J
2
3
4
SDO DO2 SCK
SDI
DO1
GND
5
6
7
8
CS SDOE ON
VL
VCC
H
I1
GND2
AVCC2
AV–
AV+
K
J
I1
GND2
AVCC2 AV–
AV+
V–
V+
K
L
I2
DNC SCL2 SDA2 O1
VCC2
V–
V+
BGA PACKAGE
32-PIN (15mm × 11.25mm × 3.42mm)
TJMAX = 125°C, θJA = 30°C/W, θJC(BOTTOM) = 15.7°C/W,
θJC(TOP) = 25°C/W, θJBOARD = 14.5°C/W
θ VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g
L
SDO2
I2
SCK2 SDI2 CS2 VCC2
BGA PACKAGE
32-PIN (15mm × 11.25mm × 3.42mm)
TJMAX = 125°C, θJA = 30°C/W, θJC(BOTTOM) = 15.7°C/W,
θJC(TOP) = 25°C/W, θJBOARD = 14.5°C/W
θ VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g
2883f
2
LTM2883
Order Information
LTM2883 C
Y
-3
S
#PBF
LEAD FREE DESIGNATOR
PBF = Lead Free
LOGIC OPTION
I = Inter-IC (I2C) Bus
S = Serial Peripheral Interface (SPI) Bus
INPUT VOLTAGE RANGE
3 = 3V to 3.6V
5 = 4.5V to 5.5V
PACKAGE TYPE
Y = Ball Grid Array (BGA)
TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
I = Industrial Temperature Range (–40°C to 85°C)
H = Automotive Temperature Range (–40°C to 105°C)
PRODUCT PART NUMBER
Product Selection Guide
PART NUMBER
PART MARKING*
PACKAGE
INPUT VOLTAGE
LTM2883-3I
LTM2883Y-3I
BGA
3V to 3.6V
LOGIC OPTION
Inter-IC Bus (I2C)
LTM2883-3S
LTM2883Y-3S
BGA
3V to 3.6V
Serial Peripheral Interface Bus (SPI)
LTM2883-5I
LTM2883Y-5I
BGA
4.5V to 5.5V
Inter-IC Bus (I2C)
LTM2883-5S
LTM2883Y-5S
BGA
4.5V to 5.5V
Serial Peripheral Interface Bus (SPI)
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
This product is moisture sensitive. For more information go to: http://www.linear.com/packaging/
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, and GND =
GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supplies
VCC
Input Supply Range
LTM2883-3
LTM2883-5
l
l
3
4.5
3.3
5
3.6
5.5
V
V
VL
Logic Supply Range
LTM2883-S
LTM2883-I
l
l
1.62
3
5
5.5
5.5
V
V
ICC
Input Supply Current
ON = 0V
LTM2883-3, ON = VL, No Load
LTM2883-5, ON = VL, No Load
l
l
l
0
25
19
10
35
28
µA
mA
mA
IL
Logic Supply Current
ON = 0V
LTM2883-S, ON = VL
LTM2883-I, ON = VL
l
0
10
10
µA
µA
µA
150
2883f
3
LTM2883
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, and GND =
GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
4.75
5
5.25
V
5.5
V
25
100
mV
8
80
mV
600
615
mV
Output Supplies
VCC2
ICC2
V+
I+
V–
Regulated Output Voltage
No Load
Output Voltage Operating Range
(Note 2)
Line Regulation
ILOAD = 1mA, MIN ≤ VCC ≤ MAX
l
Load Regulation
ILOAD = 100µA to 20mA
l
ADJ Pin Voltage
ILOAD = 100µA to 20mA
l
Voltage Ripple
ILOAD = 20mA (Note 2)
Efficiency
ILOAD = 20mA (Note 2)
45
%
Output Short Circuit Current
VCC2 = 0V
45
mA
Current Limit
ΔVCC2 = –5%
l
20
Regulated Output Voltage
No Load
l
12
Line Regulation
ILOAD = 1mA, MIN ≤ VCC ≤ MAX
l
l
3
585
1
mVRMS
mA
12.5
13
V
5
30
mV
200
mV
1.220
1.260
mV
Load Regulation
ILOAD = 100µA to 20mA
l
ADJ Pin Voltage
ILOAD = 100µA to 20mA
l
Voltage Ripple
ILOAD = 20mA (Note 2)
Efficiency
ILOAD = 20mA (Note 2)
45
%
Output Short Circuit Current
V+ = 0V
70
mA
Current Limit
ΔV+ = –0.5V
l
20
Regulated Output Voltage
No Load
l
–12
Line Regulation
ILOAD = –1mA, MIN ≤ VCC ≤ MAX
Load Regulation
1.170
3
mVRMS
mA
–12.5
–13
V
l
4
15
mV
ILOAD = 100µA to 15mA
ILOAD = 100µA to 15mA, H-Grade
l
35
35
150
mV
mV
ADJ Pin Voltage
ILOAD = 100µA to 15mA
l
–1.220
–1.256
Voltage Ripple
ILOAD = 15mA (Note 2)
2
mVRMS
Efficiency
ILOAD = 15mA (Note 2)
45
%
Output Short-Circuit Current
V– = 0V
30
mA
Current Limit
ΔV– = 0.5V, V+ = 1.5mA
l
15
mA
VITH
Input Threshold Voltage
ON, DI1, SDOE, SCK, SDI, CS 1.62V ≤ VL < 2.35V
ON, DI1, SDOE, SCK, SDI, CS 2.35V ≤ VL
I1, I2, SDO2
l 0.25 • VL
l 0.33 • VL
l 0.33 • VCC2
IINL
Input Current
VHYS
Input Hysteresis
(Note 2)
VOH
Output High Voltage
DO1, DO2, SDO
ILOAD = –1mA, 1.62V ≤ VL < 3V
ILOAD = –4mA, 3V ≤ VL ≤ 5.5V
l
VL – 0.4
V
O1, SCK2, SDI2, CS2, ILOAD = –4mA
l
VCC2 – 0.4
V
DO1, DO2, SDO
ILOAD = 1mA, 1.62V ≤ VL < 3V
ILOAD = 4mA, 3V ≤ VL ≤ 5.5V
l
0.4
V
O1, SCK2, SDI2, CS2, ILOAD = 4mA
l
0.4
V
0V ≤ (DO1, DO2, SDO) ≤ VL
0V ≤ (O1, SCK2, SDI2, CS2) ≤ VCC2
l
±85
mA
mA
I–
–1.184
10
mV
Logic/SPI
VOL
ISC
Output Low Voltage
Short-Circuit Current
l
0.75 • VL
0.67 • VL
0.67 • VCC2
V
V
V
±1
µA
150
±60
mV
2883f
4
LTM2883
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, and GND =
GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I2C
VIL
Low Level Input Voltage
SCL, SDA
SDA2
l
l
VIH
High Level Input Voltage
SCL, SDA
SDA2
l
l
IINL
Input Current
SCL, SDA = VL or 0V
l
VHYS
Input Hysteresis
SCL, SDA
SDA2
VOH
Output High Voltage
SCL2, ILOAD = –2mA
DO2, ILOAD = –2mA
l
l
VOL
Output Low Voltage
SDA, VL = 3V, ILOAD = 3mA
DO2, VL = 3V, ILOAD = 2mA
SCL2, ILOAD = 2mA
SDA2, No Load, SDA = 0V, 4.5V ≤ VCC2 < 5.5V
SDA2, No Load, SDA = 0V, 3V < VCC2 < 4.5V
l
l
l
l
l
0.3 • VL
0.3 • VCC2
0.7 • VL
0.7 • VCC2
V
V
V
V
±1
0.05 • VL
0.05 • VCC2
µA
mV
mV
VCC2 – 0.4
VL – 0.4
V
V
0.3
0.4
0.4
0.4
0.45
0.55
V
V
V
V
V
CIN
Input Pin Capacitance
SCL, SDA, SDA2 (Note 2)
l
10
pF
CB
Bus Capacitive Load
SCL2, Standard Speed (Note 2)
SCL2, Fast Speed
SDA, SDA2, SR ≥ 1V/μs, Standard Speed (Note 2)
SDA, SDA2, SR ≥ 1V/μs, Fast Speed
l
l
l
l
400
200
400
200
pF
pF
pF
pF
Minimum Bus Slew Rate
SDA, SDA2
l
Short-Circuit Current
SDA2 = 0, SDA = VL
0V ≤ SCL2 ≤ VCC2
0V ≤ DO2 ≤ VL
SDA = 0, SDA2 = VCC2
SDA = VL, SDA2 = 0
l
ISC
1
V/µs
±30
±30
6
–1.8
100
mA
mA
mA
mA
mA
ESD (HBM) (Note 2)
Isolation Boundary
(VCC2, V+, V–, GND2) to (VCC, VL, GND)
±10
kV
Switching Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, and GND =
GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
60
100
ns
Logic
Maximum Data Rate
tPHL, tPLH Propagation Delay
Ix → DOx, CL = 15pF (Note 3)
l
10
CL = 15pF (Figure 1)
l
35
MHz
tR
Rise Time
CL = 15pF (Figure 1)
LTM2883-I, DO2, CL = 15pF (Figure 1)
l
l
3
20
12.5
35
ns
ns
tF
Fall Time
CL = 15pF (Figure 1)
LTM2883-I, DO2, CL = 15pF (Figure 1)
l
l
3
20
12.5
35
ns
ns
Maximum Data Rate
Bidirectional Communication (Note 3)
Unidirectional Communication (Note 3)
l
l
4
8
CL = 15pF (Figure 1)
l
35
SPI
tPHL, tPLH Propagation Delay
tPWU
Output Pulse Width Uncertainty
SDI2, CS2 (Note 2)
–20
MHz
MHz
60
100
ns
50
ns
2883f
5
LTM2883
Switching Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V, VL = 3.3V, and GND =
GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
3
12.5
ns
3
12.5
ns
tR
Rise Time
CL = 15pF (Figure 1)
l
tF
Fall Time
CL = 15pF (Figure 1)
l
tPZH, tPZL Output Enable Time
SDOE = ↓, RL = 1kΩ, CL = 15pF (Figure 2)
l
50
ns
tPHZ, tPLZ Output Disable Time
SDOE = ↑, RL = 1kΩ, CL = 15pF (Figure 2)
l
50
ns
I2C
(Note 3)
l
tPHL, tPLH Propagation Delay
Maximum Data Rate
SCL → SCL2, CL = 15pF (Figure 1)
SDA → SDA2, RL = Open, CL = 15pF (Figure 3)
SDA2 → SDA, RL = 1.1kΩ, CL = 15pF (Figure 3)
l
l
l
tPWU
Output Pulse Width Uncertainty
SDA, SDA2 (Note 2)
tHD;DAT
Data Hold Time
(Note 2)
tR
Rise Time
SDA2, CL = 200pF (Figure 3)
SDA2, CL = 200pF (Figure 3)
SDA, RL = 1.1kΩ, CL = 200pF (Figure 3)
SCL2, CL = 200pF (Figure 1)
l
l
l
SDA2, CL = 200pF (Figure 3)
SDA, RL = 1.1kΩ, CL = 200pF (Figure 3)
SCL2, CL = 200pF (Figure 1)
tF
Fall Time
tSP
Pulse Width of Spikes
Suppressed by Input Filter
400
kHz
150
150
200
–20
225
250
350
ns
ns
ns
50
ns
600
ns
40
40
40
250
300
250
250
ns
ns
ns
ns
l
l
l
40
40
250
250
250
ns
ns
ns
l
0
50
ns
0.6
0.6
0.6
2
2
2.5
ms
ms
ms
TYP
MAX
Power Supply
Power-Up Time
ON = ↑ to VCC2 (Min)
ON = ↑ to V+ (Min)
ON = ↑ to V– (Min)
Isolation Characteristics
l
l
l
TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
MIN
VISO
1 Minute, Derived from 1 Second Test
2500
1 Second (Note 5)
±4400
VIORM
Rated Dielectric Insulation Voltage
UNITS
VRMS
V
Common Mode Transient Immunity
LTM2883-3 VCC = 3.3V, LTM2883-5 VCC = 5V,
VL = ON = 3.3V, VCM = 1kV, ∆t = 33ns (Note 2)
30
kV/µs
Maximum Working Insulation Voltage
(Notes 2, 5)
560
400
VPEAK
VRMS
Partial Discharge
VPD = 1050VPEAK (Notes 2, 5)
Input to Output Resistance
(Notes 2, 5)
Input to Output Capacitance
(Notes 2, 5)
Creepage Distance
(Note 2)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Guaranteed by design and not subject to production test.
Note 3: Maximum data rate is guaranteed by other measured parameters
and is not tested directly.
5
109
pC
Ω
6
pF
9.48
mm
Note 4: This module includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above specified maximum operating junction
temperature may result in device degradation or failure.
Note 5: Device considered a 2-terminal device. Pin group A1 through B8
shorted together and pin group K1 through L8 shorted together.
2883f
6
LTM2883
Typical Performance Characteristics
LTM2883-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.
VCC Supply Current
vs Temperature
30
Isolated Supplies
vs Equal Load Current
Isolated Supplies
vs Equal Load Current
14
NO LOAD, REFRESH DATA ONLY
LTM2883-5
VCC = 5V
15
10
8
6
4
VCC2
V+
V–
2
–25
0
50
25
75
TEMPERATURE (°C)
100
0
125
0
5
10
15
20
LOAD CURRENT (mA)
4.0
3.5
11.5
11.0
10.5
9.5
9.0
40
0
10
20
30
40
LOAD CURRENT (mA)
4.0
3.5
50
10
20
30
LOAD CURRENT (mA)
–13.0
60
2883 G07
10
20
LOAD CURRENT (mA)
12.0
–10.0
LTM2883-5
+
–9.5 ICC2 = I = 0A
11.5
11.0
10.5
9.0
10
20
30
40
LOAD CURRENT (mA)
–10.5
VCC = 4.5V
VCC = 4.75V
VCC = 5V
VCC = 5.5V
–11.0
–11.5
–12.0
VCC = 4.5V
VCC = 4.75V
VCC = 5V
VCC = 5.5V
0
30
V– Line Regulation
vs Load Current
–9.0
9.5
40
0
2883 G06
13.0
10.0
VCC = 4.5V
VCC = 5V
VCC = 5.5V
0
–11.5
–12.5
V– VOLTAGE (V)
V+ VOLTAGE (V)
VCC2 VOLTAGE (V)
4.5
2.5
–11.0
–12.0
LTM2883-5
–
12.5 ICC2 = I = 0A
5.0
30
VCC = 3V
VCC = 3.15V
VCC = 3.3V
VCC = 3.6V
–10.5
V+ Line Regulation
vs Load Current
LTM2883-5
I+ = I– = 0A
25
LTM2883-3
+
–9.5 ICC2 = I = 0A
2883 G05
VCC2 Line Regulation
vs Load Current
3.0
10
15
20
LOAD CURRENT (mA)
–9.0
VCC = 3V
VCC = 3.15V
VCC = 3.3V
VCC = 3.6V
2883 G04
5.5
5
–10.0
10.0
VCC = 3V
VCC = 3.3V
VCC = 3.6V
6.0
0
V– Line Regulation
vs Load Current
V– VOLTAGE (V)
4.5
10
20
30
LOAD CURRENT (mA)
VCC2
V+
V–
2883 G03
12.0
0
4
0
25
LTM2883-3
ICC2 = I– = 0A
12.5
V+ VOLTAGE (V)
VCC2 VOLTAGE (V)
13.0
5.0
2.5
6
V+ Line Regulation
vs Load Current
LTM2883-3
I+ = I– = 0A
3.0
8
2883 G02
VCC2 Line Regulation
vs Load Current
5.5
10
2
2883 G01
6.0
LTM2883-5
VCC = 5V
12
VCC2, V+, |V–| VOLTAGE (V)
20
VCC2, V+, |V–| VOLTAGE (V)
SUPPLY CURRENT (mA)
LTM2883-3
VCC = 3.3V
14
LTM2883-3
VCC = 3.3V
12
25
10
–50
TA = 25°C, LTM2883-3 VCC = 3.3V,
–12.5
50
60
2883 G08
–13.0
0
10
20
30
LOAD CURRENT (mA)
40
2883 G09
2883f
7
LTM2883
Typical Performance Characteristics
LTM2883-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.
V+ Load Regulation
vs Temperature
VCC2 Load Regulation
vs Temperature
12.8
5.20
5.05
5.00
4.90
–50
–25
12.6
25
75
0
50
TEMPERATURE (°C)
100
12.4
LTM2883-3
VCC = 3.3V
ICC2 = I– = 0A
12.2
–50
125
–25
25
75
0
50
TEMPERATURE (°C)
100
–12.5
–12.6
–12.7
–12.8
–50
125
–25
25
75
0
50
TEMPERATURE (°C)
12.7
5.20
LTM2883-5
VCC = 5V
5.15 I+ = I– = 0A
5.05
5.00
–12.2
12.5
I– = 1mA
I– = 20mA
LTM2883-5
VCC = 5V
ICC2 = I+ = 0A
–12.3
V– VOLTAGE (V)
V+ VOLTAGE (V)
5.10
125
V– Load Regulation
vs Temperature
I+ = 1mA
I+ = 5mA
I+ = 10mA
I+ = 15mA
I+ = 20mA
12.6
100
2883 G14
V+ Load Regulation
vs Temperature
VCC2 Load Regulation
vs Temperature
LTM2883-3
VCC = 3.3V
ICC2 = I+ = 0A
–12.4
2883 G12
2883 G10
VCC2 VOLTAGE (V)
I– = 1mA
I– = 15mA
–12.3
12.5
12.3
ICC2 = 1mA
ICC2 = 20mA
–12.2
V– VOLTAGE (V)
5.10
V– Load Regulation
vs Temperature
I+ = 1mA
I+ = 5mA
I+ = 10mA
I+ = 15mA
I+ = 20mA
12.7
V+ VOLTAGE (V)
VCC2 VOLTAGE (V)
LTM2883-3
VCC = 3.3V
5.15 I+ = I– = 0A
4.95
TA = 25°C, LTM2883-3 VCC = 3.3V,
12.4
12.3
–12.4
–12.5
4.95
4.90
–50
ICC2 = 1mA
ICC2 = 20mA
–25
LTM2883-5
VCC = 5V
ICC2 = I– = 0A
12.2
25
75
0
50
TEMPERATURE (°C)
100
125
12.1
–50
–25
0
50
25
75
TEMPERATURE (°C)
100
EFFICIENCY (%)
0.5
5
0.4
4
EFFICIENCY
30
0.3
20
0.2
0
POWER LOSS
I+ = I– = 0A
0
100
125
2883 G15
10
20
30
LOAD CURRENT (mA)
40
2883 G16
150
I+ = I– = 0A
125
VOLTAGE
100
3
75
ICC CURRENT
2
0.1
1
0
0
50
LTM2883-3, VCC = 3.3V
LTM2883-5, VCC = 5V
0
10
20
30
LOAD CURRENT (mA)
40
ICC CURRENT (mA)
6
POWER LOSS (W)
40
0.6
VCC2 VOLTAGE (V)
LTM2883-3, VCC = 3.3V
LTM2883-5, VCC = 5V
10
25
75
0
50
TEMPERATURE (°C)
VCC2 Voltage and ICC Current
vs Load Current
VCC2 Efficiency
50
–25
2883 G13
2883 G11
60
–12.6
–50
125
25
0
2883 G17
2883f
8
LTM2883
Typical Performance Characteristics
LTM2883-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.
V+ Voltage and ICC Current
vs Load Current
V+ Efficiency
LTM2883-3, VCC = 3.3V
LTM2883-5, VCC = 5V
1.0
12
300
10
250
0.8
EFFICIENCY
30
0.6
20
0.4
POWER LOSS
10
0
ICC2 = I– = 0A
0
10
40
20
30
LOAD CURRENT (mA)
50
ICC2 = I– = 0A
VOLTAGE
8
6
150
4
100
0.2
2
0
0
LTM2883-3, VCC = 3.3V
LTM2883-5, VCC = 5V
0
10
20
30
40
LOAD CURRENT (mA)
V– VOLTAGE (V)
EFFICIENCY (%)
0.2
POWER LOSS
0.1
10
0
30
10
20
LOAD CURRENT (mA)
–10.0
240
–10.5
200
ICC CURRENT
–11.0
120
–12.0
80
–13.0
40
VOLTAGE
10
20
LOAD CURRENT (mA)
0
2883 G20
30
0
2883 G21
V+ Transient Response
20mA Load Step
VCC2 Transient Response
20mA Load Step
160
–11.5
–12.5
0
280
ICC CURRENT (mA)
0.3
POWER LOSS (W)
0.4
320
LTM2883-3, VCC = 3.3V
LTM2883-5, VCC = 5V
–9.5
0.5
30
0
–9.0
0.6
EFFICIENCY
20
0
V– Voltage and ICC Current
vs Load Current
LTM2883-3, VCC = 3.3V
LTM2883-5, VCC = 5V
40
50
50
2883 G19
V– Efficiency
50
200
ICC CURRENT
2883 G18
60
350
ICC CURRENT (mA)
40
14
POWER LOSS (W)
EFFICIENCY (%)
50
1.2
V+ VOLTAGE (V)
60
TA = 25°C, LTM2883-3 VCC = 3.3V,
V– Transient Response
20mA Load Step
I+ = 1.5mA
VCC2
100mV/DIV
V+
200mV/DIV
V–
200mV/DIV
ICC2
10mA/DIV
I+
10mA/DIV
I–
10mA/DIV
100µs/DIV
2883 G22
100µs/DIV
2883 G23
100µs/DIV
2883 G24
2883f
9
LTM2883
Typical Performance Characteristics
LTM2883-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.
V+ Ripple
VCC2 Ripple
2mV/DIV
I– = 1mA
5mV/DIV
5mV/DIV
I+ = 20mA
I– = 20mA
500ns/DIV
2883 G26
V+ Noise
VCC2 Noise
2mV/DIV
1ms/DIV
60
3.5
VCC = 5V
ICC2 = I+ = I– = 0
50
40
30
20
2883 G29
Logic Input Threshold
vs VL Supply Voltage
10k
100k
1M
DATA RATE (Hz)
10M
100M
3.0
5.0
2.5
INPUT RISING
2.0
INPUT FALLING
1.5
1.0
2883 G31
0
2883 G30
6.0
VL = 5.5V
VL = 3.3V
VL = 1.62V
4.0
3.0
2.0
1.0
0.5
1k
1ms/DIV
Logic Output Voltage
vs Load Current
OUTPUT VOLTAGE (V)
CL = 1nF
CL = 330pF
CL = 100pF
CL = 20pF
THRESHOLD VOLTAGE (V)
70
2883 G27
2mV/DIV
2883 G28
VCC Supply Current
vs Single Channel Data Rate
500ns/DIV
V– Noise
2mV/DIV
1ms/DIV
VCC CURRENT (mA)
V– Ripple
I+ = 1mA
2883 G25
500ns/DIV
10
TA = 25°C, LTM2883-3 VCC = 3.3V,
1
2
3
4
5
VL SUPPLY VOLTAGE (V)
6
2883 G32
0
0
1
2
3 4 5 6 7
LOAD CURRENT (mA)
8
9
10
2883 G33
2883f
10
LTM2883
Typical Performance Characteristics
LTM2883-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.
TA = 25°C, LTM2883-3 VCC = 3.3V,
VCC2 Cross Regulation
vs V+, V– Load
Power On Sequence
ON
5V/DIV
5.1
12
11
10
5.0
9
4.9
V–
4.8
2883 G34
200µs/DIV
14
LTM2883-3
VCC = 3.3V
13
ICC2 = 15mA
8
VCC2
V+
V–
0
V+, |V–| VOLTAGE (V)
VCC2
VCC2 VOLTAGE (V)
V+
5.2
7
40
10
20
30
LOAD CURRENT (mA)
6
2883 G35
VCC2 Cross Regulation
vs V+, V– Load
5.2
Isolated Supply Efficiency with
Equal Load Current
9
8
4.9
VCC2
V+
V–
0
EFFICIENCY (%)
VCC2 VOLTAGE (V)
10
5.0
0.9
40
0.7
40
EFFICIENCY
0.6
30
0.5
0.4
20
0.3
POWER LOSS
10
7
10
20
30
LOAD CURRENT (mA)
0.8
6
0
0.2
LTM2883-3, VCC = 3.3V 0.1
LTM2883-5, VCC = 5V
0
5
15
25
10
20
LOAD CURRENT (mA)
0
2883 G36
2883 G37
V+ Cross Regulation vs V– Load
14
12
11
10
9
8
V+, I+ = 10mA
V–, I+ = 10mA
V+, I+ = 15mA
V–, I+ = 15mA
7
6
14
0
5
10
15
20
LOAD CURRENT (mA)
LTM2883-5
VCC = 5V
13
V+, |V–| VOLTAGE (V)
V+, |V–| VOLTAGE (V)
V+ Cross Regulation vs V– Load
LTM2883-3
VCC = 3.3V
13
POWER LOSS (W)
11
1.0
50
V+, |V–| VOLTAGE (V)
12
5.1
4.8
60
14
LTM2883-5
VCC = 5V
13
ICC2 = 15mA
12
11
10
9
8
V+, I+ = 10mA
V–, I+ = 10mA
V+, I+ = 15mA
V–, I+ = 15mA
7
25
2883 G38
6
0
5
10
15
20
25
LOAD CURRENT (mA)
30
35
2883 G39
2883f
11
LTM2883
Pin Functions
(LTM2883-I)
Logic Side
DO2 (A1): Digital Output, Referenced to VL and GND. Logic
output connected to I2 through isolation barrier. Under
the condition of an isolation communication failure this
output is in a high impedance state.
DNC (A2): Do Not Connect Pin. Pin connected internally.
SCL (A3): Serial I2C Clock Input, Referenced to VL and
GND. Logic input connected to isolated side SCL2 pin
through isolation barrier. Clock is unidirectional from logic
to isolated side. Do not float.
The logic state on I2 translates to the same logic state on
DO2. Do not float.
DNC (L2): Do Not Connect Pin. Pin connected internally.
SCL2 (L3): Serial I2C Clock Output, Referenced to VCC2
and GND2. Logic output connected to logic side SCL pin
through isolation barrier. Clock is unidirectional from logic
to isolated side. SCL2 has a push-pull output stage, do not
connect an external pull-up device. Under the condition of
an isolation communication failure this output defaults to
a high state.
SDA (A4): Serial I2C Data Pin, Referenced to VL and GND.
Bidirectional logic pin connected to isolated side SDA2 pin
through isolation barrier. Under the condition of an isolation communication failure this pin is in a high impedance
state. Do not float.
SDA2 (L4): Serial I2C Data Pin, Referenced to VCC2 and
GND2. Bidirectional logic pin connected to logic side SDA
pin through isolation barrier. Output is biased high by a
1.8mA current source. Do not connect an external pullup device to SDA2. Under the condition of an isolation
communication failure this output defaults to a high state.
DI1 (A5): Digital Input, Referenced to VL and GND. Logic
input connected to O1 through isolation barrier. The logic
state on DI1 translates to the same logic state on O1. Do
not float.
O1 (L5): Digital Output, Referenced to VCC2 and GND2.
Logic output connected to DI1 through isolation barrier.
Under the condition of an isolation communication failure
O1 defaults to a high state.
GND (A6, B2 to B6): Circuit Ground.
VCC2 (L6): 5V Nominal Isolated Supply Voltage. Internally
generated from VCC by an isolated DC/DC converter and
regulated to 5V. Internally bypassed with 2.2µF.
ON (A7): Enable. Enables power and data communication through the isolation barrier. If ON is high the part is
enabled and power and communications are functional
to the isolated side. If ON is low the logic side is held in
reset, all digital outputs are in a high impedance state, and
the isolated side is unpowered. Do not float.
VL (A8): Logic Supply. Interface supply voltage for pins
DI1, SCL, SDA, DO1, DO2, and ON. Operating voltage is
3V to 5.5V. Internally bypassed with 2.2µF.
DO1 (B1): Digital Output, Referenced to VL and GND. Logic
output connected to I1 through isolation barrier. Under
the condition of an isolation communication failure this
output is in a high impedance state.
VCC (B7 to B8): Supply Voltage. Operating voltage is 3V
to 3.6V for LTM2883-3 and 4.5V to 5.5V for LTM2883-5.
Internally bypassed with 2.2µF.
V– (L7): –12.5V Nominal Isolated Supply Voltage. Internally
generated from VCC by an isolated DC/DC converter and
regulated to –12.5V. Internally bypassed with 1µF.
V+ (L8): 12.5V Nominal Isolated Supply Voltage. Internally
generated from VCC by an isolated DC/DC converter and
regulated to 12.5V. Internally bypassed with 1µF.
I1 (K1): Digital Input, Referenced to VCC2 and GND2.
Logic input connected to DO1 through isolation barrier.
The logic state on I1 translates to the same logic state on
DO1. Do not float.
GND2 (K2 to K5): Isolated Ground.
AVCC2 (K6): 5V Nominal Isolated Supply Voltage Adjust.
The adjust pin voltage is 600mV referenced to GND2.
Isolated Side
AV– (K7): –12.5V Nominal Isolated Supply Voltage Adjust.
The adjust pin voltage is –1.22V referenced to GND2.
I2 (L1): Digital Input, Referenced to VCC2 and GND2.
Logic input connected to DO2 through isolation barrier.
AV+ (K8): 12.5V Nominal Isolated Supply Voltage Adjust.
The adjust pin voltage is 1.22V referenced to GND2.
2883f
12
LTM2883
Pin Functions
(LTM2883-S)
Logic Side
Isolated Side
SDO (A1): Serial SPI Digital Output, Referenced to VL
and GND. Logic output connected to isolated side SDO2
pin through isolation barrier. Under the condition of an
isolation communication failure this output is in a high
impedance state.
SDO2 (L1): Serial SPI Digital Input, Referenced to VCC2
and GND2. Logic input connected to logic side SDO pin
through isolation barrier. Do not float.
DO2 (A2): Digital Output, Referenced to VL and GND. Logic
output connected to I2 through isolation barrier. Under
the condition of an isolation communication failure this
output is in a high impedance state.
SCK (A3): Serial SPI Clock Input, Referenced to VL and
GND. Logic input connected to isolated side SCK2 pin
through isolation barrier. Do not float.
SDI (A4): Serial SPI Data Input, Referenced to VL and GND.
Logic input connected to isolated side SDI2 pin through
isolation barrier. Do not float.
CS (A5): Serial SPI Chip Select, Referenced to VL and GND.
Logic input connected to isolated side CS2 pin through
isolation barrier. Do not float.
SDOE (A6): Serial SPI Data Output Enable, Referenced to
VL and GND. A logic high on SDOE places the logic side
SDO pin in a high impedance state, a logic low enables
the output. Do not float.
ON (A7): Enable. Enables power and data communication through the isolation barrier. If ON is high the part is
enabled and power and communications are functional
to the isolated side. If ON is low the logic side is held in
reset, all digital outputs are in a high impedance state, and
the isolated side is unpowered. Do not float.
VL (A8): Logic Supply. Interface supply voltage for pins
SDI, SCK, SDO, DO1, DO2, CS, and ON. Operating voltage
is 1.62V to 5.5V. Internally bypassed with 2.2µF.
DO1 (B1): Digital Output, Referenced to VL and GND. Logic
output connected to I1 through isolation barrier. Under
the condition of an isolation communication failure this
output is in a high impedance state.
GND (B2 to B6): Circuit Ground.
VCC (B7 to B8): Supply Voltage. Operating voltage is 3V
to 3.6V for LTM2883-3 and 4.5V to 5.5V for LTM2883-5.
Internally bypassed with 2.2µF.
I2 (L2): Digital Input, Referenced to VCC2 and GND2.
Logic input connected to DO2 through isolation barrier.
The logic state on I2 translates to the same logic state on
DO2. Do not float.
SCK2 (L3): Serial SPI Clock Output, Referenced to VCC2
and GND2. Logic output connected to logic side SCK pin
through isolation barrier. Under the condition of an isolation
communication failure this output defaults to a low state.
SDI2 (L4): Serial SPI Data Output, Referenced to VCC2
and GND2. Logic output connected to logic side SDI pin
through isolation barrier. Under the condition of an isolation
communication failure this output defaults to a low state.
CS2 (L5): Serial SPI Chip Select, Referenced to VCC2 and
GND2. Logic output connected to logic side CS pin through
isolation barrier. Under the condition of an isolation communication failure this output defaults to a high state.
VCC2 (L6): 5V Nominal Isolated Supply Voltage. Internally
generated from VCC by an isolated DC/DC converter and
regulated to 5V. Internally bypassed with 2.2µF.
V– (L7): –12.5V Nominal Isolated Supply Voltage. Internally
generated from VCC by an isolated DC/DC converter and
regulated to –12.5V. Internally bypassed with 1µF.
V+ (L8): 12.5V Nominal Isolated Supply Voltage. Internally
generated from VCC by an isolated DC/DC converter and
regulated to 12.5V. Internally bypassed with 1µF.
I1 (K1): Digital Input, Referenced to VCC2 and GND2.
Logic input connected to DO1 through isolation barrier.
The logic state on I1 translates to the same logic state on
DO1. Do not float.
GND2 (K2 to K5): Isolated Ground.
AVCC2 (K6): 5V Nominal Isolated Supply Voltage Adjust.
The adjust pin voltage is 600mV Referenced to GND2.
AV– (K7): –12.5V Nominal Isolated Supply Voltage Adjust.
The adjust pin voltage is –1.22V Referenced to GND2.
AV+ (K8): 12.5V Nominal Isolated Supply Voltage Adjust.
The adjust pin voltage is 1.22V Referenced to GND2.
2883f
13
LTM2883
Block Diagram
REG
VCC
VL
110k
2.2µF
2.2µF
2.2µF
VCC2
AVCC2
15k
GND2
GND
REG
150k
1µF
AV+
16.2k
REG
DC/DC
CONVERTER
16.2k
150k
ON
1µF
REG
ISOLATED
COMMUNICATIONS
INTERFACE
DI1
SDA
V+
AV–
V–
ISOLATED
COMMUNICATIONS
INTERFACE
O1
SDA2
SCL
SCL2
DO2
I2
DO1
I1
2882 BDa
LTM2883-I
REG
VCC
VL
110k
2.2µF
2.2µF
2.2µF
AVCC2
15k
GND2
GND
REG
150k
1µF
REG
DC/DC
CONVERTER
16.2k
150k
ON
REG
SDOE
SDI
SCK
ISOLATED
COMMUNICATIONS
INTERFACE
V+
AV+
16.2k
CS
VCC2
ISOLATED
COMMUNICATIONS
INTERFACE
1µF
AV–
V–
CS2
SDI2
SCK2
DO2
I2
SDO
SDO2
DO1
I1
2883 BDb
LTM2883-S
2883f
14
LTM2883
Test Circuits
INPUT
0V
OUTPUT
CL
INPUT
VL
OUTPUT
CL
INPUT
OUTPUT
90%
tPHL
10%
½VCC2
10%
90%
tR
tF
VCC2
0V
OUTPUT
tPLH
VOH
VOL
INPUT
½VL
½VCC2
tPLH
VOH
VOL
90%
tPHL
10%
½VL
10%
90%
tR
tF
2883 F01
Figure 1. Logic Timing Measurements
VL OR 0V
VL
SDOE
RL
0V
SDO2 OR
VCC2
SDO
CL
½VL
0V
SDO
SDOE
SDO
tPZH
VOH
tPHZ
VOH – 0.5V
½VL
0V
VL
tPLZ
tPZL
½VL
VOL
VOL + 0.5V
2883 F02
Figure 2. Logic Enable/Disable Time
VL
RL
SDA
0V
SDA2
CL
SDA
VL
SDA2
½VL
tPHL
VOH
VOL
½VCC2
tPLH
30%
70%
70%
30%
tF
tR
VL
RL
SDA2
0V
SDA
CL
VCC2
SDA2
SDA
½VCC2
tPHL
VOH
VOL
½VL
tPLH
70%
30%
70%
tF
30%
tR
2883 F03
Figure 3. I2C Timing Measurements
2883f
15
LTM2883
Applications Information
Overview
Performance of the –12.5V supply is enhanced by loading
the 12.5V supply. A load current of 1.5mA is sufficient to
improve static and dynamic load regulation characteristics
of the –12.5V output. The increased load allows the boost
regulator to operate continuously and in turn improves the
regulation of the inverting charge pump.
The LTM2883 digital µModule isolator provides a galvanically-isolated robust logic interface, powered by an
integrated, regulated DC/DC converter, complete with
decoupling capacitors. The LTM2883 is ideal for use in
networks where grounds can take on different voltages.
Isolation in the LTM2883 blocks high voltage differences,
eliminates ground loops and is extremely tolerant of common mode transients between ground planes. Error-free
operation is maintained through common mode events
greater than 30kV/μs providing excellent noise isolation.
The internal power solution is sufficient to provide a minimum of 20mA of current from VCC2 and V+, and 15mA
from V–. VCC and VCC2 are each bypassed with 2.2µF
ceramic capacitors, and V+ and V– are bypassed with 1µF
ceramic capacitors.
Isolator µModule Technology
VL Logic Supply
The LTM2883 utilizes isolator µModule technology to
translate signals and power across an isolation barrier.
Signals on either side of the barrier are encoded into
pulses and translated across the isolation boundary using
coreless transformers formed in the µModule substrate.
This system, complete with data refresh, error checking,
safe shutdown on fail, and extremely high common mode
immunity, provides a robust solution for bidirectional
signal isolation. The µModule technology provides the
means to combine the isolated signaling with multiple
regulators and a powerful isolated DC/DC converter in
one small package.
A separate logic supply pin VL allows the LTM2883 to interface with any logic signal from 1.62V to 5.5V as shown
in Figure 4. Simply connect the desired logic supply to VL.
The LTM2883 contains a fully integrated DC/DC converter,
including the transformer, so that no external components
are necessary. The logic side contains a full-bridge driver,
running at 2MHz, and is AC-coupled to a single transformer primary. A series DC blocking capacitor prevents
transformer saturation due to driver duty cycle imbalance.
The transformer scales the primary voltage, and is rectified by a full-wave voltage doubler. This topology allows
for a single diode drop, as in a center tapped full-wave
bridge, and eliminates transformer saturation caused by
secondary imbalances.
3V TO 3.6V LTM2883-3
4.5V TO 5.5V LTM2883-5
LTM2883-S
VCC2
VCC
AVCC2
V+
ANY VOLTAGE FROM
1.62V TO 5.5V
AV+
VL
ON
SDOE
CS
SDI
EXTERNAL
DEVICE
SCK
V–
ISOLATION BARRIER
DC/DC Converter
There is no interdependency between VCC and VL; they
may simultaneously operate at any voltage within their
specified operating ranges and sequence in any order. VL
is bypassed internally by a 2.2µF capacitor.
AV–
CS2
SDI2
SCK2
DO2
I2
SDO
SDO2
DO1
I1
GND
GND2
2883 F04
Figure 4. VCC and VL Are Independent
The DC/DC converter is connected to a low dropout regulator (LDO) to provide a regulated 5V output.
Hot-Plugging Safely
An integrated boost converter generates a regulated 14V
supply and a charge pumped –14V supply. These rails are
regulated to ±12.5V respectively by low dropout regulators.
Caution must be exercised in applications where power
is plugged into the LTM2883’s power supplies, VCC or VL,
due to the integrated ceramic decoupling capacitors. The
16
2883f
LTM2883
Applications Information
parasitic cable inductance along with the high Q characteristics of ceramic capacitors can cause substantial
ringing which could exceed the maximum voltage ratings
and damage the LTM2883. Refer to Linear Technology Application Note 88, entitled Ceramic Input Capacitors Can
Cause Overvoltage Transients for a detailed discussion
and mitigation of this phenomenon.
The three isolated power rails may be adjusted by connection of a single resistor from the adjust pin of each
output to its associated output voltage or to GND2. The
pre-configured voltages represent the maximums for
guaranteed performance. Figure 5 illustrates configuration of the output power rails for VCC2 = 3.3V, V+ = 10V,
and V– = –10V.
LTM2883-5S
5V
VCC2
AVCC2
AV+
ON
CS
SDI
SCK
AV–
530k
3.3V
10V
–10V
CS2
SDI2
SCK2
DO2
I2
SDO
SDO2
DO1
I1
GND
530k
V–
ISOLATION BARRIER
SDOE
174k
V+
VL
OUTPUT
VOLTAGE
RESISTOR (Ax TO Vx) TO
REDUCE OUTPUT
GND2
RESISTOR (Ax TO GND2) TO
INCREASE OUTPUT
110k • ( VCC2 – 0.6 )
VCC2
66k
VCC2 – 5
5 – VCC2
(
150k • V + ,V – – 1.22
V+, V–
Isolated Supply Adjustable Operation
VCC
Table 1. Voltage Adjustment Formula
+
12.5 – V ,V
)
–
183k
+
V ,V – – 12.5
Channel Timing Uncertainty
Multiple channels are supported across the isolation boundary by encoding and decoding of the inputs and outputs. Up
to three signals in each direction are assembled as a serial
packet and transferred across the isolation barrier. The time
required to transfer all 3 bits is 100ns maximum, and sets
the limit for how often a signal can change on the opposite
side of the barrier. Encoding transmission is independent
for each data direction. The technique used assigns SCK or
SCL on the logic side, and SDO2 or I2 on the isolated side,
the highest priority such that there is no jitter on the associated output channels, only delay. This preemptive scheme
will produce a certain amount of uncertainty on the other
isolation channels. The resulting pulse width uncertainty on
these low priority channels is typically ±6ns, but may vary
up to ±44ns if the low priority channels are not encoded
within the same high priority serial packet.
Serial Peripheral Interface (SPI) Bus
2883 F05
Figure 5. Adjustable Voltage Rails
To decrease the output voltage a resistor must be connected
from the output voltage pin to the associated adjust pin.
To increase the output voltage connect a resistor to the
adjust pin to GND2. Use the equations listed in Table 1
to calculate the resistances required to adjust each output.
The output voltage adjustment range for VCC2 is 3V to 5.5V.
Adjustment range for V+ and V– is ±1.22V to approximately
±13.5V. Operation at low output voltages for V+ or V– may
result in thermal shutdown due to low dropout regulator
power dissipation.
The LTM2883-S provides a SPI compatible isolated interface. The maximum data rate is a function of the inherent
channel propagation delays, channel to channel pulse
width uncertainty, and data direction requirements. Channel timing is detailed in Figures 5 through 8 and Tables
3 and 4. The SPI protocol supports four unique timing
configurations defined by the clock polarity (CPOL) and
clock phase (CPHA) summarized in Table 2.
Table 2. SPI Mode
CPOL
CPHA
DATA TO (CLOCK) RELATIONSHIP
0
0
Sample (Rising)
Set-Up (Falling)
0
1
Set-Up (Rising)
Sample (Falling)
1
0
Sample (Falling)
Set-Up (Rising)
1
1
Set-Up (Falling)
Sample (Rising)
2883f
17
LTM2883
Applications Information
The maximum data rate for bidirectional communication
is 4MHz, based on a synchronous system, as detailed in
the timing waveforms. Slightly higher data rates may be
achieved by skewing the clock duty cycle and minimizing the SDO to SCK set-up time, however the clock rate
is still dominated by the system propagation delays. A
discussion of the critical timing paths relative to Figure 6
and 7 follows.
• CS to SCK (master sample SDO, 1st SDO valid)
t0 → t1
≈50ns, CS to CS2 propagation delay
t1 → t1+ Isolated slave device propagation
(response time), asserts SDO2
t1 → t3
≈50ns, SDO2 to SDO propagation delay
t3 → t5
Set-up time for master SDO to SCK
CPHA = 0
CS = SDOE
CS2
SDI
SDI2
SCK (CPOL = 0)
SCK2 (CPOL = 0)
SCK (CPOL = 1)
SCK2 (CPOL = 1)
INVALID
SDO
SDO2
t0
t1 t2
t3 t4
t5
t6
t7
t8
t9
t10
t11 t12
t13
t14
t15
t17
t18
2883 F06
Figure 6. SPI Timing, Bidirectional, CPHA = 0
CPHA = 1
CS = SDOE
CS2
SDI
SDI2
SCK (CPOL = 0)
SCK2 (CPOL = 0)
SCK (CPOL = 1)
SCK2 (CPOL = 1)
INVALID
SDO
SDO2
t0
t1 t2
t3 t4
t5
t6
t7
t8
t9
t10
t11 t12
t13
t14
t15
t16 t17
t18
2883 F07
Figure 7. SPI Timing, Bidirectional, CPHA = 1
2883f
18
LTM2883
Applications Information
• SDI to SCK (master data write to slave)
t2 → t4
≈50ns, SDI to SDI2 propagation delay
t5 → t6
≈50ns, SCK to SCK2 propagation delay
t2 → t5
≥50ns, SDI to SCK, separate packet
non-zero set-up time
t4 → t6
≥50ns, SDI2 to SCK2, separate packet
non-zero set-up time
• SDO to SCK (master sample SDO, subsequent
SDO valid)
t8
set-up data transition SDI and SCK
t8 → t10 ≈50ns, SDI to SDI2 and SCK to SCK2
propagation delay
t10
SDO2 data transition in response to SCK2
t10 → t11 ≈50ns, SDO2 to SDO propagation delay
t11 → t12 Set-up time for master SDO to SCK
Table 3. Bidirectional SPI Timing Event Description
TIME
CPHA
EVENT DESCRIPTION
t0
0, 1
Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. Logic side slave data output
enabled, initial data is not equivalent to slave device data output
t0 to t1, t17 to t18
0, 1
Propagation delay chip select, logic to isolated side, 50ns typical
t1
0, 1
Slave device chip select output data enable
t2
0
Start of data transmission, data set-up
1
Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge
t1 to t3
0, 1
Propagation delay of slave data, isolated to logic side, 50ns typical
t3
0, 1
Slave data output valid, logic side
t2 to t4
0
Propagation delay of data, logic side to isolated side
1
Propagation delay of data and clock, logic side to isolated side
t5
0, 1
Logic side data sample time, half clock period delay from data set-up transition
t5 to t6
0, 1
Propagation delay of clock, logic to isolated side
t6
0, 1
Isolated side data sample time
t8
0, 1
Synchronous data and clock transition, logic side
t7 to t8
0, 1
Data to clock delay, must be ≤13ns
t8 to t9
0, 1
Clock to data delay, must be ≤3ns
t8 to t10
0, 1
Propagation delay clock and data, logic to isolated side
t10, t14
0, 1
Slave device data transition
t10 to t11, t14 to t15
0, 1
Propagation delay slave data, isolated to logic side
t11 to t12
0, 1
Slave data output to sample clock set-up time
t13
t13 to t14
t15
t15 to t16
0
Last data and clock transition logic side
1
Last sample clock transition logic side
0
Propagation delay data and clock, logic to isolated side
1
Propagation delay clock, logic to isolated side
0
Last slave data output transition logic side
1
Last slave data output and data transition, logic side
1
Propagation delay data, logic to isolated side
t17
0, 1
Asynchronous chip select transition, end of transmission. Disable slave data output logic side
t18
0, 1
Chip select transition isolated side, slave data output disabled
2883f
19
LTM2883
Applications Information
Maximum data rate for single direction communication,
master to slave, is 8MHz, limited by the systems encoding/decoding scheme or propagation delay. Timing details
for both variations of clock phase are shown in Figures 8
and 9 and Table 4.
• SDI and SCK set-up data transition occur within the
same data packet. Referencing Figure 6, SDI can precede SCK by up to 13ns (t7 → t8) or lag SCK by 3ns
(t8 → t9) and not violate this requirement. Similarly in
Figure 8, SDI can precede SCK by up to 13ns (t4 → t5)
or lag SCK by 3ns (t5 → t6).
Additional requirements to insure maximum data rate
are:
Inter-IC Communication (I2C) Bus
• CS is transmitted prior to (asynchronous) or within the
same (synchronous) data packet as SDI
The LTM2883-I provides an I2C compatible isolated interface, Clock (SCL) is unidirectional, supporting master mode
only, and data (SDA) is bidirectional. The maximum data
CPHA = 0
CS = SDOE
CS2
SDI
SDI2
SCK (CPOL = 0)
SCK2 (CPOL = 0)
SCK (CPOL = 1)
SCK2 (CPOL = 1)
t0
t1 t2
t3
t4 t5
t6
t7
t8
t9
t11
t12
2883 F08
Figure 8. SPI Timing, Unidirectional, CPHA = 0
CPHA = 1
CS = SDOE
CS2
SDI
SDI2
SCK (CPOL = 0)
SCK2 (CPOL = 0)
SCK (CPOL = 1)
SCK2 (CPOL = 1)
t0
t1 t2
t3
t4 t5
t6
t7
t8
t9
t10 t11
t12
2883 F09
Figure 9. SPI Timing, Unidirectional, CPHA = 1
2883f
20
LTM2883
Applications Information
Table 4. Unidirectional SPI Timing Event Description
TIME
CPHA
EVENT DESCRIPTION
t0
0, 1
Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns
t0 to t1
0, 1
Propagation delay chip select, logic to isolated side
t2
t2 to t3
0
Start of data transmission, data set-up
1
Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge
0
Propagation delay of data, logic side to isolated side
1
Propagation delay of data and clock, logic side to isolated side
t3
0, 1
Logic side data sample time, half clock period delay from data set-up transition
t3 to t5
0, 1
Clock propagation delay, clock and data transition
t4 to t5
0, 1
Data to clock delay, must be ≤13ns
t5 to t6
0, 1
Clock to data delay, must be ≤3ns
t5 to t7
0, 1
Data and clock propagation delay
t8
t8 to t9
t9 to t10
0
Last clock and data transition
1
Last clock transition
0
Clock and data propagation delay
1
Clock propagation delay
1
Data propagation delay
t11
0, 1
Asynchronous chip select transition, end of transmission
t12
0, 1
Chip select transition isolated side
rate is 400kHz which supports fast-mode I2C. Timing is
detailed in Figure 10. The data rate is limited by the slave
acknowledge setup time (tSU;ACK), consisting of the I2C
standard minimum setup time (tSU;DAT) of 100ns, maximum
clock propagation delay of 225ns, glitch filter and isolated
data delay of 350ns maximum, and the combined isolated
and logic data fall time of 500ns at maximum bus loading. The total setup time reduces the I2C data hold time
(tHD;DAT) to a maximum of 125ns, guaranteeing sufficient
data setup time (tSU;ACK).
The isolated side bidirectional serial data pin, SDA2,
simplified schematic is shown in Figure 11. An internal
1.8mA current source provides a pull-up for SDA2. Do not
connect any other pull-up device to SDA2. This current
source is sufficient to satisfy the system requirements for
bus capacitances greater than 200pF in FAST mode and
greater than 400pF in STANDARD mode.
Additional proprietary circuitry monitors the slew rate on
the SDA and SDA2 signals to manage directional control
across the isolation barrier. Slew rates on both pins must
be greater than 1V/μs for proper operation.
The logic side bidirectional serial data pin, SDA, requires a
pull-up resistor or current source connected to VL. Follow
SLAVE ACK
SDA
SDA2
SCL
1
8
9
SCL2
START
tPROP
tSU;DAT
tHD;DAT
tSU;ACK
STOP
2883 F10
Figure 10. I2C Timing Diagram
2883f
21
LTM2883
Applications Information
TO
LOGIC
SIDE
GLITCH FILTER
1.8mA
SDA2
FROM
LOGIC
SIDE
2883 F11
Figure 11. Isolated SDA2 Pin Schematic
the requirements in Figures 12 and 13 for the appropriate pull-up resistor on SDA that satisfies the desired rise
time specifications and VOL maximum limits for FAST and
STANDARD modes. The resistance curves represent the
maximum resistance boundary; any value may be used
to the left of the appropriate curve.
30
V = 3V
V = 3.3V
V = 3.6V
V = 4.5V TO 5.5V
RPULL_UP (kΩ)
25
20
15
10
5
0
10
100
CBUS (pF)
1000
2883 F12
Figure 12. Maximum Standard Speed Pull-Up Resistance on SDA
10
V = 3V
V = 3.3V
V = 3.6V
V = 4.5V TO 5.5V
9
RPULL_UP (kΩ)
8
The isolated side clock pin, SCL2, has a weak push-pull
output driver; do not connect an external pull-up device.
SCL2 is compatible with I2C devices without clock stretching. On lightly loaded connections, a 100pF capacitor
from SCL2 to GND2 or RC low-pass filter (R = 500Ω C =
100pF) can be used to increase the rise and fall times and
minimize noise.
Some consideration must be given to signal coupling
between SCL2 and SDA2. Separate these signals on a
printed circuit board or route with ground between. If
these signals are wired off board, twist SCL2 with VCC2
and/or GND2 and SDA2 with GND2 and/or VCC2, do not
twist SCL2 and SDA2 together. If coupling between SCL2
and SDA2 is unavoidable, place the aforementioned RC
filter at the SCL2 pin to reduce noise injection onto SDA2.
RF, Magnetic Field Immunity
The isolator µModule technology used within the LTM2883
has been independently evaluated, and successfully passed
the RF and magnetic field immunity testing requirements
per European Standard EN 55024, in accordance with the
following test standards:
EN 61000-4-3
Radiated, Radio-Frequency,
Electromagnetic Field Immunity
EN 61000-4-8
Power Frequency Magnetic Field
Immunity
EN 61000-4-9
Pulsed Magnetic Field Immunity
Tests were performed using an unshielded test card designed per the data sheet PCB layout recommendations.
Specific limits per test are detailed in Table 5.
7
Table 5.
6
TEST
5
EN 61000-4-3 Annex D
4
3
2
1
0
10
100
CBUS (pF)
1000
2883 F13
FREQUENCY
FIELD STRENGTH
80MHz to 1GHz
10V/m
1.4MHz to 2GHz
3V/m
2GHz to 2.7GHz
1V/m
EN 61000-4-8 Level 4
50Hz and 60Hz
30A/m
EN 61000-4-8 Level 5
60Hz
100A/m*
EN 61000-4-9 Level 5
Pulse
1000A/m
*non IEC method
Figure 13. Maximum Fast Speed Pull-Up Resistance on SDA
2883f
22
LTM2883
Applications Information
PCB Layout
The high integration of the LTM2883 makes PCB layout
very simple. However, to optimize its electrical isolation
characteristics, EMI, and thermal performance, some
layout considerations are necessary.
• Under heavily loaded conditions VCC and GND current
can exceed 300mA. Sufficient copper must be used
on the PCB to insure resistive losses do not cause the
supply voltage to drop below the minimum allowed
level. Similarly, the VCC2 and GND2 conductors must
be sized to support any external load current. These
heavy copper traces will also help to reduce thermal
stress and improve the thermal conductivity.
• Input and output decoupling is not required, since these
components are integrated within the package. An additional bulk capacitor with a value of 6.8µF to 22µF is
recommended. The high ESR of this capacitor reduces
board resonances and minimizes voltage spikes caused
by hot plugging of the supply voltage. For EMI sensitive
applications, an additional low ESL ceramic capacitor of
1µF to 4.7µF, placed as close to the power and ground
terminals as possible, is recommended. Alternatively, a
number of smaller value parallel capacitors may be used
to reduce ESL and achieve the same net capacitance.
any high frequency differential voltages and substantially
reducing radiated emissions. Discrete capacitance will
not be as effective due to parasitic ESL. In addition, voltage rating, leakage, and clearance must be considered
for component selection. Embedding the capacitance
within the PCB substrate provides a near ideal capacitor
and eliminates component selection issues; however,
the PCB must be 4 layers. Care must be exercised in
applying either technique to insure the voltage rating
of the barrier is not compromised.
The PCB layout in Figures 14a and 14b shows the low
EMI demo board for the LTM2883. The demo board uses
a combination of EMI mitigation techniques, including
both embedded PCB bridge capacitance and discrete GND
to GND2 capacitors. Two safety rated type Y2 capacitors
are used in series, manufactured by MuRata, part number
GA342QR7GF471KW01L. The embedded capacitor effectively suppresses emissions above 400MHz, whereas
the discrete capacitors are more effective below 400MHz.
EMI performance is shown in Figure 15, measured using
a Gigahertz Transverse Electromagnetic (GTEM) cell and
method detailed in IEC 61000-4-20, Testing and Measurement Techniques – Emission and Immunity Testing in
Transverse Electromagnetic Waveguides.
• Do not place copper on the PCB between the inner columns of pads. This area must remain open to withstand
the rated isolation voltage.
• The use of solid ground planes for GND and GND2
is recommended for non-EMI critical applications to
optimize signal fidelity, thermal performance, and to
minimize RF emissions due to uncoupled PCB trace
conduction. The drawback of using ground planes,
where EMI is of concern, is the creation of a dipole
antenna structure which can radiate differential voltages
formed between GND and GND2. If ground planes are
used it is recommended to minimize their area, and
use contiguous planes as any openings or splits can
exacerbate RF emissions.
• For large ground planes a small capacitance (≤330pF)
from GND to GND2, either discrete or embedded within
the substrate, provides a low impedance current return
path for the module parasitic capacitance, minimizing
TECHNOLOGY
Figure 14a. LTM2883 Low EMI Demo Board Layout
2883f
23
LTM2883
Applications Information
Top Layer
Inner Layer 2
Inner Layer 1
Bottom Layer
Figure 14b. LTM2883 Low EMI Demo Board Layout (DC1748A)
2883f
24
LTM2883
Applications Information
60
50
CISPR 22 CLASS B LIMIT
40
dBµV/m
30
DC1748A-B
20
10
DC1748A-A
0
DETECTOR = QuasiPeak
RBW = 120kHz
VBW = 300kHz
SWEEP TIME = 17s
# OF POINTS = 501
–10
–20
–30
0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
2883 F15
Figure 15. LTM2883 Low EMI Demo Board Emissions
Typical Applications
0.1µF
B8
5V
A8
1µF
LTM2883-5I
VCC
VL
A7
VCC
A5
SDA
µC
A6
SCL
GND
A4
A3
A2
A1
B1
B2
AV+
V–
K8
L7
K7
AV–
1.7k
1.7k
12.5V
L8
V+
ON
GND
DI1
VCC2
AVCC2
O1
SDA
SDA2
SCL
SCL2
DNC
DNC
DO2
I2
DO1
I1
GND
GND2
L6
1µF
12.5V
3
–12.5V
2
5V
+
8
1/2 LTC2055
–
K6
1
7
8
9
–
10
4
LTC2631A-LM12, DAC
1
8
CA0 R_SEL
2
7
VOUT
SCL
3
6
SDA
REF
4
5
VCC
GND
L4
L3
L2
L1
K1
K2
1.25V
2
5
6
2883 F16
0.1µF
10
11
12
1
2
3
VDD
GND
AD0
REFC
AD1
VREF
GND
IN–
SDA
IN+
SCL
GND
+
5
4
±10V OUT
0.1µF
–12.5V
+
1/2 LTC2055
7
–
0.1µF
2.5V
LTC2301, ADC
0.1µF
3
2.5V F.S.
6
LT1991
G=8
1
L5
0.1µF
12.5V
9
8
7
6
7
10µF
0.1µF
6
5
4
1µF
4V F.S.
8
–
LT1991
G = 0.2
0.1µF
5
9
10
1
+
2
±10V IN
3
4
–12.5V
Figure 16. Isolated I2C 12-Bit, ±10V Analog Input and Output
2883f
25
LTM2883
Typical Applications
B8
3.3V
A8
10k
1nF
Cx
CLR
B
A7
A6
A
A5
Q
A4
A3
A2
VCC
A1
CSA
B1
CSB
B2
µC MOSI
VL
74VC1G123
Rx/Cx
1µF
LTM2883-3S
VCC
V+
AV
L8
+ K8
V–
L7
K7
AV–
ON
SDOE
VCC2
AVCC2
CS
CS2
SDI
SDI2
SCK
SCK2
DO2
I2
SDO
SDO2
DO1
I1
GND
GND2
L6
K6
L5
L4
L3
L2
L1
K1
CSB
CSA
MOSI
SCK
MISO
K2
2883 F17
SCK
MISO
GND
CSA
CSB
MOSI
SCK
Figure 17. Isolated SPI Device Expansion
2883f
26
LTM2883
Typical Applications
B8
5V
A8
10k
10k
A7
A6
ENABLE
SDA
SCLIN
A5
A4
A3
A2
A1
B1
B2
LTM2883-5I
VCC
VL
V+
AV
L8
+ K8
V–
L7
K7
AV–
ON
GND
DI1
VCC2
AVCC2
O1
SDA
SDA2
SCL
SCL2
DNC
DNC
DO2
I2
DO1
I1
GND
GND2
L6
K6
L5
8.66k
10k
L4
1
L3
2
L2
3
L1
4
K1
5
K2
137Ω
SDAIN
SDAOUT
SCLIN
SCLOUT
CONN LTC4302-1
VCC
ADDR
GPIO2
GND
GPIO1
10
9
8
7
6
10k
SDA
SCLOUT
GPIO2
GPIO1
2883 F18
Figure 18. Isolated I2C Buffer with Programmable Outputs
2883f
27
LTM2883
Typical Applications
B8
5V
A8
1µF
A7
A6
VCC
A5
Oz
A4
Oy
µC
A3
Ox
A2
A1
Iy
B1
GND Ix
B2
LTM2883-5S
V+
VCC
AV
VL
L8
+ K8
V–
L7
K7
AV–
VCC2
ON
SDOE
AVCC2
CS
CS2
SDI
SDI2
SCK
SCK2
DO2
I2
SDO
SDO2
DO1
I1
GND
GND2
NTC THERMISTORS, MURATA NTSD1WD104, 100k
L6
K6
L3
L2
LTC1799
5
L1
K1
4
K2
OUT
V+
GND
DIV
SET
1
2
3
1M
3.01k
3
11
10
6
7
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
110
120
1.23
1.46
1.87
2.58
3.77
5.67
8.64
13.09
19.53
28.47
40.65
55.87
74.45
96.08
119.83
144.73
169.36
–t°
DG4051A
16
9
FREQUENCY (kHz)
–t°
–t°
L4
2883 F19
TEMPERATURE (°C)
–t°
–t°
L5
8
VCC
X0
X
X1
A
X2
B
X3
C
X4
ENABLE X5
VEE
X6
GND
X7
–t°
–t°
–t°
13
14
15
12
1
5
2
4
–t°
–t°
–t°
–t°
LTC1799
5
4
OUT
V+
GND
DIV
SET
1
2
3
1M
3.01k
DG4051A
16
3
11
10
9
6
7
8
VCC
X0
X
X1
A
X2
B
X3
C
X4
ENABLE X5
VEE
X6
GND
X7
13
–t°
–t°
–t°
–t°
14
15
12
1
5
2
4
Figure 19. 16-Channel Isolated Temperature to Frequency Converter
2883f
28
LTM2883
Typical Applications
IRF7509
100k
5V
B8
A8
A7
A6
–12.5V ENABLE
12.5V ENABLE
5V ENABLE
12.5V UV
–12.5V UV
5V UV
A5
A4
A3
A2
A1
B1
B2
SWITCHED 12.5V
LTM2883-5S
VCC
VL
V+
AV
V–
AV–
ON
SDOE
CS
L8
IRF7509
+ K8
VCC2
AVCC2
CS2
SDI
SDI2
SCK
SCK2
DO2
I2
SDO
SDO2
DO1
I1
GND
GND2
100k
L7
SWITCHED –12.5V
K7
L6
IRF7509
K6
L5
100k
IRLML2402
100k
L4
SWITCHED 5V
L3
L2
226k
L1
K1
K2
LTC2902
2883 F20
1
2
3
0.1µF
4
10k
5
6
7
8
COMP3
COMP2
COMP1
COMP4
V3
V2
V1
V4
CRT
VREF
RST
VPG
T0
GND
RDIS
T1
16
15
196k
14
13
12
11
10
9
20k
93.1k
9.53k
Figure 20. Digitally Switched Triple Power Supply with Undervoltage Monitor
2883f
29
LTM2883
Typical Applications
0.1µF
12.5V
7
8
9
10
–
LT1991
G=8
1
2
3
+
4
5
6
±10V OUTA
0.1µF
–12.5V
0.1µF
5V
B8
3.3V
1µF
A8
A7
A6
VCC
CS
MOSI
µC
SCK
MISO
GND
A5
A4
A3
A2
A1
B1
B2
0.1µF
LTM2883-3S
VCC
VL
V+
AV
+ K8
V–
AV–
ON
SDOE
CS
L8
VCC2
AVCC2
CS2
SDI
SDI2
SCK
SCK2
DO2
I2
SDO
SDO2
DO1
I1
GND
GND2
L7
K7
12.5V
LTC2654-L16
L6
15
K6
6
L5
7
L4
9
L3
8
L2
11
L1
10
K1
12
K2
1.25V
–12.5V
VCC
LDAC
CS
REFOUT
REFC
VOUTA
SDI
VOUTB
SCK
VOUTC
CLR
VOUTD
SDO
REFLO
PORSEL
GND
5
3
4
+
5
LTC2054
–
0.1µF
12.5V
7
8
1
2
9
10
3
2
LT1991
G=8
1
2
3
–
+
4
4
5
6
±10V OUTB
0.1µF
–12.5V
13
14
1
16
0.1µF
0.1µF
12.5V
7
8
2883 F21
9
10
–
LT1991
G=8
1
2
3
+
4
5
6
±10V OUTC
0.1µF
–12.5V
0.1µF
12.5V
7
8
9
10
–
LT1991
G=8
1
2
3
+
4
5
6
±10V OUTD
0.1µF
–12.5V
Figure 21. Quad 16-Bit ±10V Output Range DAC
2883f
30
LTM2883
Typical Applications
B8
5V
A8
1µF
LTM2883-5I
AV
VL
A7
10k
A6
A5
Ox
µC
A4
SDA
A3
SCL
A2
Ix
A1
GND
B1
B2
+ K8
L7
V–
K7
AV–
10k
VCC
L8
V+
VCC
L6
VCC2
ON
K6
AVCC2
GND
L5
O1
DI1
SDA
SDA2
SCL
SCL2
DNC
DNC
DO2
I2
DO1
I1
GND
GND2
L4
L3
10k
L2
L1
K1
K2
VEE
–48V RTN
1k, ×4 IN SERIES
1/4W EACH
453k
8
9
16.9k
10
11
19
20
26
1
25
24
11.8k
7
1µF
47nF
–48V INPUT
VEE
10k
FLTIN
SCL
ADIN2
SDAI
SDAO
OV
ALERT
SS
LTC4261CGN
TMR
ON
EN
PGI
PGI0
ADR1
PG
ADR0
ADIN
VEE
SENSE
GATE
DRAIN RAMP
14
15
16
220nF
0.1µF
VIN
UVH
13
100nF
21
INTVCC
UVL
0.1µF
47nF
0.008Ω
1%
10Ω
22
6
5
4
3
2
28
PWRGD2
27
PWRGD1
23
18
1M
+
1k
10nF
100V
IRF1310NS
330µF
100V
VOUT
402k
2883 F22
Figure 22. –48V, 200W Hot Swap Controller with Isolated I2C Interface
2883f
31
LTM2883
Typical Applications
3.3V
B8
1µF
A8
A7
A6
VCC
CS
µC
MOSI
SCK
MISO
GND
A5
A4
A3
A2
A1
B1
B2
LTM2883-3S
VCC
VL
V+
AV
L8
+ K8
3.3k
3.3k
3.3k
3.3k
43
L7
V–
42
L6
40
K6
39
41
K7
AV–
ON
SDOE
44
VCC2
AVCC2
CS
CS2
SDI
SDI2
SCK
SCK2
DO2
I2
SDO
SDO2
DO1
I1
GND
GND2
L5
1µF
1µF
38
L4
37
L3
36
L2
35
L1
34
K1
K2
74LVC3G07
100k
100k
33
32
31
2883 F23
30
100k
100k
29
28
27
26
25
24
23
LTC6803-1
CSI
CSO
SDO
SDOI
SDI
SCKO
SCKI
1
2
3
+ 4
V
VMODE
C12
GPIO2
S12
GPIO1
C11
WDT
S11
MM
C10
TOS
S10
VREG
C9
VREF
S9
VTEMP2
C8
VTEMP1
S8
NC
C7
V–
S7
S1
C6
C1
S6
S2
C5
C2
S5
S3
C4
C3
S4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Figure 23. 12-Cell Battery Stack Monitor with Isolated SPI Interface and Low Power Shutdown
2883f
32
LTM2883
Typical Applications
B8
3.3V
A8
1µF
LTM2883-3I
VCC
VL
10k
A7
10k
VCC
A6
A5
µC
SDA
SCL
GND
A4
A3
A2
A1
B1
B2
ON
GND
DI1
SDA
SCL
DNC
DO2
DO1
GND
V+
AV
L8
+ K8
L7
V–
K7
AV–
L6
VCC2
K6
AVCC2
L5
O1
L4
SDA2
L3
SCL2
L2
DNC
L1
I2
K1
I1
K2
GND2
0.02Ω
48V
VOUT
SENSE+ SENSE– VIN
SHDN
SDA
SCL
100k AT 25°C, 1%
VISHAY 2381 6154.104
LTC4151
ADIN
ADR0
ADR1
1.37k
1%
GND
2883 F24
T(°C) =
3950
− 273, −40°C < T < 150°C
 1000 
8.965 + LN 
− 1
 NADIN 
NADIN IS THE DIGITAL CODE MEASURED
BY THE ADC AT THE ADIN PIN
Figure 24. Isolated I2C Voltage, Current and Temperature Power Supply Monitor
2883f
33
LTM2883
Typical Applications
B8
5V
A8
10k
LTM2883-5I
VCC
VL
ENABLE
SDA
SCLIN
A7
A6
A5
A4
A3
A2
A1
INTERRUPT
B1
B2
AV
L8
+ K8
V–
L7
0.1µF
K7
AV–
10k
SHUTDOWN
V+
ON
GND
DI1
VCC2
AVCC2
O1
SDA
SDA2
SCL
SCL2
DNC
DNC
DO2
I2
DO1
I1
GND
GND2
L6
174k
K6
100k
L5
0.1µF
SHDN1 VDD
RESET
L4
BYP
SDAIN
L3
SCL
L2
SDAOUT
L1
AUTO
K1
DETECT
1/4 LTC4266
INT
K2
AD0
AD1
AD2
AD3
Q1: FAIRCHILD IRFM120A OR PHILIPS PHT6NQ10T
FB1, FB2: TDK MPZ2012S601A
T1: PULSE H609NL OR COILCRAFT ETH1-230LD
CMPD3003
VEE
DGND AGND
SMAJ58A
1µF
SENSE GATE
OUT
0.25Ω
Q1
–48V
S1B
S1B
0.22µF
FB1
•
•
RJ45
CONNECTOR
1
•
10nF
•
•
T1
75Ω
75Ω
2
10nF
3
•
4
5
PHY
6
7
•
•
•
8
•
10nF
•
(NETWORK
PHYSICAL
LAYER
CHIP)
FB2
75Ω
75Ω
10nF
•
2883 F25
1nF
Figure 25. One Complete Isolated Powered Ethernet Port
2883f
34
3.175
SUGGESTED PCB LAYOUT
TOP VIEW
1.905
aaa Z
0.630 ±0.025 Ø 32x
E
0.000
PACKAGE TOP VIEW
0.635
4
0.635
PIN “A1”
CORNER
1.905
Y
X
D
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
6.350
5.080
0.000
5.080
6.350
aaa Z
2.45 – 2.55
4.445
3.175
4.445
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
aaa
bbb
ccc
ddd
eee
NOM
3.42
0.60
2.82
0.75
0.63
15.0
11.25
1.27
12.70
8.89
DIMENSIONS
0.15
0.10
0.20
0.30
0.15
MAX
3.62
0.70
2.92
0.90
0.66
NOTES
DETAIL B
PACKAGE SIDE VIEW
TOTAL NUMBER OF BALLS: 32
MIN
3.22
0.50
2.72
0.60
0.60
DETAIL A
ddd M Z X Y
eee M Z
DETAIL B
b1
0.27 – 0.37
SUBSTRATE
A1
A2
A
Z
e
8
DETAIL A
b
7
5
G
4
e
3
PACKAGE BOTTOM VIEW
6
2
1
L
K
J
H
G
F
E
D
C
B
A
3
SEE NOTES
PIN 1
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
BALL DESIGNATION PER JESD MS-028 AND JEP95
TRAY PIN 1
BEVEL
BGA 32 0211 REV C
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
µModule
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
F
b
COMPONENT
PIN “A1”
(Reference LTC DWG # 05-08-1851 Rev C)
MOLD
CAP
ccc Z
Øb (32 PLACES)
// bbb Z
BGA Package
32-Lead (15mm × 11.25mm × 3.42mm)
LTM2883
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
2883f
35
LTM2883
Typical Application
Precision 4mA to 20mA Sink/Source with Current Monitor
B8
3.3V
A8
LTM2883-3S
VCC
VL
1µF
A7
A6
VCC
A5
CS
µC
A4
MOSI
A3
SCK
A2
MISO
GND
A1
B1
B2
V+
AV
V–
AV–
ON
SDOE
L8
12.5V
+ K8
VCC2
AVCC2
CS
CS2
SDI
SDI2
SCK
SCK2
DO2
I2
SDO
SDO2
DO1
I1
GND
GND2
1µF
L7
75k
K7
LTC2641, DAC
1
2
L6
3
K6
4
L5
REF
GND
CS
VDD
SCK VOUT
DIN
CLR
8
7
SINK
3
+
6
5
2
7
–
L4
4
1k
6
LTC1050
Si1555DL_N
0.1µF
0.01µF
L3
5V
L2
10
L1
14
K1
K2
100k
3V
2883 TA02
3
LT6660-3
IN
OUT
1
GND
2
0.1µF
LTC2452, ADC
3
7
1
8
REF
VCC
IN+
CS
15
3
+
LTC1100
G = 10
4
2
–
11
6
15Ω
0.1%
7
6
– 5
SCK
IN
SDO
GND
2
SOURCE
0.1µF
RETURN
–5V
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTM2881
Isolated RS485/RS422 µModule Transceiver Plus Power 20Mbps 2500VRMS Isolation with Power in LGA/BGA Package
LTM2882
Dual Isolated RS232 µModule Transceiver Plus Power
20Mbps 2500VRMS Isolation with Power in LGA/BGA Package
LTC4310
Hot-Swappable I2C Isolators
Bidirectional I2C Communication, Low Voltage Level Shifting
LTC6803
Multistack Battery Monitor
Individual Battery Cell Monitoring of High Voltage Battery Stacks, Multiple
Devices Interconnected via SPI
LTC2309/LTC2305/ 12-Bit, 8-/2-/1-Channel, 14ksps SAR ADCs with I2C
LTC2301
5V, Internal Reference, Software Compatible Family
LTC2631/LTC2630
Single 12-/10-/8-Bit I2C or SPI VOUT DACs with
10ppm/°C Reference
180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
Rail-to-Rail Output
LTC2641/LTC2642
16-/14-/12-Bit VOUT DACs
±1LSB INL/DNL, 0.5nV • s Glitch, 1μs Settling, 3mm × 3mm DFN
LTC2452/LTC2453
Ultra-Tiny 16-Bit Differential ±5.5V Δ∑ ADCs, SPI/I2C
2LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT Packages
LTC1859/LTC1858/ 8-Channel 16-/14-/12-Bit, 100ksps, ±10V SoftSpan™
LTC1857
SAR ADCs with SPI
5V Supply, Up to ±10V Configurable Unipolar/Bipolar Input Range, Pin
Compatible Family in SSOP-28 package
LTC2487/LTC2486
16-Bit 2- or 4-Channel Δ∑ ADCs with Easy Drive™ Inputs 16-Bit and 24-Bit Δ∑ ADC Family, Up to 16 Input Channels and Integrated
and I2C/SPI Interface
Temperature Sensor
LTC4303/LTC4304
Hot Swappable I2C Bus Buffers
2.7V to 5.5V Supply, Rise Time Acceleration, Stuck Bus Protection,
±15kV ESD
LTC1100
Zero-Drift Instrumentation Amplifier
Fixed Gain of 10 or 100
LT1991
Precision, Pin Configurable Gain Difference Amplifier
Gain Range –13 to +14
LTC2054/LTC2055
Micropower Zero-Drift Op Amps
3V/5V/±5V Supply
LTC4151
High Voltage I2C Current and Voltage Monitor
Wide Operating Range: 7V to 80V
LTC4261
Negative Voltage Hot Swap™ Controller with ADC and
I2C Monitoring
Floating Topology Allows Very High Voltage Operation
LTC1799
Wide Frequency Range Silicon Oscillator
1kHz to 30MHz
LTC6990
TimerBlox™ Voltage Controlled Oscillator
488Hz to 2MHz
2883f
36 Linear Technology Corporation
LT 0912 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2012