ETC1 CS18LV02565AC-55 High speed super low power sram Datasheet

High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
Revision History
Rev. No.
2.0
History
Initial issue with new naming rule
1
Issue Date
Dec.29,2004
Remark
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
GENERAL DESCRIPTION
The CS18LV02565 is a high performance, high speed and super low power CMOS Static Random
Access Memory organized as 32,768 words by 8bits and operates for a single 4.5 to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high speed, super low power features
and maximum access time of 55/70ns in 5.0V operation. Easy memory expansion is provided by an
active LOW chip enable (/CE) and active LOW output enable (/OE).
The CS18LV02565 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS18LV02565 is available in JEDEC standard 28-pin TSOP I
(8x13.4 mm), SOP (330 mil) and PDIP (600 mil) packages.
FEATURES
Wide operation voltage : 4.5 ~ 5.5V
Ultra low power consumption : 2mA＠1MHz (Max.) , Vcc=5.0V.
1.0 uA (Typ.) CMOS standby current
High speed access time : 55/70ns.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible.
Data retention supply voltage as low as 1.5V.
Easy expansion with /CE and /OE options.
PRODUCT FAMILY
Product Family
Operating Temp.
Vcc Range
Speed (ns)
Standby Current(Typ.)
ICCSB1
Package Type
28 SOP
0~70oC
CS18LV02565
55/70
1.0 uA
(Vcc = 5.0V)
28 TSOP I
28 PDIP
Dice
4.5~5.5V
28 SOP
-40~85oC
55/70
1.5 uA
(Vcc= 5.0V)
28 TSOP I
28 PDIP
Dice
2
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
PIN CONFIGURATIONS
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28TSOP(I)-8x13.4mm
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
FUNCTIONAL BLOCK DIAGRAM
A5
A6
A7
A8
A9
A11
A12
A13
A14
Address
Input
Buffer
18
Row
Decoder
512
Memory Array
512x512
512
8
DQ0
DQ7
Data Input
Buffer
8
Data Output
Buffer
8
Column I/O
8
Write Driver
Sense Amp
64
Column Decoder
/CE
/WE
/OE
12
Control
Address Input Buffer
VCC
GND
A0 A1 A2 A3 A4 A10
3
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
PIN DESCRIPTIONS
Name
Type
A0 – A14
Input
Function
Address inputs for selecting one of the 32,768 x 8 bit words in the RAM
/CE is active LOW. Chip enable must be active when data read from or write
Input
/CE
to the device. If chip enable is not active, the device is deselected and in a
standby power mode. The DQ pins will be in high impedance state when the
device is deselected.
The Write enable input is active LOW. It controls read and write operations.
Input
/WE
With the chip selected, when /WE is HIGH and /OE is LOW, output data will
be present on the DQ pins, when /WE is LOW, the data present on the DQ
pins will be written into the selected memory location.
The output enable input is active LOW. If the output enable is active while the
Input
/OE
chip is selected and the write enable is inactive, data will be present on the
DQ pins and they will be enabled. The DQ pins will be in the high impedance
state when /OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the
DQ0~DQ7
I/O
Vcc
Power
Power Supply
Gnd
Power
Ground
RAM.
TRUTH TABLE
Mode
/CE
/WE
/OE
DQ0~7
Vcc Current
Standby
H
X
X
High Z
ICCSB, ICCSB1
Output Disabled
L
H
H
High Z
ICC
Read
L
H
L
DOUT
ICC
Write
L
L
X
DIN
ICC
4
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameter
Rating
Unit
-0.5 to Vcc+0.5
V
VTERM
Terminal Voltage with Respect to GND
TBIAS
Temperature Under Bias
-40 to +125
O
TSTG
Storage Temperature
-60 to +150
O
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
C
C
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range
Ambient Temperature
Vcc
o
Commercial
0~70 C
4.5~5.5V
Industrial
-40~85oC
4.5~5.5V
CAPACITANCE(1)(TA=25℃,f=1.0MHz)
Symbol
Parameter
Conduction
MAX.
Unit
CIN
Input Capacitance
VIN=0V
6
pF
CDQ
Input/Output Capacitance
VI/O=0V
8
pF
1. This parameter is guaranteed, and not 100% tested.
5
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
DC ELECTRICAL CHARACTERISTICS
Name
Parameter
Guaranteed Input Low
VIL
Voltage (2)
Guaranteed Input High
VIH
Voltage (2)
Test Condition
o
TYP(1)
MIN
MAX
Unit
Vcc=5.0V
-0.5
1.5
V
Vcc=5.0V
2.5
Vcc+0.2
V
VCC=MAX, VIN=0 to VCC
-1
1
uA
-1
1
uA
0.4
V
IIL
Input Leakage Current
IOL
Output Leakage Current
VOL
Output Low Voltage
VCC=MAX, IOL = 1mA
VOH
Output High Voltage
VCC=MIN, IOH = -1mA
Operating Power Supply
/CE=VIL, IDQ=0mA,
Current
F=FMAX =1/ tRC
ICCSB
TTL Standby Supply
/CE=VIH, IDQ=0mA,
ICCSB1
CMOS Standby Current
ICC
o
( TA = 0 ~70 C, Vcc = 5.0V)
VCC=MAX, /CE=VIN, or
/OE=VIN , VIO=0V to VCC
2.2
V
/CE≧VCC-0.2V, VIN≧
20
mA
1
mA
4
uA
1.0
VCC-0.2V or VIN≦0.2V,
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
DATA RETENTION CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V )
Name
Parameter
VCC for Data Retention
VDR
Test Condition
/CE ≧ VCC-0.2V,
VIN ≧
VCC-0.2V or VIN≦0.2V
Data Retention Current
ICCDR
MIN TYP(1) MAX
1.5
/CE≧VCC-0.2V, VIN≧
Chip Deselect to Data
TCDR
Retention Time
tR
Operation Recovery Time
Refer to
Retention Waveform
V
0.5
VCC-0.2V or VIN≦0.2V
Unit
3
uA
0
ns
tRC (2)
ns
o
1. TA = 25 C.
2. tRC= .Read Cycle Time.
6
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
LOW Vcc DATA RETENTION WAVEFORM ( /CE Controlled )
Vcc
Data Retention Mode
VDR >= 1.5V
tCDR
CE
CE >= VCC - 0.2V
VIH
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
Vcc/0V
tR
VIH
KEY TO SWITCHING WAVEFORMS
WAVEFORMS
5ns
INPUTS
OUTPUTS
MUST BE STEADY MUST BE STEADY
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE CHANGE FROM H
TO L
MAY CHANGE
FROM L TO H
WILL BE CHANGE FROM L
TO H
DON’T CARE ANY
CHANGE
PERMITTED
CHANGE STATE
UNKNOWN
DOES NOT APPLY
CENTER LINE IS HIGH
IMPEDANCE OFF STATE
AC TEST LOADS AND WAVEFORMS
FIGURE 1A
FIGURE 1B
7
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
AC ELECTRICAL CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V )
< READ CYCLE >
JEDEC
Name
Symbol
-55
tAVAX
tRC
Read Cycle Time
tAVQV
tAA
Address Access Time
55
70
ns
tELQV
tACE
Chip Select Access Time
55
70
ns
tGLQV
tOE
Output Enable to Output
30
50
ns
Description
MIN
-70
MAX
55
MIN
MAX
70
Unit
ns
Valid
tELQX
tCLZ
Chip Select to Output Low Z
10
10
ns
tGLQX
tOLZ
Output Enable to Output in
5
5
ns
Low Z
tEHQZ
tCHZ
Chip Deselect to Output in
0
35
0
35
ns
0
30
0
30
ns
High Z
tGHQZ
tOHZ
Output Disable to Output in
High Z
tAXOX
tOH
Address Change to Out
10
10
ns
Disable
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
tRC
ADDRESS
tOH
tAA
tOH
DOUT
8
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
READ CYCLE2 (1,3,4)
READ CYCLE3 (1,4)
tRC
ADDRESS
tAA
tOH
OE
tOE
tOHZ (1,5)
tOLZ
CE
tCLZ (5)
tCE
tCHZ (5)
DOUT
NOTES:
1. /WE is high in read Cycle.
2. Device is continuously selected when /CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. /OE = VIL.
5. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input
pulse levels of 0V to VCC and output loading specified in Figure 1A.
6. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
9
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
AC ELECTRICAL CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V )
< WRITE CYCLE >
JEDEC
Name
Symbol
tAVAX
tWC
Write Cycle Time
55
70
ns
tE1LWH
tCW
Chip Select to End of Write
55
70
ns
tAVWL
tAS
Address Setup Time
0
0
ns
tAVWH
tAW
Address Valid to End of Write
55
70
ns
tWLWH
tWP
Write Pulse Width
40
50
ns
tWHAX
tWR
Write Recovery Time
0
0
ns
tWLQZ
tWHZ
Write to Output in High Z
tDVWH
tDW
Data to Write Time Overlap
20
30
ns
tWHDX
tDH
Data Hold for Write End
0
0
ns
tGHQZ
tOHZ
Output Disable to Output in
0
Description
-55
-70
MIN MAX MIN MAX
25
30
35
0
30
Unit
ns
ns
High Z
tWHOX
tOW
End of Write to Output Active
10
5
5
ns
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (Write Enable Controlled)
WRITE CYCLE2 (Chip Enable Controlled)
11
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
NOTES:
1.
/WE must be high during address transitions.
2.
The internal write time of the memory is defined by the overlap of /CE and /WE low. All signals must be active
to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold
timing should be referenced to the second transition edge of the signal that terminates the write.
3.
TWR is measured from the earlier of /CE or /WE going high at the end of write cycle.
4.
During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs
must not be applied.
5.
If the /CE low transition occurs simultaneously with the /WE low transitions or after the /WE transition, output
remain in a high impedance state.
6.
/OE is continuously low (/OE = VIL ).DOUT is the same phase of write data of this write cycle.
7. DOUT is the read data of next address.
8. If /CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase
to the outputs must not be applied to them.
9. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input pulse
levels of 0V to VCC and output loading specified in Figure 1A.
10. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
11. TCW is measured from the later of /CE going low to the end of write.
ORDER INFORMATION
12
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
PACKAGE DIMENSIONS
28 pin SOP (330 mil) :
SYMBOL
A
UNIT
mm
b1
c
0.35
_
0.20
_
0.20 17.983 8.280 11.506 1.118
_
18.110 8.407 11.811 1.270
0.700 1.520
_
0.964 1.720
_
0.45
0.32
0.28 18.237 8.534 12.116 1.422
1.228 1.920
0.1
_
Max. 2.844 0.350
2.616
0.50
0.100 0.004
c1
D
E
e
y
b
2.489
2.540 0.102 2.362
E1
L
L1
0.093 0.014 0.014 0.008 0.008 0.708 0.326 0.453 0.044 0.0276 0.0598
_
_
_
_
0.713 0.331 0.465 0.050 0.0380 0.0677
Nom. 0.106 0.009 0.098
Max. 0.112 0.014
0.103 0.020
0.018 0.012
_
0.011 0.718 0.336 0.477 0.056 0.0484 0.0756 0.004
0°
_
10°
0°
_
10°
28 pin TSOP I (8x13.4 mm) :
12°(2x)
12°(2x)
HD
e
cL
28
14
15
b
E
1
y
Seating Plane
12°(2X)
"A"
D
A
0
15
14
0.254
A
GAUGE PLANE
A2
-
A2
Nom. 2.692 0.226
Min.
inch
A1
0.35
_
Min.
A1
-
A
SEATING PLANE
12°(2X)
L
L1
"A" DATAIL VIEW
b
WITH PLATING
1
c c1
28
b1
BASE METAL
SECTION A-A
SYMBOL
A
A1
A2
b
b1
c
c1
D
E
e
HD
L
L1
y
1.00
0.050
0.95
0.17
0.17
7.90
0.45
13.20
0.40
0.70
_
0.115
1.00
0.22
0.20
0.10
_
11.70
Nom. 1.10
0.10
_
11.80
8.00
0.55
13.40
0.50
0.80
_
1.20
0.180
1.05
0.27
0.23
0.21
0.16
11.90
8.10
0.65
13.60
0.70
0.90
Min. 0.0393 0.0019 0.037
0.007
0.007
0.009
0.008
0.004
_
0.520 0.0157 0.0275
Nom. 0.0433 0.0045 0.039
0.004
_
0.1
_
0.465
0.315
0.022
0.528 0.0197 0.0315
_
Max. 0.0473 0.0071 0.041
0.011 0.009
0.008
0.006
0.469
0.319
0.026
0.536 0.0277 0.0355 0.004
UNIT
Min.
mm
Max.
inch
13
0.461
0.311 0.018
0°
_
8°
0°
_
8°
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
-
28 pin PDIP (600mil):
SYMBOL
A1
UNIT
0.254
_
Nom.
_
Max.
Min.
mm
0.010
_
Nom.
_
Max.
Min.
inch
A2
B
B1
3.683 0.330 1.270
c
D
E
E1
0.152 36.957 14.986 13.716
e
eB
L
3°
2.032 1.778
6°
2.286 1.905
9°
0.120
0.070
0.065
3°
0.130
0.080
0.070
6°
0.140
0.090
0.075
9°
0.457 1.524
3.937
0.584 1.778
2.540
0.254 37.084 15.240 13.818 (TYP) 16.256 3.302
0.356 37.211 15.494 13.920
16.764 3.556
0.145
0.013 0.050
0.006 1.455
0.590
0.150
0.018 0.060
0.010 1.460
0.600
0.155
0.023 0.070
0.014 1.465
0.610
14
0.620
0.100
0.544 (TYP) 0.640
0.660
0.548
Q1
1.651
3.810
0.540
S
15.748 3.048 1.778
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.