Ordering number : ENA1687 LC75879PT CMOS IC 1/4, 1/3-Duty General-Purpose LCD Display Driver http://onsemi.com Overview The LC75879PT is the 1/4 duty and 1/3 duty general-purpose microprocessor-controlled LCD driver that can be used in applications such as frequency display in products with electronic tuning.In addition to being able to drive up to 272 segments directly, the LC75879PT can also control up to 8 general-purpose output ports. Because it has the PWM output of a maximum of 3 ch, the brightness control of the LED backlight of RGB can be done. Incorporation of an oscillation circuit helps to reduce the number of external resistors and capacitors required. Features • Support for 1/4-duty 1/3-bias or 1/3-duty 1/3-bias drive techniques under serial data control. When 1/4-duty: Capable of driving up to 272 segments When 1/3-duty: Capable of driving up to 207 segments • Serial data input supports CCB format communication with the system controller (Support 3.3V and 5V operation). • Serial data control of the power-saving mode based backup function and the all segments forced off function. • Serial data control of switching between the segment output port and general-purpose output portfunction. (Support for up to 8 general-purpose output ports) • Support for the PWM output function of a maximum of 3ch (It can output from the general-purpose output port). • Support for clock output function of 1ch (It can output from the general-purpose output port). • Serial data control of the frame frequency of the common and segment output waveforms. • Serial data control of switching between the internal oscillator operating mode and external clock operating mode. • High generality, since display data is displayed directly without the intervention of a decoder circuit. • Built-in display contrast adjustment circuit. • The INH pin allows the display to be forced to the off state. • Incorporation of an oscillator circuit (Incorporation of resistor and capacitor for an oscillation). • CCB is ON Semiconductor® ’s original format. All addresses are managed by ON Semiconductor® for this format. • CCB is a registered trademark of Semiconductor Components Industries, LLC. Semiconductor Components Industries, LLC, 2013 July, 2013 51910HKIM 20100420-S00013 No.A1687-1/35 LC75879PT Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0V Parameter Maximum supply voltage Input voltage Output voltage Output current Allowable power dissipation Symbol VDD max Conditions Ratings VDD Unit -0.3 to +6.8 V VIN1 CE, CL, DI, INH VIN2 OSCI, VDD1, VDD2 -0.3 to VDD+0.3 VOUT S1 to S69, COM1 to COM4, P1 to P8 -0.3 to VDD+0.3 V IOUT1 S1 to S68 300 μA IOUT2 COM1 to COM4, S69 3 IOUT3 P1 to P8 5 Pd max Ta=85°C -0.3 to +6.8 200 V mA mW Operating temperature Topr -40 to +85 °C Storage temperature Tstg -55 to +125 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Allowable Operating Ranges at Ta = -40 to +85°C, VSS = 0V Parameter Symbol Ratings Conditions min typ Unit max Supply voltage VDD VDD Input voltage VDD1 VDD1 2/3VDD0 VDD0 *1 VDD2 VDD2 1/3VDD0 VDD0 Input high level voltage VIH1 CE, CL, DI, INH 0.4VDD 6.3 VIH2 OSCI: External clock operating mode 0.4VDD VDD VIL1 CE, CL, DI, INH 0 0.2VDD VIL2 OSCI: External clock operating mode 0 0.2VDD fCK OSCI: External clock operating mode Input low level voltage External clock operating frequency External clock duty cycle 4.5 [Figure4] DCK OSCI: External clock operating mode [Figure4] 6.3 V V V V 10 300 600 kHz 30 50 70 % Data setup time tds CL, DI [Figure2], [Figure3] 160 ns Data hold time tdh CL, DI [Figure2], [Figure3] 160 ns CE wait time tcp CE, CL [Figure2], [Figure3] 160 ns CE setup time tcs CE, CL [Figure2], [Figure3] 160 ns CE hold time tch CE, CL [Figure2], [Figure3] 160 ns High level clock pulse width tφH CL [Figure2], [Figure3] 160 ns Low level clock pulse width tφL CL [Figure2], [Figure3] 160 tr CE, CL, DI [Figure2], [Figure3] 160 ns Fall time tf CE, CL, DI [Figure2], [Figure3] 160 ns INH switching time tc INH, CE [Figure5], [Figure6] Rise time [Figure7], [Figure8] 10 ns μs Note : *1. VDD0=0.70VDD to VDD No.A1687-2/35 LC75879PT Electrical Characteristics for the Allowable Operating Ranges Parameter Symbol Pin Conditions Ratings min typ Unit max Hysteresis VH CE, CL, DI, INH Input high level current IIH1 CE, CL, DI, INH VI=6.3V 5.0 IIH2 OSCI VI=VDD: External clock operating mode 5.0 IIL1 CE, CL, DI, INH VI=0V -5.0 IIL2 OSCI VI=0V: External clock operating mode -5.0 S1 to S69 IO=-20μA VDD0-0.9 VDD0-0.9 Input low level current Output high level voltage *1 VOH1 0.03VDD V μA VOH2 COM1 to COM4 IO=-100μA VOH3 P1 to P8 IO=-1mA Output low level VOL1 S1 to S69 IO=20μA 0.9 voltage VOL2 COM1 to COM4 IO=100μA 0.9 VOL3 P1 to P8 IO=1mA 0.9 VMID1 S1 to S69 1/3 bias IO=±20μA Output middle level 2/3VDD0 Current drain +0.9 1/3VDD0 S1 to S69 1/3 bias IO=±20μA 1/3VDD0 -0.9 +0.9 VMID3 COM1 to COM4 1/3 bias IO=±100μA 2/3VDD0 2/3VDD0 -0.9 +0.9 VMID4 COM1 to COM4 1/3 bias IO=±100μA 1/3VDD0 1/3VDD0 -0.9 +0.9 Internal Internal oscillator oscillator circuit operating mode IDD1 VDD Power-saving mode IDD2 VDD VDD=6.3V Output open fosc 240 V 2/3VDD0 -0.9 VMID2 *2 Oscillator frequency V VDD-0.9 voltage *1 μA 300 360 V kHz 100 1000 Internal oscillator 2000 operating mode IDD3 VDD μA VDD=6.3V Output open External clock 1000 operating mode 2000 fCK=300kHz VIH2=0.5VDD VIL2=0.1VDD Note: *1. VDD0=0.70VDD to VDD Note: *2. Excluding the bias voltage generation divider resistors built in the VDD1 and VDD2. (See Figure 1.) VDD CONTRAST ADJUSTER VDD0 VDD1 To the common and segment drivers VDD2 VSS Except these resistors. [Figure 1] No.A1687-3/35 LC75879PT ≈ 1. When CL is stopped at the low level VIH1 VIL1 ≈ CE tφL tf tcp VIH1 DI tch tcs ≈ ≈ tr ≈ ≈ CL ≈ ≈ tφH VIH1 50% VIL1 VIL1 tdh tds [Figure 2] 2. When CL is stopped at the high level ≈ VIH1 CE ≈ VIL1 tφH VIH1 50% VIL1 tr tcp ≈ ≈ VIH1 VIL1 DI tch tcs ≈ ≈ tf ≈ CL ≈ tφL tdh tds [Figure 3] 3. OSCI pin clock timing in external clock operating mode tCKH OSCI VIH2 50% VIL2 tCKL fCK = 1 [kHz] tCKH+ tCKL tCKH ×100[%] DCK= tCKH+ tCKL [Figure 4] No.A1687-4/35 LC75879PT Package Dimensions unit : mm (typ) 3290 14.0 60 0.5 12.0 41 40 80 21 1 14.0 12.0 61 20 0.125 0.2 0.5 0.1 1.2max (1.0) (1.25) SANYO : TQFP80J(12X12) S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 Pin Assignment 60 61 50 41 40 LC75879PT 70 30 (TQFP80J) 80 1 10 21 20 P3/S3 P4/S4 P5/S5 P6/S6 P7/S7 P8/S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S63 S64 S65 S66 COM1 COM2 COM3 S67/COM4 S68 VDD VDD1 VDD2 VSS S69/OSCI INH CE CL DI P1/S1 P2/S2 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 Top view No.A1687-5/35 LC75879PT COMMON DRIVER S1/P1 S2/P2 S8/P8 S9 S66 S68 COM4/S67 COM2 COM3 COM1 Block Diagram SEGMENT DRIVER & LATCH INH CLOCK GENERATOR S69/OSCI CONTROL REGISTER VDD CONTRAST ADJUSTER SHIFT REGISTER VDD0 VDD1 CCB INTERFACE VDD2 CE CL DI VSS No.A1687-6/35 LC75879PT Pin Functions Handling Pin Pin No. Function Active I/O when unused S1/P1 to 79, 80, Segment outputs for displaying the display data transferred by serial data S8/P8 1 to 6 input. The S1/P1 to S8/P8 pins can be used as general-purpose output S9 to S66 7 to 64 ports under serial data control. S68 69 COM1 to COM3 65 to 67 COM4/S67 68 The frame frequency is fo[Hz]. S69/OSCI 74 Segment output. This pin can also be used as the external clock input pin Common driver outputs - O OPEN - O OPEN - I/O OPEN H I GND The COM4/S67 pin can be used as a segment output in 1/3 duty. when the external clock operating mode is selected by control data. CE 76 Serial data transfer inputs. Must be connected to the controller. CE: Chip enable CL 77 CL: Synchronization clock I DI: Transfer data DI 78 INH 75 Display off control input •INH=low(VSS)….Display forced off S1/P1 to S8/P8=low (VSS) - I L I GND - I OPEN OPEN (These pins are forcibly set to the general-purpose output port function and held at the VSS level.) S9 to S66,S68=low(VSS) COM1 to COM3=low(VSS) COM4/S67=low(VSS) S69/OSCI=low(VSS) (This pin is forcibly set to the segment output port function and held at the VSS level.) Stops the internal oscillator. Inhibits external clock input. Display contrast adjustment circuit stopped. •INH=high(VDD)…Display on Enables the internal oscillator circuit. (Internal oscillator operating mode) Enables external clock input. (External clock operating mode) Display contrast adjustment circuit operation is enabled. However, serial data transfer is possible when the display is forced off. VDD1 71 Used to apply the LCD drive 2/3 bias voltage externally. VDD2 72 Used to apply the LCD drive 1/3 bias voltage externally. - I VDD 70 Power supply pin. A power voltage of 4.5 to 6.3V must be applied to this pin. - - - VSS 73 Ground pin. Must be connected to ground. - - - No.A1687-7/35 LC75879PT Serial Data Input 1. 1/4 duty (1) When CL is stopped at the low level CL DI 1 0 1 0 0 0 1 0 D1 D2 D60 D61 D62 D63 D64 D65 D66 D67 D68 0 0 0 PS10 PS11 PS2 PS3 PS4 EXF DN OC P0 P1 P2 P3 DT SC BU 0 0 B0 B1 B2 B3 A0 A1 A2 A3 Display data 68 bits Control data 18 bits DD 2bits ∼ 0 1 0 0 0 1 0 D69 D70 D128 D129 D130 D131 D132 D133 D134 D135 D136 0 0 0 0 0 0 0 0 PF0 PF1 PF2 PF3 FC0 FC1 FC2 CT0 CT1 CT2 0 1 Display data 68 bits Control data 18 bits DD 2bits ∼ ∼ ∼ ∼ ∼ CCB address 8 bits 1 0 1 0 0 0 1 0 D137 D138 D196 D197 D198 D199 D200 0 0 0 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 1 0 B0 B1 B2 B3 A0 A1 A2 A3 Display data 64 bits DD 2bits Control data 22 bits ∼ CCB address 8 bits ∼ ∼ ∼ ∼ ∼ ∼ 1 B0 B1 B2 B3 A0 A1 A2 A3 1 0 1 0 0 0 1 0 D201 D202 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Display data 72 bits Fixed data 14 bits DD 2bits Note: DD is the direction data. No.A1687-8/35 ∼ ∼ ∼ ∼ ∼ ∼ ∼ CCB address 8 bits ∼ ∼ ∼ ∼ CE LC75879PT (2) When CL is stopped at the high level CL DI 1 0 1 0 0 0 1 0 D1 D2 D60 D61 D62 D63 D64 D65 D66 D67 D68 0 0 0 PS10 PS11 PS2 PS3 PS4 EXF DN OC P0 P1 P2 P3 DT SC BU 0 0 B0 B1 B2 B3 A0 A1 A2 A3 Display data 68bits Control data 18 bits DD 2bits ∼ ∼ 0 1 0 0 0 1 0 D69 D70 D128 D129 D130 D131 D132 D133 D134 D135 D136 0 0 0 0 0 0 0 0 PF0 PF1 PF2 PF3 FC0 FC1 FC2 CT0 CT1 CT2 0 1 CCB address 8 bits Display data 68 bits Control data 18 bits ∼ ∼ ∼ ∼ ∼ ∼ DD 2bits 1 0 1 0 0 0 1 0 D137 D138 D196 D197 D198 D199 D200 0 0 0 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 1 0 B0 B1 B2 B3 A0 A1 A2 A3 Display data 64 bits Control data 22 bits DD 2bits ∼ ∼ CCB address 8 bits ∼ ∼ ∼ ∼ 1 B0 B1 B2 B3 A0 A1 A2 A3 1 0 1 0 0 0 1 0 D201 D202 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Display data 72 bits Fixed data 14 bits DD 2bits Note: DD is the direction data • CCB address ……………….. “45H” • D1 to D272 ………………… Display data • PS10, PS11, PS2 to PS4 …. .. General-purpose output port (P1 to P4) function setting control data • EXF ………………………… External clock operating frequency setting control data • DN …………………………. S68 pin and S69/OSCI pin state setting control data • OC …………………………. Internal oscillator operating mode/external clock operating mode switching control data • P0 to P3 …………………….. Segment output port/general-purpose output port switching control data • DT ………………………….. 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data • SC ………………………..… Segment on/off control data • BU ………………………..… Normal mode/power-saving mode control data • PF0 to PF3 ………………… PWM output waveform frame frequency setting control data • FC0 to FC2 ………………… Common/segment output waveform frame frequency setting control data • CT0 to CT2 ………………… Display contrast setting control data • W10 to W15, W20 to W25, ... PWM data of the PWM output W30 to W35 No.A1687-9/35 ∼ ∼ ∼ ∼ ∼ ∼ CCB address 8 bits ∼ ∼ ∼ ∼ CE LC75879PT 2. 1/3 duty (1) When CL is stopped at the low level CL DI 1 0 1 0 0 0 1 0 D1 D2 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 0 0 PS10 PS11 PS2 PS3 PS4 EXF DN OC P0 P1 P2 P3 DT SC BU 0 0 B0 B1 B2 B3 A0 A1 A2 A3 Display data 69 bits Control data 17 bits DD 2bits ∼ 1 0 1 0 0 0 1 0 D70 D71 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 0 0 0 0 PF0 PF1 PF2 PF3 FC0 FC1 FC2 CT0 CT1 CT2 0 1 B0 B1 B2 B3 A0 A1 A2 A3 Display data 72 bits Control data 14 bits DD 2bits ∼ ∼ ∼ ∼ CCB address 8 bits 1 0 1 0 0 0 1 0 D142 D143 D201 D202 D203 D204 D205 D206 D207 0 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 1 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Display data 66 bits Control data 20 bits DD 2bits Note: DD is the direction data. No.A1687-10/35 ∼ ∼ ∼ ∼ ∼ ∼ ∼ CCB address 8 bits ∼ ∼ ∼ ∼ CE LC75879PT (2) When CL is stopped at the low level CL DI 1 0 1 0 0 0 1 0 D1 D2 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 0 0 PS10 PS11 PS2 PS3 PS4 EXF DN OC P0 P1 P2 P3 DT SC BU 0 0 B0 B1 B2 B3 A0 A1 A2 A3 Display data 69 bits Control data 17 bits DD 2bits 1 0 1 0 0 0 1 0 D70 D71 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 0 0 0 0 PF0 PF1 PF2 PF3 FC0 FC1 FC2 CT0 CT1 CT2 0 1 B0 B1 B2 B3 A0 A1 A2 A3 Display data 72 bits Control data 14 bits DD 2bits ∼ ∼ ∼ ∼ CCB address 8 bits 1 0 1 0 0 0 1 0 D142 D143 D201 D202 D203 D204 D205 D206 D207 0 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 1 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Note: DD is the direction data. • CCB address ……………….. • D1 to D207 ……………….... • PS10, PS11, PS2 to PS4 ….... • EXF ………………………... • DN …………………………. • OC …………………………. • P0 to P3 ……………………. • DT …………………………. • SC ………………………….. • BU …………………………. • PF0 to PF3 …………………. • FC0 to FC2 ………………… • CT0 to CT2 ………………… • W10 to W15, W20 to W25, ... W30 to W35 Display data 66 bits Control data 20 bits DD 2bits “45H” Display data General-purpose output port (P1 to P4) function setting control data External clock operating frequency setting control data S68 pin and S69/OSCI pin state setting control data Internal oscillator operating mode/external clock operating mode switching control data Segment output port/general-purpose output port switching control data 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data Segment on/off control data Normal mode/power-saving mode control data PWM output waveform frame frequency setting control data Common/segment output waveform frame frequency setting control data Display contrast setting control data PWM data of the PWM output No.A1687-11/35 ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ CCB address 8 bits ∼ ∼ ∼ ∼ CE LC75879PT 3. 1/4 duty (Simple mode transfer) (1) When CL is stopped at the low level CL 1 0 1 0 0 0 1 0 D1 D2 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 0 DN OC P0 P1 P2 P3 DT SC BU 0 0 B0 B1 B2 B3 A0 A1 A2 A3 Control data 10 bits Display data 68 bits DD 2bits ∼ 1 0 1 0 0 0 1 0 D69 D70 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 0 0 0 0 FC0 FC1 FC2 CT0 CT1 CT2 0 1 B0 B1 B2 B3 A0 A1 A2 A3 Display data 68 bits Control data 10 bits DD 2bits ∼ ∼ ∼ ∼ ∼ CCB address 8 bits ∼ ∼ ∼ ∼ ∼ ∼ ∼ CCB address 8 bits 1 0 1 0 0 0 1 0 D137 D138 D191 D192 D193 D194 D195 D196 D197 D198 D199 D200 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 Display data 64 bits Fixed data 14 bits DD 2bits ∼ ∼ ∼ ∼ CCB address 8 bits ∼ ∼ ∼ DI ∼ ∼ ∼ ∼ CE 1 0 1 0 0 0 1 0 D201 D202 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272 0 0 0 0 0 0 1 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Display data 72 bits Fixed data 6 bits DD 2bits Note: DD is the direction data. No.A1687-12/35 LC75879PT (2) When CL is stopped at the high level CL 1 0 1 0 0 0 1 0 D1 D2 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 0 DN OC P0 P1 P2 P3 DT SC BU 0 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits DD 2bits Control data 10 bits ∼ 1 0 1 0 0 0 1 0 D69 D70 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 0 0 0 0 FC0 FC1 FC2 CT0 CT1 CT2 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Control data 10 bits DD 2bits ∼ ∼ ∼ ∼ ∼ Display data 68 bits 1 0 1 0 0 0 1 0 D137 D138 D191 D192 D193 D194 D195 D196 D197 D198 D199 D200 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Fixed data 14 bits Display data 64 bits DD 2bits ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ Display data 68 bits 1 0 1 0 0 0 1 0 D201 D202 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272 0 0 0 0 0 0 1 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Display data 72 bits Fixed data 6 bits DD 2bits Note: DD is the direction data. • CCB address ....... "45H" • D1 to D272 .......... Display data • DN ……………... S68 pin and S69/OSCI pin state setting control data • OC ……………... Internal oscillator operating mode/external clock operating mode switching control data • P0 to P3 ………... Segment output port/general-purpose output port switching control data • DT ……………... 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data • SC …………….... Segment on/off control data • BU ……………... Normal mode/power-saving mode control data • FC0 to FC2 …..... Common/segment output waveform frame frequency setting control data • CT0 to CT2 ……. Display contrast setting control data No.A1687-13/35 ∼ ∼ ∼ DI ∼ ∼ ∼ ∼ CE LC75879PT 4. 1/3 duty (Simple mode transfer) (1) When CL is stopped at the low level CL 1 0 1 0 0 0 1 0 D1 D2 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 DN OC P0 P1 P2 P3 DT SC BU 0 0 B0 B1 B2 B3 A0 A1 A2 A3 Control data 9 bits Display data 69 bits DD 2bits ∼ ∼ ∼ ∼ ∼ CCB address 8 bits 1 0 1 0 0 0 1 0 D70 D71 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 FC0 FC1 FC2 CT0 CT1 CT2 0 1 B0 B1 B2 B3 A0 A1 A2 A3 Display data 72 bits Control data 6 bits DD 2bits ∼ ∼ ∼ ∼ CCB address 8 bits ∼ ∼ ∼ DI ∼ ∼ ∼ ∼ CE 1 0 1 0 0 0 1 0 D142 D143 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207 0 0 0 0 0 0 0 0 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Display data 66 bits Fixed data 12 bits DD 2bits Note: DD is the direction data. No.A1687-14/35 LC75879PT (2) When CL is stopped at the high level CL 1 0 1 0 0 0 1 0 D1 D2 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 DN OC P0 P1 P2 P3 DT SC BU 0 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Control data 9 bits DD 2bits ∼ ∼ ∼ ∼ ∼ ∼ Display data 69 bits 1 0 1 0 0 0 1 0 D70 D71 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 FC0 FC1 FC2 CT0 CT1 CT2 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Control data 6 bits DD 2bits ∼ ∼ ∼ ∼ Display data 72 bits ∼ ∼ DI ∼ ∼ ∼ ∼ CE 1 0 1 0 0 0 1 0 D142 D143 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207 0 0 0 0 0 0 0 0 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Display data 66 bits Fixed data 12 bits DD 2bits Note: DD is the direction data • CCB address …………… “45H” • D1 to D207 …………….. Display data • DN ……………………… S68 pin and S69/OSCI pin state setting control data • OC ……………………… Internal oscillator operating mode/external clock operating mode switching control data • P0 to P3 ………………… Segment output port/general-purpose output port switching control data • DT ……………………… 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data • SC ……………………… Segment on/off control data • BU ……………………… Normal mode/power-saving mode control data • FC0 to FC2 …………….. Common/segment output waveform frame frequency setting control data • CT0 to CT2 …………….. Display contrast setting control data No.A1687-15/35 LC75879PT Serial Data Transfer Example (1) 1/4 duty • When 201 or more segments are used All 352 bits of serial data must be sent. 8 bits 1 0 1 0 0 88 bits 0 1 0 D1 D2 D60 D61 D62 D63 D64 D65 D66 D67 D68 0 0 0 PS10 PS11 PS2 PS3 PS4 EXF DN OC P0 P1 P2 P3 DT SC BU 0 0 D69 D70 D128 D129 D130 D131 D132 D133 D134 D135 D136 0 0 0 0 PF0 PF1 PF2 PF3 FC0 FC1 FC2 CT0 CT1 CT2 0 1 D137 D138 D196 D197 D198 D199 D200 0 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 1 0 D201 D202 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272 0 1 1 B0 B1 B2 B3 A0 A1 A2 A3 1 0 1 0 0 0 1 0 0 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 1 0 0 0 1 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 • When fewer than 201 segments are used The 264 bits of serial data must be sent. However, the serial data shown below (the D1 to D200 display data and the control data) must always be sent. 8 bits 1 0 1 0 0 88 bits 0 1 0 D1 D2 D60 D61 D62 D63 D64 D65 D66 D67 D68 0 0 0 PS10 PS11 PS2 PS3 PS4 EXF DN OC P0 P1 P2 P3 DT SC BU 0 0 D69 D70 D128 D129 D130 D131 D132 D133 D134 D135 D136 0 0 0 0 PF0 PF1 PF2 PF3 FC0 FC1 FC2 CT0 CT1 CT2 0 1 D137 D138 D196 D197 D198 D199 D200 0 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 1 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 1 0 0 0 1 0 0 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 1 0 0 0 1 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 2. 1/3 duty All 264 bits of serial data must be sent. 8 bits 1 0 1 0 0 88 bits 0 1 0 D1 D2 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 0 0 PS10 PS11 PS2 PS3 PS4 EXF DN OC P0 P1 P2 P3 DT SC BU 0 D70 D71 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 0 D142 D143 D201 D202 D203 D204 D205 D206 D207 0 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 1 0 0 0 1 0 0 0 0 PF0 PF1 PF2 PF3 FC0 FC1 FC2 CT0 CT1 CT2 0 1 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 1 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 No.A1687-16/35 LC75879PT 3. 1/4 duty (Simple mode transfer) • When 201 or more segments are used All 320 bits of serial data must be sent. 8 bits 1 0 1 0 0 80 bits 0 1 0 D1 D2 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 0 DN OC P0 P1 P2 P3 DT SC BU 0 0 D69 D70 D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 0 0 0 0 FC0 FC1 FC2 CT0 CT1 CT2 0 1 D137 D138 D188 D189 D190 D191 D192 D193 D194 D195 D196 D197 D198 D199 D200 0 0 0 0 0 0 0 0 0 0 1 0 D201 D202 D252 D253 D254 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272 0 0 0 0 0 0 1 1 D1 D2 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 0 DN OC P0 P1 P2 P3 DT SC BU 0 0 D69 D70 D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 0 0 FC0 FC1 FC2 CT0 CT1 CT2 0 1 D1 D2 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 DN OC P0 P1 P2 P3 DT SC BU 0 0 D70 D71 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 FC0 FC1 FC2 CT0 CT1 CT2 0 1 D142 D143 D193 D194 D195 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207 0 1 0 D1 D2 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 DN OC P0 P1 P2 P3 DT SC BU 0 0 D70 D71 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 FC0 FC1 FC2 CT0 CT1 CT2 0 1 B0 B1 B2 B3 A0 A1 A2 A3 1 0 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 1 0 0 0 1 0 0 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 • When fewer than 201 segments are used Either 160 or 240 bits of serial data must be sent, depending on the number of segments to be used. However, the serial data shown below (the D1 to D136 display data and the control data) must always be sent. 8 bits 1 0 1 0 0 80 bits 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 1 0 0 0 1 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 4. 1/3duty (Simple mode transfer) • When 142 or more segments are used All 240 bits of serial data must be sent. 8 bits 1 0 1 0 0 80 bits 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 • When fewer than 142 segments are used The 160 bits of serial data must be sent. However, the serial data shown below (the D1 to D141 display data and the control data) must always be sent. 80 bits 8 bits 1 0 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 1 0 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 No.A1687-17/35 LC75879PT Control Data Functions (1) PS10 and PS11, PS2 to PS4 … General-purpose output port (P1 to P4) function setting control data These control data bits set the general-purpose output function (High or low level output), clock output function or PWM output function of the P1 output pin, and the general-purpose output function (High or low level output) or PWM output function of the P2 to P4 output pins. However, be careful of being unable to set a PWM output function when the external clock operating frequency is set the fCK2=38[kHz] typ (EXF="1") in external clock operating mode (OC= "1"). In addition, be careful of setting of the general-purpose output function (High or low level output) in the case of the simple mode transfer forcibly. PS10 PS11 0 0 General-purpose output function (High or low level output ) General-purpose output port (P1) function 1 0 Clock output function (Clock frequency : fosc/2, fCK/2 ) 0 1 Clock output function (Clock frequency : fosc/8, fCK/8 ) 1 1 PWM output function (Support for PWM data W10 to W15) PS2 General-purpose output port (P2) function 0 General-purpose output function (High or low level output ) 1 PWM output function (Support for PWM data W20 to W25) PS3 General-purpose output port (P3) function 0 General-purpose output function (High or low level output ) 1 PWM output function (Support for PWM data W30 to W35) PS4 General-purpose output port (P4) function 0 General-purpose output function (High or low level output ) 1 PWM output function (Support for PWM data W10 to W15) (2) EXF … External clock operating frequency setting control data This control data bit sets the operating frequency of the external clock which input into the OSCI pin, when the external clock operating mode (OC="1") is set. However, be careful of setting the fCK1=300[kHz]typ when the external clock operating mode (OC="1") is set in the case of the simple mode transfer forcibly. In addition, this data is effective only when external clock operating mode (OC= "1") is set. EXF External clock operating frequency fCK[kHz] 0 fCK1=300[kHz] typ 1 fCK2=38[kHz] typ (3) DN … S68 pin and S69/OSCI pin state setting control data This control data bit sets state of the S68 pin and the S69/OSCI pin. DN Number of display segments Pin state 1/4 duty 1/3 duty S68 S69/OSCI 0 Up to 264 segments Up to 201 segment “L”(VSS) “L”(VSS)/OSCI 1 Up to 272 segments Up to 207 segment S68 S69/OSCI Note: "L" (VSS) : Low (VSS) level output S68 : Segment output "L" (VSS)/OSCI : Low (VSS) level output in internal oscillator operating mode (OC=0) External clock input in external clock operating mode (OC=1) S69/OSCI : Segment output in internal oscillator operating mode (OC=0) External clock input in external clock operating mode (OC=1) No.A1687-18/35 LC75879PT (4) OC … Internal oscillator operating mode/external clock operating mode switching control data This control data bit selects either the internal oscillator operating mode or external clock operating mode. OC Fundamental clock operating mode 0 Internal oscillator operating mode S69 1 External clock operating mode OSCI Note: S69 OSCI I/O pin (S69/OSCI) state : Segment output : External clock input (5) P0 to P3 … Segment output port/general-purpose output port switching control data These control data bits switch the segment output port/general-purpose output port functions of the S1/P1 to S8/P8 output pins. Control data Output pin state P0 P1 P2 P3 S1/P1 S2/P2 S3/P3 S4/P4 S5/P5 S6/P6 S7/P7 S8/P8 0 0 0 0 S1 S2 S3 S4 S5 S6 S7 S8 0 0 0 1 P1 S2 S3 S4 S5 S6 S7 S8 0 0 1 0 P1 P2 S3 S4 S5 S6 S7 S8 0 0 1 1 P1 P2 P3 S4 S5 S6 S7 S8 0 1 0 0 P1 P2 P3 P4 S5 S6 S7 S8 0 1 0 1 P1 P2 P3 P4 P5 S6 S7 S8 0 1 1 0 P1 P2 P3 P4 P5 P6 S7 S8 0 1 1 1 P1 P2 P3 P4 P5 P6 P7 S8 1 0 0 0 P1 P2 P3 P4 P5 P6 P7 P8 Note1: Sn(n=1 to 8): Segment output ports Pn(n=1 to 8): General-purpose output ports Note2: When are setting (P0,P1,P2,P3)=(1,0,0,1), (1,0,1,0), (1,0,1,1) and (1,1,X,X), the all P1/S1 to P8/S8 output pins selects the segment output port. X: don’t care The table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports (general-purpose output function). Correspondence display data Output pin 1/4 duty 1/3 duty S1/P1 D1 D1 S2/P2 D5 D4 S3/P3 D9 D7 S4/P4 D13 D10 S5/P5 D17 D13 S6/P6 D21 D16 S7/P7 D25 D19 S8/P8 D29 D22 For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output port and is set general-purpose output function, the S4/P4 output pin will output a high level when the display data D13 is 1, and will output a low level when D13 is 0. (6) DT … 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data This control data bit selects either 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive. DT Drive scheme The COM4/S67 pin state 0 1/4-duty 1/3-bias drive COM4 1 1/3-duty 1/3-bias drive S67 Note: COM4 : Common output S67 : Segment output No.A1687-19/35 LC75879PT (7) SC … Segment on/off control data This control data bit controls the on/off state of the segments. SC Display state 0 On 1 Off Note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. (8) BU … Normal mode/power-saving mode control data This control data bit selects either normal mode or power-saving mode. BU Mode Normal mode 0 Power saving mode In this mode, the internal oscillator circuit stops oscillation (the S69/OSCI pin is configured for segment output) if the IC is in the internal oscillator operating mode (OC=0) and the IC stops receiving external clock signals (the S69/OSCI pin is configured for external clock input) if the IC is in the external clock operating mode (OC=1). 1 The common and segment output pins go to the VSS level. However, the S1/P1 to S8/P8 output pins can be used as general-purpose output ports under the control of the data bits P0 to P3. (The general-purpose output port P1 to P4 can not be used as clock output or PWM output). (9) PF0 to PF3 … PWM output waveform frame frequency setting control data These control data bits set the frame frequency of the PWM output waveforms. However, when the PWM output function isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency is set the fCK2=38[kHz] typ (EXF="1") in external clock operating mode (OC= "1") or when the serial data transfer is the simple mode transfer, these control data bits become invalid. Control data PF0 PF1 PF2 PWM output waveform frame frequency fp[Hz] PF3 Internal oscillator operating mode External clock operating mode (The control data OC is 0, (The control data OC is 1 and EXF is 0, fosc=300[kHz] typ) fCK1=300[kHz] typ) 0 0 0 0 fosc/1536 fCK1/1536 1 0 0 0 fosc/1408 fCK1/1408 0 1 0 0 fosc/1280 fCK1/1280 1 1 0 0 fosc/1152 fCK1/1152 0 0 1 0 fosc/1024 fCK1/1024 1 0 1 0 fosc/896 fCK1/896 0 1 1 0 fosc/768 fCK1/768 1 1 1 0 fosc/640 fCK1/640 0 0 0 1 fosc/512 fCK1/512 1 0 0 1 fosc/384 fCK1/384 0 1 0 1 fosc/256 fCK1/256 Note : When is setting (PF0,PF1,PF2,PF3)=(1,1,0,1) and (X,X,1,1), the frame frequency is same as frame frequency at the time of the (PF0,PF1,PF2,PF3)=(1,0,1,0) setting (fosc/896, fCK1/896). X: don’t care No.A1687-20/35 LC75879PT (10) FC0 to FC2 … Common/segment output waveform fram frequency control data These control data bits set the frame frequency of the common and segment output waveforms. Control data FC0 FC1 Common/segment output waveform frame frequency fo[Hz] FC2 Internal oscillator External clock External clock operating mode operating mode operating mode (The control data OC is 0, (The control data OC is 1 (The control data OC is 1 fosc=300[kHz] typ) and EXF is 0, and EXF is 1, fCK1=300[kHz] typ) fCK2=38[kHz] typ) 1 1 0 fosc/6144 fCK1/6144 fCK2/768 1 1 1 fosc/4608 fCK1/4608 fCK2/576 0 0 0 fosc/3072 fCK1/3072 fCK2/384 0 0 1 fosc/2304 fCK1/2304 fCK2/288 0 1 0 fosc/1536 fCK1/1536 fCK2/192 0 1 1 fosc/1152 fCK1/1152 fCK2/144 1 0 0 fosc/768 fCK1/768 fCK2/96 Note: When is setting (FC0,FC1,FC2)=(1,0,1), the frame frequency is same as frame frequency at the time of the (FC0,FC1,FC2)=(0,0,0) setting (fosc/3072, fCK1/3072, fCK2/384). (11) CT0 to CT2 … Display contrast setting control data These control data bits set display contrast. CT0 to CT2: Sets the display contrast (7 steps) CT0 CT1 CT2 LCD drive 3/3 bias voltage VDD0 level 0 0 0 1.00VDD=VDD-(0.05VDD×0) 1 0 0 0.95VDD=VDD-(0.05VDD×1) 0 1 0 0.90VDD=VDD-(0.05VDD×2) 1 1 0 0.85VDD=VDD-(0.05VDD×3) 0 0 1 0.80VDD=VDD-(0.05VDD×4) 1 0 1 0.75VDD=VDD-(0.05VDD×5) 0 1 1 0.70VDD=VDD-(0.05VDD×6) Note: When is setting (CT0,CT1,CT2)=(1,1,1), the LCD drive 3/3 bias voltage VDD0 level is 1.00VDD. Note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it can also be adjusted by modifying the supply pin VDD voltage level. No.A1687-21/35 LC75879PT (12) W10 to W15, W20 to W25, W30 to W35 …… PWM data of the PWM output These control data bits set the pulse width of the PWM output P1 to P4. However, when the PWM output function isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency is set the fCK2=38[kHz] typ (EXF="1") in external clock operating mode (OC= "1") or when the serial data transfer is the simple mode transfer, these control data bits become invalid. Wn0 Wn1 Wn2 Wn3 Wn4 Wn5 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 1 1 0 Pulse width of Pulse width of Wn0 Wn1 Wn2 Wn3 Wn4 Wn5 (1/64)×Tp 0 0 0 0 0 1 (33/64)×Tp (2/64)×Tp 1 0 0 0 0 1 (34/64)×Tp 0 (3/64)×Tp 0 1 0 0 0 1 (35/64)×Tp 0 0 (4/64)×Tp 1 1 0 0 0 1 (36/64)×Tp 0 0 (5/64)×Tp 0 0 1 0 0 1 (37/64)×Tp 0 0 0 (6/64)×Tp 1 0 1 0 0 1 (38/64)×Tp 1 0 0 0 (7/64)×Tp 0 1 1 0 0 1 (39/64)×Tp 1 0 0 0 (8/64)×Tp 1 1 1 0 0 1 (40/64)×Tp 0 0 1 0 0 (9/64)×Tp 0 0 0 1 0 1 (41/64)×Tp 1 0 0 1 0 0 (10/64)×Tp 1 0 0 1 0 1 (42/64)×Tp 0 1 0 1 0 0 (11/64)×Tp 0 1 0 1 0 1 (43/64)×Tp 1 1 0 1 0 0 (12/64)×Tp 1 1 0 1 0 1 (44/64)×Tp 0 0 1 1 0 0 (13/64)×Tp 0 0 1 1 0 1 (45/64)×Tp 1 0 1 1 0 0 (14/64)×Tp 1 0 1 1 0 1 (46/64)×Tp 0 1 1 1 0 0 (15/64)×Tp 0 1 1 1 0 1 (47/64)×Tp 1 1 1 1 0 0 (16/64)×Tp 1 1 1 1 0 1 (48/64)×Tp 0 0 0 0 1 0 (17/64)×Tp 0 0 0 0 1 1 (49/64)×Tp 1 0 0 0 1 0 (18/64)×Tp 1 0 0 0 1 1 (50/64)×Tp 0 1 0 0 1 0 (19/64)×Tp 0 1 0 0 1 1 (51/64)×Tp 1 1 0 0 1 0 (20/64)×Tp 1 1 0 0 1 1 (52/64)×Tp 0 0 1 0 1 0 (21/64)×Tp 0 0 1 0 1 1 (53/64)×Tp 1 0 1 0 1 0 (22/64)×Tp 1 0 1 0 1 1 (54/64)×Tp 0 1 1 0 1 0 (23/64)×Tp 0 1 1 0 1 1 (55/64)×Tp 1 1 1 0 1 0 (24/64)×Tp 1 1 1 0 1 1 (56/64)×Tp 0 0 0 1 1 0 (25/64)×Tp 0 0 0 1 1 1 (57/64)×Tp 1 0 0 1 1 0 (26/64)×Tp 1 0 0 1 1 1 (58/64)×Tp 0 1 0 1 1 0 (27/64)×Tp 0 1 0 1 1 1 (59/64)×Tp 1 1 0 1 1 0 (28/64)×Tp 1 1 0 1 1 1 (60/64)×Tp 0 0 1 1 1 0 (29/64)×Tp 0 0 1 1 1 1 (61/64)×Tp 1 0 1 1 1 0 (30/64)×Tp 1 0 1 1 1 1 (62/64)×Tp 0 1 1 1 1 0 (31/64)×Tp 0 1 1 1 1 1 (63/64)×Tp 1 1 1 1 1 0 (32/64)×Tp 1 1 1 1 1 1 (64/64)×Tp PWM output Note: W10 to W15 … PWM data of the output pin S1/P1 and S4/P4 W20 to W25 … PWM data of the output pin S2/P2 W30 to W35 … PWM data of the output pin S3/P3 PWM output 1 Tp= fp No.A1687-22/35 LC75879PT Display Data and Output Pin Correspondence (1/4 Duty) Output pin COM1 COM2 COM3 COM4 Output pin COM1 COM2 COM3 COM4 S1/P1 D1 D2 D3 D4 S35 D137 D138 D139 D140 S2/P2 D5 D6 D7 D8 S36 D141 D142 D143 D144 S3/P3 D9 D10 D11 D12 S37 D145 D146 D147 D148 S4/P4 D13 D14 D15 D16 S38 D149 D150 D151 D152 S5/P5 D17 D18 D19 D20 S39 D153 D154 D155 D156 S6/P6 D21 D22 D23 D24 S40 D157 D158 D159 D160 S7/P7 D25 D26 D27 D28 S41 D161 D162 D163 D164 S8/P8 D29 D30 D31 D32 S42 D165 D166 D167 D168 S9 D33 D34 D35 D36 S43 D169 D170 D171 D172 S10 D37 D38 D39 D40 S44 D173 D174 D175 D176 S11 D41 D42 D43 D44 S45 D177 D178 D179 D180 S12 D45 D46 D47 D48 S46 D181 D182 D183 D184 S13 D49 D50 D51 D52 S47 D185 D186 D187 D188 S14 D53 D54 D55 D56 S48 D189 D190 D191 D192 S15 D57 D58 D59 D60 S49 D193 D194 D195 D196 S16 D61 D62 D63 D64 S50 D197 D198 D199 D200 S17 D65 D66 D67 D68 S51 D201 D202 D203 D204 S18 D69 D70 D71 D72 S52 D205 D206 D207 D208 S19 D73 D74 D75 D76 S53 D209 D210 D211 D212 S20 D77 D78 D79 D80 S54 D213 D214 D215 D216 S21 D81 D82 D83 D84 S55 D217 D218 D219 D220 S22 D85 D86 D87 D88 S56 D221 D222 D223 D224 S23 D89 D90 D91 D92 S57 D225 D226 D227 D228 S24 D93 D94 D95 D96 S58 D229 D230 D231 D232 S25 D97 D98 D99 D100 S59 D233 D234 D235 D236 S26 D101 D102 D103 D104 S60 D237 D238 D239 D240 S27 D105 D106 D107 D108 S61 D241 D242 D243 D244 S28 D109 D110 D111 D112 S62 D245 D246 D247 D248 S29 D113 D114 D115 D116 S63 D249 D250 D251 D252 S30 D117 D118 D119 D120 S64 D253 D254 D255 D256 S31 D121 D122 D123 D124 S65 D257 D258 D259 D260 S32 D125 D126 D127 D128 S66 D261 D262 D263 D264 S33 D129 D130 D131 D132 S68 D265 D266 D267 D268 S34 D133 D134 D135 D136 S69/OSCI D269 D270 D271 D272 Note: This table assumes that pins S1/P1 to S8/P8 and S69/OSCI are configured for segment output. No.A1687-23/35 LC75879PT For example, the table below lists the output states for the S21 output pin. Display data Output pin (S21) state D81 D82 D83 D84 0 0 0 0 The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off. 0 0 0 1 The LCD segment corresponding to COM4 is on. 0 0 1 0 The LCD segment corresponding to COM3 is on. 0 0 1 1 The LCD segment corresponding to COM3 and COM4 are on. 0 1 0 0 The LCD segment corresponding to COM2 is on. 0 1 0 1 The LCD segment corresponding to COM2 and COM4 are on. 0 1 1 0 The LCD segment corresponding to COM2 and COM3 are on. 0 1 1 1 The LCD segments corresponding to COM2, COM3, and COM4 are on. 1 0 0 0 The LCD segment corresponding to COM1 is on. 1 0 0 1 The LCD segment corresponding to COM1 and COM4 are on. 1 0 1 0 The LCD segment corresponding to COM1 and COM3 are on. 1 0 1 1 The LCD segments corresponding to COM1, COM3, and COM4 are on. 1 1 0 0 The LCD segment corresponding to COM1 and COM2 are on. 1 1 0 1 The LCD segments corresponding to COM1, COM2, and COM4 are on. 1 1 1 0 The LCD segments corresponding to COM1, COM2, and COM3 are on. 1 1 1 1 The LCD segments corresponding to COM1, COM2, COM3, and COM4 are on. No.A1687-24/35 LC75879PT Display Data and Output Pin Correspondence (1/3 Duty) Output pin COM1 COM2 COM3 Output pin COM1 COM2 COM3 S1/P1 D1 D2 D3 S36 D106 D107 D108 S2/P2 D4 D5 D6 S37 D109 D110 D111 S3/P3 D7 D8 D9 S38 D112 D113 D114 S4/P4 D10 D11 D12 S39 D115 D116 D117 S5/P5 D13 D14 D15 S40 D118 D119 D120 S6/P6 D16 D17 D18 S41 D121 D122 D123 S7/P7 D19 D20 D21 S42 D124 D125 D126 S8/P8 D22 D23 D24 S43 D127 D128 D129 S9 D25 D26 D27 S44 D130 D131 D132 S10 D28 D29 D30 S45 D133 D134 D135 S11 D31 D32 D33 S46 D136 D137 D138 S12 D34 D35 D36 S47 D139 D140 D141 S13 D37 D38 D39 S48 D142 D143 D144 S14 D40 D41 D42 S49 D145 D146 D147 S15 D43 D44 D45 S50 D148 D149 D150 S16 D46 D47 D48 S51 D151 D152 D153 S17 D49 D50 D51 S52 D154 D155 D156 S18 D52 D53 D54 S53 D157 D158 D159 S19 D55 D56 D57 S54 D160 D161 D162 S20 D58 D59 D60 S55 D163 D164 D165 S21 D61 D62 D63 S56 D166 D167 D168 S22 D64 D65 D66 S57 D169 D170 D171 S23 D67 D68 D69 S58 D172 D173 D174 S24 D70 D71 D72 S59 D175 D176 D177 S25 D73 D74 D75 S60 D178 D179 D180 S26 D76 D77 D78 S61 D181 D182 D183 S27 D79 D80 D81 S62 D184 D185 D186 S28 D82 D83 D84 S63 D187 D188 D189 S29 D85 D86 D87 S64 D190 D191 D192 S30 D88 D89 D90 S65 D193 D194 D195 S31 D91 D92 D93 S66 D196 D197 D198 S32 D94 D95 D96 S67/COM4 D199 D200 D201 S33 D97 D98 D99 S68 D202 D203 D204 S34 D100 D101 D102 S69/OSCI D205 D206 D207 S35 D103 D104 D105 Note: This table assumes that pins S1/P1 to S8/P8, S67/COM4 and S69/OSCI are configured for segment output. For example, the table below lists the output states for the S21 output pin. Display data Output pin (S21) state D61 D62 D63 0 0 0 The LCD segments corresponding to COM1, COM2, and COM3 are off. 0 0 1 The LCD segment corresponding to COM3 is on. 0 1 0 The LCD segment corresponding to COM2 is on. 0 1 1 The LCD segment corresponding to COM2 and COM3 are on. 1 0 0 The LCD segment corresponding to COM1 is on. 1 0 1 The LCD segment corresponding to COM1 and COM3 are on. 1 1 0 The LCD segment corresponding to COM1 and COM2 are on. 1 1 1 The LCD segments corresponding to COM1, COM2, and COM3 are on. No.A1687-25/35 LC75879PT Output Waveforms (1/4-Duty 1/3-Bias Drive Scheme) fo[Hz] COM1 COM2 COM3 COM4 LCD driver output when all LCD segments corresponding to COM1, COM2, COM3, and COM4 are off. LCD driver output when only LCD segments corresponding to COM1 are on. LCD driver output when only LCD segments corresponding to COM2 are on. LCD driver output when LCD segments corresponding to COM1 and COM2 are on. LCD driver output when only LCD segments corresponding to COM3 are on. LCD driver output when LCD segments corresponding to COM1 and COM3 are on. LCD driver output when LCD segments corresponding to COM2 and COM3 are on. LCD driver output when LCD segments corresponding to COM1, COM2, and COM3 are on. LCD driver output when only LCD segments corresponding to COM4 are on. LCD driver output when LCD segments corresponding to COM2 and COM4 are on. LCD driver output when all LCD segments corresponding to COM1, COM2, COM3, and COM4 are on. VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V No.A1687-26/35 LC75879PT Control data FC0 FC1 Common/segment output waveform frame frequency fo[Hz] FC2 Internal oscillator operating mode External clock operating mode (The control data OC is 0, (The control data OC is 1 External clock operating mode (The control data OC is 1 fosc=300[kHz] typ) and EXF is 0, fCK1=300[kHz] typ) and EXF is 1, fCK2=38[kHz] typ) 1 1 0 fosc/6144 fCK1/6144 fCK2/768 1 1 1 fosc/4608 fCK1/4608 fCK2/576 0 0 0 fosc/3072 fCK1/3072 fCK2/384 0 0 1 fosc/2304 fCK1/2304 fCK2/288 0 1 0 fosc/1536 fCK1/1536 fCK2/192 0 1 1 fosc/1152 fCK1/1152 fCK2/144 1 0 0 fosc/768 fCK1/768 fCK2/96 Note: When is setting (FC0,FC1,FC2)=(1,0,1), the frame frequency is same as frame frequency at the time of the (FC0,FC1,FC2)=(0,0,0) setting (fosc/3072, fCK1/3072, fCK2/384). No.A1687-27/35 LC75879PT Output Waveforms (1/3-Duty 1/3-Bias Drive Scheme) fo[Hz] COM1 VDD0 VDD1 VDD2 0V COM2 VDD0 VDD1 VDD2 0V COM3 VDD0 VDD1 VDD2 0V LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are off. LCD driver output when only LCD segments corresponding to COM1 are on. VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V LCD driver output when only LCD segments corresponding to COM2 are on. VDD0 VDD1 VDD2 0V LCD driver output when LCD segments corresponding to COM1 and COM2 are on. VDD0 VDD1 VDD2 0V LCD driver output when only LCD segments corresponding to COM3 are on. VDD0 VDD1 VDD2 0V LCD driver output when LCD segments corresponding to COM1 and COM3 are on. VDD0 VDD1 VDD2 0V LCD driver output when LCD segments corresponding to COM2 and COM3 are on. VDD0 VDD1 VDD2 0V LCD driver output when all LCD segments corresponding to COM1, COM2,and COM3 are on. VDD0 VDD1 VDD2 0V No.A1687-28/35 LC75879PT Control data FC0 FC1 Common/segment output waveform frame frequency fo[Hz] External clock operating mode Internal oscillator operating mode External clock operating mode (The control data OC is 0, (The control data OC is 1 (The control data OC is 1 fosc=300[kHz] typ) and EXF is 0, fCK1=300[kHz] typ) and EXF is 1, fCK2=38[kHz] typ) FC2 1 1 0 fosc/6144 fCK1/6144 fCK2/768 1 1 1 fosc/4608 fCK1/4608 fCK2/576 0 0 0 fosc/3072 fCK1/3072 fCK2/384 0 0 1 fosc/2304 fCK1/2304 fCK2/288 0 1 0 fosc/1536 fCK1/1536 fCK2/192 0 1 1 fosc/1152 fCK1/1152 fCK2/144 1 0 0 fosc/768 fCK1/768 fCK2/96 Note: When is setting (FC0,FC1,FC2)=(1,0,1), the frame frequency is same as frame frequency at the time of the (FC0,FC1,FC2)=(0,0,0) setting (fosc/3072, fCK1/3072, fCK2/384). PWM output port waveforms VDD P1/P4 (56/64)×Tp (1) VSS (56/64)×Tp VDD P2 (48/64)×Tp VSS (48/64)×Tp VDD P3 (40/64)×Tp VSS (40/64)×Tp VDD P1/P4 (8/64)×Tp (2) VSS (8/64)×Tp VDD P2 VSS (16/64)×Tp (16/64)×Tp VDD P3 VSS (24/64)×Tp (24/64)×Tp VDD P1/P4 (32/64)×Tp (3) VSS (32/64)×Tp VDD P2 (32/64)×Tp VSS (32/64)×Tp VDD P3 (32/64)×Tp VSS (32/64)×Tp Tp Tp= Tp 1 fp Control data PWM output W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 waveforms 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 0 1 (1) 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 (2) 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 (3) No.A1687-29/35 LC75879PT Control data PF0 PF1 PWM output waveform frame frequency fp[Hz] PF2 PF3 Internal oscillator operating mode External clock operating mode (The control data OC is 0, (The control data OC is 1 and fosc=300[kHz] typ) EXF is 0, fCK1=300[kHz] typ) 0 0 0 0 fosc/1536 fCK1/1536 1 0 0 0 fosc/1408 fCK1/1408 0 1 0 0 fosc/1280 fCK1/1280 1 1 0 0 fosc/1152 fCK1/1152 0 0 1 0 fosc/1024 fCK1/1024 1 0 1 0 fosc/896 fCK1/896 0 1 1 0 fosc/768 fCK1/768 1 1 1 0 fosc/640 fCK1/640 0 0 0 1 fosc/512 fCK1/512 1 0 0 1 fosc/384 fCK1/384 0 1 0 1 fosc/256 fCK1/256 Note: When is setting (PF0,PF1,PF2,PF3)=(1,1,0,1) and (X,X,1,1), the frame frequency is same as frame frequency at the time of the (PF0,PF1,PF2,PF3)=(1,0,1,0) setting (fosc/896, fCK1/896). X: don’t care Clock output waveforms Control data P1 Tc/2 Tc= 1 fc Tc Clock frequency of clock output P1 PS10 PS11 fc(=1/Tc)[Hz] 1 0 Clock output function (fosc/2, fCK/2) 0 1 Clock output function (fosc/8, fCK/8) No.A1687-30/35 LC75879PT Display Control and the INH Pin Since the LSI internal data (1/4 duty : the display data D1 to D272 and the control data, 1/3 duty : the display data D1 to D207 and the control data) is undefined when power is first applied, applications should set the INH pin low at the same time as power is applied to turn off the display (This sets the S1/P1 to S8/P8, S9 to S66, COM1 to COM3, COM4/S67, S68, and S69/OSCI pins to the VSS level.) and during this period send serial data from the controller. The controller should then set the INH pin high after the data transfer has completed. This procedure prevents meaningless display at power on (See Figure 5, Figure 6, Figure 7 and Figure 8.) (1)1/4 duty t1 ≈ t2 ≈ VDD INH VIL1 CE Display data and control data transferred VIL1 ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ tc Internal data D1 to D68, PS10, PS11, PS2 to PS4, EXF, DN, OC, P0 to P3, DT, SC, BU Undefined Defined Undefined Internal data D69 to D136, PF0 to PF3, FC0 to FC2, CT0 to CT2 Undefined Defined Undefined Internal data D137 to D200, W10 to W15, W20 to W25, W30 to W35 Undefined Defined Undefined Internal data (D201 to D272) Undefined Undefined Defined Note: t1>1ms t2>0 tc … 10μs min [Figure 5] (2) 1/3 duty t2 ≈ t1 ≈ VDD INH VIL1 CE D1 to D69, PS10, PS11, PS2 to PS4, EXF, DN, OC, P0 to P3, DT, SC, BU Display data and control data transferred VIL1 ≈ ≈ ≈ ≈ ≈ ≈ ≈ tc Undefined Defined Undefined Internal data D70 to D141, PF0 to PF3, FC0 to FC2, CT0 to CT2 Undefined Defined Undefined Internal data D142 to D207, W10 to W15, W20 to W25, W30 to W35 Undefined Defined Undefined Internal data [Figure 6] Note: t1>1ms t2>0 tc … 10μs min No.A1687-31/35 LC75879PT (3)1/4 duty (Simple mode transfer) t2 ≈ t1 ≈ VDD INH VIL1 CE Display data and control data transferred VIL1 ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ tc Internal data D1 to D68, DN, OC, P0 to P3, DT, SC, BU Undefined Defined Undefined Internal data D69 to D136, FC0 to FC2, CT0 to CT2 Undefined Defined Undefined Undefined Defined Undefined Undefined Defined Undefined Internal data (D137 to D200) Internal data (D201 to D272) Note: t1>1ms t2>0 tc …10μs min [Figure 7] (4)1/3 duty (Simple mode transfer) t2 ≈ t1 ≈ VDD INH VIL1 Internal data D1 to D69, DN, OC, P0 to P3, DT, SC, BU Display data and control data transferred Defined Undefined Internal data D70 to D141, FC0 to FC2, CT0 to CT2 Undefined Internal data (D142 to D207) Undefined VIL1 ≈ ≈ ≈ ≈ ≈ ≈ ≈ tc CE Defined Defined [Figure 8] Undefined Undefined Undefined Note: t1>1ms t2>0 tc …10μs min No.A1687-32/35 LC75879PT Notes on Controller Transfer of Display Data When using the LC75879PT in 1/4 duty, applications transfer the display data (D1 to D272) in four operations, and in 1/3 duty, they transfer the display data (D1 to D207) in three operations. In either case, applications should transfer all of the display data within 30 ms to maintain the quality of displayed image. S69/OSCI Pin Peripheral Circuit (1) Internal oscillator operating mode (control data OC=0) Connect the S69/OSCI pin to the LCD panel when the internal oscillator operating mode is selected. OSCI/S69 To LCD panel (2) External clock operating mode (control data OC=1) When the external clock operating mode is selected, insert a current protection resistor Rg (2.2 to 22kΩ) between the S69/OSCI pin and external clock output pin (external oscillator). Determine the value of the resistance according to the allowable current value at the external clock output pin. Also make sure that the waveform of the external clock is not heavily distorted. External clock output pin OSCI/S69 Rg External oscillator Note: Allowable current value at external clock output pin > VDD Rg (3) Unused pin treatment When the S69/OSCI pin is not to be used, select the internal oscillator operating mode (setting control data OC to 0) to keep the pin open. OSCI/S69 OPEN P1 to P4 pin peripheral circuit It is recommended the circuit shown below be used to adjust the brightness of the LED backlight using the PWM output P1 to P4 +5V LED P1 to P4 No.A1687-33/35 LC75879PT Sample Application Circuit 1 1/4 Duty, 1/3Bias (P1) (P2) (P8) VDD +5V General-purpose output ports Used for functions such as backlight control COM1 COM2 VDD1 LCD panel (up to 272 segments) COM3 S67/COM4 VDD2 C C P1/S1 P2/S2 VSS P8/S8 S9 C≥0.047μF INH CE From the controller CL S66 S68 *3 DI *4 OSCI/S69 *3 The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3V or 5V. *4 Connect the S69/OSCI pin to the LCD panel in the internal oscillator operating mode and insert a current protection resistor Rg (2.2 to 22kΩ) between the S69/OSCI pin and external clock output pin (external oscillator) in the external clock operating mode (see “S69/OSCI Pin Peripheral Circuit”). Sample Application Circuit 2 1/3 Duty, 1/3 Bias (P1) (P2) (P8) VDD +5V General-purpose output ports Used for functions such as backlight control COM1 COM3 P1/S1 C C VDD2 P2/S2 VSS P8/S8 S9 C≥0.047μF From the controller INH CE CL DI S66 COM4/S67 *3 LCD panel (up to 207 segments) COM2 VDD1 S68 *4 OSCI/S69 *3 The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3V or 5V. *4 Connect the S69/OSCI pin to the LCD panel in the internal oscillator operating mode and insert a current protection resistor Rg (2.2 to 22kΩ) between the S69/OSCI pin and external clock output pin (external oscillator) in the external clock operating mode (see “S69/OSCI Pin Peripheral Circuit”) No.A1687-34/35 LC75879PT ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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