ON NCV97310 3 buck regulator Datasheet

NCV97310
Automotive BatteryConnected Low-Iq MultiOutput Power Management
Unit with 3 Buck Regulators
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Description
The NCV97310 is a 3−output regulator consisting of a low−Iq
battery−connected 3 A, 2 MHz non−synchronous switcher and two
low−voltage 1.5 A, 2 MHz synchronous switchers; all using integrated
power transistors.
The high−voltage switcher is capable of converting a 4.1 V to 18 V
battery input to a 5 V or 3.3 V output at a constant 2 MHz switching
frequency, delivering up to 3 A. In overvoltage conditions up to 36 V,
the switching frequency folds back to 1 MHz; in load dump conditions
up to 45 V the regulator shuts down.
The output of the battery−connected buck regulator serves as the low
voltage input for the 2 downstream synchronous switchers. Each
downstream output is adjustable from 1.2 V to 3.3 V, with a 1.5 A
average current limit and a constant 2 MHz switching frequency. Each
switcher has an independent enable and reset pin, giving extra power
management flexibility.
For low−Iq operating mode, the low−voltage switchers are disabled
and the standby rail is supplied by a low−Iq LDO (up to 150 mA) with
a typical Iq of 30 mA. The LDO regulator is in parallel to the
high−voltage switcher, and is activated when the switcher is forced in
standby mode.
All 3 SMPS outputs use peak current mode control with internal
slope compensation, internally−set soft−start, battery undervoltage
lockout, battery overvoltage protection, cycle−by−cycle current
limiting, hiccup mode short−circuit protection and thermal shutdown.
An error flag is available for diagnostics.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
5.0 V and 3.3 V Versions Available
Low Quiescent Current in Standby Mode
Programmable Spread Spectrum for EMI Reduction
2 Microcontroller Enabled Low Voltage Synchronous
Buck Converters
Large Conversion Ratio of 18 V to 3.3 V Battery
Connected Switcher
Wide Input of 4.1 to 45 V with Undervoltage Lockout
(UVLO)
Fixed Frequency Operation Adjustable from 2.0 to
2.6 MHz
Internal 1.5 ms Soft−starts
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 4
•
1
32
QFN32
MW SUFFIX
CASE 488AM
MARKING DIAGRAM
1
NCV97310
XX
AWLYYWWG
G
XX
A
WL
YY
WW
G
= 33 or 50
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 24 of this data sheet.
Cycle−by−cycle Current Limit Protections
Hiccup Overcurrent Protections (OCP)
Individual Reset Pins with Adjustable Delays
QFN Package with Wettable Flanks (pin edge plating)
NCV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change
Requirements; AEC−Q100 Qualified and PPAP
Capable
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
Typical Applications
• Infotainment, Body Electronics, Telematics, ECU
1
Publication Order Number:
NCV97310/D
NCV97310
STBYB
VDRV
VDRV1
VDD
BST1
REGULATOR 1
VBAT
SW1
5.0 V
STEP DOWN
COMP1
VINL
LOGIC
RSTB
RMIN
LINEAR
RSTB1
VOUT
REGULATOR
EN
Master Enable
GND1
Exposed
Pad
VDRV
VDRV2
BST2
REGULATOR 2
VIN2
1.2 V −−> 3.3 V
STEP DOWN
SW2
FB2
EN2
RSTB
RSTB2
GND2
BST3
REGULATOR 3
VIN3
1.2 −−> 3.3 V
SW3H
STEP DOWN
SW3L
FB3
EN3
RSTB
RSTB3
GND3
TEMP
OT
WARNING
OSC
ROSC
VIN_UVLO
ERR
VIN_OV
RMOD
RSTB1
RDEPTH
RSTB2
ERRB
RSTB3
Figure 1. NCV97310 Block Diagram − 5.0 V Version
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NCV97310
VDRV
STBYB
VDRV1
VDD
BST1
REGULATOR 1
SW1
3.3 V
VBAT
STEP DOWN
COMP1
VINL
RSTB
NC
LINEAR
RSTB1
VOUT
REGULATOR
EN
Master Enable
GND1
Exposed
Pad
VDRV
VDRV2
BST2
REGULATOR 2
VIN2
1.2 V −−> 3.3 V
STEP DOWN
SW2
FB2
EN2
RSTB
RSTB2
GND2
BST3
REGULATOR 3
VIN3
1.2 V −−> 3.3 V
SW3H
STEP DOWN
SW3L
FB3
EN3
RSTB
RSTB3
GND3
TEMP
OT
WARNING
OSC
ROSC
VIN_UVLO
VIN_OV
ERR
RMOD
RSTB1
RDEPTH
RSTB2
ERRB
RSTB3
Figure 2. NCV97310 Block Diagram − 3.3 V Version
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NCV97310
TYPICAL APPLICATION
COUT1
L1
D1
CBST1
VOUT1
RFB2D
CDRV1
CBST2
RMIN
RFB2U
32
VBAT
1
CIN1
25
SW1 VDRV1
VBAT
EN
BST1
VINL
VOUT
FB2
COUT2
RMIN BST2
GND2 24
VOUT2
SW2
Exposed
Pad
L2
RDEPTH
RMOD
CCOMP1
RCOMP1
STBYB
VIN2
RDEPTH
VIN3
RMOD
VDRV2
RSTB1
SW3H
COMP1
SW3L
L3
ROSC
GND3
COUT3
8
ROSC
ERRB
EN2
RSTB2 GND1 RSTB3
FB3
9
EN3
BST3
CIN2
CDRV2
17
16
RFB3U
CBST3
Figure 3. Typical Application − 5.0 V Version
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VOUT3
NCV97310
C OUT1
D1
C BST1
L1
V OUT1
R FB2D
C DRV1
C BST2
R FB2U
V BAT
1
C IN1
RDEPTH
32
SW1 VDRV1 BST1 VINL VOUT
VBAT
EN
FB2
NC
Exposed
Pad
25
BST2
GND2 24
SW2
STBYB
VIN2
RDEPTH
VIN3
R MOD RMOD
VDRV2
RSTB1
SW3H
C COMP1 R COMP1 COMP1
R OSC
ROSC
8
ERRB EN2 RSTB2 GND1 RSTB3 FB3
9
EN3
C OUT2
L2
C IN2
C DRV2
SW3L
L3
GND3
C OUT3
BST3
16
17
R FB3U
C BST3
Figure 4. Typical Application − 3.3 V Version
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5
V OUT2
V OUT3
NCV97310
Table 1. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
−0.3 to 45
V
45
V
−0.7 to 40
V
−3.0
V
Min/Max Voltage BST1, STBYB, EN
−0.3 to 40
V
Min/Max Voltage VIN2, VIN3, BST2, BST3, SW2, SW3H, SW3L, VOUT, RMIN
−0.3 to 12
V
Min/Max Voltage on RSTB2, RSTB3, EN2, EN3, FB2, FB3
−0.3 to 6
V
Min/Max Voltage on RSTB1, ERRB (3.3 V version)
−0.3 to 3.6
V
Min/Max Voltage on RSTB1, ERRB (5.0 V version)
−0.3 to 6
V
3.6
V
Min/Max Voltage VBAT, VINL
Max Voltage VBAT to SW1
Min/Max Voltage SW1
Min Voltage SW1, SW2, SW3 − 20 ns
Max Voltage BST1 to SW1, BST2 to SW2, BST3 to SW3x
Min/Max Voltage VDRV1, VDRV2, COMP1, ROSC, RMOD, RDEPTH
Thermal Resistance, 5 x 5 QFN Junction – to – Ambient (Note 1)
−0.3 to 3.6
V
25
°C/W
−55 to +150
°C
TJ
−40 to +150
°C
VESD
2.0*
200
kV
V
MSL
Level 1
RθJA
Storage Temperature Range
Operating Junction Temperature Range
ESD Withstand Voltage
Human Body Model
Machine Model
Moisture Sensitivity
Peak Reflow Soldering Temperature
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Mounted on 1 sq. in. of a 4−layer PCB with 1 oz. copper thickness.
*BST2, BST3 HBM 1.5 kV
Table 2. RECOMMENDED OPERATING CONDITIONS
Rating
Value
VIN Range
4.5 V to 36 V
Ambient Temperature Range
−40°C to 125°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NCV97310
Table 3. PIN FUNCTION DESCRIPTIONS
Pin No.
Symbol
Description
1
VBAT
Input voltage from battery. Place an input filter capacitor in close proximity to this pin. Must be tied to Pin 29 −
VINL.
2
EN
High−voltage (battery), TTL−compatible, master enable signal. Grounding this input stops all outputs and
reduces Iq to a minimum (shutdown mode).
3
STBYB
High−voltage (battery), TTL−compatible, mode selection signal. Grounding this input activates the low−Iq
mode of operation for switcher 1 (standby mode).
4
RDEPTH
5
RMOD
Modulation frequency adjustment for spread spectrum. Set with a resistor to GND.
6
RSTB1
Reset with adjustable delay. Goes low when the output is out of regulation.
7
COMP1
Output of the error amplifier for switcher 1
8
ROSC
Provides Frequency Adjustment
9
ERRB
Error flag combining temperature and input and output voltage sensing
10
EN2
11
RSTB2
Reset with adjustable delay. Goes low when the output is out of regulation.
12
GND1
Ground reference for the IC.
13
RSTB3
Reset with adjustable delay. Goes low when the output is out of regulation.
14
FB3
Output voltage sensing, provides adjustability.
15
EN3
TTL compatible low voltage input. Grounding this input stops switcher 3.
16
BST3
Bootstrap input provides drive voltage higher than VIN3 to the high−side N−channel Switch for optimum
switch RDS(on) and highest efficiency.
17
GND3
Ground connection for the source of the low−side switch of switcher 3.
18
SW3L
Drain of the low−side switch. Connect the output inductor to this pin. Must be tied to SW3H.
19
SW3H
Source of the high−side switch. Connect the output inductor to this pin. Must be tied to SW3L.
20
VDRV2
Internal supply voltage for driving the low−voltage internal switches. Connect a capacitor for noise filtering
purposes.
21
VIN3
Low Input voltage for switcher 3. Place an input filter capacitor in close proximity to this pin. Must be
connected to Pin 22 − VIN2 and Pin 28 − VOUT.
22
VIN2
Low Input voltage for switcher 2. Place an input filter capacitor in close proximity to this pin. Must be
connected to Pin 21 − VIN3 and Pin 28 − VOUT.
23
SW2
Switching node of the switcher 2 regulator. Connect the output inductor to this pin.
24
GND2
Ground connection for the source of the low−side switch of switcher 2.
25
BST2
Bootstrap input provides drive voltage higher than VIN2 to the high−side N−channel Switch for optimum
switch RDS(on) and highest efficiency.
26
RMIN
5.0 V Version: Minimum load pull−down for switcher mode. Connect a resistor to VOUT1, if needed
(see applications section for details).
NC
3.3 V Version: This pin is a no−connect. Leave the pin floating.
27
FB2
Output voltage sensing, provides adjustability.
28
VOUT
Output voltage sensing. Delivers the output current in low−Iq mode
29
VINL
Input voltage from battery. Place an input filter capacitor in close proximity to this pin. Must be tied to Pin1 −
VBAT.
30
BST1
Bootstrap input provides drive voltage higher than VBAT to the N−channel Power Switch for optimum switch
Rdson and highest efficiency.
31
VDRV1
32
SW1
Exposed
Pad
Modulation depth adjustment (% of FSW) for spread spectrum. Set with a resistor to GND.
TTL compatible low voltage input. Grounding this input stops switcher 2.
Internal supply voltage for driving the low−voltage internal switch. Connect a capacitor for noise filtering
purposes.
Switching node of the Regulator. Connect the output inductor and cathode of the freewheeling diode to this pin.
Must be connected to GND1 (electrical ground) and to a low thermal resistance path to the ambient
temperature environment.
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NCV97310
Table 4. ELECTRICAL CHARACTERISTICS (VBAT = VINL = 4.5 V to 28 V, VEN = VSTBYB = VEN2 = VEN3 = 5 V, VBSTx = VSWx +
3.0 V, CDRV1 = 0.1 mF, CDRV2 = 0.47 mF. Min/Max values are valid for the temperature range −40°C ≤ TJ ≤ 150°C unless noted otherwise,
and are guaranteed by test, design or statistical correlation.)
Parameter
Symbol
Conditions
Quiescent Current, shutdown
IqSD
Quiescent Current, standby
Min
Typ
Max
Unit
VBAT = VINL= 13.2 V, TJ=25°C,
VEN = 0 V
8
12
mA
IqEN
VBAT = VINL = 13.2 V, TJ=25°C
VEN = 3 V,
VSTBYB = VEN2 = VEN3 = 0 V
25
35
mA
VBAT UVLO Start Threshold
VUV1ST
VBAT rising
4.45
4.85
V
VBAT UVLO Stop Threshold
VUV1SP
VBAT falling
3.7
4.1
V
VBAT UVLO Hysteresis
VUV1HY
QUIESCENT CURRENT
UNDERVOLTAGE LOCKOUT – VBAT (UVLO)
0.75
V
ENABLE
Logic Low (Voltage input needed to
guarantee logic low)
VENLO, VEN2LO,
VEN3LO, VSTBYBLO
Logic High (Voltage input needed to
guarantee logic high)
VENHI, VEN2HI,
VEN3HI, VSTBYBHI
Enable pin input Current
0.8
2
V
V
mA
IEN
VEN = 5 V
0.125
1.0
ISTBYB
VSTBYB = 5 V
0.5
2.0
IEN2, IEN3
VEN2 = VEN3 = 5 V
50
70
tSTBYB
STBYB ‘High’ to Switcher 1 ready
60
200
ms
Switcher 1 output
VOUT
5.0 V Version
3.3 V Version
5.0
3.3
5.1
3.37
V
VOUT Line regulation in Low−Iq mode
VLine1
IOUT = 50 mA, VSTBYB = 0 V,
6 V < VINL = VBAT < 28 V
5
25
mV
VOUT Load regulation in Low−Iq mode
VLoad1
VINL = VBAT = 13.2 V, VSTBYB = 0 V,
1 mA < IOUT < 150 mA
10
35
mV
Voltage drop−out in Low−Iq mode
VDROP1
IOUT = 150 mA, VSTBYB = 0 V
500
mV
Switchers 2 and 3 FB Pin Voltage
during regulation
VFB2R, VFB3R
OUTx connected to FBx
through a 10 kW resistor
V
gm
VCOMP = 1.1 V
4.5 V < VBAT < 18 V
20 V < VBAT < 28 V
Switcher 1 start−up time
30
OUTPUT VOLTAGE
4.9
3.23
1.179
1.200
1.221
0.6
0.35
1.0
0.55
1.4
0.75
ERROR AMPLIFIER − SWITCHER 1
Transconductance (Note 2)
gm(HV)
Output Resistance
COMP Source Current Limit
COMP Sink Current Limit
mmho
ROUT
ISOURCE
ISINK
1.4
MW
mA
VOUT = 4.0 V, VCOMP = 1.1 V
4.5 V < VBAT < 18 V
20 V < VBAT < 28 V
50
25
75
40
100
55
VOUT = 6.0 V, VCOMP = 1.1 V
4.5 V < VBAT < 18 V
20 V < VBAT < 28 V
50
25
75
40
100
55
0.15
0.3
Minimum COMP voltage
VCMPMIN
VOUT = 6.0 V
Maximum COMP voltage
VCMPMAX
VOUT = 4.0 V
mA
1.3
1.6
V
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Not tested in production. Limits are guaranteed by design.
3. Minimum load parameters are only valid for the 5.0 V version, OPN: NCV97310MW50R2G
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NCV97310
Table 4. ELECTRICAL CHARACTERISTICS (VBAT = VINL = 4.5 V to 28 V, VEN = VSTBYB = VEN2 = VEN3 = 5 V, VBSTx = VSWx +
3.0 V, CDRV1 = 0.1 mF, CDRV2 = 0.47 mF. Min/Max values are valid for the temperature range −40°C ≤ TJ ≤ 150°C unless noted otherwise,
and are guaranteed by test, design or statistical correlation.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
fSW1
fSW1(HV)
4.5 < VBAT < 18 V, ROSC = open
20 V < VBAT < 28 V, ROSC = open
1.8
0.9
2.0
1.0
2.2
1.1
MHz
fSW2, fSW3
ROSC = open
1.8
2.0
2.2
MHz
Switching Frequency − ROSC
fROSC
ROSC = 12.5 kW
2.3
2.5
2.8
MHz
ROSC reference voltage
VROSC
ROSC = 25 kW
0.9
1.0
1.1
V
36
V
OSCILLATOR
Switching Frequency − switcher 1
Switching Frequency − switchers 2 & 3
VBAT OVERVOLTAGE SHUTDOWN MONITOR
Overvoltage Stop Threshold
VOV1SP
Overvoltage Start Threshold
VOV1ST
30
Overvoltage Hysteresis
VOV1HY
0.6
V
1.4
2.4
V
20
19.8
V
VBAT FREQUENCY FOLDBACK MONITOR
Frequency Foldback Threshold
VFL1U
VFL1D
VBAT rising
VBAT falling
18.4
18
Frequency Foldback Hysteresis
VFL1HY
0.2
0.3
0.4
V
tSS1, tSS2, tSS3
0.8
1.4
2.0
ms
1.8
0.8
3.4
1.6
A/ms
1.9
3.7
A/ms
360
mW
10
mA
SOFT−START
Soft−Start Completion Time
SLOPE COMPENSATION
Ramp Slope (Note 2) – switcher 1
(With respect to switch current)
Ramp Slope (Note 2) – switchers 2 & 3
Sramp1
Sramp1(HV)
4.5 < VBAT < 18 V
20 V < VBAT < 28 V
Sramp2
POWER SWITCH − SWITCHER 1
ON Resistance
RDS1ON
VBST1 = VSW1 + 3.0 V, ISW1 = 500 mA
185
Leakage current VBAT to SW1
ILKSW1
VEN = 0 V, VSW1 = 0, VBAT = 18 V
Minimum ON Time
tON1MIN
Measured at SW1 pin
45
Minimum OFF Time
tOFF1MIN
Measured at SW1 pin
30
High−Side ON Resistance
RHS2ON
Low−Side ON Resistance
70
ns
50
70
ns
VBST2 = VSW2 + 3.0 V,
ISW2 = 500 mA
165
300
mW
RLS2ON
ISW2 = 500 mA
130
230
mW
Leakage current high−side switch
ILKSW2
VEN2 = 0 V, VSW2 = 0, VIN2 = 5.5 V
5
mA
Minimum ON Time
tON2MIN
Measured at SW2 pin
60
80
95
ns
Minimum OFF Time
tOFF2MIN
Measured at SW2 pin
35
55
75
ns
POWER SWITCHES − SWITCHER 2
Non−overlap time
tNOVLP
10
ns
POWER SWITCHES − SWITCHER 3
High−Side ON Resistance
RHS3ON
VBST3 = VSW3H + 3.0 V,
ISW3H = 500 mA
140
250
mW
Low−Side ON Resistance
Leakage current high−side switch
RLS3ON
ISW3L = 500 mA
130
230
mW
ILKSW3
VEN3 = 0 V, VSW3H = 0, VIN3 = 5.5 V
5
mA
Minimum ON Time
tON3MIN
Measured at SW3x pin
60
80
95
ns
Minimum OFF Time
tOFF3MIN
Measured at SW3x pin
35
55
75
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Not tested in production. Limits are guaranteed by design.
3. Minimum load parameters are only valid for the 5.0 V version, OPN: NCV97310MW50R2G
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NCV97310
Table 4. ELECTRICAL CHARACTERISTICS (VBAT = VINL = 4.5 V to 28 V, VEN = VSTBYB = VEN2 = VEN3 = 5 V, VBSTx = VSWx +
3.0 V, CDRV1 = 0.1 mF, CDRV2 = 0.47 mF. Min/Max values are valid for the temperature range −40°C ≤ TJ ≤ 150°C unless noted otherwise,
and are guaranteed by test, design or statistical correlation.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
POWER SWITCHES − SWITCHER 3
Non−overlap time
tNOVLP
10
ns
PEAK CURRENT LIMITS
A
Current Limit Threshold – switcher 1
Normal mode
Low−Iq mode
ILIM1,stby
Current Limit Threshold – switcher 2
Current Limit Threshold – switcher 3
ILIM1
VSTBYB = 5 V
VSTBYB = 0 V
3.9
0.15
4.4
0.2
4.9
0.25
ILIM2
2.6
2.9
3.2
A
ILIM3
2.6
2.9
3.2
A
SHORT CIRCUIT FREQUENCY FOLDBACK – SWITCHER1
fSW1AF
fSW1AFHV
VOUT = 0 V, 4.5 V < VBAT < 18 V
VOUT = 0 V, 20 V < VBAT < 28 V
450
225
550
275
650
325
kHz
fSW1HIC,
fSW2HIC,
fSW3HIC
VSWx = 0 V
24
32
40
kHz
Reset Threshold − Switcher 1 (as a
ratio of VOUT1)
KRES_LO1
KRES_HI1
VOUT1 decreasing
VOUT1 increasing
90
90.5
92.5
95
97
%
Reset Threshold − Switchers 2 & 3 (at
FBx)
KRES_LO2
KRES_HI2
FBx decreasing
FBx increasing
1.1
Reset Hysteresis (ratio of VOUTx)
KRES_HYS
0.5
Noise−filtering delay
tRES_FILT
5
Lowest Foldback Frequency
Lowest Foldback Frequency – high VIN
HICCUP MODE
Hiccup Mode
RESET
Reset delay time
Reset Output Low level
tRESET
IRSTBx = 2 mA
IRSTBx = 1 mA
IRSTBx = 100 mA
VRESL
V
1.164
3.5
15
%
1.0
4.5
30
IRSTBx = 2 mA
25
ms
5.5
50
ms
ms
ms
0.4
V
BOOTSTRAP VOLTAGE SUPPLY
VDRV1, VDRV2
3.1
3.3
3.5
V
VDRVx POR Start Threshold
VDRV1ST
VDRV2ST
2.7
2.35
2.85
2.5
3.05
2.65
V
VDRVx POR Stop Threshold
VDRV1SP
VDRV2SP
2.55
2.2
2.75
2.35
2.95
2.5
V
2.9
V
Output Voltage
MINIMUM LOAD − 5.0 V VERSION (Note 3)
RMIN Saturation Voltage
VBAT Threshold to Activate RMIN
VRMIN
IRMIN = 100 mA into the pin
VRMIN_TH
0.9
7.2
7.5
7.9
V
SPREAD SPECTRUM
VRMOD
RMOD = 10 kW
0.54
0.60
0.66
V
RDEPTH Pin Voltage
VRDEPTH
RDEPTH = 10 kW
0.54
0.60
0.66
V
Modulation Frequency
fMOD
RMOD = RDEPTH = 10 kW
22
25
28
kHz
fDEPTH,max
RMOD = RDEPTH = 10 kW
2.05
2.3
2.55
MHz
RSSDIS
RMOD or RDEPTH
150
kW
RMOD Pin Voltage
Modulation Depth (Top Frequency)
Spread Spectrum Disable
1.7
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Not tested in production. Limits are guaranteed by design.
3. Minimum load parameters are only valid for the 5.0 V version, OPN: NCV97310MW50R2G
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10
NCV97310
Table 4. ELECTRICAL CHARACTERISTICS (VBAT = VINL = 4.5 V to 28 V, VEN = VSTBYB = VEN2 = VEN3 = 5 V, VBSTx = VSWx +
3.0 V, CDRV1 = 0.1 mF, CDRV2 = 0.47 mF. Min/Max values are valid for the temperature range −40°C ≤ TJ ≤ 150°C unless noted otherwise,
and are guaranteed by test, design or statistical correlation.)
Parameter
Symbol
Conditions
VERRBL
IERRB = 1 mA
Min
Typ
Max
Unit
0.4
V
ERROR FLAG
ERRB Output Low level
THERMAL SHUTDOWN
Thermal Warning Activation
Temperature (Note 2)
TWARN
°C
150
Thermal Shutdown Activation
Temperature (Note 2)
TSD
150
190
°C
Hysteresis (Note 2)
THYS
5
20
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Not tested in production. Limits are guaranteed by design.
3. Minimum load parameters are only valid for the 5.0 V version, OPN: NCV97310MW50R2G
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11
NCV97310
15
25
14
24
IqEN, QUIESCENT CURRENT,
STANDBY (mA)
IqSD, QUIESCENT CURRENT,
SHUTDOWN (mA)
TYPICAL CHARACTERISTICS
13
12
11
10
9
8
7
6
5
−50
−25
0
25
50
75
100
125
23
22
21
20
19
18
17
16
15
−50
150
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Quiescent Current (Shutdown)
vs. Junction Temperature
Figure 6. Quiescent Current (Standby)
vs. Junction Temperature
5.5
150
5.010
5.005
1 mA
5.0
5.000
VOUT, LDO (V)
UVLO (V)
Rising
4.5
Falling
4.0
4.995
150 mA
4.990
4.985
4.980
3.5
4.975
3.0
−50
−25
0
25
50
75
100
125
4.970
−50
150
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. UVLO vs. Junction Temperature
Figure 8. VOUT vs. Junction Temperature
1.2014
150
1.2011
1.2010
1.2012
VREF, SW3 (V)
VREF, SW2 (V)
1.2009
1.2010
1.2008
1.2006
1.2008
1.2007
1.2006
1.2005
1.2004
1.2002
−50
1.2004
−25
0
25
50
75
100
125
150
1.2003
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. SW2 VREF vs. Junction Temperature
Figure 10. SW3 VREF vs. Junction
Temperature
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150
NCV97310
TYPICAL CHARACTERISTICS
1.7
2.016
SOFT START TIME (ms)
2.014
fSW (MHz)
2.012
2.010
2.008
2.006
2.004
1.65
SW1
1.6
SW2
1.55
SW3
1.5
1.45
2.002
−25
0
25
50
75
100
125
1.4
−50
150
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. FSW vs. Junction Temperature
Figure 12. Soft Start Time vs. Junction
Temperature
300
300
250
250
200
150
100
50
150
200
150
100
50
0
−50
−25
0
25
50
75
100
125
0
−50
150
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. SW1 RDS(on) vs. Junction
Temperature
Figure 14. SW2 High Side RDS(on) vs. Junction
Temperature
250
250
200
200
RHS3(on), SW3 (mW)
RLS2(on), SW2 (mW)
−25
TJ, JUNCTION TEMPERATURE (°C)
RHS2(on), SW2 (mW)
RDS(on), SW1 (mW)
2.000
−50
150
100
150
100
50
50
0
−50
−25
0
25
50
75
100
125
150
0
−50
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. SW2 Low Side RDS(on) vs. Junction
Temperature
Figure 16. SW3 High Side RDS(on) vs. Junction
Temperature
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NCV97310
TYPICAL CHARACTERISTICS
202
CURRENT LIMIT, LDO (mA)
250
RLS3(0n), SW3 (mW)
200
150
100
50
0
−50
−25
0
25
50
75
100
125
199
198
197
196
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. SW3 Low Side RDS(on) vs. Junction
Temperature
Figure 18. LDO Current Limit vs. Junction
Temperature
4540
4520
4500
4480
4460
4440
4420
4400
4380
−50
150
2860
PEAK CURRENT LIMIT, SW2 (mA)
PEAK CURRENT LIMIT, SW1 (mA)
200
195
−50
150
4560
−25
0
25
50
75
100
125
150
2850
2840
2830
2820
2810
2800
2790
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. SW1 Peak Current Limit vs.
Junction Temperature
Figure 20. SW2 Peak Current Limit vs.
Junction Temperature
2930
150
3.3325
2920
3.332
2910
2900
VDRV1 (V)
PEAK CURRENT LIMIT, SW3 (mA)
201
2890
2880
2870
3.3315
3.331
3.3305
2860
2850
−50
−25
0
25
50
75
100
125
150
3.33
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. SW3 Peak Current Limit vs.
Junction Temperature
Figure 22. VDRV1 Voltage vs. Junction
Temperature
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150
NCV97310
TYPICAL CHARACTERISTICS
3.2985
3.298
VDRV2 (V)
3.2975
3.297
3.2965
3.296
3.2955
3.295
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. VDRV2 Voltage vs. Junction
Temperature
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150
NCV97310
APPLICATION INFORMATION
General Description
The NCV97310 consists of one 2 MHz battery−connected 2.5 A switcher (switcher 1) with a parallel low−Iq 150 mA LDO,
and two low−voltage 2 MHz 1.5 A switchers (switchers 2 and 3).
STBYB
VDRV
VDRV1
VDD
BST1
REGULATOR 1
VBAT
SW1
5V or 3V3
STEP DOWN
COMP1
VINL
Switcher 1 and low−Iq LDO
LOGIC
RSTB
RMIN
LINEAR
RSTB1
VOUT
REGULATOR
EN
Master Enable
GND1
Exposed
Pad
VDRV
VDRV2
BST2
REGULATOR 2
VIN2
1V2 ... 3V3
STEP DOWN
SW2
Switcher 2
FB2
EN2
RSTB
RSTB2
GND2
BST3
REGULATOR 3
VIN3
1V2...3V3
SW3H
STEP DOWN
SW3L
FB3
EN3
RSTB
RSTB3
GND3
TEMP
OT
WARNING
OSC
ROSC
VIN_UVLO
ERR
VIN_OV
RMOD
RSTB1
RDEPTH
RSTB2
ERRB
RSTB3
Figure 24. NCV97310 Block Schematic
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16
Switcher 3
NCV97310
COMMON BLOCKS
Input Voltage
Manually adjusting the oscillator frequency using the
ROSC pin changes the switching frequency of all 3
switchers, since they share a common oscillator. When
switcher 1 enters maximum duty cycle frequency foldback,
though, switchers 2 and 3 remain at their nominal switching
frequency. The foldback for switcher 1 takes place in logic
outside of the oscillator. The same applies for both
switcher 2 and switcher 3. When switcher 2, for example,
enters maximum duty cycle frequency foldback, the other
two switchers remain at their nominal switching frequency.
The main supply for the part is taken from the VBAT pin,
which much always be tied to a voltage source between
4.1 V and 36 V.
• Below 4.1 V an Undervoltage Lockout (UVLO) circuit
inhibits all switching, resets the Soft−start circuits, and
turns off the LDO.
• Above 36 V, an Overvoltage Shutdown circuit inhibits
all switching and allows the NCV97310 to survive a
45 V load dump. Normal operation resumes when
VBAT goes back down below 30 V.
Although the LDO has its own input pin VINL (that can
also survive a 45 V load dump), it must always be connected
to VBAT for proper operation.
Switcher 2 and switcher 3 each have a dedicated input pin,
VIN2 and VIN3. VIN2 and VIN3 should be shorted together
right at the pin because they share a common drive pin,
VDRV2. Please note that VIN2 and VIN3 are strictly low
voltage (up to 12 V when disabled and 9.5 V when
switching) and there is no voltage sensing present.
It is recommended to connect VIN2 (and VIN3) to
VOUT1, although a different rail could be used to supply
switchers 2 and 3, as long as VBAT is powered and switcher
1 enabled (see Oscillator section for details).
Spread Spectrum
In SMPS devices, switching translates to higher
efficiency. Unfortunately, the switching leads to a much
noisier EMI profile. We can greatly decrease some of the
radiated emissions with some spread spectrum techniques.
Spread spectrum is used to reduce the peak electromagnetic
emissions of a switching regulator.
Time Domain
Frequency Domain
Unmodulated
V
Oscillator
All three switchers share the same oscillator, which
defaults to 2.0 MHz and can be adjusted from 2.0 to 2.6 MHz
using an external resistor (ROSC) to ground. The range of
ROSC value for this range of frequency adjustment is
between 12.5 kW and 50 kW (see Figure 25). For resistor
values below 10 kW, the frequency is safely clamped to 2.8
MHz.
Instead of a resistor, one can force a current out of the
ROSC pin, between 20 mA (corresponding to 2 MHz) and
80ĂmA (corresponding to 2.5 MHz), typical.
t
OSCILLATOR FREQUENCY (MHz)
3fc 5fc 7fc 9fc
fc
3fc 5fc 7fc 9fc
Modulated
V
t
Figure 26.
The spread spectrum used in the NCV97310 is an
“up−spread” technique, meaning the switching frequency is
spread upward from the 2.0 MHz base frequency. For
example, a 5% spread means that the switching frequency is
swept (spread) from 2.0 MHz up to 2.1 MHz in a linear
fashion – this is called the modulation depth. The rate at
which this spread takes place is called the modulation
frequency. For example, a 10 kHz modulation frequency
means that the frequency is swept from 2.0 MHz to 2.1 MHz
in 50 ms and then back down from 2.1 MHz to 2.0 MHz in
50 ms.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
fc
0
10
20
30
40
50
60
ROSC, (kW)
Figure 25. Oscillator Frequency vs. ROSC Value
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17
NCV97310
Spread spectrum is automatically turned off when there is
a short to GND or an open circuit on either the RMOD pin
or the RDEPTH pin. Please be sure that the ROSC pin is an
open circuit when using spread spectrum.
Spread spectrum is automatically turned off when there is
a short to GND or an open circuit on either the RMOD pin
or the RDEPTH pin. Please be sure that the ROSC pin is an
open circuit when using spread spectrum.
Master Enable
The NCV97310 can be completely disabled (shutdown
mode) by connecting the EN pin to ground. As a result, all
outputs are stopped and the internal current consumption
drops below 10 mA.
The EN pin is designed to accept either a logic level signal
or the battery voltage.
Figure 27.
Reset
The modulation depth and modulation frequency are each
set by an external resistor to GND. The modulation
frequency can be set from 5 kHz up to 50 kHz using a resistor
from the RMOD pin to GND. The modulation depth can be
set from 3% up to 30% of the nominal switching frequency
using a resistor from the RDEPTH pin to GND. Please see
the curves below for typical values:
When the voltage on the OUTx pin drops below the reset
threshold (92.5% typically for RSTB1, 93.5% typically for
RSTB2 & RSTB3), the open−drain output RSTBx is pulled
low. The RSTB1 pin is fully operational in Low−Iq mode.
The RSTB2 & RSTB3 pins are asserted (pulled low) when
the associated switcher is disabled and when in Low−Iq
mode (STBYB low).
MODULATION FREQUENCY (kHz)
52
Delay
47
Each of the RSTB signals can either be used as a reset with
delay or a power good (no delay). The delay is determined
by the current into the RSTBx pin, set by a resistor, shown
in Figure 30.
42
37
32
VOUT1
27
22
R RSTBx
17
12
7
RSTBx
RSTx
2
0
10
20
30
RMOD, (kW)
40
50
60
Figure 28. Modulation Frequency vs. RMOD Value
Figure 30. Reset Delay Time
MODULATION DEPTH (%FSW)
35
Use the following equation to determine the ideal reset
delay time using currents less than 1 mA:
30
25
t delay +
20
10
5
0
10
20
30
RDEPTH, (kW)
40
50
I RSTBx
) 1.2
(eq. 1)
where:
tdelay: ideal reset delay time [ms]
IRSTBx: current into the RSTBx pin [mA]
Using IRSTBx = 2 mA removes the delay and allows the reset
to act as a “power good” pin.
The RSTBx resistor is commonly tied to VOUT1. For the
5.0 V version, typical delay times can be achieved with the
following resistor values:
15
0
3000
60
Figure 29. Modulation Depth vs. RDEPTH Value
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NCV97310
RRSTBx (kΩ)
tDLY (ms)
5
4.4
10
7.3
20
13.0
30
18.8
50
31.5
When the master enable pin EN is forced low, the error
flag is not active anymore.
Thermal Shutdown
A thermal shutdown circuit inhibits switching, resets the
Soft−start circuits, and removes DRVx voltages if the
internal temperature exceeds a safe level. Switching is
automatically restored when the temperature returns to a
safer level.
For the 3.3 V version, typical delay times can be achieved
with the following resistor values:
RRSTBx (kΩ)
tDLY (ms)
3.3
4.5
5
5.9
10
10.3
20
19.3
30
28.9
Inductor Selection
By default, a 4.7 mH inductor is recommended for the
primary switching output. If you’d like to choose a different
value, please follow the equation, below.
ǒ
V out 1 *
L+
V OUT
VIN,max
Ǔ
dI r @ f sw @ I out
where:
VOUT: dc output voltage [V]
VIN,max: maximum dc input voltage [V]
dIr: inductor current ripple [%]
fSW: switching frequency [Hz]
IOUT: dc output current [A]
Minimum Dropout Voltage
When operating at low input voltages, two parameters
play a major role in imposing a minimum voltage drop
across the regulator: the minimum off time (that sets the
maximum duty cycle) and the on−state resistance.
When operating in continuous conduction mode (CCM),
the output voltage is equal to the input voltage multiplied by
the duty ratio. Because each switcher needs a sufficient
bootstrap voltage to operate, its duty cycle cannot be 100%:
it needs a minimum off time (toff,min) to periodically re−fuel
the bootstrap capacitor, CBST. This imposes a maximum
duty ratio DMAX= 1 – toff,min ⋅ FSW(min) with the switching
frequency being folded back to FSW(min) = 500 kHz to keep
regulating at the lowest input voltage possible. The drop due
to the on−state resistance is simply the voltage drop across
the switch at the given output current: VSW,drop = IOUT ⋅
RDS(on). Which leads to the maximum output voltage in low
Vin condition: VOUT = DMAX ⋅ VIN(min) − VSW,drop
Discontinuous Mode
In order to ensure continuous conduction mode, the ripple
(half of the peak−to−peak ripple) needs to be less than the
average current through the inductor. The limit can be found
using the following equation for borderline conduction
mode:
I BCM + 1 @
2
ǒ
1*
VOUT
V IN,max
f sw
Ǔ
@
V OUT
L
where:
IBCM: borderline conduction mode output current [A]
VOUT: dc output voltage [V]
VIN,max: maximum dc input voltage [V]
fSW: switching frequency [Hz]
L: inductor value [H]
Average output currents above IBCM will operate in
continuous mode while average output currents below IBCM
will operate in discontinuous mode.
Error Flag
An open drain ERRB pin (active low) flags the status of
several internal error detectors: VBAT undervoltage, VBAT
overvoltage, thermal warning, switcher 1 reset, as well as the
reset flags RSTB2 and RSTB3 if their respective switchers
are enabled. Note that overvoltage is not flagged in Low−Iq
standby mode.
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19
NCV97310
SWITCHER 1
Output Voltage
The NCV97310 comes in a 5.0 V version and a 3.3 V
version. The output of switcher 1, as well as the output of the
low−Iq LDO, are fixed at 5.0 V and 3.3 V, respectively.
switching frequency is lower than its normal mode value
(typically 2 MHz) until the output voltage approaches
regulation. There is no soft−start if the output is already
above the reset threshold.
High Voltage Frequency Foldback
Error Amplifier
To limit the power lost in generating the drive voltage for
the Power Switch, the switching frequency is reduced by a
factor of 2 when the input voltage exceeds the VBAT
Frequency Foldback threshold VFL1U (see Figure 31).
Frequency reduction is automatically terminated when the
input voltage drops back below the VBAT Frequency
Foldback threshold VFL1D.
The error amplifier is a transconductance type amplifier.
The output voltage of the error amplifier controls the peak
inductor current at which the power switch shuts off. The
Current Mode control method employed allows the use of a
simple, type II compensation to optimize the dynamic
response according to system requirements.
The compensation components must be connected
between the output of the error amplifier and the electrical
ground (between pins COMP1 and GND1). For most
applications, the following compensation circuitry is
recommended:
FSW
(MHz)
2
COMP
12.4k
1
22 pF
330 pF
VIN (V)
4
18 20
30
36
45
Figure 31. Switcher 1 Switching Frequency
Reduction at High Input Voltage
Figure 32. Recommended Compensation for
Primary Switcher
Low−IQ Mode
The NCV97310 can be put in a low−Iq regulating mode
by connecting the STBYB pin to ground. As a result,
Switcher 1 turns off and the low−Iq LDO turns on,
maintaining regulation on VOUT (up to 150 mA). In this
mode the VOUT reset monitor is still active (RSTB1 pin),
as well as the under−voltage sensing on VBAT and the
thermal sensing, and they’re all flagged on the ERRB pin.
Switchers 2 and 3 are automatically disabled, with their
respective reset pins pulled low.
Upon enabling, voltage is established at the DRV1 pin,
followed by a pre−charge of the bootstrap capacitor before
switcher 1 starts switching. There is no soft−start unless
VOUT is below the reset threshold
It is recommended to wait at least 200 ms after toggling
STBYB before applying a load higher than 150 mA.
The STBYB pin is designed to accept either a logic level
signal or the battery voltage.
Slope Compensation
A fixed slope compensation signal is generated internally
and added to the sensed current to avoid increased output
voltage ripple due to bifurcation of inductor ripple current
at duty cycles above 50% (sub−harmonics oscillations). The
fixed amplitude of the slope compensation signal requires
the inductor to be greater than a minimum value, depending
on output voltage, in order to avoid sub−harmonic
oscillations. For both 3.3 V and 5.0 V versions, the
recommended inductor value is either 2.2 mH or 4.7 mH.
To determine the minimum inductor required to avoid
sub−harmonic oscillations, please refer to the following
equation:
L min +
Soft−Start
V OUT
ǒ2 * SrampǓ
where:
Lmin: minimum inductor required to avoid sub-harmonic
oscillations [mH]
Upon being enabled or released from a fault condition,
and after the DRV1 voltage is established, a soft−start circuit
ramps the switching regulator error amplifier reference
voltage to the final value. During soft−start, the average
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NCV97310
maintains a minimum 6.8 V on the input. The following
chart describes the ways in which the RMIN pin is
recommended to be used:
Vout: output voltage [V]
Sramp: internal slope compensation [A/ms]
Short Circuit Frequency Foldback
During severe output overloads or short circuits,
switcher 1 automatically reduces its switching frequency.
This creates duty cycles small enough to limit the peak
current in the power components, while maintaining the
ability to automatically reestablish the output voltage if the
overload is removed. If the current is still too high after the
switching frequency folds back to 500 kHz (250 kHz for
VIN > 20 V), the regulator enters hiccup mode (32 kHz) that
further reduces the dissipated power.
Bootstrap
At the DRV1 pin an internal regulator provides a
ground−referenced voltage to an external capacitor
(CDRV1), to allow fast recharge of the external bootstrap
capacitor (CBST1) used to supply power to the power switch
gate driver. If the voltage at the DRV1 pin goes below the
DRV UVLO Threshold VDRVSTP, switching is inhibited and
the Soft−start circuit is reset, until the DRV1 pin voltage
goes back up above VDRVSTT.
In order for the bootstrap capacitor to stay charged, the
Switch node needs to be pulled down to ground regularly. In
very light load condition, when switcher 1 skips switching
cycles to keep the output voltage in regulation, the bootstrap
voltage could collapse and the regulator stop switching. To
prevent this, an internal minimum load is connected on
VOUT to operate correctly in all cases (it is disconnected in
low Iq mode, when the STBYB pin is low).
A fast−charge circuit ensures the bootstrap capacitor is
always charged prior to starting the switcher after it has been
enabled.
VOUT1
Pre−
boost?
VBAT
Condition
RMIN
Resistor
5.0 V
No
VBAT <
6.8 V
Populated
Resistor
connected
from VOUT1
to RMIN pin
5.0 V
Yes
VBAT set
to 6.8 V
from pre−
boost
Not
Populated
RMIN not
connected
3.3 V
No
VBAT <
6.8 V
Not
Populated
RMIN not
connected
3.3 V
Yes
VBAT set
to 6.8 V
from pre−
boost
Not
Populated
RMIN not
connected
Configuration
The RMIN resistance (from VOUT1 to RMIN) should be
between 27 and 35 W. When using an external minimum
load, 3 x 100 W, ¼ W resistors are recommended to be
placed in parallel from VOUT1 to the RMIN pin of the IC.
VOUT1
NCV97310
VBAT
120 W
RMIN
RMIN
VIN
Sense
Minimum Load
For a 3.3 V output, an external minimum load is not
required. The internal minimum load ensures stability under
low−battery conditions. For a 5.0 V output, an external
minimum load is required when not using a pre−boost that
Figure 33. Internal Control for Minimum Load Circuit
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NCV97310
SW1 Maximum Output Current − Worst Case (A)
Current Limiting
Due to the ripple on the inductor current, the average
output current of a buck converter is lower than the peak
current setpoint of the regulator. Figure 34 shows − for a
4.7 mH inductor − how the variation of inductor peak current
with input voltage affects the maximum DC current
switcher 1 can deliver to a load. Figure 35 shows the same
for 2.2 mH inductor.
4.5
4
3.5
Vout1 = 3.3 V
3
Vout1 = 5 V
2.5
2
1.5
1
0.5
0
0
5
10
15
20
25
30
35
INPUT VOLTAGE, (V)
SW1 Maximum Output Current − Worst Case (A)
Figure 34. Switcher 1 Load Current Capability with a
4.7 mH Inductor
4.5
4
3.5
3
Vout1 = 3.3 V
2.5
2
Vout1 = 5 V
1.5
1
0.5
0
0
5
10
15
20
25
30
35
INPUT VOLTAGE, (V)
Figure 35. Switcher 1 Load Current Capability with a
2.2 mH Inductor
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NCV97310
SWITCHERS 2 & 3
Enable
power-on reset procedure. If the short has been removed
then the output re−enables and operates normally; if,
however, the short is still present the cycle begins again. The
hiccup mode is continuous until the short is removed.
When a dc logic high (CMOS/TTL compatible) voltage is
applied to the EN2 or EN3 pin and the STBYB pin is high
Switcher 2 or Switcher 3, respectively, are allowed to
operate. Switcher 1 soft start needs to complete before
Switcher 2 or Switcher 3 is allowed to turn on. A dc logic
low on EN2 or EN3 shuts off the respective regulators.
Current Limiting
Due to the ripple on the inductor current, the average output
current of a buck converter is lower than the peak current
setpoint of the regulator. Figure 36 shows how the variation
of inductor peak current with input voltage affects the
maximum DC current switcher 2 or 3 can deliver to a load.
Soft−Start
SW2 & SW3 Maximum Output Current − Worst Case (A)
Upon being enabled or released from a fault condition,
voltage is first established on the VDRV2 pin (for the first
of switcher 2 or 3 to be enabled). Then a soft−start circuit
ramps the switching regulator error amplifier reference
voltage to the final value, for a duration tSS independent of
the switching frequency (1.4 ms typically).
The low−side switch is always turned on first to ensure a
proper charge of the bootstrap capacitor.
Error Amplifier
The error amplifier is a voltage type amplifier with fixed
internal compensation, optimized for the range of input and
output voltage combinations. The output voltage of the error
amplifier controls the peak inductor current at which the
power shuts off (current−mode operation).
Because the compensation is internally fixed, the value of
the upper feedback resistor (in series between the output and
the feedback pin) must be 10 kW to ensure stability,
including in the case of a 1.2 V output, when no lower
feedback resistor is used. In addition, it is recommended to
use 1 or 2 10 mF capacitors on the output, depending on your
ripple requirement; and an inductor value between 1 mH and
4.7 mH (see slope compensation section).
2.5
VOUT = 1.8 V (L = 1.0 mH)
VOUT = 1.2 V (L = 1.0 mH)
2
1.5
VOUT = 3.3 V (L = 2.2 mH)
1
0.5
0
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
INPUT VOLTAGE, (V)
Figure 36. Switcher 2 or 3 Load Current
Capability vs. Input Voltage
Output Voltage Selection
The voltage outputs for switcher 2 and switcher 3 are
adjustable and can be set with a resistor divider. The FB
reference for both switchers is 1.2 V.
Slope Compensation
A fixed slope compensation signal is generated internally
and added to the sensed current to avoid increased output
voltage ripple due to bifurcation of inductor ripple current
at duty cycles above 50% (sub−harmonic oscillations). The
fixed amplitude of the slope compensation signal requires
the inductor to be greater than a minimum value, dependent
on the output voltage, in order to avoid sub−harmonic
oscillations.
• For a 5 V output, the recommended inductor value is
4.7 mH.
• For 3.3 V or 2.5 V output, the recommended inductor
value is 2.2 mH.
• For 1.2 V or 1.5 V output, the recommended inductor
value is 1.0 mH.
VOUT2 (VOUT3)
RUPPER
FBx = 1.2 V
RLOWER
Figure 37. Output Voltage Selection with
Feedback Divider
The upper resistor is set to 10 kW and is part of the
feedback loop. To maintain stability over all conditions, it is
recommended to change the only the lower feedback resistor
to set the output voltage. Use the following equation:
Short Circuit Frequency Foldback
During severe output overloads or short circuits,
switchers 2 and 3 (independently) automatically enter an
auto−recovery burst mode in order to self−protect. When a
short−circuit is detected, the switcher disables its output and
remains off for the hiccup time and then goes through the
R LOWER + R UPPER
www.onsemi.com
23
V FB
V OUT * V FB
NCV97310
Noise Performance for Heavy Load
Some common setups are listed below:
Desired
Output (V)
VREF (V)
RUPPER
(kW, 1%)
RLOWER
(kW, 1%)
1.2
1.2
10.0
NP
1.5
1.2
10.0
40.0
1.8
1.2
10.0
20.0
2.5
1.2
10.0
9.31
3.3
1.2
10.0
5.76
For heavy load conditions (> 1 A) on the downstream
switching outputs, a snubber circuit is recommended for
improved noise performance. The following circuit can be
used for all output voltage combinations:
SW2
(SW3)
10
100 pF
Figure 38. RC Snubber Circuit for Noise Performance
at Heavy Loads
ORDERING INFORMATION
Device
Package
NCV97310MW50R2G (5.0 V)
QFN32
(Pb−Free)
NCV97310MW33R2G (3.3 V)
QFN32
(Pb−Free)
Shipping†
5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
24
NCV97310
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 488AM
ISSUE A
A
B
D
PIN ONE
LOCATION
ÉÉ
L
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L1
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
0.15 C
0.15 C
A
DETAIL B
0.10 C
ÉÉÉ
ÇÇÇ
EXPOSED Cu
TOP VIEW
(A3)
A1
DETAIL B
ALTERNATE
CONSTRUCTION
0.08 C
SEATING
PLANE
C
SIDE VIEW
NOTE 4
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
9
K
D2
5.30
17
8
32X
MOLD CMPD
MILLIMETERS
MIN
MAX
1.00
0.80
0.05
−−−
0.20 REF
0.30
0.18
5.00 BSC
3.25
2.95
5.00 BSC
2.95
3.25
0.50 BSC
0.20
−−−
0.30
0.50
−−−
0.15
32X
0.63
3.35
L
E2
1
32
3.35 5.30
25
e
e/2
32X
b
0.10
M
C A B
0.05
M
C
BOTTOM VIEW
NOTE 3
0.50
PITCH
32X
0.30
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
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USA/Canada
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Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
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25
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCV97310/D