ams AS1369-BWLT-33 200ma ultra-compact low dropout regulator Datasheet

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Datasheet
AS1369
200mA Ultra-Compact Low Dropout Regulator
2 Key Features
The AS1369 is fully operational with small input and output capacitor
of only 0.47µF offering PSRR of 72dB typical and a noise level of
30µVRMS.
200mA High Maximum Load Current
2.0V to 5.5V Input Voltage
1.2V to 5.0V Output Voltage (in 100mV steps)
High Accuracy: ±2% Over Temperature
Thermal and Over Current Protection
25µA Quiescent Current
<0.1µA Standby Current
High PSRR: 72dB @ 1kHz
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Typical quiescent current is around 25µA while in shutdown the
AS1369 requires less than 0.1µA quiescent current.
Low Dropout Voltage: typ. 40mV @ 100mA
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The AS1369 is an ultra compact high-performance low-dropout
200mA voltage regulator designed for use with very-low ESR output
capacitors. The device can deliver superior performance in all
specifications critical to battery-powered designs, and is perfectly
suited for mobile phones, PDAs, MP3 players, and other battery
powered devices.
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1 General Description
Regulation performance is excellent even under low dropout
conditions, when the power transistor has to operate in linear mode.
The AS1369 offers excellent low-noise performance requiring no
external bypass capacitance.
Multiple output voltage options between 1.2V and 5.0V in 100mV
steps are available and the minimum input voltage is as low as 2.0V
(depending on the output voltage version), so the component can be
used with the new and emerging battery technologies.
No Noise Bypass Capacitor Required
Low Noise: 30µVRMS
Enable Pin
Package: 4-bump WL-CSP
0.5mm pitch
3 Applications
The device is ideal for mobile communication, battery powered
systems and any electronic equipment.
The AS1369 is available in a 4-bump WL-CSP package.
Figure 1. AS1369 - Block Diagram
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VOUT
VREF
On/Off
Control
_
+
C2 1µF
Thermal &
Over Current
Protection
GND
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C1 1µF
AS1369
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VIN
EN
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Revision 1.7
A2
EN
B2
VIN
A1
GND
B1
VOUT
(WLP; Top Through View)
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AS1369
Datasheet - P i n A s s i g n m e n t s
4 Pin Assignments
B2
VIN
A1
GND
B1
VOUT
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A2
EN
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Figure 2. Pin Assignments (Top View)
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AS1369
(WLP; Top Through View)
4.1 Pin Descriptions
Table 1. Pin Descriptions
WLP
Name
A1
GND
A2
EN
B1
VOUT
VIN
Ground
Logic-High Enable Input.
VIH  1.2V: VOUT is enabled.
VIH  0.4V: VOUT is disabled.
Note: This pin is internally pulled down and must not float.
Regulated Output Voltage
Input Voltage
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B2
Description
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Revision 1.7
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AS1369
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
1
Parameter
Min
Max
Units
Comments
Electrical Parameters
Input Supply Voltage
-0.3
+7
V
Shutdown Input Voltage
-0.3
+7
V
Output Voltage
-0.3
+7
V
2
-0.3
+7
V
Latch-Up
-100
+100
mA
Electrostatic Discharge
ESD
Norm: JEDEC 78
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Input/Output Voltage
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Short-circuit protected
IOUT
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Table 2. Absolute Maximum Ratings
2
kV
Norm: MIL 883 E method 3015
500
V
CDM JESD22-C101C methods
Temperature Ranges and Storage Conditions
Thermal Resistance, JA
3
345
ºC/W
The maximum allowable power dissipation is a function of the
maximum junction temperature (TJ(MAX), the junction-toambient thermal resistance (JA), and the ambient
temperature (TAMB). The maximum allowable power
dissipation at any ambient temperature is calculated as:
(EQ 1)
P(MAX) = (TJ(MAX) - (TAMB))/JA
Where:
The value of JA for the WLP package is 345°C/W.
Operating Junction Temperature
-40
+125
ºC
Storage Temperature Range
-65
+150
ºC
Package Body Temperature
+260
ºC
The reflow peak soldering temperature (body temperature)
specified is in accordance with IPC/JEDEC J-STD-020
“Moisture/Reflow Sensitivity Classification for Non-Hermetic
Solid State Surface Mount Devices”.
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1. The AS1369 uses an internal protective structure against light influence. However, exposing the WLP package to direct light could
cause device malfunction.
2. The output PNP structure contains a diode between pins VIN and VOUT that is normally reverse-biased. reversing the polarity of pins
VIN and VOUT will activate this diode.
3. Exceeding the maximum allowable dissipation will cause excessive device temperature and the regulator will go into thermal shutdown.
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Revision 1.7
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AS1369
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
TAMB = -40°C to +85°C, VIN = VOUT(NOM) + 0.5V, COUT = CIN = 0.47µF, IOUT = 1mA, VIH = 1.2V (unless otherwise specified)
Table 3. Electrical Characteristics
Accuracy
VDROP
1
Line Regulation
%
-2
+2
20
40
60
80
0.02
50
100
150
200
0.1
%/V
ppm/°C
Output current
Maximum output current
ILOAD = 0mA
ILOAD = 200mA
In Shutdown
25
35
5
mA
µA
µA
nA
Turn On Time
210
2
PSRR
Output Noise Voltage
IEN
Enable Input Current
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Enable Input Logic Low
Enable Input Logic High
Startup Peak Current
Short Circuit Current
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Temperature Shutdown
Output Capacitor
50
60
500
%/mA
30
µs
IOUT = 10mA, f = 1kHz, VOUT = 1.5V
72
dB
IOUT = 10mA, f = 100kHz, VOUT = 1.5V
55
dB
IOUT = 10mA, f = 1kHz, VOUT = 2.8V
IOUT = 10mA, f = 100kHz, VOUT = 2.8V
1 to 150mA, Trise = Tfall = 1µs,
COUT = CIN = 1µF, ESR load capacitor = 0
BW = 400Hz to 80kHz, COUT = 1µF,
IOUT = 30mA
VEN = 0.4V, VIN = 5.5V
80
56
dB
dB
±65
mV
30
µVRMS
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Load transient response
0.2
0.003
0.003
mV
50
tON
COUT
+0.7
IOUT = 5mA
Standby current
TOFF
-0.7
Output voltage/temperature
ISHDN
IIN(start)
ISC
Over full VIN, VOUT, TAMB = 25°C
including line and load regulation
Over full VIN, VOUT and temperature
including line and load regulation
IOUT = 50mA
IOUT = 100mA
IOUT = 150mA
IOUT = 200mA
VIN = VOUT(NOM) + 0.5V to 5.5V, VOUT  2.5V
VIN = VOUT(NOM) + 0.5V to 5.5V, VOUT  2.5V
Unit
ºC
V
V
IOUT = 5 to 100mA
IOUT = 5 to 200mA
Quiescent current
VEN
1.8
Max
+85
5.5
Load Regulation
IQ
eN
Typ
0.02
0.001
0.001
VOUT
VOUT /
TAMB
Min
-40
2.0
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Dropout Voltage
Condition
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Parameter
Operating Temperature Range
Operational Voltage Range
Input Undervoltage Lockout
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Symbol
TAMB
VIN = 2.0V to 5.5V, TAMB = -40°C to 85°C
IOUT = 0mA
VOUT = 0V
Temperature rising
Hysteresis
Load Capacitor Range
Maximum ESR Load
±1
µA
0.4
V
1.2
210
340
350
mA
mA
160
20
ºC
0.47
µF
0.5

1. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value (does not apply to
input voltages below 2.0V).
2. Turn on time is time measured between the enable input just exceeding the VEN high value and the output voltage just reaching 95% of
its nominal value.
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Revision 1.7
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AS1369
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Figure 3. AC Line Regulation Input Voltage Test Signal
10µs
600µs
600mV
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620µs
10µs
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VIN=VOUT(NOM)+2V
Figure 4. SVR Input Voltage Test Signal
VIN
500mV
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VOUT(NOM) + 1V
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Revision 1.7
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AS1369
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
VIN = VOUT + 0.5V, CIN = COUT = 1µF, TAMB = 25°C (unless otherwise specified).
Figure 6. VOUT vs. VIN; VOUT(NOM)=2.8V
Figure 5. VOUT vs. VIN; VOUT(NOM)=1.5V
-10
-20
Tamb = -40°C
0
-10
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0
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10
Output Voltage (mV) .
Output Voltage (mV) .
10
-20
TAM B = -40°C
TAM B = 25°C
TAM B = 85°C
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Tamb = 25°C
Tamb = 85°C
-30
-30
0
1
2
3
4
5
3
6
3.5
4
Input Voltage (V)
Figure 7. VOUT vs. (VIN-VOUT); TAMB = -40°C
40
-20
-40
-60
-80
50mA
150mA
1mA
100mA
200mA
20
ca
-50
0
50
100
150
-40
-60
-80
VOUT(NOM) = 2.8V
-100
-100
200
-50
0
ni
100
150
200
Figure 10. Dropout Voltage vs. IOUT; VOUT=2.8V
140
50mA
150mA
.
TAM B = 25°C
TAM B = 85°C
120
TAM B = -40°C
Dropout Voltage (mV)
ch
50
VIN - VOUT (mV)
Figure 9. VOUT vs. (VIN-VOUT); TAMB = +85°C
1mA
100mA
200mA
50mA
150mA
-20
VIN - VOUT (mV)
0
-20
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Output Voltage (mV) .
6
0
VOUT(NOM) = 2.8V
20
5.5
Figure 8. VOUT vs. (VIN-VOUT); TAMB = +25°C
Output Voltage (mV) .
Output Voltage (mV) .
0
40
5
40
1mA
100mA
200mA
20
-100
-100
4.5
Input Voltage (V)
-40
-60
-80
100
80
60
40
20
VOUT(NOM) = 2.8V
-100
-100
0
-50
0
50
100
150
200
0
VIN - VOUT (mV)
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50
100
150
200
Load Current (mA)
Revision 1.7
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AS1369
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 11. VOUT vs. IOUT; VOUT(NOM)=1.5V
Figure 12. VOUT vs. IOUT; VOUT(NOM)=2.8V
1.53
2.86
TAM B = -40°C
TAM B = 25°C
TAM B = 85°C
2.84
1.51
1.5
1.49
2.8
2.78
2.76
1.47
2.74
0
50
100
150
200
0
50
TAM B = -40°C
TAM B = -40°C
40
TAM B = 25°C
TAM B = 85°C
TAM B = 25°C
TAM B = 85°C
VOUT (mV) .
30
20
10
0
-10
-20
-30
-40
-50
0
50
100
150
0
200
50
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Figure 15. VOUT vs. Temperature; VOUT(NOM)=1.5V
150
200
Figure 16. VOUT vs. Temperature; VOUT(NOM)=2.8V
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VOUT (mV) .
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0
-5
-10
Te
100
Output Current (mA)
Output Current (mA)
VOUT (mV) .
200
50
30
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
0
150
Figure 14. VOUT vs. IOUT; VOUT(NOM)=2.8V


VOUT (mV) .
Figure 13. VOUT vs. IOUT; VOUT(NOM)=1.5V
5
100
Output Current (mA)
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Output Current (mA)
10
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1.48
2.82
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Output Voltage (V) .
1.52
Output Voltage (V) .
TAM B = -40°C
TAM B = 25°C
TAM B = 85°C
-15
-10
-20
-30
-20
-25
1mA
100mA
200mA
-30
-45 -30 -15
0
-40
50mA
150mA
15
30
45
60
75
90
-50
-45 -30 -15
Ambient Temperature (°C)
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1mA
100mA
200mA
0
50mA
150mA
15
30
45
60
75
90
Ambient Temperature (°C)
Revision 1.7
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AS1369
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 17. Dropout Voltage vs. Temperature; VOUT=2.8V
140
120
100
80
60
40
20
0
-45 -30 -15
0
15
30
45
60
75
350
300
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160
250
Vout = 1.5V
Vout = 2.8V
200
-45 -30 -15
90
Figure 19. Quiescent Current vs. VIN
100
45
60
75
90
Standby Current (nA) .
80
70
60
50
40
30
20
Vout = 1.5V
9
Vout = 2.8V
.
Quiescent Current (µA)
30
10
10
Vout = 2.8V
8
7
6
5
4
3
2
1
0
0
0
1
2
3
4
5
6
0
1
2
Figure 21. Ground Current vs. IOUT
6
Vout = 1.5V
90
Vout = 2.8V
ch
80
5
100
Vout = 1.5V
Vout = 2.8V
.
90
4
Figure 22. Quiescent Current vs. Temperature
Quiescent Current (µA)
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100
3
Input Voltage (V)
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Input Voltage (V)
.
15
Figure 20. Standby Current vs. VIN
Vout = 1.5V
90
70
60
50
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Ground Current (µA)
0
Ambient Temperature (°C)
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Ambient Temperature (°C)
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Dropout Voltage (mV) .
180
400
50mA
150mA
Maximum Output Current (mA)
1mA
100mA
200mA
Figure 18. IOUT(MAX) vs. Temperature
.
200
40
30
20
10
80
70
60
50
40
30
20
10
0
0
40
80
120
160
200
0
-45 -30 -15
Output Current (mA)
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0
15
30
45
60
75
90
Ambient Temperature (°C)
Revision 1.7
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AS1369
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 23. Ground Current vs. Temperature; VOUT=1.5V
Figure 24. Ground Current vs. Temperature; VOUT=2.8V
60
50mA
0mA
50mA
100mA
200mA
100mA
200mA
40
30
20
40
30
20
10
0
15
30
45
60
75
0
-45 -30 -15
90
0
15
30
45
Figure 25. IEN vs. VOUT; VOUT=1.5V
2.5
Ien
1.5
3
1
2
1
0.5
1
0
0
2
0.5
0
0.5
1
1.5
Ien (µA) .
4
Vout (V)
Ien (µA) .
2
3
1
2
0
0
2
1.4
Vout = 2.8V
1.2
Ien (µA) .
1
0.8
0.6
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Ven (V) .
1.5
Vout = 1.5V
1
0.8
0.6
0.4
0.4
0.2
0.2
0
1
Figure 28. IEN vs. Temperature
ch
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Figure 27. VEN vs. Temperature
0
-45 -30 -15
0.5
Input Voltage (V)
ca
Input Voltage (V)
1.2
5
Vout
4
1.5
90
Ien
Vout
2
1.4
75
Figure 26. IEN vs. VOUT; VOUT=2.8V
5
2.5
0
60
Ambient Temperature (°C)
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Ambient Temperature (°C)
Vout (V)
0
-45 -30 -15
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10
50
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.
50
0mA
Ground Current (µA)
Ground Current (µA)
.
60
15
30
45
60
75
90
0
-45 -30 -15
Ambient Temperature (°C)
www.austriamicrosystems.com/LDOs/AS1369
0
15
30
45
60
75
90
Ambient Temperature (°C)
Revision 1.7
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AS1369
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 29. PSRR vs. VIN-VOUT(NOM), VOUT=1.5V
Figure 30. PSRR vs. VIN-VOUT(NOM), VOUT=2.8V
0
0
10mA
100mA
200mA
-10
50mA
150mA
-50
-60
-40
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-40
-30
-50
-60
-70
-70
-80
-80
-90
0
0.5
1
1.5
2
2.5
3
3.5
0
4
0.3
0.6 0.9 1.2
1.5 1.8 2.1
2.4 2.7
Vin - Vout(nom) (V)
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Vin - Vout(nom) (V)
Figure 31. PSRR vs. Frequency, IOUT=10mA
0
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PSRR (dB) .
-30
-90
Figure 32. Spectral Noise vs. Frequency, IOUT=10mA
10
-10
Vout = 1.5V
-20
-30
-40
-50
-60
-70
-80
VOUT = 2.8V
.
Output Noise Density (µV/ Hz)
Vout = 2.8V
PSRR (dB) .
50mA
150mA
-20
-20
PSRR (dB) .
10mA
100mA
200mA
-10
VOUT = 1.5V
1
0.1
0.01
-90
0.01
0.1
1
10
100
10
1000
Frequency (kHz)
100
1000
10000
100000
ca
Frequency (Hz)
Figure 33. Voltage Noise vs. VOUT, IOUT=30mA
ni
100
90
70
60
50
Te
eN (µVrms) .
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80
40
30
20
10
0
1.5
2
2.5
3
3.5
4
4.5
VOUT (V)
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Revision 1.7
10 - 21
AS1369
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
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200mV/Div
20mV/DIV
VIN
VOUT
100µs/Div
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100µs/Div
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200mV/Div
Figure 35. Line Transient Response; IOUT=50mA, VOUT=2.8V,
VIN=4.8V to 4.2V
20mV/DIV
VIN
VOUT
100µs/Div
ca
100µs/Div
200mV/Div
200mV/Div
Figure 37. Line Transient Response; IOUT=100mA, VOUT=2.8V,
VIN=4.8V to 4.2V
20mV/DIV
VOUT
VIN
Figure 36. Line Transient Response; IOUT=100mA, VOUT=1.5V,
VIN = 3.5V to 2.9V
20mV/DIV
VOUT
VIN
Figure 34. Line Transient Response; IOUT=50mA, VOUT=1.5V,
VIN=3.5V to 2.9V
Figure 39. Line Transient Response; IOUT=200mA, VOUT=2.8V,
VIN=4.8V to 4.2V
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200mV/Div
VIN
VOUT
100µs/Div
20mV/DIV
200mV/Div
20mV/DIV
VOUT
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VIN
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Figure 38. Line Transient Response; IOUT=200mA, VOUT=1.5V,
VIN=3.5V to 2.9V
100µs/Div
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AS1369
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
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100mA/Div
100mA/Div
IOUT
VOUT
10µs/Div
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1V/Div
50mA/DIV
IIN
IIN
50mA/DIV
1V/Div
VOUT
VOUT
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VEN
1V/Div
Figure 45. Shutdown
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Figure 44. Startup
100µs/Div
ca
100µs/Div
100mV/DIV
100mA/Div
Figure 43. Load Transient; IOUT= 1mA to 150mA
VIN=3.0V, VOUT=2.8V, in Dropout
100mV/DIV
VOUT
IOUT
Figure 42. Load Transient; IOUT= 0mA to 150mA
VIN=3.0V, VOUT=2.8V, in Dropout
VEN
100mV/DIV
IOUT
VOUT
100µs/Div
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100µs/Div
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100mA/Div
Figure 41. Load Transient; IOUT= 0mA to 150mA
VIN=3.3V, VOUT=2.8V
100mV/DIV
VOUT
IOUT
Figure 40. Load Transient; IOUT= 0mA to 150mA
VIN=2.0V, VOUT=1.5V
250µs/Div
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AS1369
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8 Application Information
VIN
VOUT
_
+
C2
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VREF
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Figure 46. Typical Application Diagram
On/Off
Control
Thermal &
Over Current
Protection
GND
EN
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Figure 46 shows the block diagram of the AS1369. It identifies the basics of a series linear regulator employing a P-Channel MOSFET as the
control element. A stable voltage reference (REF in Figure 46) is compared with an attenuated sample of the output voltage. Any difference
between the two voltages (reference and sample) creates an output from the error amplifier that drives the series control element to reduce the
difference to a minimum. The error amplifier incorporates additional buffering to drive the relatively large gate capacitance of the series pass Pchannel MOSFET, when additional drive current is required under transient conditions. Input supply variations are absorbed by the series
element, and output voltage variations with loading are absorbed by the low output impedance of the regulator.
8.1 Dropout Voltage
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Dropout is the input to output voltage difference, below which the linear regulator ceases to regulate. At this point, the output voltage change
follows the input voltage change. Dropout voltage may be measured at different load currents, but is usually specified at maximum output. As a
result, the MOSFET maximum series resistance over temperature is obtained. More generally:
VDROPOUT = ILOAD x RSERIES
(EQ 2)
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Dropout is probably the most important specification when the regulator is used in a battery application. The dropout performance of the
regulator defines the useful “end of life” of the battery before replacement or re-charge is required.
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AS1369
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 47. Graphical Representation of Dropout Voltage
VIN
VIN=VOUT(TYP)+0.5V
VOUT
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Dropout
Voltage
100mV
VIN
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VOUT
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VOUT
VIN
Figure 47 shows the variation of VOUT as VIN is varied for a certain load current. The practical value of dropout is the differential voltage (VOUT
- VIN) measured at the point where the LDO output voltage has fallen by 100mV below the nominal, fully regulated output value. The nominal
regulated output voltage of the LDO is that obtained when there is 500mV (or greater) input-output voltage differential.
8.2 Efficiency
Low quiescent current and low input-output voltage differential are important in battery applications amongst others, as the regulator efficiency is
directly related to quiescent current and dropout voltage. Efficiency is given by:
V LOAD  I LOAD
Efficiency = -----------------------------------------  100 %
V IN  I Q + I LOAD 
(EQ 3)
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Where:
IQ = Quiescent current of LDO
8.3 Power Dissipation
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Maximum power dissipation (PD) of the LDO is the sum of the power dissipated by the internal series MOSFET and the quiescent current
required to bias the internal voltage reference and the internal error amplifier, and is calculated as:
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PD  MAX   Seriespass  = I LOAD  MAX   V IN  MAX  – V OUT  MIN   Watts
(EQ 4)
Internal power dissipation as a result of the bias current for the internal voltage reference and the error amplifier is calculated as:
PD  MAX   Bias  = V IN  MAX  I Q Watts
(EQ 5)
PD  MAX   Total  = PD  MAX   Seriespass  + PD  MAX   Bias  Watts
(EQ 6)
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Total LDO power dissipation is calculated as:
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AS1369
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.4 Junction Temperature
Under all operating conditions, the maximum junction temperature should not be allowed to exceed 125°C (unless otherwise specified in the
datasheet). Limiting the maximum junction temperature requires knowledge of the heat path from junction to case (JC°C/W fixed by the IC
manufacturer), and adjustment of the case to ambient heat path (CA°C/W) by manipulation of the PCB copper area adjacent to the IC position.
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Figure 48. Package Physical Arrangements
Chip
Package
Transfer Layer
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PCB
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CS-WLP Package
Solder Balls
Figure 49. Steady State Heat Flow Equivalent Circuit
Junction
TJ°C
Package
TC°C
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RJC
Ambient
TA°C
PCB/Heatsink
TS°C
RCS
RSA
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Chip
Power
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Total Thermal Path Resistance:
RJA = RJC + RCS + RSA
(EQ 7)
TJ = (PD(MAX) x RJA) + TAMB ºC
(EQ 8)
Junction Temperature (TJ ºC) is determined by:
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Revision 1.7
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AS1369
Datasheet
8.5 Explanation of Steady State Specifications
8.5.1
Line Regulation
Line regulation is defined as the change in output voltage when the input (or line) voltage is changed by a known quantity. It is a measure of the
regulator’s ability to maintain a constant output voltage when the input voltage changes. Line regulation is a measure of the DC open loop gain
of the error amplifier. More generally:
V OUT
Line Regulation = ----------------- and is a pure number
V IN
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(EQ 9)
In practise, line regulation is referred to the regulator output voltage in terms of % / VOUT. This is particularly useful when the same regulator is
available with numerous output voltage trim options.
8.5.2
Load Regulation
(EQ 10)
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V OUT
100
Line Regulation = -----------------  ------------- % / V
V IN
V OUT
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Load regulation is defined as the change of the output voltage when the load current is changed by a known quantity. It is a measure of the
regulator’s ability to maintain a constant output voltage when the load changes. Load regulation is a measure of the DC closed loop output
resistance of the regulator. More generally:
V OUT
Load Regulation = ----------------- and is units of ohms ()
I OUT
(EQ 11)
In practise, load regulation is referred to the regulator output voltage in terms of % / mA. This is particularly useful when the same regulator is
available with numerous output voltage trim options.
V OUT 100
Load Regulation = -----------------  ------------- % / mA
I OUT V OUT
8.5.3
Setting Accuracy
(EQ 12)
Accuracy of the final output voltage is determined by the accuracy of the ratio of R1 and R2, the reference accuracy and the input offset voltage
of the error amplifier. When the regulator is supplied pre-trimmed, the output voltage accuracy is fully defined in the output voltage specification.
When the regulator has a SET terminal, the output voltage may be adjusted externally. In this case, the tolerance of the external resistor network
must be incorporated into the final accuracy calculation. Generally:
R1  R1
V OUT =  V SET  V SET   1 + ---------------------
R2  R2
(EQ 13)
8.5.4
Total Accuracy
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The reference tolerance is given both at 25°C and over the full operating temperature range.
Away from dropout, total steady state accuracy is the sum of setting accuracy, load regulation and line regulation. Generally:
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Total % Accuracy = Setting % Accuracy + Load Regulation % + Line Regulation %
(EQ 14)
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8.6 Explanation of Dynamic Specifications
8.6.1
Power Supply Rejection Ratio (PSRR)
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Known also as Ripple Rejection, this specification measures the ability of the regulator to reject noise and ripple beyond DC. PSRR is a
summation of the individual rejections of the error amplifier, reference and AC leakage through the series pass transistor. The specification, in
the form of a typical attenuation plot with respect to frequency, shows up the gain bandwidth compromises forced upon the designer in low
quiescent current conditions. Generally:
V OUT
PSRR = 20Log ----------------- dB using lower case  to indicate AC values
V IN
(EQ 15)
Power supply rejection ratio is fixed by the internal design of the regulator. Additional rejection must be provided externally.
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AS1369
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.6.2
Output Capacitor ESR
The series regulator is a negative feedback amplifier, and as such is conditionally stable. The ESR of the output capacitor is usually used to
cancel one of the open loop poles of the error amplifier in order to produce a single pole response. Excessive ESR values may actually cause
instability by excessive changes to the closed loop unity gain frequency crossover point. The range of ESR values for stability is usually shown
either by a plot of stable ESR versus load current, or a maximum value in the datasheet.
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Some ceramic capacitors exhibit large capacitance and ESR variations with variations in temperature. Z5U and Y5V capacitors may be required
to ensure stability at temperatures below TAMB = -10°C. With X7R or X5R capacitors, a 1µF capacitor should be sufficient at all operating
temperatures.
Larger output capacitor values (10µF) help to reduce noise and improve load transient-response, stability and power-supply rejection.
8.6.3
Input Capacitor
8.6.4
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An input capacitor at VIN is required for stability. It is recommended that a 1.0µF capacitor be connected between the AS1369 power supply
input pin VIN and ground (capacitance value may be increased without limit subject to ESR limits). This capacitor must be located at a distance
of not more than 1cm from the VIN pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used
at the input.
Noise
8.6.5
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The regulator output is a DC voltage with noise superimposed on the output. The noise comes from three sources; the reference, the error
amplifier input stage, and the output voltage setting resistors. Noise is a random fluctuation and if not minimized in some applications, will
produce system problems.
Transient Response
The series regulator is a negative feedback system, and therefore any change at the output will take a finite time to be corrected by the error
loop. This “propagation time” is related to the bandwidth of the error loop. The initial response to an output transient comes from the output
capacitance, and during this time, ESR is the dominant mechanism causing voltage transients at the output. More generally:
V TRANSIENT = I OUTPUT  R ESR
Units are Volts, Amps, Ohms.
(EQ 16)
Thus an initial +50mA change of output current will produce a -12mV transient when the ESR=240m. Remember to keep the ESR within
stability recommendations when reducing ESR by adding multiple parallel output capacitors.
After the initial ESR transient, there follows a voltage droop during the time that the LDO feedback loop takes to respond to the output change.
This drift is approx. linear in time and sums with the ESR contribution to make a total transient variation at the output of:
T
V TRANSIENT = I OUTPUT   R ESR + ----------------- Units are Volts, Seconds, Farads, Ohms.

C LOAD
(EQ 17)
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Where:
CLOAD is output capacitor
T= Propagation Delay of the LDO
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This shows why it is convenient to increase the output capacitor value for a better support for fast load changes. Of course the formula holds for
t < “propagation time”, so that a faster LDO needs a smaller cap at the load to achieve a similar transient response. For instance 50mA load
current step produces 50mV output drop if the LDO response is 1usec and the load cap is 1µF.
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There is also a steady state error caused by the finite output impedance of the regulator. This is derived from the load regulation specification
discussed above.
8.6.6
Turn On Time
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This specification defines the time taken for the LDO to awake from shutdown. The time is measured from the release of the enable pin to the
time that the output voltage is within 5% of the final value. It assumes that the voltage at VIN is stable and within the regulator min and max limits.
Shutdown reduces the quiescent current to very low, mostly leakage values (<1µA).
8.6.7
Thermal Protection
To prevent operation under extreme fault conditions, such as a permanent short circuit at the output, thermal protection is built into the device.
Die temperature is measured, and when a 150°C threshold is reached, the device enters shutdown. When the die cools sufficiently, the device
will restart (assuming input voltage exists and the device is enabled). Hysteresis of 20°C prevents low frequency oscillation between start-up and
shutdown around the temperature threshold.
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Revision 1.7
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AS1369
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
9 Package Drawings and Markings
The AS1369 is available in a 4-bump WL-CSP package.
Figure 50. 4-bump WL-CSP Package
Bottom view (ball side)
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Top through view
Die size after cutting 1015x1015 ±20µm
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ASRW
XXXX
Notes:
1. ccc – Coplanarity
2. All dimensions are in µm.
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AS1369
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
Revision History
Revision
Date
Owner
Description
1.4
Initial revision
1.5
Package marking updated
21 Sep, 2011
1.7
12 Dec, 2011
Changes made across the document
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Updated equations in Power Dissipation section
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Note: Typos may not be explicitly mentioned under revision history.
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AS1369
Datasheet - O r d e r i n g I n f o r m a t i o n
10 Ordering Information
The AS1369 is available as the standard versions listed in Table 4. Other versions are available upon request. Contact austriamicrosystems, AG
for more information.
Table 4. Ordering Information
Marking
Output
Description
Delivery Form
Package
AS1369-BWLT-12
ASRW
1.2V
200mA Ultra-Compact Low
Dropout Regulator
Tape and Reel
4-bump WL-CSP
AS1369-BWLT-13
ASRX
1.3V
200mA Ultra-Compact Low
Dropout Regulator
Tape and Reel
4-bump WL-CSP
AS1369-BWLT-15
ASPZ
1.5V
200mA Ultra-Compact Low
Dropout Regulator
Tape and Reel
4-bump WL-CSP
AS1369-BWLT-18
ASP0
1.8V
200mA Ultra-Compact Low
Dropout Regulator
Tape and Reel
4-bump WL-CSP
AS1369-BWLT-25
ASP1
2.5V
200mA Ultra-Compact Low
Dropout Regulator
Tape and Reel
4-bump WL-CSP
AS1369-BWLT-30
AS1369-BWLT-33
AS1369-BWLT-45
AS1369-BWLT-50
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AS1369-BWLT-28
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Ordering Code
ASP2
2.8V
200mA Ultra-Compact Low
Dropout Regulator
Tape and Reel
4-bump WL-CSP
ASP3
3.0V
200mA Ultra-Compact Low
Dropout Regulator
Tape and Reel
4-bump WL-CSP
ASP4
3.3V
200mA Ultra-Compact Low
Dropout Regulator
Tape and Reel
4-bump WL-CSP
ASP5
4.5V
200mA Ultra-Compact Low
Dropout Regulator
Tape and Reel
4-bump WL-CSP
ASP6
5.0V
200mA Ultra-Compact Low
Dropout Regulator
Tape and Reel
4-bump WL-CSP
1. Available upon request. Contact austriamicrosystems AG for details.
Note: All products are RoHS compliant and austriamicrosystems green.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
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Technical Support is available at http://www.austriamicrosystems.com/Technical-Support
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For further information and requests, please contact us mailto:[email protected]
or find your local distributor at http://www.austriamicrosystems.com/distributor
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AS1369
Datasheet - O r d e r i n g I n f o r m a t i o n
Copyrights
Copyright © 1997-2011, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
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Disclaimer
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Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding
the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are
specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
Headquarters
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Contact Information
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The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not
be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use,
interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
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Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
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http://www.austriamicrosystems.com/contact
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