Allegro A5950GEUSR-T Motor lead short-to-ground protection Datasheet

A5950
DC Motor Driver
FEATURES AND BENEFITS
DESCRIPTION
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Designed for pulse-width-modulated (PWM) control of DC
motors, the A5950 is capable of peak output currents up to
±3 A and operating voltages up to 40 V.
Overcurrent protection (OCP)
Motor lead short-to-ground protection
Motor lead short-to-battery protection
Motor short protection
Low-power standby mode
Fault output
Adjustable current limit option
Current-to-voltage output
Synchronous rectification – high-side
Internal UVLO
Crossover-current protection
Thermal warning and shutdown function
AEC-Q100 Grade 1 qualified – K version
Input terminals are provided for use in controlling the speed and
direction of a DC motor with externally applied PWM control
signals. Internal synchronous rectification control circuitry is
provided to lower power dissipation during PWM operation.
Internal circuit protection includes overcurrent protection,
motor lead short to ground or supply, thermal shutdown with
hysteresis, undervoltage monitoring of VBB, and crossovercurrent protection.
The A5950 is supplied in a low-profile 4 mm × 4 mm 16-contact
QFN (suffix “EU”) package with wettable flank option (suffix
“-P”), or a 16-lead eTSSOP (suffix “LP”), all three with exposed
power tab for enhanced thermal performance.
PACKAGES:
Not to scale
16-lead QFN
with exposed themal pad
(suffix EU, option -T)
16-lead QFN
with exposed themal pad
and wettable flank (suffix EU, option -P)
16-lead TSSOP
with exposed themal pad
(suffix LP)
CP2
VCP
CP1
OCL2
OCP
FAULTn
UVLO
TWarn
RESETn
CHARGE
PUMP
VBB
Load
Supply
Disable
PHASE
OUT1
ENABLE
CONTROL
LOGIC
MODE
OUT2
7V
LSS
OCLSEL
RSENSE (optional)
GND
OCL1
OCL2
×5
VREF
÷10
AIOUT
500 mV
Figure 1: Functional Block Diagram
A5950-DS, Rev. 2
MCO-0000177
May 11, 2017
A5950
DC Motor Driver
SPECIFICATIONS
SELECTION GUIDE
Part Number
Operating Ambient
Temperature Range TA (°C)
A5950GEUSR-T
–40 to 105
16-lead QFN with exposed pad
6000 pieces per 13-in. reel
A5950GLPTR-T
–40 to 105
16-lead TSSOP with exposed pad
4000 pieces per 13-in. reel
A5950KEUSR-J
–40 to 125
16-lead QFN with exposed pad and wettable flank
6000 pieces per 13-in. reel
A5950KLPTR-T
–40 to 125
16-lead TSSOP with exposed pad
4000 pieces per 13-in. reel
Packaging
Packing
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Notes
Rating
Unit
V
Load Supply Voltage
VBB
40
Motor Outputs
VOUT
–2 to 42
V
±0.5
V
±2.5
V
3
A
LSS
VLSS
Output Current
IOUT
Transient Output Current
IOUTPK
tw < 200 ns
Continuous [1]
internally limited
A
VREF
–0.3 to 6
V
Logic Input Voltage Range
VIN
–0.3 to 6
V
Junction Temperature
TJ
150
°C
Storage Temperature Range
Tstg
VREF
Operating Temperature Range
[1]
TA
tw < 500 ns
–55 to 150
°C
Range G
–40 to 105
°C
Range K
–40 to 125
°C
Power dissipation and thermal limits must be observed.
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Package Thermal Resistance
[2] Additional
Symbol
RqJA
Test Conditions [2]
Value
Unit
16-lead TSSOP
(suffix LP)
JEDEC Hi-K board
34
°C/W
2 layer PCB, 1-in.2 copper
51
°C/W
16-lead QFN
(suffix EU)
JEDEC Hi-K board
2 layer PCB, 1-in.2 copper
36
°C/W
TBD
°C/W
thermal information available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A5950
DC Motor Driver
OUTB
VBB
LSS
OUTA
16
15
14
13
PINOUT DIAGRAMS AND TERMINAL LIST TABLE
FAULTn
1
12 GND
RESETn
2
11
VREF
3
OCLSEL
4
PAD
10 CP2
8
VCP
AIOUT
6
7
MODE
PHASE
5
9
ENABLE
CP1
16-Lead QFN (EU) Package Pinout Diagram
CP1 1
16 CP2
GND 2
15 VCP
14 AIOUT
OUTA 3
LSS 4
PAD
VBB 5
13 MODE
12 ENABLE
11 PHASE
OUTB 6
FAULTn 7
10 OCLSEL
RESETn 8
9 VREF
16-Lead TSSOP (LP) Package Pinout Diagram
Terminal List Table
Name
Number
Function
EU
LP
AIOUT
8
14
Analog sense voltage output
CP1
11
1
Charge pump capacitor
CP2
10
16
Charge pump capacitor
ENABLE
6
12
Logic control input
FAULTn
1
7
Open drain logic output, active low
GND
12
2
Ground terminal
LSS
14
4
Sense voltage
MODE
7
13
Logic control input
OCLSEL
4
10
Logic control input
OUTA
13
3
Motor output
OUTB
16
6
Motor output
PHASE
5
11
Logic control input
RESETn
2
8
Logic control input, active low
Supply voltage
VBB
15
5
VCP
9
15
Charge pump capacitor
VREF
3
9
Analog input to set current limit
–
PAD
PAD
Exposed pad of the package providing enhanced thermal dissipation
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A5950
DC Motor Driver
ELECTRICAL CHARACTERISTICS:
G Range Version: Valid at TA = 25°C, VBB = 5.5 to 40 V (unless noted otherwise)
K Range Version: Valid at TA = –40°C to 125°C, VBB = 5.5 to 40 V (unless noted otherwise)
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
–
5.8
9
mA
–
1
5
µA
GENERAL
VBB Supply Current
IBB
Outputs off or Brake mode
IBB(STANDBY) Standby Mode
OUTPUT DRIVERS
Source Driver On Resistance
Sink Driver On Resistance
RDSON(source)
RDSON(sink)
I = 3 A, TJ = 25°C, VBB = 8 V
–
335
–
mΩ
I = 3 A, TJ = 125°C, VBB = 8 V
–
530
700
mΩ
I = 3 A, TJ = 25°C, VBB = 5.5 V
–
370
–
mΩ
I = 3 A, TJ = 125°C, VBB = 5.5 V
–
590
775
mΩ
I = 3 A, TJ = 25°C, VBB = 8 V
–
365
–
mΩ
I = 3 A, TJ = 125°C, VBB = 8 V
–
590
775
mΩ
I = 3 A, TJ = 25°C, VBB = 5.5 V
–
390
–
mΩ
I = 3 A, TJ = 125°C, VBB = 5.5 V
–
670
875
mΩ
Body Diode Forward Voltage
VF
I=3A
–
1.15
1.4
V
Output Rise time
tR
VBB = 12 V, 10% to 90%
50
100
200
ns
Output Fall Time
tF
VBB = 12 V, 90% to 10%
50
100
200
ns
Dead Time (Crossover)
tD
–
350
550
ns
LOGIC INPUT AND OUTPUT
Logic Output Voltage
VO
I = 2 mA, fault asserted
–
0.2
0.5
V
Logic Output Leakage
IFLTn
V=5V
–
–
5
µA
VIH
PHASE, ENABLE, MODE, OCLSEL
2.0
–
5.5
V
VIL
PHASE, ENABLE, MODE, OCLSEL
0
–
0.8
V
Logic Input Voltage
Logic Input Hysteresis
VIHRESETn
RESETn
2.5
–
5.5
V
VILRESETn
RESETn
0
–
0.4
V
mV
VHYS
PHASE, ENABLE, MODE, OCLSEL
200
355
500
Logic Input Pull-Up Current
IPU
OCLSEL, MODE; VIN = 0 V
–20
–55
–90
µA
Logic Input Pull-Down Resistor
RPD
RESETn, PHASE, ENABLE
25
50
80
kΩ
[1] For
[2] For
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
Range G devices, specified limits are tested at a single temperature and assured over operating temperature range by design and characterization.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A5950
DC Motor Driver
ELECTRICAL CHARACTERISTICS (continued):
G Range Version: Valid at TA = 25°C, VBB = 5.5 to 40 V (unless noted otherwise)
K Range Version: Valid at TA = –40°C to 125°C, VBB = 5.5 to 40 V (unless noted otherwise)
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
2.7
3.2
3.7
µs
µs
PWM TIMING
Blank Time
tBLK
Fixed Off-time
tOFF
Percent Fast Decay
PFD
VREF Input Current
IVREF
VREF Input Range
VREF
Current Sense Accuracy, External
AVREV
SENSE Trip Level, Internal
VTRIP
Internal PWM chop
VREF = 2 V, VREF / VLSS
22
25.5
29
16
18
20
%
–5
<1
5
µA
0
–
4.5
V
9.5
10
10.5
V/V
VREF = 250 mV, VREF / VLSS
8.4
10
11.6
V/V
OCLSEL = low
450
500
550
mV
I = 200 µA, VLSS = 50 to 200 mV
4.3
5
5.7
V/V
I = 200 µA, VLSS = –50 to –200 mV
–4.3
–5
–5.7
V/V
tPU
–
250
400
µs
Overcurrent Threshold
IOCP
3.0
–
–
A
Overcurrent Blank Time
tOCBLK
2.9
3.4
3.9
µs
tOCP
1.0
1.2
1.4
ms
AIOUT Gain
AV
Power Up Delay
PROTECTION CIRCUITS
Overcurrent Off-Time
UVLO Enable Threshold
VBBUVLO
UVLO Hysteresis
VBBUVLO
VCP Undervoltage
VCPUVLO
Thermal Warning Temperature
Thermal Warning Hysteresis
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
[1] For
[2] For
TJW
ΔTJWHYS
VBB rising
VCP falling
Temperature increasing
Recovery = TJW – ΔTJ
5.1
–
5.4
V
250
300
350
mV
4.0
4.5
5.0
V
–
160
–
°C
–
20
–
°C
TJSD
Temperature increasing
155
175
–
°C
ΔTJSDHYS
Recovery = TJSD – ΔTJ
–
20
–
°C
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
Range G devices, specified limits are tested at a single temperature and assured over operating temperature range by design and characterization.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A5950
DC Motor Driver
FUNCTIONAL DESCRIPTION
Device Operation
Overcurrent Protection
The A5950 is designed to operate DC motors. The output drivers
are capable of 40 V and 3 A peak operating currents. Actual 100%
steady-state DC current capability depends on thermal capability of
the package and PCB, and ambient temperature. N-channel DMOS
drivers feature internal synchronous rectification to reduce power
dissipation. Peak current can be regulated by fixed off-time pulsewidth-modulated (PWM) control circuitry.
A current monitor will protect the IC from damage due to output
shorts. If a short is detected, the IC will disable the outputs. The
fault latch is cleared after a timer of duration tOCP expires, and the
outputs are re-enabled. During OCP events, the absolute maximum
ratings may be exceeded for a short time before the device latches off.
Protection circuitry includes thermal shutdown, protection against
shorted loads, or protection against output shorts to ground or supply.
Undervoltage lockout prevents damage by keeping the outputs off
until the driver has enough power supply voltage to operate normally.
Internal PWM Current Control
When the OCLSEL input is left open or tied high, peak output current
is set by sensing the current through an external sense resistor.
IPEAK = VREF / (10 × RSENSE )
When the peak current is exceeded, the driver will operate in mixed
decay mode for fixed time tOFF before re-enabling the next drive cycle.
To disable the current control feature, leave OCLSEL open or tie
OCLSEL high, and connect LSS to GND.
Blank Function
Thermal Monitoring
If the die temperature increases to approximately TJSD, the full bridge
outputs will be disabled unit the internal temperature falls below a
hysteresis level of TJSDHYS. Thermal warning occurs approximately
20 degrees less than TJSD. Thermal warning triggers a fault but does
not disable the drivers.
OCL Option
If the OCLSEL input is left open or tied high, inrush and stall current
can be controlled by selection of VREF and the sense resistor value.
If the OCLSEL input is connected to GND, the VREF pin is ignored,
and the bridge outputs are latched off when the voltage on SENSE
exceeds 500 mV typically. While the outputs are latched off in this
condition, the FAULTn output will be asserted and pulled low. As
with OCP events, the device will then be re-enabled after a timer
of duration TOCP expires.
FAULTn Output
FAULTn is an open-drain output and is driven low to indicate any
of the following conditions:
The internal current sense circuit is ignored for some time after
PWM transitions so as not to falsely sense overcurrent events due
to motor capacitance and switching transients. This blank time,
typically 3 µs, results in a minimum on-time of the PWM.
1. OCP fault event – Short to VBB, GND, shorted load
Standby Mode
AIOUT
Low-power standby mode is activated when RESETn is low. Lowpower standby mode disables most of the internal circuitry, including
the charge pump and the regulator. When the A5950 is coming out
of standby mode, the charge pump should be allowed to reach its
regulated voltage (a maximum delay of 400 µs) before any PWM
commands are issued to the device.
An analog output can be used to monitor the load current flowing
through the external sense resistor (if a sense resistor is installed).
Positive voltage on the sense resistor is gained by 5 and output on the
AIOUT terminal. Negative voltage on the sense resistor is gained by
–5 and output on the AIOUT terminal. As the load current does not
flow through the sense resistor during a slow-decay (brake) condition,
the AIOUT output is approximately 0 V when in slow-decay.
2. OCL event (if OCLSEL = low)
3. Thermal warning
4. Undervoltage (VBB or VCP)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A5950
DC Motor Driver
Table 1: Control Logic
RESETn
PHASE
ENABLE
MODE
I > ICL
OUT1
OUT2
1
1
1
X
false
H
L
Forward
1
0
1
X
false
L
H
Reverse
1
X
0
1
false
H
H
Brake (slow decay)
1
1
0
0
false
L
H
Fast Decay SR [1]
1
0
0
0
false
H
L
Fast Decay SR [1]
1
1
1
X
true
L/H
H
Chop (mixed decay) [1]
1
0
1
X
true
H
L/H
Chop (mixed decay) [1]
X
X
X
X
Z
Z
0
[1] Outputs
Function
Standby Mode
change to Hi-Z state when in fast decay and load current approaches zero.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A5950
DC Motor Driver
PACKAGE OUTLINE DRAWINGS
0.35
4.00 ±0.15
1
0.65
16
16
0.95
A
1
2
2
4.00 ±0.15
2.70
4.10
2.70
4.10
17X
D
SEATING
PLANE
0.08 C
0.30 ±0.05
0.75 ±0.05
0.65
C
C
PCB Layout Reference View
For Reference Only
(reference JEDEC MO-220WGGC)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
0.40 ±0.10
B
2
1
2.70
C Reference land pattern layout (reference IPC7351
QFN65P400X400X80-17W2M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
16
2.70
Figure 2: EU Package, 16-Lead QFN with Exposed Thermal Pad
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A5950
DC Motor Driver
4.00 ±0.10
16
1
A
2
4.00 ±0.10
DETAIL A
17X
C
SEATING
PLANE
0.08 C
0.30 ±0.05
0.75 ±0.05
0.65 BSC
B
2
DETAIL A
0.10 REF
0.05 REF
Terminal Thickness
0.203 REF
0.20
2.15 ±0.10
1
For Reference Only
(reference JEDEC MO-220)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
16
0.25
Terminal Length
0.55 ±0.10
SLP PLATED AREA
0.10
0.55 ±0.10
C
0.375 REF
2.15 ±0.10
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Coplanarity includes exposed thermal pad and terminals
Figure 3: EU Package, 16-Lead QFN with Exposed Thermal Pad and Wettable Flank
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A5950
DC Motor Driver
For Reference Only – Not for Tooling Use
(Reference MO-153 ABT)
Dimensions in millimeters. NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
8º
0º
5.00 ±0.10
16
0.20
0.09
NNNNNNN
YYWW
LLLL
B
2.997
4.40 ±0.10
6.40 ±0.20
A
1
D Standard Branding Reference View
0.60 ±0.15
1.00 (REF)
1
2
2.997
0.25
Branded Face
SEATING PLANE
C
16X
0.10
C
0.30
0.19
N = Device part number
= Supplier emblem
Y = Last two digits of year of manufacture
W = Week of manufacture
L = Characters 5-8 of lot number
GAUGE PLANE
SEATING
PLANE
1.20 (MAX)
0.65 (BSC)
0.100
0.025
A
Terminal #1 mark area
B
Exposed thermal pad (bottom surface); dimensions may vary with device
C
Branding scale and appearance at supplier discretion
Figure 4: LP Package, 16-Lead TSSOP with Exposed Thermal Pad
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
A5950
DC Motor Driver
Revision History
Number
Date
–
November 14, 2016
Description
1
April 24, 2017
Updated Selection Guide
2
May 11, 2017
Corrected packing options in Selection Guide
Initial release
Copyright ©2017, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11