Cypress CY2HH8110ACT 1.5v 1:10 hstl fanout buffer Datasheet

CY2HH8110
1.5V 1:10 HSTL Fanout Buffer
Features
DC to 150-MHz operation
1.5V power supply
One single-ended HSTL input
Ten single-ended Class II HSTL outputs
Less than 1.9% Duty Cycle distortion
Balanced 16-mA output drive
Output Enable/Disable
Low output-output skew
Operating temperature range: 0°C to +85°C
32-pin TQFP package
The class II HSTL outputs are balanced Push-Pull in design
capable of delivering 16 mA into 10 pF load. This class allows
both source series termination and symmetrically double
parallel termination.
The CY2HH8110 low-output duty cycle distortion makes it
suitable for Double Data Rate (DDR) applications.
Q1
Q2
VDD
GND
Q9
VDD
OE
GND
IN
OE
VDD
G ND
8
GND
Q3
Q2
San Jose, CA 95134
GND
Q4
Q5
VDD
VDD
Q6
Q7
G ND
GND
Q8
Q9
VDD
VDD
•
Q10
3901 North First Street
GND
•
VDD
17
9 10 11 12 13 14 15 16
GND
Cypress Semiconductor Corporation
Document #: 38-07556 Rev **
VDD
32 31 30 29 28 27 26 25
24
1
23
2
22
3
21
4
CY2HH8110 20
5
19
6
7
18
IN
Q 10
Q1
Pin Configuration
GND
Block Diagram
The CY2HH8110 is a low-voltage HSTL fanout buffer
designed for data communications, clock management, and
specialty memory applications.
GND
•
•
•
•
•
•
•
•
•
•
Description
•
408-943-2600
Revised August 1, 2003
CY2HH8110
Pin Description[1]
Pin
6
Name
IN
I/O
Type
Description
I
HSTL
HSTL reference clock input
30, 27, 26, 23, 22, 19, 18, Q(1:10)
15, 14, 11
O
HSTL
HSTL clock outputs
4
I, PD
LVCMOS
Output enable/disable input. When held
LOW, outputs are enabled. When set HIGH, all
outputs are disabled LOW.
1, 3, 7, 12, 13, 20, 21, 28, VDD
29
Supply
VDD
1.5V power supply[2]
2, 5, 8, 9, 10, 16, 17, 24,
25, 31, 32
Supply
Ground
Common ground
OE
GND
Notes:
1. PD = Internal pull down.
2. A 0.1-uF bypass capacitor should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the trace.
Document #: 38-07556 Rev **
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CY2HH8110
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
DC Supply Voltage
–0.5
2.5
V
VDD
DC Operating Voltage
Functional
1.35
1.65
V
VIN
DC Input Voltage
Relative to VSS, with or VDD
applied
-0.5
VDD + 0.5
V
DC Output Voltage
Relative to VSS
–0.5
VDD + 0.5
V
VDD ÷ 2
V
150
mVp-p
–65
+150
°C
0
+85
°C
VOUT
VTT
Output termination Voltage
LU
Latch Up Immunity
Functional
RPS
Power Supply Ripple
Ripple Frequency < 100 kHz
TS
Temperature, Storage
Non-functional
TA
Temperature, Operating Ambient
Functional
TJ
200
mA
Temperature, Junction
Functional
+150
°C
ØJC
Dissipation, Junction to Case
Functional
42
°C/W
ØJA
Dissipation, Junction to Ambient
Functional
105
°C/W
ESDH
FIT
ESD Protection (Human Body
Model)
Failure in Time
1600
Manufacturing test
V
10
ppm
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications (VDD = 1.5V ± 8%, TA = 0°C to +85°C)
Parameter
Description
VIL
Input Voltage, Low
VIH
Input Voltage, High
VIL
Input Voltage, Low
VIH
Input Voltage, High
VOL
Output Voltage, Low[3]
VOH
Output Voltage, High[3]
IIL
Input Current, Low[4]
IIH
Input Current, High[4]
Condition
HSTL input, VREF = 0.75V
OE# input
Min.
Typ.
Max.
Unit
–0.30
–
0.65
V
0.85
–
1.80
V
-0.30
–
0.3 * VDD
V
0.7 * VDD
–
VDD + 0.3
V
IOL = 16 mA
-0.3
–
0.4
V
IOH = –16 mA
1.0
–
VDD + 0.3
V
VIL = VSS
–
–
–10
µA
VIH = VDD
–
–
100
µA
Quiescent Supply Current
VIN = 0V, outputs disabled
–
–
1
mA
IDD
Dynamic Supply Current
Outputs loaded @ 62.5 MHz
–
215
250
mA
CIN
IDDQ
Input Pin Capacitance
–
–
6
pF
COUT
Output Pin Capacitance
–
4.5
6
pF
ZOUT
Output Impedance
–
25
–
Ω
Condition
Min.
Typ.
Max.
Unit
–
–
150
MHz
0.95
–
–
–
0.55
V
0.3
–
1.5
ns
%
AC Electrical Specifications (VDD = 1.5V ± 8%, TA = 0°C to +85°C) [5]
Parameter
Description
fin
Input Frequency
VIL(AC)
AC Input HIGH Voltage
VIH(AC)
AC Input LOW Voltage
VREF =VDD/2, Internal Voltage
Reference
tr , tf
Output rise/fall time[6]
20% to 80%
DC
Output duty cycle
V
Fout < 100 MHz
48
–
52
Fout > 100 MHz
45
–
55
Notes:
3. Driving 50Ω series terminated or symmetrically double parallel terminated transmission line to a termination voltage of VTT.
4. Inputs have pull-down resistors that affect the input current.
5. AC characteristics apply for series or parallel output termination to VTT. Parameters are guaranteed by characterization and are not 100% tested.
6. tr/tf times are faster with parallel terminated loads.
Document #: 38-07556 Rev **
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CY2HH8110
AC Electrical Specifications (VDD = 1.5V ± 8%, TA = 0°C to +85°C) (continued)[5]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
Measure Jitter delay between
input and output at VDD/2 @
fREF = 62.5 MHz
–
–
|300|
ps
–
–
|1.9|
%
–
–
200
ps
–
–
2
ns
–
–
7
ns
Propagation Delay, High to Low
–
–
7
ns
Output Disable Time
–
–
7
ns
tQon
Output Enable Time
–
–
7
ns
tJIT(CC)
Cycle-to-Cycle Jitter, Deterministic
jitter
–
10
50
ps
tjit_DCD
Output Duty Cycle Distortion
tsk(O)
Output-to-Output Skew
tsk(pp)
Part-to-Part Skew
tPLH
Propagation Delay, Low to High
tPHL
tQoff
DCD @ fREF = 62.5 MHz
Parameter Measurement Information
Output
tjit_D(cc)
Figure 1. Cycle-to-Cycle Jitter
Input
80%
20%
Output
80%
20%
tPLH & tPHL
Figure 2. Propagation Delay from Input Reference to Output n
O u tp u t n
O u tp u t m
ts k (0 )
Figure 3. Output to Output Skew
OE
Qn
tQ o n
tQ o ff
Figure 4. Output Enable/Disable Time
Document #: 38-07556 Rev **
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CY2HH8110
VTT = VDDQ / 2
RT = 50 ohm
RT
RT
50 ohm
Cload = 10pf
Figure 5. An Example HSTL Symmetrically Double Parallel Terminated Output Load |
and CLASS II HSTL AC Test Load [7,8]
25 ohm
C lo a d = 1 0 p F
50 ohm
Figure 6. An Example HSTL Source Series Terminated Output Load[7,8]
Ordering Information
Part Number
Package Type
CY2HH8110AC
32-pin TQFP
CY2HH8110ACT
32-pin TQFP – Tape and Reel
Product Flow
Commercial, 0°C to +85°C
Notes:
7. HSTL to HSTL input.
8. Cload includes probe and test board capacitance.
Document #: 38-07556 Rev **
Page 5 of 7
CY2HH8110
Package Drawing and Dimensions
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0mm A32
51-85063-*B
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07556 Rev **
Page 6 of 7
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2HH8110
Document History Page
Document Title:CY2HH8110 1.5V 1:10 HSTL Fanout Buffer
Document Number: 38-07556
REV.
ECN No.
Issue Date
Orig. of
Change
**
128398
08/04/03
RGL
Document #: 38-07556 Rev **
Description of Change
New Data Sheet
Page 7 of 7
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