Samsung K4M563233E-N 2m x 32bit x 4 banks mobile sdram in 90fbga Datasheet

K4M563233E - M(E)E/N/G/C/L/F
Mobile-SDRAM
2M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
FEATURES
GENERAL DESCRIPTION
• 3.0V & 3.3V power supply.
The K4M563233E is 268,435,456 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits,
fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high performance memory system applications.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
• DQM for masking.
• Auto refresh.
•
•
•
•
64ms refresh period (4K cycle).
Commercial Temperature Operation (-25°C ~ 70°C).
Extended Temperature Operation (-25°C ~ 85°C).
2Chips DDP 90Balls FBGA with 0.8mm ball pitch
( -MXXX : Leaded, -EXXX : Lead Free).
ORDERING INFORMATION
Part No.
Max Freq.
K4M563233E-M(E)E/N/G/C/L/F75
133MHz(CL=3)
K4M563233E-M(E)E/N/G/C/L/F80
125MHz(CL=3)
K4M563233E-M(E)E/N/G/C/L/F1H
105MHz(CL=2)
K4M563233E-M(E)E/N/G/C/L/F1L
105MHz(CL=3)*1
Interface
Package
LVCMOS
90 FBGA
Leaded (Lead Free)
- M(E)E/N/G : Normal / Low / Low Power, Extended Temperature(-25°C ~ 85°C)
- M(E)C/L/F : Normal / Low / Low Power, Commercial Temperature(-25°C ~ 70°C)
NOTES :
1. In case of 40MHz Frequency, CL1 can be supported.
2. Samsung shall not offer for sale or sell either directly or through and third-party proxy, and DRAM memory products that include "Multi-Die Plastic
DRAM" for use as components in general and scientific computers such as, by way of example, mainframes, servers, work stations or desk top
computers for the first three years of five year term of this license. Nothing herein limits the rights of Samsung to use Multi-Die Plastic DRAM in other
products or other applications under paragrangh such as mobile, telecom or non-computer application(which include by way of example laptop or
notebook computers, cell phones, televisions or visual monitors)
Violation may subject the customer to legal claims and also excludes any warranty against infringement from Samsung."
3. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific
purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
February 2004
K4M563233E - M(E)E/N/G/C/L/F
Mobile-SDRAM
FUNCTIONAL BLOCK DIAGRAM
I/O Control
Data Input Register
Bank Select
2M x 32
2M x 32
Output Buffer
Sense AMP
Row Decoder
Row Buffer
Refresh Counter
ADD
Address Register
CLK
2M x 32
LWE
LDQM
DQi
2M x 32
Col. Buffer
LCBR
LRAS
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LRAS
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
February 2004
K4M563233E - M(E)E/N/G/C/L/F
Mobile-SDRAM
Package Dimension and Pin Configuration
< Top View*2 >
< Bottom View*1 >
E1
9
8
7
6
5
90Ball(6x15) FBGA
4
3
2
1
1
2
3
7
8
9
A
DQ26
DQ24
VSS
VDD
DQ23
DQ21
B
B
DQ28
VDDQ
VSSQ
VDDQ
VSSQ
DQ19
C
C
VSSQ
DQ27
DQ25
DQ22
DQ20
VDDQ
D
D
VSSQ
DQ29
DQ30
DQ17
DQ18
VDDQ
E
VDDQ
DQ31
NC
NC
DQ16
VSSQ
F
VSS
DQM3
A3
A2
DQM2
VDD
G
A4
A5
A6
A10
A0
A1
e
A
D
E
F
D1
G
H
J
K
D/2
L
M
N
P
R
H
A7
A8
NC
NC
BA1
A11
J
CLK
CKE
A9
BA0
CS
RAS
K
DQM1
NC
NC
CAS
WE
DQM0
L
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
M
VSSQ
DQ10
DQ9
DQ6
DQ5
VDDQ
N
VSSQ
DQ12
DQ14
DQ1
DQ3
VDDQ
P
DQ11
VDDQ
VSSQ
VDDQ
VSSQ
DQ4
R
DQ13
DQ15
VSS
VDD
DQ0
DQ2
E
E/2
A
A1
Substrate(2Layer)
z
b
< Top View*2 >
#A1 Ball Origin Indicator
Pin Name
Pin Function
CLK
System Clock
CS
Chip Select
CKE
Clock Enable
A0 ~ A11
Address
BA0 ~ BA1
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
DQM0 ~ DQM3
Data Input/Output Mask
DQ0 ~ 31
Data Input/Output
SAMSUNG
Week
K4M563233E-XXXX
VDD/VSS
Power Supply/Ground
VDDQ/VSSQ
Data Output Power/Ground
[Unit:mm]
Symbol
Min
Typ
Max
A
-
1.30
1.40
A1
0.30
0.35
0.40
E
-
11.00
-
E1
-
6.40
-
D
-
13.00
-
D1
-
11.20
-
e
-
0.80
-
b
0.40
0.45
0.50
z
-
-
0.10
February 2004
K4M563233E - M(E)E/N/G/C/L/F
Mobile-SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 4.6
V
TSTG
-55 ~ +150
°C
Power dissipation
PD
1.0
W
Short circuit current
IOS
50
mA
Storage temperature
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
Parameter
Symbol
Min
Typ
Max
Unit
Note
VDD
2.7
3.0
3.6
V
VDDQ
2.7
3.0
3.6
V
Input logic high voltage
VIH
2.2
3.0
VDDQ + 0.3
V
1
Input logic low voltage
VIL
-0.3
0
0.5
V
2
Output logic high voltage
VOH
2.4
-
-
V
IOH = -2mA
Output logic low voltage
VOL
-
-
0.4
V
IOL = 2mA
ILI
-10
-
10
uA
3
Supply voltage
Input leakage current
NOTES :
1. VIH (max) = 5.3V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
CAPACITANCE (VDD = 3.0V & 3.3V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)
Pin
Symbol
Min
Max
Unit
CCLK
3.0
8.0
pF
RAS, CAS, WE, CS, CKE
CIN
3.0
8.0
pF
DQM
CIN
1.5
4.0
pF
Address
CADD
3.0
8.0
pF
DQ0 ~ DQ31
COUT
3.0
6.5
pF
Clock
Note
February 2004
K4M563233E - M(E)E/N/G/C/L/F
Mobile-SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
Version
Parameter
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
Symbol
ICC1
ICC2P
Precharge Standby Current
in non power-down mode
ICC2NS
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
-75/-80
-1H
-1L
150
150
140
CKE ≤ VIL(max), tCC = 10ns
ICC3P
ICC3NS
Note
mA
1
mA
1.2
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
20
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
10
CKE ≤ VIL(max), tCC = 10ns
8
mA
mA
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
ICC3N
Unit
1.2
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
ICC2N
Active Standby Current
in power-down mode
Test Condition
8
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
45
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
40
mA
ICC4
IO = 0 mA
Page burst
4Banks Activated
tCCD = 2CLKs
190
160
160
mA
1
ICC5
tRC ≥ tRC(min)
320
300
290
mA
2
-E/C
2000
4
uA
-N/L
Self Refresh Current
ICC6
CKE ≤ 0.2V
1100
5
Internal TCSR
Max 40
Max 85/70
4Banks
700
1100
2Banks
600
900
1Bank
550
800
°C
3
uA
6
-G/F
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported.
In commercial Temp : Max 40°C/Max 70°C, In extended Temp : Max 40°C/Max 85°C
4. K4M563233E-M(E)E/C**
5. K4M563233E-M(E)N/L**
6. K4M563233E-M(E)G/F**
7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
February 2004
K4M563233E - M(E)E/N/G/C/L/F
Mobile-SDRAM
AC OPERATING TEST CONDITIONS(VDD = 2.7V ∼ 3.6V, TA = -25 to 85°C for Extended,
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
-25 to 70°C for Commercial)
Value
Unit
2.4 / 0.4
V
1.4
V
tr/tf = 1/1
ns
1.4
V
See Figure 2
VDDQ
1200Ω
Vtt=0.5 x VDDQ
VOH (DC) = 2.4V, IOH = -2mA
Output
VOL (DC) = 0.4V, IOL = 2mA
870Ω
50Ω
30pF
Output
Z0=50Ω
30pF
Figure 1. DC Output Load Circuit
Figure 2. AC Output Load Circuit
February 2004
K4M563233E - M(E)E/N/G/C/L/F
Mobile-SDRAM
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
-75
-80
-1H
-1L
Unit
Note
Row active to row active delay
tRRD(min)
15
16
19
19
ns
1
RAS to CAS delay
tRCD(min)
19
19
19
24
ns
1
Row precharge time
tRP(min)
19
19
19
24
ns
1
tRAS(min)
45
48
50
60
ns
1
Row active time
tRAS(max)
Row cycle time
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to Active delay
100
64
67
us
ns
1
2
CLK
2
tDAL(min)
tRDL + tRP
-
3
Last data in to new col. address
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
4
Number of valid output
CAS latency=3
2
Number of valid output
CAS latency=2
1
ea
5
Number of valid output
CAS latency=1
-
69
84
0
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next
higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP).
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
February 2004
K4M563233E - M(E)E/N/G/C/L/F
Mobile-SDRAM
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)
-75
Parameter
-80
-1H
-1L
Symbol
Unit Note
Min
Max
Min
Max
Max
Max
CAS latency=3
tCC
7.5
CLK cycle time
CAS latency=2
tCC
9.5
CLK cycle time
CAS latency=1
tCC
-
CLK to valid output delay
CAS latency=3
tSAC
5.4
6
7
7
CLK to valid output delay
CAS latency=2
tSAC
7
7
7
8
CLK to valid output delay
CAS latency=1
tSAC
-
-
-
20
Output data hold time
CAS latency=3
tOH
2.5
2.5
2.5
2.5
Output data hold time
CAS latency=2
tOH
2.5
2.5
2.5
2.5
Output data hold time
CAS latency=1
tOH
-
-
-
2.5
CLK high pulse width
tCH
2.5
2.5
3.0
CLK low pulse width
tCL
2.5
2.5
Input setup time
tSS
2.0
Input hold time
tSH
CLK to output in Low-Z
tSLZ
CLK to output in Hi-Z
CAS latency=2
CAS latency=1
tSHZ
1000
9.5
Min
CLK cycle time
CAS latency=3
8.0
Min
ns
1
ns
1,2
ns
2
3.0
ns
3
3.0
3.0
ns
3
2.0
2.5
2.5
ns
3
1.0
1.0
1.5
1.5
ns
3
1
1
1
1
ns
2
9.5
1000
9.5
-
9.5
1000
-
12
1000
25
5.4
6
7
7
7
7
7
8
-
-
-
20
ns
NOTES :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
February 2004
K4M563233E - M(E)E/N/G/C/L/F
Mobile-SDRAM
SIMPLIFIED TRUTH TABLE
COMMAND
Register
CKEn-1 CKEn
Mode Register Set
H
Auto Refresh
X
Entry
Self
Refresh
RAS
CAS
WE
L
L
L
L
X
OP CODE
L
L
L
H
X
X
L
H
H
H
Exit
3
L
L
3
H
3
X
H
X
X
X
X
3
Bank Active & Row Addr.
H
X
L
L
H
H
X
V
Read &
Auto Precharge Disable
Column Address
Auto Precharge Enable
H
X
L
H
L
H
X
V
Write &
Auto Precharge Disable
Column Address
Auto Precharge Enable
H
X
L
H
L
L
X
V
Burst Stop
H
X
L
H
H
L
X
H
Entry
Column
Address
(A0~A8)
H
L
X
L
L
H
L
H
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
Exit
L
H
Entry
H
L
Precharge Power Down
Mode
Column
Address
(A0~A8)
H
X
V
L
X
H
X
All Banks
Clock Suspend or
Active Power Down
Row Address
L
Bank Selection
Precharge
Note
1, 2
H
H
Refresh
DQM BA0,1 A10/AP
A11,
A9 ~ A0
CS
4
4, 5
4
4, 5
6
X
X
X
X
X
X
Exit
L
DQM
H
No Operation Command
H
H
X
X
H
X
X
X
L
H
H
H
X
V
X
X
X
7
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
NOTES :
1. OP Code : Operand Code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
Partial self refresh can be issued only after setting partial self refresh mode of EMRS.
4. BA0 ~ BA1 : Bank select addresses.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation,
it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
February 2004
K4M563233E - M(E)E/N/G/C/L/F
Mobile-SDRAM
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with Normal MRS
BA0 ~ BA1
A11 ~ A10/AP
A9*2
"0" Setting for
Normal MRS
RFU*1
W.B.L
Address
Function
A8
A7
A6
Test Mode
A5
A4
A3
CAS Latency
A2
BT
A1
A0
Burst Length
Normal MRS Mode
Test Mode
CAS Latency
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT=0
BT=1
0
0
Mode Register Set
0
0
0
Reserved
0
Sequential
0
0
0
1
1
0
1
Reserved
0
0
1
1
1
Interleave
0
0
1
2
2
1
0
Reserved
0
1
0
2
0
1
0
4
4
1
1
Reserved
0
1
1
3
0
1
1
8
8
Write Burst Length
1
0
0
Reserved
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
A9
Length
1
0
1
Mode Select
BA1 BA0
Setting
for Normal MRS
Reserved
0
0
Burst
1
1
0
Reserved
1
Single Bit
1
1
1
Reserved
Mode
0
Full Page Length x32 : 256Mb(512)
Register Programmed with Extended MRS
Address
Function
BA1
BA0
A11 ~ A10/AP
Mode Select
A9
A8
A7
A6
A5
A4
DS
RFU*1
A3
A2
A1
A0
PASR
RFU*1
EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength)
Mode Select
Driver Strength
PASR
BA1
BA0
Mode
A6
A5
Driver Strength
A2
A1
A0
# of Banks
0
0
Normal MRS
0
0
Full
0
0
0
4 Banks
0
1
Reserved
0
1
1/2
0
0
1
2 Banks
1
0
EMRS for Mobile SDRAM
1
0
Reserved
0
1
0
1 Bank
1
1
Reserved
1
1
Reserved
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Reserved Address
A11~A10/AP
A9
A8
A7
A4
A3
0
0
0
0
0
0
NOTES:
1. RFU(Reserved for future use) should stay "0" during MRS cycle.
2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
February 2004
K4M563233E - M(E)E/N/G/C/L/F
Mobile-SDRAM
Partial Array Self Refresh
1. In order to save power consumption, Mobile SDRAM has PASR option.
2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : 4 Banks(256Mb), 2 Banks(128Mb) and 1 Bank(64Mb).
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
- 4 Banks
- 1 Bank
- 2 Banks
Partial Self Refresh Area
Temperature Compensated Self Refresh
1. In order to save power consumption, Mobile-DRAM includes the internal temperature sensor and control units to control the self
refresh cycle automatically according to the two temperature range : Max 40 °C and Max 85 °C(for Extended), Max 70 °C(for
Commercial).
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
Self Refresh Current (Icc6)
Temperature Range
- G/F
- E/C
Max 85/70 °C
Max 40 °C
2000
Unit
-N/L
4 Banks
2 Banks
1 Bank
1100
900
800
700
600
550
1100
uA
B. POWER UP SEQUENCE
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.
EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used.
The default state without EMRS command issued is the full driver strength and all 4 banks refreshed.
The device is now ready for the operation selected by EMRS.
For operating with DS or PASR, set DS or PASR mode in EMRS setting stage.
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not
needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
February 2004
K4M563233E - M(E)E/N/G/C/L/F
Mobile-SDRAM
C. BURST SEQUENCE
1. BURST LENGTH = 4
Initial Address
Sequential
Interleave
A1
A0
0
0
0
1
2
3
0
1
2
3
0
1
1
2
3
0
1
0
3
2
1
0
2
3
0
1
2
3
0
1
1
1
3
0
1
2
3
2
1
0
2. BURST LENGTH = 8
Initial Address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
February 2004