Dialog IW1691-03 Digital pwm current-mode controller for quasi-resonant operation Datasheet

iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
1.0 Features
2.0 Description
●● Primary-side feedback eliminates opto-isolators and
simplifies design
●● Quasi-resonant operation for highest overall efficiency
●● EZ-EMI ® design to easily meet global EMI standards
●● Up to 130 kHz switching frequency enables small
adapter size
●● Built-in cable drop compensation
●● Very tight output voltage regulation
●● No external compensation components required
●● Complies with CEC/EPA no-load power consumption
and average efficiency regulations
●● Built-in output constant-current control with primary-side
feedback
●● Low start-up current (10 µA typical)
●● Built-in soft start
●● Built-in short circuit protection and output overvoltage
protection
The iW1691 is a high performance AC/DC power supply
controller which uses digital control technology to build
peak current mode PWM flyback power supplies. The
device operates in quasi-resonant mode at heavy load to
provide high efficiency along with a number of key built-in
protection features while minimizing the external component
count, simplifying EMI design and lowering the total bill of
material cost. The iW1691 removes the need for secondary
feedback circuitry while achieving excellent line and load
regulation. It also eliminates the need for loop compensation
components while maintaining stability over all operating
conditions. Pulse-by-pulse waveform analysis allows for a
loop response that is much faster than traditional solutions,
resulting in improved dynamic load response. The built-in
current limit function enables optimized transformer design
in universal off-line applications over a wide input voltage
range.
The ultra-low operating current at light load ensures that
the iW1691 is ideal for applications targeting the newest
regulatory standards for average efficiency and standby
power.
3.0 Applications
●● Optional AC line under/overvoltage protection
●● PFM operation at light load
●● Current sense resistor short protection
●● AC/DC adapter/chargers for cell phones, PDAs, digital
still cameras
●● Overtemperature Protection
●● AC/DC adapters for consumer electronics
L
N
+
+
VOUT
RTN
+
Optional
NTC
Thermistor
1
NC
2
VSENSE
VCC 8
3
VIN
ISENSE 6
4
SD
GND 5
OUTPUT 7
U1
iW1691
Figure 3.1 : Typical Application Circuit
Rev. 2.0
iW1691
February 3, 2012
Page 1
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
4.0 Pinout Description
iW1691
1
NC
2
VSENSE
3
4
VCC
8
OUTPUT
7
VIN
ISENSE
6
SD
GND
5
Pin #
Name
Type
Pin Description
1
NC
-
2
VSENSE
3
VIN
Analog Input Rectified AC line average voltage sense.
4
SD
Analog Input
5
GND
Ground
6
ISENSE
7
OUTPUT
Output
8
VCC
Power Input
No connection.
Analog Input Auxiliary voltage sense (used for primary side regulation).
External shutdown control. Connect to ground through a resistor if not used.
(see section 10.16)
Ground.
Analog Input Primary current sense (used for cycle-by-cycle peak current control and limit).
Gate drive for external MOSFET switch.
Power supply for control logic and voltage sense for power-on reset circuitry.
5.0 Absolute Maximum Ratings
Absolute maximum ratings are the parameter values or ranges which can cause permanent damage if exceeded. For
maximum safe operating conditions, refer to Electrical Characteristics in Section 6.0.
Parameter
Symbol
Value
Units
DC supply voltage range (pin 8, ICC = 20mA max)
VCC
-0.3 to 18
V
DC supply current at VCC pin
ICC
20
mA
Output (pin 7)
-0.3 to 18
V
VSENSE input (pin 2, IVsense ≤ 10 mA)
-0.7 to 4.0
V
VIN input (pin 3)
-0.3 to 18
V
ISENSE input (pin 6)
-0.3 to 4.0
V
SD input (pin 4)
-0.3 to 18
V
Power dissipation at TA ≤ 25°C
PD
526
mW
Maximum junction temperature
TJ MAX
125
°C
Storage temperature
TSTG
–65 to 150
°C
Lead temperature during IR reflow for ≤ 15 seconds
TLEAD
260
°C
θJA
160
°C/W
ESD rating per JEDEC JESD22-A114
2,000
V
Latch-Up test per JEDEC 78
±100
mA
Thermal Resistance Junction-to-Ambient
Rev. 2.0
iW1691
February 3, 2012
Page 2
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
6.0 Electrical Characteristics
VCC = 12 V, -40°C ≤ TA ≤ 85°C, unless otherwise specified (Note 1)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VINSTLOW
TA= 25°C, positive edge
335
369
406
mV
IINST
VIN = 10 V, CVCC = 10 µF
10
15
µA
VUVDC
TA= 25°C, negative edge
221
243
mV
VIN SECTION (Pin 3)
Start-up low voltage threshold
Start-up current
Shutdown low voltage threshold
Input impedance
ZIN
After start-up
IBVS
VSENSE = 2 V
201
25
kW
VSENSE SECTION (Pin 2)
Input leakage current
1
μA
Nominal voltage threshold
VSENSE(NOM)
TA=25°C, negative edge
1.523
1.538
1.553
V
Output OVP threshold
- 00, -01, -03 , -11 (Note 2)
VSENSE(MAX)
TA=25°C, negative edge
1.754
1.846
1.938
V
OUTPUT OVP threshold -09 (Note 2)
VSENSE(MAX)
TA=25°C, negative edge
1.797
1.892
1.987
V
Output OVP threshold -04, -08
(Note 2)
VSENSE(MAX)
TA=25°C, negative edge,
Load = 100%
1.836
1.933
2.030
V
Output OVP threshold -10 (Note 2)
VSENSE(MAX)
TA=25°C, negative edge,
Load = 100%
1.871
1.969
2.067
V
OUTPUT SECTION (Pin 7)
Output low level ON-resistance
RDS(ON)LO
ISINK = 5 mA
40
W
Output high level ON-resistance
RDS(ON)HP
ISOURCE = 5 mA
175
W
Rise time (Note 2)
tR
TA = 25°C, CL = 330 pF
10% to 90%
200
300
ns
Fall time (Note 2)
tF
TA = 25°C, CL = 330 pF
90% to 10%
40
60
ns
Any combination of
line and load
130
140
kHz
Maximum switching frequency
-00, -01, -03, -04, -08, -09,-10, -11
(Note 3)
Rev. 2.0
fSW(MAX)
iW1691
February 3, 2012
Page 3
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
6.0 Electrical Characteristics (cont.)
VCC = 12 V, -40°C ≤ TA ≤ 85°C, unless otherwise specified (Note 1)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
16
V
VCC SECTION (Pin 8)
Maximum operating voltage (Note 2)
VCC(MAX)
Start-up threshold
VCC(ST)
VCC rising
10.8
12
13.2
V
Undervoltage lockout threshold
VCC(UVL)
VCC falling
5.5
6.0
6.6
V
3.5
5
mA
Operating current
ICCQ
CL = 330 pF,
VSENSE = 1.5 V
ISENSE SECTION (Pin 6)
Peak limit threshold
VPEAK
1.045
1.1
1.155
V
Isense short protection reference
VRSNS
0.127
0.15
0.173
V
CC regulation threshold limit (Note 2)
VREG-TH
1.0
V
SD SECTION (Pin 4)
Shutdown threshold
Shutdown threshold in Startup
(Note 2)
VSD-TH
TA = 25°C
0.95
VSD-TH(ST)
1.0
1.05
1.2
Input leakage current
IBVSD
VSD = 1.0 V
Pull down resistance
RSD
TA = 25°C
7916
8333
V
V
1
µA
8750
W
Notes:
Note 1. Adjust VCC above the start-up threshold before setting at 12 V.
Note 2. Guaranteed by design and characterization. Minimum output OVP threshold is specified for 100% load; for loads
less than 100% the minimum output OVP threshold will be less.
Note 3. Operating frequency varies based on the line and load conditions, see Theory of Operation for more details.
Rev. 2.0
iW1691
February 3, 2012
Page 4
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
VCC Start-up Threshold (V)
VCC Supply Start-up Current (µA)
7.0 Typical Performance Characteristics
9.0
6.0
3.0
0.0
0.0
2.0
4.0
8.0
6.0
VCC (V)
10.0
12.0
14.0
12.2
12.0
11.8
11.6
-50
Internal Reference Voltage (V)
% Deviation of Switching Frequency from Ideal
0.3 %
-0.3 %
-0.9 %
-25
0
25
50
75
Ambient Temperature (°C)
100
125
Figure 7.3 : % Deviation of Switching Frequency to
Ideal Switching Frequency vs. Temperature
Rev. 2.0
0
25
50
75
Ambient Temperature (°C)
100
125
Figure 7.2 : Start-Up Threshold vs. Temperature
Figure 7.1 : VCC vs. VCC Supply Start-up Current
-1.5 %
-50
-25
2.01
2.00
1.99
1.98
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
Figure 7.4 : Internal Reference vs. Temperature
iW1691
February 3, 2012
125
Page 5
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
8.0 Functional Block Diagram
VIN
3
ENABLE
VSENSE
2
ISD
VIN_A
0.2 V ~ 2.0 V
Signal
Conditioning
VVMS
Gate
Driver
Digital
Logic
Control
VFB
Detection Switch
–
IPEAK
VIPK
5
1.1 V
6
ISENSE
DAC
RSD
GND
–
VSD-TH
OUTPUT
60 kΩ
VOCP
+
4
7
ADC
+
SD
VCC
Start-up
ENABLE
ZVin
25 kΩ
8
0V~1V
+
– –
Figure 8.1 : iW1691 Functional Block Diagram
9.0 Theory of Operation
The iW1691 is a digital controller which uses a proprietary
primary-side control technology to eliminate the optoisolated feedback and secondary regulation circuits required
in traditional designs. This results in a low-cost solution for
AC/DC adapters. The iW1691 uses Critical Discontinuous
Conduction Mode (CDCM) or Pulse Width Modulation
(PWM) mode at high output power levels and switches to
Pulse Frequency Modulation (PFM) mode at light load to
minimize power dissipation to meet EPA 2.0 specification.
Furthermore, iWatt’s digital control technology enables fast
dynamic response, tight output regulation, and full featured
circuit protection with primary-side control.
control algorithm to reduce system design time and improve
reliability.
Referring to the block diagram in Figure 8.1, the digital logic
control block generates the switching on-time and off-time
information based on the line voltage and the output voltage
feedback signal and provides commands to dynamically
control the external MOSFET current. The system loop is
compensated internally by a digital error amplifier. Adequate
system phase and gain margin are guaranteed by design
and no external analog components are required for loop
compensation. The iW1691 uses an advanced digital
iWatt’s digital control scheme is specifically designed to
address the challenges and trade-offs of power conversion
design. This innovative technology is ideal for balancing new
regulatory requirements for green mode operation with more
practical design considerations such as lowest possible cost,
smallest size and highest performance output control.
Rev. 2.0
Furthermore, accurate secondary constant-current operation
is achieved without the need for any secondary-side sense
and control circuits.
The built-in protection features include overvoltage protection
(OVP), output short circuit protection (SCP) and soft-start,
AC line brown out, overcurrent protection, and Isense fault
protection. Also the iW1691 automatically shuts down if it
detects any of its sense pins to be either open or short.
iW1691
February 3, 2012
Page 6
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
9.1 Pin Detail
Pin 2 – VSENSE
Sense signal input from auxiliary winding. This provides the
secondary voltage feedback used for output regulation.
If at any time the VCC voltage drops below VCC(UVL) threshold
then all the digital logic is reset. At this time VIN switch turns
off so that the VCC capacitor can be charged up again towards
the start-up threshold.
Start-up
Sequencing
Pin 3 – Vin
Sense signal input from the rectified line voltage. VIN is used
for line regulation. The input line voltage is scaled down
using a resistor network. It is used for input undervoltage
and overvoltage protection. This pin also provides the supply
current to the IC during start-up.
VIN
VCC(ST)
VCC
Pin 4 – SD
External shutdown control. If the shutdown control is not
used, this pin should be connected to GND via a resistor.
(see Section 10.16).
ENABLE
Pin 5 – GND
Figure 9.1 : Start-up Sequencing Diagram
Ground.
9.3 Understanding Primary Feedback
Pin 6 – ISENSE
Figure 9.2 illustrates a simplified flyback converter. When the
switch Q1 conducts during tON(t), the current ig(t) is directly
drawn from rectified sinusoid vg(t). The energy Eg(t) is stored
in the magnetizing inductance LM. The rectifying diode D1 is
reverse biased and the load current IO is supplied by the
secondary capacitor CO. When Q1 turns off, D1 conducts
and the stored energy Eg(t) is delivered to the output.
Primary current sense. Used for cycle by cycle peak current
control.
Pin 7 – OUTPUT
Gate drive for the external MOSFET switch.
iin(t)
Pin 8 – VCC
Power supply for the controller during normal operation. The
controller will start up when VCC reaches 12 V (typical) and
will shut-down when the VCC voltage is below 6 V (typical). A
decoupling capacitor should be connected between the VCC
pin and GND.
+
When VCC is fully charged to a voltage higher than the startup threshold VCC(ST), the ENABLE signal becomes active and
enables the control logic; the VIN switch turns on, and the
analog-to-digital converter begins to sense the input voltage.
Once the voltage on the VIN pin is above VINSTLOW , the iW1691
commences soft start function. An adaptive soft-start control
algorithm is applied at startup state, during which the initial
output pulses will be small and gradually get larger until the
full pulse width is achieved. The peak current is limited cycle
by cycle by Ipeak comparator.
Rev. 2.0
id(t)
N:1
vg(t)
vin(t)
VO
+
D1
CO
IO
VAUX
–
VAUX
TS(t)
9.2 Start-up
Prior to start-up the VIN pin charges up the VCC capacitor
through the diode between VIN and VCC (see Figure 8.1).
ig(t)
Q1
Figure 9.2 : Simplified Flyback Converter
In order to tightly regulate the output voltage, the information
about the output voltage and load current needs to be
accurately sensed. In the DCM flyback converter, this
information can be read via the auxiliary winding. During the
Q1 on-time, the load current is supplied from the output filter
capacitor CO. The voltage across LM is vg(t), assuming the
voltage dropped across Q1 is zero. The current in Q1 ramps
up linearly at a rate of:
dig (t )
dt
=
vg (t )
(9.1)
LM
At the end of on-time, the current has ramped up to:
iW1691
February 3, 2012
Page 7
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
ig _ peak (tON ) =
vg (t ) × tON
(9.2)
LM
9.4 Constant Voltage Operation
This current represents a stored energy of:
LM
E
=
× ig _ peak (tON ) 2
g
2
(9.3)
When Q1 turns off, ig(t) in LM forces a reversal of polarities on
all windings. Ignoring the communication-time caused by the
leakage inductance LK at the instant of turn-off, the primary
current transfers to the secondary at a peak amplitude of:
id =
(t )
NP
× ig _ peak (tON )
NS
(9.4)
Assuming the secondary winding is master and the auxiliary
winding is slave.
VAUX = VO x
VAUX
After soft-start has been completed, the digital control block
measures the output conditions. It determines output power
levels and adjusts the control system according to a light
load or a heavy load. If this is in the normal range, the device
operates in the Constant Voltage (CV) mode, and changes
the pulse width (TON), and off time (TOFF) in order to meet the
output voltage regulation requirements. During this mode
the PWM switching frequency is between 30 kHz and 130
kHz, depending on the line and load conditions.
If less than 0.2 V is detected on VSENSE it is assumed that the
auxiliary winding of the transformer is either open or shorted
and the iW1691 shuts down.
9.5 Valley Mode Switching
In order to reduce switching losses in the MOSFET and
EMI, the iW1691 employs valley mode switching when
IOUT is above 50%. In valley mode switching, the MOSFET
switch is turned on at the point where the resonant voltage
across the drain and source of the MOSFET is at its lowest
point (see Figure 9.4). By switching at the lowest VDS, the
switching loss will be minimized.
NAUX
NS
0V
VAUX = -VIN x
represents the output voltage and is used to regulate the
output voltage.
Gate
NAUX
NP
Figure 9.3 : Auxiliary Voltage Waveforms
The auxiliary voltage is given by:
=
VAUX
N AUX
(VO + ∆V )
NS
VDS
(9.5)
and reflects the output voltage as shown in Figure 9.3.
The voltage at the load differs from the secondary voltage by
a diode drop and IR losses. The diode drop is a function of
current, as are IR losses. Thus, if the secondary voltage is
always read at a constant secondary current, the difference
between the output voltage and the secondary voltage will
be a fixed ΔV. Furthermore, if the voltage can be read when
the secondary current is small; for example, at the knee of
the auxiliary waveform (see Figure 9.3), then ΔV will also be
small. With the iW1691, ΔV can be ignored.
The real-time waveform analyzer in the iW1691 reads the
auxiliary waveform information cycle by cycle. The part then
generates a feedback voltage VFB. The VFB signal precisely
Rev. 2.0
Figure 9.4 : Valley Mode Switching
Turning on at the lowest VDS generates lowest dV/dt, thus
valley mode switching can also reduce EMI. To limit the
switching frequency range, the iW1691 can skips valleys
(seen in the first cycle in Figure 9.4) when the switching
frequency becomes too high.
iW1691 provides valley mode switching during constant
output current operation. So, the EMI and switching losses
are still minimized during CC mode. This feature is superior
to other quasi-resonant technologies which only support
valley mode switching during constant voltage operation.
This is beneficial to applications, such as chargers, where
the power supply mainly operates in CC mode.
iW1691
February 3, 2012
Page 8
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
9.6 Constant Current Operation
9.9 Internal Loop Compensation
The constant current mode (CC mode) is useful in battery
charging applications. During this mode of operation the
iW1691 will regulate the output current at a constant level
regardless of the output voltage, while avoiding continuous
conduction mode.
The iW1691 incorporates an internal Digital Error Amplifier
with no requirement for external loop compensation. For a
typical power supply design, the loop stability is guaranteed
to provide at least 45 degrees of phase margin and –20dB
of gain margin.
To achieve this regulation the iW1691 senses the load
current indirectly through the primary current. The primary
current is detected by the ISENSE pin through a resistor from
the MOSFET source to ground.
9.10 Voltage Protection Functions
CV mode
CC mode
Output Voltage
VNOM
The iW1691 includes functions that protect against input line
undervoltage (UV) and the output overvoltage (OVP).
The input voltage is monitored by the VIN pin and the output
voltage is monitored by the VSENSE pin. If the voltage at these
pins exceed their respective undervoltage or overvoltage
thresholds the iW1691 shuts down immediately. However,
the IC remains biased which discharges the VCC supply. Once
VCC drops below the UVLO threshold, the controller resets
itself and then initiates a new soft-start cycle. The controller
continues attempting start-up until the fault condition is
removed.
9.11 PCL, OC and SRS Protection
Output Current
IOUT(CC)
Figure 9.5 : Power Envelope
9.7 PFM Mode at Light Load
The iW1691 normally operates in a fixed frequency PWM or
critical discontinuous conduction mode when IOUT is greater
than approximately 10% of the specified maximum load
current. As the output load IOUT is reduced, the on-time tON
is decreased. At the moment that the load current drops
below 10% of nominal, the controller transitions to Pulse
Frequency Modulation (PFM) mode. Thereafter, the ontime will be modulated by the line voltage and the off-time
is modulated by the load current. The device automatically
returns to PWM mode when the load current increases.
9.8 Variable Frequency Operation
At each of the switching cycles, the falling edge of VSENSE
will be checked. If the falling edge of VSENSE is not detected,
the off-time will be extended until the falling edge of VSENSE
is detected. The maximum allowed transformer reset time is
75 µs. When the transformer reset time reaches 75 µs, the
iW1691 immediately shuts off.
Peak-current limit (PCL), over-current protection (OCP) and
sense-resistor short protection (SRSP) are features built-into
the iW1691. With the ISENSE pin the iW1691 is able to monitor
the primary peak current. This allows for cycle by cycle peak
current control and limit. When the primary peak current
multiplied by the ISENSE sense resistor is greater than 1.1 V
over current is detected and the IC will immediately turn
off the gate drive until the next cycle. The output driver will
send out switching pulse in the next cycle, and the switching
pulse will continue if the OCP threshold is not reached; or,
the switching pulse will turn off again if the OCP threshold is
still reached.
If the ISENSE sense resistor is shorted there is a potential
danger of the over current condition not being detected.
Thus the IC is designed to detect this sense-resistor-short
fault after the start up, and shutdown immediately. The
VCC will be discharged since the IC remains biased. Once
VCC drops below the UVLO threshold, the controller resets
itself and then initiates a new soft-start cycle. The controller
continues attempting start-up, but does not fully start-up until
the fault condition is removed.
9.12 Shutdown
The shutdown (SD) pin in the iW1691 provides protection
against overtemperature (OTP) and additional overvoltage
(OVP) for the power supply.
The SD pin alternates between monitoring overtemperature
and over voltage conditions. During the overtemperature
monitor cycle the IC outputs a constant current, ISD, to the
Rev. 2.0
iW1691
February 3, 2012
Page 9
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
SD pin and it shuts down the device if the voltage at the SD
pin is under 1 V. During the overvoltage monitor cycle the
SD pin is tied to ground via RSD, and shutsdown the device if
the voltage at the SD pin is above 1 V. Both overtemperature
and overvoltage protection can be latched by the iW1691,
whereby the iW1691 does not attempt to start again until
after the power supply is unplugged for a few seconds and
then is reconnected (i.e. the VCC voltage needs to be 1 V
below VCC(UVL) to release the latch).
9.13 Cable Drop Compensation
The iW1691 incorporates an innovative method to
compensate for any IR drop in the secondary circuitry
including cable and cable connector. A 5 W AC adapter with
5 V DC output has 6% deviation at 1 A load current due to
the drop across a 24 AWG, 1.8 m DC cable without cable
compensation. The iW1691 compensates for this voltage
drop by providing a voltage offset to the feedback signal
based on the amount of load current detected.
To calculate the amount of cable compensation needed, take
the resistance of the cable and connector and multiply by the
maximum output current.
Rev. 2.0
iW1691
February 3, 2012
Page 10
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
10.0 Design Example
10.1 Design Procedure
This design example gives the procedure for a flyback
converter using iW1691. Refer to Figure 13.1 for the
application circuit. The design objectives for this adapter
are given in table 10.1. It meets UL, IEC, and CEC
requirements.
Determine the Design Specifications
(Vout, Iout_max, Vin_max, Vin_min, ƒline, Ripple specification)
Parameter
Symbol
VIN
85 - 264 VRMS
Frequency
fIN
47 - 64 Hz
No Load Input
PIN
100 mW
Input Voltage
Output Voltage
VOUT(Cable)
5.0 V
Output Current
IOUT
1A
Output Ripple
VRIPPLE
< 100 mV
POUT
5W
h
69%
Power Out
Determine Part Number
CEC Efficiency
Table 10.1 : iW1691 Design Specification Table
Determine Rvin Resistors
10.2 Determine Part Number
Determine Turns Ratio
Based on design specifications, choose the most suitable
part for the design. For more information on the options see
section 11.0.
Determine Operating VinTon Limit
Cable Drop Compensation
Determine Magnetizing Inductance
Determine Primary Turns
Determine Secondary Turns
Determine Bias Turns and Vcc Capacitance
No
Determine Vsense Resistors
Can you wind this transformer ?
Yes
Determine Current Sensing Resistor
Determine Input Bulk Capacitance
Determine Output Capacitance
Determine Snubber Network
Determine Current Sensing Filter
Cable Drop Compensation is an optional feature for the
iW1691. This option helps maintain the output voltage at the
end of the cable that the power supply is designed for. During
CV (constant voltage) mode the output current changes as
the voltage remains constant. This is true for the output
voltage at the output of the power supply board; however, in
certain applications the device to be charged is not directly
connected to the power supply, but rather, is connected
via a cable. This cable is seen by the power supply as a
resistance. So, as the output current increases the output
voltage at the end of the cable begins to drop. With the
cable compensation option, the iW1691 can compensate for
the resistance of the cable by incrementally increasing the
output voltage seen on the power supply board to cancel out
the selected cable resistance.
To find the right cable compensation necessary for a given
cable, pick the cable drop compensation number that is
closest to the voltage drop of the cable under maximum
output current.
Use equation 10.1 for VOUT in the following calculations,
where VFD is the forward voltage of the output diode.
VOUT = VOUT (Cable) + VCableDrop + VFD
Finish
Figure 10.1 : iW1691 Design Flow Chart
Rev. 2.0
Range
(10.1)
For this example there is no cable so VCableDrop is 0 V ,
assuming VFD is 0.5, VOUT is:
VOUT = 5.0V + 0V + 0.5V = 5.5V
iW1691
February 3, 2012
Page 11
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
10.3 Input Selection
VIN resistors are chosen primarily to scale down the input
voltage for the IC. The default scale factor for the input
voltage in the IC is 0.0043 and the internal impedance of
this pin is ZIN (25 kW). Therefore, the VIN resistors should
equate to:
=
RVin
Z IN
− Z IN
0.0043
(10.2)
From equation 10.2, ideally RVin should be 5.79 MW. A lower
value of RVin can decrease the startup time of the power
supply. The value of RVin affects the (VINTON) limits of the
IC.
(VIN ⋅ TON )limit =0.0043 × Z
(VIN ⋅ TON )PFM
=
0.0043 ×
720V ⋅ ms
IN
Z IN
( RVin + Z IN )
(10.3)
0.0043 ×
( RVin + Z IN )
=
(VIN ⋅ TON )PFM
0.0043 ×
25k W
720V ⋅ ms
Keep in mind in valley mode switching the higher the turns
ratio the lower the VDS turn-on voltage, which means less
switch turn-on power loss. Also consider the voltage stress
on the MOSFET (VDS) is higher with an increase in turns
ratio. The voltage stress on the output diode is lower with
an increase in turns ratio respectively.
10.5 Operating Maximum (VINTON)
Maximum operating VINTON or (VINTON)MAX for valley mode
switching is traditionally designed at full load and lowest
input voltage. For the iW1691, two constraints (equation
10.6 and 10.7) need to be satisfied so that indeed (VINTON)MAX
occurs at full load and lowest input voltage.
TP (QR min) >
135V ⋅ms
(10.4)
For this example RVin is chosen to be 5.1 MΩ therefore,
(VIN ⋅ TON )=
limit
A turns ratio between 11 to 15 is suggested for optimal
performance. So for this example 13.8 is chosen.
= 635V ⋅ ms
TP' (QR min) >
1
100kHz
1
+ TRES
110kHz
( 5.1M W + 25k W )
25k W
135V ⋅ ms
= 119V ⋅ ms
Gate
( 5.1M W + 25k W )
VDS
Since the iW1691 uses the exact scaled value of VIN for its
calculations, there should be a filter capacitor on the input
pin to filter out any noise that may appear on the VIN signal.
This is especially important for line in surge conditions.
10.4 Turns Ratio
The maximum allowable turns ratio between the primary
and secondary winding is determined by the minimum
detectable reset time of the transformer during PFM mode.
(VIN ⋅ TON ) PFM
TRESET (min) × VOUT
Setting TRESET(min) at 1.5 μs,
=
NTR (max)
119V ⋅ms
= 14.4
1.5ms × 5.5V
(10.5)
TRESET
TRES
TON
TPERIOD
Figure 10.2 : VDS Timing
When both criterion are met then (VINTON)MAX can be
determined by equation 10.8.


1
1
 f SW (max op) × 
+
 VINDC (min) NTR × VOUT


1
where, f SW (max op) =
TP (QRmin)
(VIN ⋅ TON )max=




−1
(10.8)
Where VINDC(min) is the minimum input voltage across the bulk
capacitor. In order to avoid input undervoltage detection
during normal operation, VINDC(min) should be set above the
input undervoltage shutdown limit.
VINDC (min) >
Rev. 2.0
(10.7)
TRES is the VDS resonant period as shown in Figure 10.2. TRES
can be estimated to be approximately 2 μs as a starting point
and then adjusted after the power supply is made.
Keep in mind, by changing RVin to be something other than
5.79 MW the minimum and maximum input voltage for startup also changes.
NTR (max) =
(10.6)
iW1691
February 3, 2012
RVin + Z IN
⋅ VUVDC
Z IN
(10.9)
Page 12
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
Assuming TRES is 2 μs then:
LM (min) =
TP ( QR min ) > 10ms
TP' (QR min) >
VINDC (min)
1
+ 2ms= 11.1ms
110kHz
5.1M W + 25k W
>
× 0.369V =
76V
25k W
=
LM (min)
To give some margin, we use 85 V for VINDC(min) in equation
10.8,
Choosing, ƒ SW(max op) =
85kHz for TP (QR min) =
11.8ms
(VIN ⋅ TON )=
max
85kHz ×

−1
( 851V + 13.8×15.5V =
)
472V ⋅ms
Also, to provide enough margin for component values,
usually:
(VIN ⋅ TON )max < (VIN ⋅ TON )limit × 0.85
(10.10)
= 540V ⋅ms
(VIN ⋅ TON )max < 635V ⋅ ms × 0.85
Since we calculated 472 V·μs as our VIN·TON we have enough
margin.
10.6 Magnetizing Inductance
A feature of the iW1691 is the lack of dependence on the
magnetizing inductance for the CC curve.
Although the constant current limit does not depend on the
magnetizing inductance, there are still restrictions on the
magnetizing inductance. The maximum LM is limited by the
amount of power that needs to come out of the transformer
in order for the power supply to regulate. This is given by:
LM (max) =
PXFMR (max) =
VOUT × I OUT
hX
(10.11)
Where ηX is the efficiency of the transformer, for this example
we assume it’s 87 %.
5.5V × 1A
=
= 6.32W
PXFMR
(max)
0.87
=
LM (max)
( 472V ⋅ ms )
2
× 85kHz
= 1.50mH
2 × 6.32W
The minimum LM is limited by the maximum allowable peak
primary current. VREG-TH corresponds to the maximum ISENSE
voltage. Therefore LM is limited by:
Rev. 2.0
V

f SW (max op) ×  REG −TH
RIsense 

2
(10.12)
2 × 6.32W
=
1.34mH
2
85kHz × 1.0V
3.0W
(
)
For this example, we choose LM to be 1.42 mH.
If these limits do not give enough tolerance for LM, increasing
(VINTON)max can raise the maximum limit on LM. Take care not
to go above (VINTON)limit. Also, keep in mind that if equation
10.6 and 10.7 are not met then (VINTON)max does not occur at
full load and lowest input voltage, thus some of the equations
here would be invalid.
10.7 Primary Winding
In order to keep the transformer from saturation, the
maximum flux density must not be exceeded. Therefore the
minimum primary winding must meet:
N PRI ≥
(VIN ⋅ TON )max
Bmax × Ae
(10.13)
Where BMAX is maximum allowed flux density and Ae is the
core area. From the transformer core datasheet we find that
for this example BMAX is 320 mT. For an EFD15 core, Ae is
15 mm2.
N PRI ≥
472V ⋅ms
320mT × 15mm 2
98T
=
For this example, we choose 138 primary turns.
10.8 Secondary Winding
(VIN ⋅ TON )2max × f sw(max op)
2 × PXFMR (max)
2 × PXFMR ( max )
From the primary winding turns, we obtain the secondary
winding.
N SEC =
N PRI
NTR
(10.14)
Thus, in our example:
N=
SEC
138T
= 10T
13.8
10.9 Bias Winding and VCC Capacitance
VCC is the supply to the iW1691 and should be below 16 V.
The bias winding needs to ensure than VCC does not exceed
16 V during normal operation.
iW1691
February 3, 2012
Page 13
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
10.11 Current Sense Resistor
N SEC (VCC + VFD )
N BIAS =
VOUT
(10.15)
Set VCC at around 10 V
=
N BIAS
10T × 10.5V
= 19T
5.5V
The VCC capacitor (CVcc) stores the VCC charge during IC
operation and the controller checks this voltage and makes
sure it is within range before starting and operating. The
startup time is a function of how quickly this capacitor can
charge up.
CVCC × VCC ( ST )
VINAC × 2
RVin
− I INST
(10.17)
(10.18)
K=
SENSE
VSENSE ( nom )
VOUT _ PCB
(10.19)
VIsense (CC )
RIsense
(10.21)
Substituting this into equation 10.20 we get:
TPERIOD
× KC
TRESET
(10.22)
NTR × KC
× hX
2 × I OUT
=
RIsense
(10.23)
From table 10.1 IOUT is given to be 1.0 A, therefore RIsense is:
We recommend using ±1% tolerance resistors for RIsense.
10.12 Input Bulk Capacitor
The input bulk capacitor, CBULK is chosen to maintain enough
input power to sustain constant output power even as the
input voltage is dropping. In order for this to be true CBULK
must be:
1.538V
= 0.3076
5.0V
From here we can find the ratio necessary for RBVsns and
RTVsns. For this example we set RTVsns to be 10 kΩ. Assuming
we use the same winding for both VSENSE and VCC:
RBVSNS
17T
0.3076
=
×
RBVSNS + 10k W 10T
2.2k W
→ RBVSNS =
At this point the transformer design is complete. This would
be a good time to confirm that this transformer is feasible to
build.
Rev. 2.0
I PRI ( pk ) =
13.8 × 0.5V
× 0.87 =3.0W
RISNS =
2 × 1A
Internally, VSENSE is compared to a reference voltage
VSENSE(nom). Where, VSENSE(nom) is 1.538 V.
K SENSE =
(10.20)
For iW1691 KC is 0.5 V, therefore RIsense depends on the
maximum output current by;
Where:
RBVsns
N
× Vsense
( RBVsns + RTVsns ) N SEC
TRESET
× hX
TPERIOD
When the maximum current output is achieved the voltage
seen on the ISENSE pin (VIsense) should reach its maximum.
Thus, at constant current limit:
(10.16)
The output voltage regulation is mainly determined by the
feedback signal VSENSE.
=
K SENSE
× NTR × I PRI ( pk ) ×
VIsense
=
(CC )
10.10 VSENSE Resistors and Winding
=
VSENSE VOUT _ PCB × K SENSE
1
2
I OUT =
Choose a value for NBIAS to be close to this number, for this
example we choose 17 turns.
tSTART −UP =
The ISENSE resistor determines the maximum current output
of the power supply. The output current of the power supply
is determined by:
V

2 × PIN × 0.25 + 21π × arcsin  INDC (min)
2 ×VINAC (min)


=
2
2
2 × VINAC
(min) − VINDC (min) × f line
CBULK
PIN =
(
VOUT (Cable ) × I OUT
)



(10.24)
hpower supply
VINAC(min) is the minimum input voltage (rms) to be inputted
into the power supply and fline is the lowest line frequency for
the power supply (in this case 47 Hz). VINDC(min) is calculated
from equation 10.9.
iW1691
February 3, 2012
Page 14
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
5.0V × 1A
= 7.25W
0.69
2 × 7.25W × 0.25 + 21π × arcsin 85V 
2 ×85Vac 

CBULK=
= 16mF
2
2
2 × ( 85Vac ) − ( 85V ) × 47 Hz
=
PIN
)
(
(
COUT ( Dynamic ) =
)
10.13 Output Capacitance
The output capacitance affects both the steady state ripple
and the dynamic response of the power supply.
Assuming an ideal capacitor where ESR (equivalent series
resistance) and ESL (equivalent series inductance) are
negligible then:
(
)
2
2
× h X × VOUT
2 × NTR
(VIN ⋅ TON )MAX
LM
(10.26)
× NTR × h X
(10.27)
472V ⋅ ms
× 13.8 × 0.87
= 3.99 A
1.42mH
2
=
QOUT
1.42mH ( 3.99 A − 1A )
= 6.97mC
2 × 13.82 × 0.87 × 5.5V
=
COUT (Steady State)
6.97mC
= 139mF
50mV
In this calculation ESR and ESL are ignored; the reason this
calculation is still valid is because of the second stage LC
filter on the output of the supply. These two components
reduce the ESR and ESL ripple; however keep in mind that
the ripple is a little higher in reality than this calculation would
suggest.
Assume that the load transient goes from no load to IOUT(HIGH).
Then from section 11.3, equation 11.3 we find that the
relationship between output capacitance (COUT(Dynamic)) and
VDROP(IC) is :
Rev. 2.0
(10.29)
RPreload × (VIN ⋅ TON ) PFM
2
2 × LM × VOUT
× hNo load
(10.30)
Assume that we want no more than 1.0 V drop on VOUT(PCB)
during load transient from no load to 50% load and the
efficiency of the power supply at no load (ηNo load) is 50%
then, COUT(Dynamic) is:
TP ( No load ) =
4.4k W × (119V ⋅ms )
2
2 × 1.42mH × ( 5.5V )
2
× 0.5 = 363ms
Since there is no cable, VDROP(cable) is 0 V.
So to keep VOUT(ripple) to be 50 mV,
I SEC=
( pk )
I OUT ( HIGH ) × TP (No load)
VDynamic ( Drop ) − VDROP (Cable ) − VDROP ( sense )
Where TP(No load) is the maximum period under no load
condition, given by equation 10.30:
(10.25)
The ISEC(pk) is:
I SEC ( pk )
=
COUT ( Dynamic ) =
=
TP ( No load )
VOUT ( ripple)
LM × I SEC ( pk ) − I OUT
(10.28)
2
QOUT
The output capacitor supplies the load current when the
secondary current is below the output current.
QOUT =
VDROP ( IC )
Then solving for VDROP(IC) from Figure 11.2, where VDynamic(DROP)
is the maximum allowable drop in voltage for the design
during dynamic response, VDROP(Cable) is the drop in voltage
due to the cable resistance, and VDROP(sense) is the drop in
voltage before VSENSE signal is low enough to register a
dynamic transient.
For this example CBULK is chosen to be 20 µF.
COUT (Steady State) =
I OUT ( HIGH ) × TP (No load)
VDROP ( sense ) =
(1.538V − 1.38V ) ×
5.0V
= 0.514V
1.538V
Plug everything into equation 10.19:
COUT ( Dynamic=
)
0.5 A × 363ms
= 373mF
1.0V − 0V − 0.514V
Pick the larger capacitance value between COUT(Dynamic) and
COUT(Steady State). In this case COUT is chosen to be 570 μF.
10.14 Snubber Network
The snubber network is implemented to reduce the voltage
stress on the MOSFET immediately following the turn off of
the gate drive. The goal is to dissipate the energy from the
leakage inductance of the transformer. For simplicity and
a more conservative design first assume the energy of the
leakage inductance is only dissipated through the snubber.
Thus:
1
2
2
2
1
 2

× Llk × I PRI
( pk ) =2 × CSNUB × VSnub ( pk ) − VSnub ( val ) 
(10.31)
Llk can be measured from the transformer and VDS is the
voltage across the MOSFET. VSnub(pk) and VSnub(val) refer to the
voltage measured across the snubber capacitor. Choose
iW1691
February 3, 2012
Page 15
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
a CSNUB, keeping in mind that the larger the value of CSNUB
the lower the voltage stress is on the MOSFET. However,
capacitors are more expensive the larger their capacitance.
Choose CSNUB based on these two criteria and select VSnub(pk)
and VSnub(val). Now a resistor needs to be selected to dissipate
VSnub(pk) to VSnub(val) during the on-time of the gate driver. The
dissipation of this resistor is given by:
VSnub (val )
VSnub ( pk )
=e
− TP ( min op)
10.16 SD Protection
The SD pin can be configured to provide three different
types of protection: OTP protection, OVP protection and
both OVP and OTP Protection. Figure 10.3 shows the three
configurations plus the configuration for no OTP and OVP
protection.
RSNUB ⋅CSNUB
(10.32)
RSD1(ext)
SD pin
Using equation 10.32 solve for RSNUB. This gives a
conservative estimate of what CSNUB and RSNUB should be.
Included in the snubber network is also a resistor in series with
a diode. The diode directs current to the snubber capacitor
when the MOSFET is turned off; however there is some
reverse current that goes through the diode immediately
after the MOSFET is turned back on. This reverse current
occurs because there is a short period of time when the
diode still conducts after switching from forward biased to
reverse biased. This conduction distorts the falling edge of
the VSENSE signal and affects the operation of the IC. So,
the resistor in series with the diode is there to diminish the
reverse current that goes through the diode immediately
after the MOSFET is turned on.
RNTC
RNTC
SD pin
RSD2(ext)
RSD(ext)
(optional)
OUTPUT
a) Overtemperature Protection only
b) Overtemperature Protection
and Overvoltage Protection
SD pin
RSD(ext)
RSD(ext)
SD pin
c) Overvoltage Protection only
d) No Overtemperature Protection
and no overvoltage protection
Figure 10.3 : SD Pin Application Configurations
10.15 TON Delay Filter
OTP Only
iW1691 also contains a feature that allows for adjustment
to match high line and low line constant current curves.
The mismatch in high line and low line is due to the delay
from the IC propagation delay, driver turn-on delay, and the
MOSFET turn-on delay. The driver turn-on delay maybe
further increased by a gate resistor to the MOSFET. To
adjust for these delays the iW1691 factors these delays into
its calculations and slightly over compensates for them to
provide flexibility. RDly and CDly provide extra delay in the
circuit to tweak the compensation. To determine values RDly
and CDly follow these steps:
To detect an overtemperature protection the iW1691 sends
a 100 mA current (ISD) to the SD pin every four cycles (see
section 11.5). On the last cycle the iW1691 observes the
voltage on the SD pin and detects an OTP fault if the voltage
is lower than VSD-TH, 1.0 V during normal operation and 1.2 V
during startup. So RSD(ext) in series with NTC must meet
1. Measure the difference between high line and low line
constant current limit without filter components.
2. Find the curve that best matches this difference from
Figure 12.7.
3. Find the LM that matches the power supply, and find the
tRC.
(10.33)
(10.34)
in order not to trigger OTP fault during normal operation.
OVP Only
For the other four cycles, the iW1691 connects the SD pin
to RSD to ground (see section 11.5). At the last cycle the
iW1691 observes the voltage on the SD pin and detects an
OVP fault if the voltage is higher than VSD-TH, 1 V. In order to
not trigger OVP fault, assuming 0 V drop across the series
diode, RSD(ext) must meet:
VOUT _ PCB
4. Find RDly and CDly from equation 10.33
t RC = RDly × CDly
( RNTC +RSD(ext ) ) × I SD > VSD−TH
N SEC
× N AUX ×
RSD
< VSD −TH
RSD + RSD (ext )
(10.35)
where, RSD = 8.333 kΩ
Rev. 2.0
iW1691
February 3, 2012
Page 16
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
Both OTP and OVP
L
N
To find RSD1(ext) so that OVP can be detected, use equation
10.35. To find RSD2(ext) in series with the NTC use equation
10.34.
Note that this means OVP is not detected through the SD pin;
however, OVP from VSENSE pin is still active and the iW1691
still shuts down if overvoltage condition is detected.
Since for this example OTP and OVP are not necessary we
place a resistor from SD pin to ground and calculate its value
from equation 10.36.
RSD (ext ) > 1.2V
100mA
=
12k W
10.17 PCB Layout
VOUT
RTN
+
3)
If OTP and OVP from the SD pin are not needed, simply
place a resistor, RSD(ext) to ground from the SD pin. Make
sure RSD(ext) meets equation 10.36 so OTP protection does
not trip.
(10.36)
+
1)
No OTP and OVP
RSD (ext ) × I SD > VSD −TH
2)
+
Optional
NTC
Thermistor
1
NC
2
VSENSE
3
VIN
4
SD
VCC 8
OUTPUT 7
ISENSE 6
GND 5
U1
iW1691
Figure 10.4 : Switching Loops
To improve ESD performance provide a low impedance path
from the ground pin of the transformer to the ac power source
and make sure this path does not go through the IC ground
pin. A discharge spark gap helps to transfer ESD and EOS
energy from the secondary side of the power supply directly
to the external ac power source.
In a switch-mode power supply there are several ground
signals, namely: the power ground, the switching ground
and the control logic ground. These ground signals should
be connected by a star connection. Ground traces should
be kept as short as possible. A thick trace on the switching
ground helps to lessen switching losses.
In the iW1691, there are two signals that are important to
control the output performance; these are the ISENSE signal
and the VSENSE signal. The ISENSE resistor should be close to
the source of the MOSFET to avoid any trace resistance from
contaminating the ISENSE signal. Also, the ISENSE signal should
be placed close to the ISENSE pin. The VSENSE signal should
be placed close to the transformer to improve the quality of
the sensing signal. Also for better output performance all
bypass capacitors should be placed close to their respective
pins.
To reduce EMI, switching loops need to be minimized. These
loops include:
1. The input bulk capacitor, primary winding, MOSFET and
RIsense loop.
2. The output diode, output capacitor and secondary
winding loop.
3. VCC winding and rectifier diode loop.
Rev. 2.0
iW1691
February 3, 2012
Page 17
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
11.0 Product Options
11.1 Startup Options
Startup options only affect the power supply in startup and
no where else.
CC Delay
CC delay forces the IC to go into CC mode after a given
amount of time, specified by the option. This helps to limit
the amount of current overshoot seen at the output during an
output short or startup into CC. The trade off of this option
is that for heavy loads the startup rise time may become
longer.
11.2 Constant Voltage Regulation
The iW1691 is designed with the capability of keeping very
tight constant voltage regulation at the end of an output cable
and also during dynamic load conditions.
The second component which affects the voltage drop during
load transient is VDROP(sense). This voltage drop is the drop in
voltage before the VSENSE signal is able to show a significant
drop in output voltage. This is determined by VMIN or the
reference voltage at which a load transient is detected. The
larger the VSENSE(min) is the smaller this drop in voltage is.
(
Cable drop compensation is an optional feature on the
iW1691 to help compensation for the degradation of the
output voltage from the output cable to the load. During
CV (constant voltage) mode the output current changes as
the voltage remains constant. This is true for the output
voltage at the output of the power supply board; however, in
certain applications the device to be charged is not directly
connected to the power supply, but rather, is connected
via a cable. This cable is seen by the power supply as a
resistance. So, as the output current increases the output
voltage at the end of the cable begins to drop. With its builtin cable compensation feature the iW1691 can incrementally
increase the output voltage with respect to the output current
to compensate for the voltage drop in the cable.
The cable compensation option refers to the percentage of
the output voltage that would be due to the voltage drop due
to the cable under maximum output current. For example,
if a 5 V power supply has a voltage drop across its cable of
300 mV then the 6% option should be chosen, since 300 mV
is 6% of 5 V.
VOUT ( PCB )
VSENSE ( nom )
(11.2)
Keep in mind that a larger VSENSE(min) is less tolerant of noise
and distortions in VSENSE than a smaller one.
The final drop in voltage is due to the time from when VSENSE
drops VSENSE(min) to when the next VSENSE signal appears.
In the worst case condition this is how much voltage drops
during the longest switching period.
VDROP ( IC ) =
Cable Drop Compensation
)
VDROP ( sense ) = VSENSE ( nom ) − VSENSE (min) ×
I OUT × TP (No load)
COUT
(11.3)
A larger output capacitance in this case greatly reduces the
VDROP(IC).
TP(dynamic) Clamp Option
The iW1691 also has an option to clamp the switching
period during dynamic transient from heavy load to light
load (TP(dynamic)). This option helps to ensure enough supply
voltage is available to support the IC during transient
condition cycles.
11.3 Output Voltage Protection
The iW1691 also offers both output overvoltage and output
undervoltage protection. For output overvoltage select the
percentage above the output voltage that the power supply
should shut down. Both of these protections are detected
by the VSENSE signal cycle-by-cycle. Output undervoltage
protection can be latched; if that is the case, then the power
supply remains in shutdown mode until VCC is 1 V below
VCC(UVL).
11.4 Input Voltage Protection
VMIN Option
There are three components that compose the voltage drop
during a load transient event.
iW1691 also offers input under voltage protection. The
power supply does not attempt to start up until input is above
VINSTLOW.
VDROP(cable) is the drop in voltage due from the increased
current going through the connector and/or the cable.
11.5 SD Pin Latch
VDROP=
RCABLE × ∆I OUT
( cable )
Rev. 2.0
(11.1)
The SD pin offers latched output overvoltage and/
or overtemperature protection.
The iW1691 switches
between monitoring overtemperature fault and overvoltage
fault. In order to detect the resistance in the NTC for an
iW1691
February 3, 2012
Page 18
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
overtemperature fault, the iW1691 connects a current
source to the SD pin and checks the voltage on the pin. To
ensure that the current source is settled before the voltage
is checked both OTP and OVP are detected on the last cycle,
as depicted in figure 11.1.
OTP
Detection
OVP
Detection
Vgate
Detection Switch
Detection Switch:
When switch is low SD pin is connected to R SD
When switch is high SD pin is connected to a current source ISD
Figure 11.1 : SD Pin Detection Cycles
During an overvoltage monitor cycle the SD pin is connected
to a resistance internal to the chip, RSD, to ground and the
voltage on the SD pin is observed.
If OTP and OVP are selected to latch then, once a fault is
detected the controller shuts down and remains in shut down
until VCC drops below 1 V of VCC(UVL).
iW1691
ISD
Detection
Switch
SD pin
OTP / OVP
Fault Detect
VSD-TH
R SD
Figure 11.2 : Internal Function of SD Pin
Rev. 2.0
iW1691
February 3, 2012
Page 19
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
12.0 Design Example Performance Characteristics
Efficiency (%)
100
80
60
Ch1: IOUT
1.0 A/div
40
Ch2: VOUT
5.0 V/div
20
0
Ch3: VSENSE
1.0 V/div
90 VAC
264 VAC
0
200
400
600
Output Current (mA)
800
1000
Ch4: VGATE
10.0 V/div
Time Scale:
20 μs/div
Figure 12.1 : Efficiency at 90 VAC and 264 VAC
Figure 12.4 : VSENSE Short at 90 VAC
VOUT (1.0 V/div)
Ch1: IOUT
1.0 A/div
Ch2: VOUT
5.0 V/div
Ch3: ISENSE
500 mV/div
0
Ch4: VGATE
10.0 V/div
0
IOUT (200 mA/div)
Time Scale:
20 μs/div
Figure 12.2 : Regulation without Cable Drop Compensation
Figure 12.5 : ISENSE Short at 90 VAC
VOUT (1.0 V/div)
Ch1: IOUT
1.0 A/div
Ch2: VOUT
5.0 V/div
Ch3: VSENSE
1.0 V/div
0
Ch4: VGATE
10.0 V/div
0
IOUT (200 mA/div)
Figure 12.3 : Regulation with Cable Drop Compensation
Rev. 2.0
iW1691
February 3, 2012
Time Scale:
200 μs/div
Figure 12.6 : Output Short Fault (50% load)
Page 20
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
12.0 Design Example Performance Characteristics (cont.)
180
∆IOUT (Note1)
50 mA
40 mA
30 mA
20 mA
10 mA
(RDly x CDly), τRC (ns)
150
120
90
60
30
0
0
0.75
1.50
2.25
Magnetizing Inductance LM (mH)
3.0
Figure 12.7 : TON Compensation Chart RDS(ON) = 55 - 250 Ω
13.0 Application Circuit
L
10 Ω / 1W
Lout (opt)
4 µH
470 µH
N
10 kΩ
+
Cbulk
10 µF
Cbulk
10 µF
Rsnub
Rvin 220 kΩ
2.7 MΩ
+
Rvin
2.4 MΩ
470 pF
Rtvsns
10.0 kΩ
Rbvsns
2.2 kΩ
22 pF
1
NC
2
VSENSE
3
VIN
ISENSE 6
4
SD
GND 5
Rsd(ext)
20 kΩ
VCC 8
OUTPUT 7
U1
iW1691
Cout +
470 µF
Csnub
470 pF
Cout (opt) +
100 µF
VOUT
Rpreload
2.2 kΩ
RTN
330 Ω
+
330 Ω
Cvcc
10 µF
Rgate (opt)
10 Ω
Rdly (opt)
402 Ω
Cdly (opt)
33 pF
Risense
3.0 Ω
Figure 13.1 : Typical Application Circuit
Note 1: ΔIOUT refers to the difference in constant current limit between 264 Vac and 90 Vac when no RDLY and CDLY are applied.
Rev. 2.0
iW1691
February 3, 2012
Page 21
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
14.0 Physical Dimensions
8-Lead Small Outline (SOIC) Package
E
8
5
1
4
H
e
h x 45°
A1
COPLANARITY
0.10 (0.004)
A2
B
MIN
MAX
MIN
MAX
A
0.053
0.069
1.35
1.75
A1
0.0040
0.010
0.10
0.25
A2
0.049
0.059
1.25
1.50
B
0.014
0.019
0.35
0.49
C
0.007
0.010
0.19
0.25
D
0.189
0.197
4.80
5.00
E
0.150
0.157
3.80
4.00
e
A
SEATING
PLANE
Inches
Symbol
D
α
L
C
0.050 BSC
Millimeters
1.27 BSC
H
0.228
0.244
5.80
6.20
h
0.10
0.020
0.25
0.50
L
0.016
0.049
0.4
1.25
α
0°
8°
Figure 14.1 : Physical dimensions, 8-lead SOIC package
Compliant to JEDEC Standard MS12F
Controlling dimensions are in inches; millimeter dimensions are for reference only
This product is RoHS compliant and Halide free.
Soldering Temperature Resistance:
[a] Package is IPC/JEDEC Std 020D Moisture Sensitivity Level 1
[b] Package exceeds JEDEC Std No. 22-A111 for Solder Immersion Resistance; package can withstand
10 s immersion < 270˚C
Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion. Interlead flash or
protrusion shall not exceed 0.25 mm per side.
The package top may be smaller than the package bottom. Dimensions D and E1 are determined at the
outermost extremes of the plastic bocy exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
Rev. 2.0
iW1691
February 3, 2012
Page 22
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
15.0 Ordering Information
Part Number
Options
Package
Description
iW1691-00
Cable Comp = 0 mV, VSENSE(min) = 1.38 V, fSW(MAX) = 140 kHz
SOIC-8
Tape & Reel1
iW1691-01
Cable Comp = 0 mV, VSENSE(min) = 1.515 V, OTP/OVP latch,
Output Low Protection latch, fSW(MAX) = 140 kHz
SOIC-8
Tape & Reel1
iW1691-03
Cable Comp = 0 mV, VSENSE(min) = 1.515 V, OTP/OVP latch,
fSW(MAX) = 140 kHz
SOIC-8
Tape & Reel1
iW1691-04
Cable Comp = 300 mV, CC Delay = 30 μs, VSENSE(min) = 1.48 V,
fSW(MAX) = 140 kHz
SOIC-8
Tape & Reel1
iW1691-08
Cable Comp = 300 mV, CC Delay = 30 μs, VSENSE(min) = 1.48 V,
fSW(MAX) = 140 kHz, TP(dynamic) = 200 μs
SOIC-8
Tape & Reel1
iW1691-09
Cable Comp = 150 mV, VSENSE(min) = 1.515 V, OTP/OVP latch
fSW(MAX) = 140 kHz, TP(dynamic) = 200 μs
SOIC-8
Tape & Reel1
iW1691-10
Cable Comp = 400 mV, CC Delay = 30 μs, VSENSE(min) = 1.48 V,
fSW(MAX) = 140 kHz, TP(dynamic) = 200 μs
SOIC-8
Tape & Reel1
iW1691-11
Cable Comp = 0 mV, VSENSE(min) = 1.515 V, OTP/OVP latch,
7.5 ms Output OCP latch-off time,
Output Low Protection latch, fSW(MAX) = 140 kHz
SOIC-8
Tape & Reel1
Note 1: Tape & Reel packing quantity is 2,500/reel.
Rev. 2.0
iW1691
February 3, 2012
Page 23
iW1691
Digital PWM Current-Mode Controller for Quasi-Resonant Operation
About iWatt
iWatt Inc. is a fabless semiconductor company that develops intelligent power management ICs for computer, communication,
and consumer markets. The company’s patented pulseTrain™ technology, the industry’s first truly digital approach to power
system regulation, is revolutionizing power supply design.
Trademark Information
© 2012 iWatt, Inc. All rights reserved. iWatt, EZ-EMI, Intelligent AC-DC and LED Power, and pulseTrain are trademarks of
iWatt, Inc. All other trademarks and registered trademarks are the property of their respective owners.
Contact Information
Web: https://www.iwatt.com
E-mail: [email protected]
Phone: 408-374-4200
Fax: 408-341-0455
iWatt Inc.
675 Campbell Technology Parkway, Suite 150
Campbell, CA 95008
Disclaimer
iWatt reserves the right to make changes to its products and to discontinue products without notice. The applications
information, schematic diagrams, and other reference information included herein is provided as a design aid only and are
therefore provided as-is. iWatt makes no warranties with respect to this information and disclaims any implied warranties of
merchantability or non-infringement of third-party intellectual property rights.
iWatt cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an iWatt product. No
circuit patent licenses are implied.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property
or environmental damage (“Critical Applications”).
iWatt SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO
BE SUITABLE FOR USE IN LIFE‑SUPPORT APPLICATIONS, DEVICES OR SYSTEMS, OR OTHER CRITICAL
APPLICATIONS.
Inclusion of iWatt products in critical applications is understood to be fully at the risk of the customer. Questions concerning
potential risk applications should be directed to iWatt, Inc.
iWatt semiconductors are typically used in power supplies in which high voltages are present during operation. High-voltage
safety precautions should be observed in design and operation to minimize the chance of injury.
Rev. 2.0
iW1691
February 3, 2012
Page 24