APW7337 3A 24V 340kHz synchronous Buck Converter Features General Description • Wide Input Voltage from 4.5V to 24V • 3A Continuous Output Current APW7337 is a 3A synchronous buck converter with integrated 85mΩ power MOSFETs. The APW7337 design • Adjustable Output Voltage from 0.8V to 20V • Intergrated High/Low Side MOSFET • PFM/PWM mode Operation • Fixed 340kHz Switching Frequency • Stable with Low ESR Ceramic Output Capacitors • Power-On-Reset Detection • Programmable Soft-Start • Over-Temperature Protection • Current-Limit Protection with Frequency Foldback • Enable/Shutdown Function • Small TDFN3x3-10 Package • Lead Free and Green Devices Available with a current-mode control scheme, can convert wide input voltage of 4.5V to 24V to the output voltage adjustable from 0.8V to 20V to provide excellent output voltage regulation. The APW7337 is equipped with an automatic PFM/PWM mode operation. At light load, the IC operates in the PFM mode to reduce the switching losses. At heavy load, the IC works in PWM. The APW7337 is also equipped with Power-on-reset, softstart, and whole protections (over-temperature, and current-limit) into a single package. This device, available TDFN3x3-10, provides a very compact system solution external components and PCB area. (RoHS Compliant) Applications • LCD Monitor/TV • Set-Top Box • DSL, Switch HUB • Notebook Computer Pin Configuration APW7337 EN SS BS VIN VIN 11 GND 10 COMP 9 FB 8 GND 7 GND 6 LX TDFN3x3-10 (Top View) Simplified Application Circuit 11 Exposed Pad The pin 7 and 8 must be connected to the pin 11 (Exposed Pad) VIN APW7337 1 2 3 4 5 VOUT ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 1 www.anpec.com.tw APW7337 Ordering and Marking Information Package Code QB : TDFN3x3-10 Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7337 Assembly Material Handling Code Temperature Range Package Code APW7337 QB : APW 7337 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol Parameter VIN VIN Supply Voltage (VIN to GND) VLX LX to GND Voltage EN, FB, COMP, SS to GND Voltage Rating Unit -0.3 ~ 30 V -1 ~VIN+0.3 V -0.3 ~ 6 V VBS BS to GND Voltage VLX-0.3 ~ VLX+6 V PD Power Dissipation Internally Limited W TJ Junction Temperature TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature, 10 Seconds 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Thermal Characteristics Symbol Parameter θJA Junction-to-Ambient Resistance in Free Air θJC Junction-to-Case Resistance in Free Air Typical Value Unit (Note 2) o TDFN3x3-10 54 TDFN3x3-10 11 C/W o C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad is soldered directly on the PCB. Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 2 www.anpec.com.tw APW7337 Recommended Operating Conditions (Note 4) Symbol Range Unit VIN Supply Voltage 4.5 ~ 24 V VOUT Converter Output Voltage 0.8 ~20 V IOUT Converter Output Current TA Ambient Temperature VIN TJ Parameter 0~3 Junction Temperature A -40 ~ 85 o -40 ~ 125 o C C Note 4 : Refer to the typical application circuit. Electrical Characteristics Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V, VEN=3V and TA=25°C. Symbol Parameter APW7337 Test Conditions Unit Min. Typ. Max. SUPPLY CURRENT IVIN IVIN_SD VIN Supply Current VFB=1V, VEN=3V, LX=NC - 1.9 - mA VIN Shutdown Supply Current VEN=0V - 0.3 - µA 3.8 4.05 4.4 V - 0.3 - V 0.784 0.8 0.816 V 300 340 380 kHz POWER-ON-RESET (POR) VIN POR Voltage Threshold VIN Rising VIN POR Hysteresis REFERENCE VOLTAGE VREF Reference Voltage Regulated on FB pin OSCILLATOR AND DUTY CYCLE FOSC Oscillator Frequency Foldback Frequency VFB=0V - 110 - kHz Maximum Converter’s Duty VFB=0.8V - 90 - % Minimum On Time (Note 5) - 220 - ns PFM MODE OPERATION IPK_PFM PFM Mode Current Limit - 0.8 - A IPK_TH PWM to PFM Inductor Peak Threshold - 0.6 - A - 110 - mΩ - - 10 µA Error Amplifier Transconductance - 820 - µA/V Error Amplifier Voltage Gain - 80 - V/V Switch Current to COMP Voltage Transresistance - 5.2 - A/V POWER MOSFET High/low Side MOSFET On Resistance High/Low Side MOSFET Leakage Current VEN=0V, VLX=0V CURRENT-MODE PWM CONVERTER GEA Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 3 www.anpec.com.tw APW7337 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V, VEN=3V and TA= 25°C. Symbol Parameter APW7337 Test Conditions Min. Unit Typ. Max. PROTECTIONS ILIM High Side MOSFET Current-Limit - 5.6 - A TOTP Over-Temperature Trip Point Peak Current - 160 - °C Over-Temperature Hysteresis - 50 - °C Over-Voltage Protection - 120 - % - 6 - µA - 1.5 - V 2.2 2.5 2.7 V - 200 - mV SOFT-START, ENABLE AND INPUT CURRENTS ISS Soft-Start Current EN Enable Threshold Voltage VIN=4.5~24V EN Under-Voltage Lockout (UVLO) Threshold VEN rising EN UVLO Hysteresis Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 4 www.anpec.com.tw APW7337 Typical Operating Characteristics Efficiency vs. Output Current Efficiency vs. Output Current 100 100 90 90 80 80 70 Efficiency (%) Efficiency (%) 70 60 50 VIN = 19V 40 30 VIN = 12V VOUT = 1.2V 60 50 VOUT = 1.8V 40 30 VOUT = 2.5V 20 20 10 10 VOUT = 5V 0 0 0.001 0.01 0.1 1 0.001 10 0.01 1 10 Soft Start Time vs. SS pin to GND Capacitance VIN Supply Current vs. VIN Supply Voltage 80 1.90 TA=25oC VIN =12V, VOUT =3.3V, TA=25oC, The time of 10%~90%VOUT 70 1.85 Soft Start Time, tSS (ms) VIN Supply Current, IVIN (mA) 0.1 Output Current (A) Output Current (A) 1.80 1.75 1.70 60 50 40 30 20 10 1.65 5 10 15 20 0 25 0 100 200 300 400 500 VIN Supply Voltage (V) SS pin to GND Capacitance (nF) EN UVLO Threshold Voltage vs. VIN Supply Voltage Reference Voltage vs. VIN Supply Voltage 2.6 0.805 TA=25oC 2.5 Reference Voltage, VREF (V) EN UVLO Threshold Voltage, VEN (V) VIN = 12V VOUT = 3.3V 2.4 VEN Rising 2.3 2.2 VEN Falling 2.1 2.0 0.803 0.801 0.799 0.797 0.795 5 10 15 20 25 5 VIN Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 10 15 20 25 VIN Supply Voltage (V) 5 www.anpec.com.tw APW7337 Typical Operating Characteristics 360 360 VIN = 12V 355 Switching Frequency, FOSC(kHz) Switching Frequency, FOSC(kHz) Switching Frequency vs. VIN Supply Voltage Switching Frequency vs. Junction Temperature 350 345 340 335 330 325 358 356 354 352 350 320 -50 0 50 100 5 150 10 15 20 25 VIN Supply Voltage (V) Junction Temperature (oC) Reference Voltage vs. Junction Temperature 0.82 Reference Voltage, VREF(V) TA = 25oC VIN = 12V 0.815 0.81 0.805 0.8 0.795 0.79 -50 0 50 100 150 o Junction Temperature ( C) Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 6 www.anpec.com.tw APW7337 Operating Waveforms The test condition is VIN=12V, TA= 25oC unless otherwise specified. Power On Power Off VIN V OUT 1 1 2 2 IL 3 3 VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, no load CH1: VIN, 5V/Div, DC CH2: VOUT , 2V/Div, DC CH3: IL, 0.5A/Div, DC VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, no load CH1: VIN, 5V/Div, DC CH2: VOUT , 2V/Div, DC CH3: IL, 0.5A/Div, DC TIME: 10ms/Div TIME: 50ms/Div Enable Shutdown VEN VEN 1 1 VOUT V OUT 2 2 IL IL 3 3 VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, RLOAD =2Ω VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, RLOAD =2Ω CH1: VEN, 5V/Div, DC CH2: VOUT , 2V/Div, DC CH3: IL, 2A/Div, DC CH1: VEN, 5V/Div, DC CH2: VOUT , 2V/Div, DC CH3: IL, 2A/Div, DC TIME:50µs/Div TIME: 5ms/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 7 www.anpec.com.tw APW7337 Operating Waveforms The test condition is VIN=12V, TA= 25oC unless otherwise specified. Current Limit & Frequency Foldback Normal Operation in Heavy Load VOUT 1 VOUT VLX VLX 1 2 3 IL IL 2 3 VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, IOUT =3A CH1: VOUT , 2V/Div, DC CH2: IL, 2A/Div, DC CH3: VLX, 10V/Div, DC VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, Ramp up IOUT into current limit CH1: VEN, 5V/Div, DC CH2: VLX, 10V/Div, DC CH3: IL, 2A/Div, DC TIME: 2µs/Div TIME: 50µs/Div Normal Operation in Light Load Load Transient VOUT VLX VOUT 1 1 3 IOUT IL 2 2 VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, IOUT =100mA CH1: VOUT , 2V/Div, DC CH2: IL, 1A/Div, DC CH3: VLX, 10V/Div, DC VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, COMP=6.8kΩ+3.9nF, IOUT =100mA-3A-100mA CH1: VOUT , 0.5V/Div, offset=3.3V CH2: IOUT , 2A/Div, DC TIME: 50µs/Div TIME: 5µs/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 8 www.anpec.com.tw APW7337 Operating Waveforms The test condition is VIN=12V, TA= 25oC unless otherwise specified. Short Circuit Load Transient VOUT VLX VOUT 1 1 VLX 2 IOUT IL 2 3 VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, VOUT short to ground. VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, COMP=6.8kΩ+3.9nF, IOUT =1A-3A-1A CH1: VOUT , 2V/Div, DC CH2: VLX, 10V/Div, DC CH3: IL, 5A/Div, DC TIME: 10µs/Div CH1: VOUT , 0.5V/Div, offset=3.3V CH2: IOUT , 2A/Div, DC TIME: 50µs/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 9 www.anpec.com.tw APW7337 Pin Description PIN FUNCTION TDFN3x3-10 Name 3 BS 4.5 VIN 6 LX 7.8 GND 9 FB 10 COMP 1 EN 2 SS Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND to set the soft-start period. A 0.1µF capacitor sets the soft-start period to 15ms. To disable the soft-start feature, leave SS unconnected. 11 Exposed Pad Connect the exposed pad to the system ground plan with large copper area for dissipating heat into the ambient air. High-Side Gate Drive Boost Input. BS supplies the voltage to drive the high-side N-channel MOSFET. At least 10nF capacitor should be connected from LX to BS to supply the high side switch. Power Input. VIN supplies the power (4.5V to 24V) to the control circuitry, gate drivers and step-down converter switches. Connecting a ceramic bypass capacitor and a suitably large capacitor between VIN and GND eliminates switching noise and voltage ripple on the input to the IC. Power Switching Output. LX is the Drain of the N-Channel power MOSFET to supply power to the output LC filter. Ground. Connect the exposed pad on backside to Pin 4. Output feedback Input. The APW7337 senses the feedback voltage via FB and regulates the voltage at 0.8V. Connecting FB with a resistor-divider from the converter’s output sets the output voltage from 0.8V to 20V. Output of the error amplifier. Connect a series RC network from COMP to GND to compensate the regulation control loop. In some cases, an additional capacitor from COMP to GND is required. Enable Input. EN is a digital input that turns the regulator on or off. EN threshold is 2.5V with 0.2V hysteresis. Pull up with 100kΩ resistor for automatic startup. Block Diagram VIN 2 Current Sense Amplifier LOC Over Temperature Protection Power-OnReset Current Limit 5V 1 BS POR 5V OTP 6µA 120%VREF SS 8 Gate Driver Fault Logics OVP Inhibit Gate Control 3 LX 5V FB 5 Gm VREF Current Compartor Error Amplifier Gate Driver COMP 6 2.5/2.3V EN 7 UVLO Enable 1.5V Slope Compensation Internal Regulator 5V VIN Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 10 Oscillator 340kHz/ 110kHz 4 GND LOC FB 0.6V Current Sense Amplifier www.anpec.com.tw APW7337 Typical Application Circuit VIN 4.5V~24V C2 (option*) C1 10µF 4,5 3 VIN C3 10nF BS R4 100k 1 LX EN VOUT 3.3V/3A 6 L1 10µH C4 22µFx2 APW7337 2 SS 10 C5 0.1µF 9 COMP FB R1 24K GND R3 6.8k 7,8 R2 7.5K C6 3.9nF * For cirtical condition, like plug in, the large capacitace and high voltage rating are needed to avoid the high spike voltage. Recommended Feedback Compensation Value Vin(V) VOUT(V) L1(µH) C2(µF) R1(KΩ) R2(KΩ) R3(KΩ) C5(nF) 24 5 10 22(Ceremic) 36 6.8 6.8 3.9 12 5 10 44 (Ceremic) 36 6.8 5 1.5 12 3.3 10 22 (Ceremic) 24 7.5 6.8 3.9 12 2.5 10 22 (Ceremic) 12 5.6 6.8 3.9 Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 11 www.anpec.com.tw APW7337 Function Description Main Control Loop Enable/Shutdown The APW7337 is a constant frequency current mode switching regulator. During normal operation, the inter- Driving EN to ground places the APW7337 in shutdown. When in shutdown, the internal N-Channel power MOSFET nal N-channel power MOSFET is turned on each cycle when the oscillator sets an internal RS latch and would turns off, all internal circuitry shuts down and the quiescent supply current reduces to 0.3µA. be turned off when an internal current comparator (ICMP) resets the latch. The peak inductor current at which ICMP Current-Limit Protection resets the RS latch is controlled by the voltage on the COMP pin, which is the output of the error amplifier The APW7337 monitors the output current, flowing through the N-Channel power MOSFET, and limits the (EAMP). An external resistive divider connected between VOUT and ground allows the EAMP to receive an output IC from damages during overload, short-circuit and overvoltage conditions. feedback voltage VFB at FB pin. When the load current increases, it causes a slight decrease in VFB relative to Frequency Foldback the 0.8V reference, which in turn causes the COMP voltage to increase until the average inductor current matches The foldback frequency is controlled by the FB voltage. When the FB pin voltage is under 0.6V, the frequency of the new load current. the oscillator will be reduced to 110kHz. This lower frequency allows the inductor current to safely discharge, VIN Power-On-Reset (POR) and EN Under-voltage Lockout thereby preventing current runaway. The oscillator’s frequency will switch to its designed rate when the feedback The APW7337 keep monitoring the voltage on VIN pin to prevent wrong logic operations which may occur when voltage on FB rises above the rising frequency foldback VIN voltage is not high enough for the internal control threshold (0.6V, typical) again. circuitry to operate. The VIN POR has a rising threshold of 4.05V (typical) with 0.3V of hysteresis. Over-Voltage Protection An external under-voltage lockout (UVLO) is sensed at the EN pin. The EN UVLO has a rising threshold of 2.5V The over-voltage function monitors the output voltage by FB pin. When the FB voltage increase over 120% of the reference voltage, the over-voltage protection compara- with 0.2V of hysteresis. The EN pin should be connected a resistor divider from VIN to EN . tor will force the high-and low-side MOSFET gate driver off. As soon as the output voltage is within regulation, the After the VIN and EN voltages exceed their respective voltage thresholds, the IC starts a start-up process and OVP comparator is disengaged. The chip will restore its normal operation. then ramps up the output voltage to the setting of output voltage. Over-Temperature Protection (OTP) The over-temperature circuit limits the junction temperature of the APW7337 When the junction temperature exceeds TJ =+160oC, a thermal sensor turns off the power MOSFET, allowing the device to cool down. The thermal sensor allows the converter to start a start-up process and regulate the output voltage again after the junction temperature cools by 50oC. The OTP designed with a 50 oC hysteresis lowers the average T J during c ontinuous thermal overload conditions, increasing life time of the IC. Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 12 www.anpec.com.tw APW7337 Application Information T=1/FOSC Setting Output Voltage The regulated output voltage is determined by: VOUT = 0.8 × (1 + R1 VLX DT I IOUT ) ⋅ (V) R2 IL To prevent stray pickup, please locate resistors R1 and R2 close to APW7337. IOUT IQ1 I ICOUT Inductor Capacitor Selection Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge cur- VOUT rent needed each time the N-channel power MOSFET (Q1) turns on. Place the small ceramic capacitors physi- VOUT Figure 1. Converter Waveforms cally close to the VIN and between the VIN and GND. The important parameters for the bulk input capacitor are Output Capacitor Selection the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and An output capacitor is required to filter the output and supply the load transient current. The filtering requirements current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor are the function of the switching frequency and the ripple current (DI). The output ripple is the sum of the voltages, voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 having phase shift, across the ESR and the ideal output capacitor. The peak-to-peak voltage of the ESR is calcu- times is a conservative guideline. The RMS current (IRMS) of the bulk input capacitor is calculated as the following ated as the following equations: equation: D = V OUT V IN ........... (1) IRMS = IOUT D × (1 − D) ⋅ ( A ) ∆I = V OUT × (1 − D ) F OSC × L ........... (2) where D is the duty cycle of the power MOSFET. For a through hole design, several electrolytic capacitors ........... (3) V ESR = ∆ I × ESR The peak- to-peak voltage of the ideal output capacitor is calculated as the following equations: may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. ∆VCOUT = CIN the AC peak-to-peak output voltage(∆VOUT) is shown below: Q1 IL LX Q2 ........... (4) For the applications using bulk capacitors, the ∆VCOUT is much smaller than the VESR and can be ignored. Therefore, VIN VIN IQ1 ∆I 8 × FOSC × COUT IOUT ∆VOUT = ∆I × ESR ⋅ ( V ) VOUT L ICOUT ESR ........... (5) For the applications using bulk capacitors, the VESR is much smaller than the ∆V COUT and can be ignored. Therefore, the AC peak-to-peak output voltage(∆VOUT) is to COUT ∆VCOUT. Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 13 www.anpec.com.tw APW7337 Application Information(Cont.) Output Capacitor Selection (Cont.) VOUT ·(VIN - VOUT) ≤ 1.2 340000 ·L ·VIN The load transient requirements are the function of the slew rate (di/dt) and the magnitude of the transient load L≥ urrent. These requirements are generally met with a mix of capacitors and careful layout. High frequency ca- VOUT ·(VIN - VOUT) 408000 ·VIN (H) ........... (6) where VIN = VIN(MAX) pacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter ca- Table2 Inductor Selection Guide Vender pacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating require- Part number Inductance DCR Current (µH) (mΩ) Rating(A) CYNTEC PCMB063T-100MS ments rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit 10 62 4 Chilisin MHCC10040-100M 10 30 6.5 Gausstek PL94P051M-10U 10 38 3.8 Input Capacitor Selection board wiring that could cancel the usefulness of these low inductance components. An aluminum electrolytic A low ESR capacitor is required to keep the noise minimum. Ceramic capacitors are better, but tantalum or capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equiva- low ESR electrolytic capacitors may also suffice. When using tantalum or electrolytic capacitors, a 0.1µF ceramic lent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the ca- capacitor should be placed as close to the IC as possible. It is recommended that the input EC capacitor should be pacitor to high slew-rate transient loading. added for applications if the APW7337 will suffer high spike input voltage (ex. hot plug test). It can eliminate the Table1 Capacitor Selection Guide Capacitance Voltage Vender Model TC Si2e Rating(V) (µF) muRata GRM31CR61E106K 10 X5R 25 1206 muRata GRM31CR61C226K 22 X5R 16 1206 spike voltage and induced the IC damage from high input voltage stress. VIN CIN1 330µF/25 V/EC x1 Inductor Value Calculation C IN2 22µF/25V /MLCC x1 APW7337 The operating frequency and inductor selection are interrelated in that higher operating frequencies permit the use of a smaller inductor for the same amount of inductor ripple current. However, this is at the expense of efficiency due to an increase in MOSFET gate charge losses. The equation (2) shows that the inductance value has a direct effect on ripple current. Accepting larger values of ripple current allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ∆I< 0.4 x IOUT(max). Please be noticed that the maximum ripple current occurs at the maximum input voltage. The minimum inductance of the inuctor is calculated by using the following equation: Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 14 www.anpec.com.tw APW7337 Application Information (Cont.) Thermal Consideration 1. Begin the layout by placing the power components first. The APW7337 maximum power dissipation depends on Orient the power circuitry to achieve a clean power flow path. If possible, make all the connections on one side of the thermal resistance and temperature difference between the die junction and ambient air. The power dissi- the PCB with wide, copper filled areas. 2. In Figure 3, the loops with same color bold lines con- pation PD across the device is: duct high slew rate current. These interconnecting impedances should be minimized by using wide and short PD = (TJ - TA) / θJA where (TJ-TA) is the temperature difference between the printed circuit traces. 3. Keep the sensitive small signal nodes (FB, COMP) junction and ambient air. θJA is the thermal resistance between Junction and ambient air. away from switching nodes (LX or others) on the PCB and it should be placed near the IC as close as possible. For normal operation, do not exceed the maximum junction temperature rating of TJ = 125 oC. The calculated Therefore, place the feedback divider and the feedback compensation network close to the IC to avoid switching power dissipation should less than: PD = (125-25)/54=1.85(W) --- (TDFN3x3-10) noise. Connect the ground of feedback divider directly to the GND pin of the IC using a dedicated ground trace. Maximum Power Dissipation, PD(W) 4. Place the decoupling ceramic capacitor C1 near the VIN as close as possible. Use a wide power ground plane 2.5 to connect the C1, C2, and Schottky diode to provide a low impedance path between the components for large and TDFN3x3-10 2 high slew rate current. 1.5 + VIN - 1 VIN BS EN 0.5 Compensation Network LX C1 L1 C3 + U1 C2 Load VOUT APW7337 COMP 0 0 25 50 75 100 R3 125 C5 Ambient Temperature, TA( oC) FB GND R1 R2 Feedback Divider Figure 2. Current Path Diagram Layout Consideration In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In general, interconnecting impedance should be minimized by using short, wide printed circuit traces. Signal and power grounds are to be kept separating and finally combined using the ground plane construction or single point grounding. Figure 3 illustrates the layout, with bold lines indicating high current paths. Components along the bold lines should be placed close together. Below is a checklist for your layout: Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 15 www.anpec.com.tw APW7337 Package Information TDFN3x3-10 D E A b Pin 1 A1 D2 A3 L K E2 Pin 1 Corner e TDFN3x3-10 S Y M B O L A MIN. MAX. MIN. MAX. 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 INCHES MILLIMETERS A3 0.20 REF 0.002 0.008 REF b 0.18 0.30 0.007 0.012 D 2.90 3.10 0.114 0.122 D2 2.20 2.70 0.087 0.106 0.122 0.069 E 2.90 3.10 0.114 E2 1.40 1.75 0.055 0.50 0.012 e 0.50 BSC L 0.30 K 0.20 0.020 BSC 0.020 0.008 Note : 1. Followed from JEDEC MO-229 VEED-5. Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 16 www.anpec.com.tw APW7337 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TDFN3x3-10 A H T1 C d D 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 4.0±0.10 8.0±0.10 W E1 12.0±0.30 1.75±0.10 F 5.5±0.05 (mm) Devices Per Unit Package Type Unit Quantity TDFN3x3-10 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 17 www.anpec.com.tw APW7337 Taping Direction Information TDFN3x3-10 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 18 www.anpec.com.tw APW7337 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 19 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7337 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Jul., 2013 20 www.anpec.com.tw