FEDL9484-01 Issue Date: Dec. 25, 2013 ML9484 Static, 1/2 Duty, 1/3 Duty, 1/4 Duty 50 Outputs LCD Driver GENERAL DESCRIPTION The ML9484 is an LCD driver LSI, consists of a 50-bit shift register, a 200-bit data latch, 50 sets of LCD drivers, and a common signal generation circuit. It can directly drive an LCD up to 50 segments for static display, 100 segments for 1/2-duty display, 150 segments for 1/3-duty display, and 200 segments for 1/4-duty display. FEATURES Logic power supply voltage : 2.7 to 5.5 V LCD drive power supply voltage : 4.5 to 5.5 V Maximum number of segments Static display : 50 segments 1/2-duty display : 100 segments 1/3-duty display : 150 segments 1/4-duty display : 200 segments Serially interfaces with the CPU using the three signal lines of DATA, CLOCK, and LOAD Selectable internal CR oscillator circuit or external clock input Built-in bias circuit Built-in common output intermediate-value voltage generation circuit Command-selectable A-waveform or B-waveform Package : 64-pin plastic TQFP 1/29 FEDL9484-01 ML9484 BLOCK DIAGRAM SEG1 SEG50 VLCD 50-Dot Segment Driver Bias Resi. 50-Ch Data Selector LOAD 50 50 50 50 50-Bit Latch4 50-Bit Latch3 50-Bit Latch2 50-Bit Latch1 LATCH SELECTOR 50 DATA CLOCK Command Decoder 50-bit Shift Register OSC I/E COM1 OSC OSC TIMING GENERATOR COMMON Driver COM2 COM3 COM4 RESETB TEST VDD GND 2/29 FEDL9484-01 ML9484 50 SEG50 49 SEG49 54 COM1 53 COM2 52 COM3 51 COM4 57 OSCI/E 56 VDD 55 VLCD 59 VSS 58 TEST 62 LOAD 61 RESETB 60 OSC 64 DATA 63 CLOCK PIN CONFIGURATION (TOP VIEW) SEG1 1 48 SEG48 SEG2 SEG3 2 47 SEG47 3 4 46 SEG46 45 SEG45 SEG5 SEG6 5 44 SEG44 6 43 SEG43 SEG7 7 42 SEG42 SEG4 SEG8 8 SEG9 9 SEG10 10 SEG11 11 41 SEG41 40 SEG40 39 SEG39 SEG31 31 SEG32 32 SEG29 29 SEG30 30 33 SEG33 SEG27 27 SEG28 28 SEG16 16 SEG25 25 SEG26 26 35 SEG35 34 SEG34 SEG23 23 SEG24 24 SEG14 14 SEG15 15 SEG21 21 SEG22 22 36 SEG36 SEG19 19 SEG20 20 SEG13 13 SEG17 17 SEG18 18 SEG12 12 38 SEG38 37 SEG37 64-Pin Plastic TQFP 3/29 FEDL9484-01 ML9484 ABSOLUTE MAXIMUM RATINGS Item Logic power supply voltage LCD drive power supply voltage Input voltage Output short-circuit current Power dissipation Storage temperature Symbol VDD VLCD VI Is PD TSTG Condition Ta = 25°C Ta = 25°C Ta = 25°C Ta = 25°C Ta ≦ 105°C — Rating -0.3 to 6.0 -0.3 to 6.0 – 0.3 to VDD + 0.3 -2.0 to +2.0 145 -55 to +150 Unit V V V mA mW °C Note: Do not use the ML9484 by short-circuiting one output pin to another output pin as well as to other pin (input pin, input/output pin, or power supply pin). RECOMMENDED OPERATION CONDITIONS Item Logic power supply voltage LCD drive power supply voltage OSC IN clock frequency Data clock frequency Operating temperature Symbol Condition Range Unit VDD* VLCD* fCP1 fCP2 Ta — — — — — 2.7 to 5.5 4.5 to 5.5 0.5 to 10 0.01 to 1.0 -40 to +105 V V kHz MHz °C Note(*): Use at VDD VLCD. 4/29 FEDL9484-01 ML9484 ELECTRICAL CHARACTERISTICS DC Characteristics Item Symbol "H" input voltage "L" input voltage Input leakage current 1 Input leakage current 2 Pull-up current VIH VIL IL1 IL2 Ipu Driver ON resistor Segment VOHS Common VOHC IDDS Static supply current ILCDS Dynamic supply current 1 Dynamic supply current 2 IDD1 ILCD1 IDD2 ILCD2 (VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta= -40 to +105°C) Applicable Condition Min. Typ. Max. Unit pin — 0.8VDD — VDD V (*1) — GND — 0.2VDD V (*1) VI = VDD or 0 V -1 — 1 μA (*2) VI = VDD -1 — 1 μA RESETB VDD = 5.0V,VI = 0 V 30 — 140 μA RESETB SEG1 to VLCD = 5V — 5 15 kΩ SEG50 COM 1 to VLCD = 5V — 5 12 kΩ COM4 VDD=VLCD=5.5 V 1 7 μA VDD — Input pin fixed to "H" or "L" Oscillation stopped, 9 15 μA VLCD — output no-load VDD=VLCD= 5.5 V (*3) 2 10 μA VDD — Clock OSC external input 9 15 μA VLCD — fCP1=1.8kHz VDD=VLCD= 5.5 V (*4) Internal oscillation=95Hz — 53 82 μA VDD — 9 15 μA VLCD (*1) : DATA, CLOCK, LOAD, RESETB, OSC, OSC I/E (*2) : DATA, CLOCK, LOAD, OSC, OSC I/E (*3) : 1/4-duty, 1/3-bias, OSCI/E=”L”, Output pin no-load. (*4) : 1/4-duty, 1/3-bias, OSCI/E=”H”, (F2, F, F0) = (0, 1, 1) 95 Hz, Output pin no-load. 5/29 FEDL9484-01 ML9484 Switching Characteristics OSC timing Item OSC IN clock frequency (External input) Clock pulse width (External input) Clock rise and fall time (External input) Internal clock frequency (Internal oscillation) (VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C) Condition Min. Typ. Max. Unit Applicable pin Symbol fCP1 tWCP1 Clock input from OSC. OSC I/E = "L" tOSC fOSC1 OSC open. (F2, F1, F0)=(0, 0, 1) OSC I/E = "H" 0.5 1.8 10 kHz OSC 40 — — μs OSC — — (*1) μs OSC 18 28.8 44 kHz OSC The relation between OSC IN clock frequency and frame frequency is as the equation below. fFRM = fCP1 /24 (*1) tOSC is a reference value. The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value. Make the rise as steep as possible. Reference value: max=2μs. Serial interface timing Item Data clock frequency Data clock pulse width Data setup time Data hold time CLOCK-LOAD timing LOAD-CLOCK timing LOAD pulse width Symbol fCP2 tWCP2 tSU tHD tCL tLC tWLD Signal rise and fall time tsr,tsf (VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C) Condition Min. Typ. Max. Unit Applicable pin 0.01 — 1 MHz CLOCK 100 — — ns CLOCK 50 — — ns DATA 50 — — ns CLOCK 100 — — ns CLOCK 100 — — ns LOAD 100 — — ns LOAD CLOCK,DATA, — — (*2) ns LOAD (*2) tsr and tsf shall be reference values. The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value. Make the rise as steep as possible. Reference value: max=10ns. 6/29 FEDL9484-01 ML9484 Timing chart (OSC) 1/fCP1 tWCP1 VIH OSC (External clock) tWCP1 VIH VIH VIL VIL tOSC Timing chart (Serial interface) VIH DATA VIL tSU V IH VIL V IL tsf tWCP2 tsr VIH VIH V IL V IL tHD tWCP2 CLOCK VIH V IH V IL V IH VIH V IL V IL VIL 1/f CP2 tCL LOAD tWLD t LC tsr tsf V IH VIH V IL V IL tsr tsf 7/29 FEDL9484-01 ML9484 POWER ON/OFF TIMING To turn on the power supply, raise the logic power supply first, then LCD drive power supply in order to prevent the IC from malfunctioning. To fall the power supply, fall the LCD drive power supply first, then the logic power supply. For a VDD pin ranging from 0 V to VDDmin, set VDD ≥ VLCD and t1 ≥ 0 [ns]. Voltage VLCD VDD t1 t1 Time INITIALIZATION SIGNAL TIMING Keep the RESETB pin at "L" level until the VDD reaches VDD min. VDD (t2 ≥ 200[ns]) VDD min RESETB VIL t2 The value of the current of the pull-up resistor is specified for RESETB pin. The customer needs to select an external capacitor that meets the timing requirements shown above. 8/29 FEDL9484-01 ML9484 PIN DESCRIPTIONS Pad number Symbol I/O 55 SEG1 to SEG50 COM1 to COM4 VLCD 56 VDD - 57 OSC I/E I 58 TEST I 59 GND - 60 OSC I 61 RESETB I 62 LOAD I 63 CLOCK I 64 DATA I 1 to 50 51 to 54 O O - Description Outputs for LCD display. Connected to the segment pins on the LCD panel. In the display off mode, all the outputs are fixed to GND. Outputs for LCD display. Connected to the common pins on the LCD panel. In the display off mode, all the outputs are fixed to GND. Power supply pin for LCD driver. Power supply pin for logic circuit. This input selects whether to use the external clock input mode or to use the Internal oscillation mode. It has a schmitt circuit. When this pin is "H", the mode is the Internal Rf oscillation mode. When this pin is "L", the mode is the external clock input mode. IC test pin. Has a pull-down resistor built-in. Use it as it is connected to GND. Ground pin. Pin for oscillation. Has a Schmitt circuit built-in. Internal Rf oscillation mode: Set the OSCI/E pin to "H", open the OSC pin. External clock input mode: Set the OSCI/E pin to "L", input the external clock to the OSC pin. Reset signal input pin for initializing inside the IC. It has a schmitt circuit. The "L" level enables the reset. This pin has an Internal pull-up resistor. The power-on reset operation is available by connecting an external capacitor. *1 Input pin for the load signal of display data. It has a schmitt circuit. The display data in the shift register is transmitted as is to the segment driver for the "H" duration. When this pin is brought into "L", the shift register is disconnected from the segment driver. The display data in the shift register immediately before it become "L" is held in the data latch and transmitted to the segment driver. Shift clock input pin for display data. It has a schmitt circuit. The display data input to the DATA pin is serially input to the shift register at the CLOCK signal rise. Display data input pin. It has a schmitt circuit. Input the display data in the order of SEG50, SEG49, ... , SEG2, and SEG1. The display data turns on at "H" and turns off at "L". *1: Reset circuit configuration VDD CRST RESETB 9/29 FEDL9484-01 ML9484 DESCRIPTION Operation description • Display data input As described in the Data configuration section, the display data consists of the data field that corresponds to each segment on/off and the command field that indicates the display data input. When inputting the display data, the "F1" command is set in the command field. When the "F2" to "F5" command is set in the command field, the display data in the data field becomes invalid. The data input to the DATA pin is loaded to the shift register at the CLOCK pulse rise, transferred to the display data latch during the LOAD pulse at the "H" level, then output via the segment driver. CLOCK DATA D1 D2 D3 D4 D48 D49 D50 C0 C1 C2 C3 C4 C5 Command field Data field LOAD Display output Old data New data • Display on, Display off The display becomes off at power-on reset. To display, write the display on command. The display off is the command that makes all segments off. Writing the display off command turns off the lights regardless of the display data. The display on is the command to release the display off. Writing the display on command returns the display to the original state. CLOCK DATA D1 D2 C4 C5 C2 C3 C4 C5 C2 C3 C4 C5 LOAD Display ON/OFF RESETB Display data input Write display ON Write Display OFF command command 10/29 FEDL9484-01 ML9484 List of Commands Command name F0 C5 C4 C3 C2 C1 C0 Operation 0 0 0 x x x Disabled 1 0 0 D1 (0) D0 (0) x 1 0 1 DSP (0) x x F6 1 1 0 x x x Data write address setting (Co1,Co0)=(0, 0): Corresponding to common 1 (Co1,Co0)=(0, 1): Corresponding to common 2 (Co1,Co0)=(1, 0): Corresponding to common 3 (Co1,Co0)=(1, 1): Corresponding to common 4 Frame frequency setting (F2, F1, F0)=(0, 0, 0): 65Hz (F2, F1, F0)=(0, 0, 1): 75Hz (F2, F1, F0)=(0, 1, 0): 85Hz (F2, F1, F0)=(0, 1, 1): 95Hz (F2, F1, F0)=(1, 0, 0): 130Hz (F2, F1, F0)=(1, 0, 1): 150Hz (F2, F1, F0)=(1, 1, 0): 170Hz (F2, F1, F0)=(1, 1, 1): 190Hz (valid for Internal CR oscillation) LCD Bias setting BIAS="0" : 1/3-bias BIAS="1" : 1/2-bias LCD Driving Waveform setting WSEL="0" : A-Waveform WSEL="1" : B-Waveform Display Duty setting (D1, D0)=(0, 0): Static (COM1=COM2=COM3=COM4) (D1, D0)=(0, 1): 1/2-duty (COM1=COM3, COM2=COM4) (D1, D0)=(1, 0): 1/3-duty (COM2=COM4) (D1, D0)=(1, 1): 1/4-duty Display on/off setting DSP="0" : Off （COM=SEG=GND） DSP="1" : On Disabled F7 1 1 1 x x x Disabled F1 F2 F3 F4 F5 0 0 1 Co1 Co0 x 0 1 0 F2 (0) F1 (0) F0 (0) 0 1 1 BIAS (0) WSEL x (0) x: Don't care ( ): Reset Value 11/29 FEDL9484-01 ML9484 Data configuration [Input data] First bit Corresponding to SEG50 Corresponding to SEG1 C5 C4 C3 C2 Command C1 C0 D50 D49 D48 D3 D2 D1 LCD display data Note 1 : The commands F4 settings become valid when the least four bits of C2 to C5 are input. (The bits from D1 to D50 and from C0 to C1 are not necessary.) The commands F3 and F4 settings become valid when the least five bits of C1 to C5 are input. (The bits from D1 to D50 and from C0 are not necessary.) The commands F2 settings become valid when the least six bits of C0 to C5 are input. (The bits from D1 to D50 are not necessary.) Note 2 : If the dummy bit is needed for the reason of number of transfer bits, put it on the first bit side. Note 3 : The command execution follows the contents of the C5 to C0 registers immediately before the LOAD becomes "H". 12/29 FEDL9484-01 ML9484 LCD Driving Waveform • Static mode (same as A-waveform and B-waveform) S E G 1 COM1 S E G 2 S E G 3 ON OFF fFRM COM1 COM2 COM3 COM4 VLCD 2VLCD/3 VLCD/3 GND VLCD SEG1 2VLCD/3 VLCD/3 GND SEG2 VLCD 2VLCD/3 VLCD/3 GND SEG3 VLCD 2VLCD/3 VLCD/3 GND 13/29 FEDL9484-01 ML9484 • 1/2-duty, 1/2-bias mode (A-waveform) S E G 1 S E G 2 S E G 3 COM1 ON COM2 OFF fFRM VLCD COM1 COM3 VLCD/2 GND COM2 COM4 VLCD VLCD/2 GND VLCD SEG1 VLCD/2 GND VLCD SEG2 VLCD/2 GND VLCD SEG3 VLCD/2 GND 14/29 FEDL9484-01 ML9484 • 1/2-duty, 1/3-bias mode (A-waveform) S E G 1 S E G 2 S E G 3 COM1 ON COM2 OFF fFRM VLCD COM1 COM3 2VLCD/3 VLCD/3 GND VLCD COM2 COM4 2VLCD/3 VLCD/3 GND VLCD SEG1 2VLCD/3 VLCD/3 GND VLCD SEG2 2VLCD/3 VLCD/3 GND VLCD SEG3 2VLCD/3 VLCD/3 GND 15/29 FEDL9484-01 ML9484 • 1/3-duty, 1/2-bias mode (A-waveform) S E G 1 S E G 2 S E G 3 COM1 ON COM2 OFF COM3 fFRM VLCD COM1 VLCD/2 GND VLCD COM2 COM4 VLCD/2 GND VLCD COM3 VLCD/2 GND VLCD SEG1 VLCD/2 GND VLCD SEG2 VLCD/2 GND VLCD SEG３ VLCD/2 GND 16/29 FEDL9484-01 ML9484 • 1/3-duty, 1/3-bias mode (A-waveform) S E G 1 S E G 2 S E G 3 COM1 ON COM2 OFF COM3 fFRM VLCD COM1 2VLCD/3 VLCD/3 GND VLCD COM2 COM4 2VLCD/3 VLCD/3 GND VLCD COM3 2VLCD/3 VLCD/3 GND VLCD SEG1 2VLCD/3 VLCD/3 GND VLCD SEG2 2VLCD/3 VLCD/3 GND VLCD SEG３ 2VLCD/3 VLCD/3 GND 17/29 FEDL9484-01 ML9484 • 1/4-duty, 1/2-bias mode (A-waveform) S E G 1 S E G 2 S E G 3 COM1 COM2 ON COM3 OFF COM4 fFRM VLCD COM1 VLCD/2 GND VLCD COM2 VLCD/2 GND VLCD COM3 VLCD/2 GND VLCD COM4 VLCD/2 GND VLCD SEG1 VLCD/2 GND VLCD SEG2 VLCD/2 GND VLCD SEG3 VLCD/2 GND 18/29 FEDL9484-01 ML9484 • 1/4-duty, 1/3-bias mode (A-waveform) S E G 1 S E G 2 S E G 3 COM1 COM2 ＯＮ COM3 OFF COM4 fFRM VLCD COM1 2VLCD/3 VLCD/3 GND VLCD COM2 2VLCD/3 VLCD/3 GND VLCD COM3 2VLCD/3 VLCD/3 GND VLCD COM4 2VLCD/3 VLCD/3 GND VLCD SEG1 2VLCD/3 VLCD/3 GND VLCD SEG2 2VLCD/3 VLCD/3 GND VLCD SEG3 2VLCD/3 VLCD/3 GND 19/29 FEDL9484-01 ML9484 • 1/2-duty, 1/2-bias mode (B-waveform) S E G 1 S E G 2 S E G 3 COM1 ON COM2 OFF fFRM VLCD COM1 COM3 VLCD/2 GND COM2 COM4 VLCD VLCD/2 GND VLCD SEG1 VLCD/2 GND VLCD SEG2 VLCD/2 GND VLCD SEG3 VLCD/2 GND 20/29 FEDL9484-01 ML9484 • 1/2-duty, 1/3-bias mode (B-waveform) S E G 1 S E G 2 S E G 3 COM1 ON COM2 OFF fFRM VLCD COM1 COM3 2VLCD/3 VLCD/3 GND VLCD COM2 COM4 2VLCD/3 VLCD/3 GND VLCD SEG1 2VLCD/3 VLCD/3 GND VLCD SEG2 2VLCD/3 VLCD/3 GND VLCD SEG3 2VLCD/3 VLCD/3 GND 21/29 FEDL9484-01 ML9484 • 1/3-duty, 1/2-bias mode (B-waveform) S E G 1 S E G 2 S E G 3 COM1 ON COM2 OFF COM3 fFRM VLCD COM1 VLCD/2 GND VLCD COM2 COM4 VLCD/2 GND VLCD COM3 VLCD/2 GND VLCD SEG1 VLCD/2 GND VLCD SEG2 VLCD/2 GND VLCD SEG３ VLCD/2 GND 22/29 FEDL9484-01 ML9484 • 1/3-duty, 1/3-bias mode (B-waveform) S E G 1 S E G 2 S E G 3 COM1 ON COM2 OFF COM3 fFRM VLCD COM1 2VLCD/3 VLCD/3 GND VLCD COM2 COM4 2VLCD/3 VLCD/3 GND VLCD COM3 2VLCD/3 VLCD/3 GND VLCD SEG1 2VLCD/3 VLCD/3 GND VLCD SEG2 2VLCD/3 VLCD/3 GND VLCD SEG３ 2VLCD/3 VLCD/3 GND 23/29 FEDL9484-01 ML9484 • 1/4-duty, 1/2-bias mode (B-waveform) S E G 1 S E G 2 S E G 3 COM1 COM2 ON COM3 OFF COM4 fFRM VLCD COM1 VLCD/2 GND VLCD COM2 VLCD/2 GND VLCD COM3 VLCD/2 GND VLCD COM4 VLCD/2 GND VLCD SEG1 VLCD/2 GND VLCD SEG2 VLCD/2 GND VLCD SEG3 VLCD/2 GND 24/29 FEDL9484-01 ML9484 • 1/4-duty, 1/3-bias mode (B-waveform) S E G 1 S E G 2 S E G 3 COM1 COM2 ＯＮ COM3 OFF COM4 fFRM VLCD COM1 2VLCD/3 VLCD/3 GND VLCD COM2 2VLCD/3 VLCD/3 GND VLCD COM3 2VLCD/3 VLCD/3 GND VLCD COM4 2VLCD/3 VLCD/3 GND VLCD SEG1 2VLCD/3 VLCD/3 GND VLCD SEG2 2VLCD/3 VLCD/3 GND VLCD SEG3 2VLCD/3 VLCD/3 GND 25/29 FEDL9484-01 ML9484 EXAMPLE OF APPLICATION CIRCUIT COM1 COM2 1/4 Duty LCD Panel COM3 COM4 SEG1 SEG50 SEG1 SEG50 COM1 COM2 COM3 LOAD DATA CPU CLOCK ML9484 COM4 VLCD +5 V VDD +5 V OSCI/E Open OSC RESETB GND TEST REFRESH Although the ML9484 holds operation state by commands, excessive external noise might change the internal state. On a chip-mounting and system level, it is necessary to take countermeasures against preventing noise from occurring. It is recommended to use the refresh sequence periodically to control sudden noise. 26/29 FEDL9484-01 ML9484 PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 27/29 FEDL9484-01 ML9484 REVISION HISTORY Page Document No. Issue Date Previous Edition New Edition FEDL9484-01 Dec .25, 2013 – – Description Final edition 1 issued 28/29 FEDL9484-01 ML9484 NOTES No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. 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