TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES PRODUCT MAY BE MADE OBSOLETE WITHOUT NOTICE 128K x 8 SRAM MSM8128 - 70/85/10/12 Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997 Description The MSM8128 is a 1Mbit monolithic SRAM organised as 128K x 8. It is currently available in a VIL Package, with access times of 70, 85, 100, 120ns. It has a low power standby version and has 3.0V battery backup capability. It is directly TTL compatible and has common data inputs and outputs. Two pinout variants (single and dual CS) are available. All versions may be screened in accordance with MIL-STD-883. 131,072 x 8 CMOS Static RAM Features Access Times of 70/85/100/120 ns JEDEC standard Dual CS footprints. Operating Power 550 mW (max) Low Power Standby (-L) 2.2 mW (max) Low Voltage Data Retention. Completely Static Operation Directly TTL compatible. May be processed in accordance with MIL-STD-883 Block Diagram Pin Definition NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND MEMORY ARRAY 512 X 2048 Package Details Pin Count Description 32 0.1" Vertical-in-LIne (VILTM) Package details on pages 8 & 9. Issue 4.5: April 2001 Package Type V 1 2 3 4 5 6 7 8 TOP VIEW S,V 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 See Page 9 for VX Pin Functions A0-A16 Address Inputs D0-7 Data Input/Output CS1 Chip Select 1 CS2 Chip Select 2 OE Output Enable WE Write Enable NC No Connect VCC Power (+5V) GND Ground VCC A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 D7 D6 D5 D4 D3 MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 DC OPERATING CONDITIONS Absolute Maximum Ratings Voltage on any pin relative to VSS Power Dissipation Storage Temperature Notes : VT PT TSTG -0.5V to 1 to -55 +7.0 V W o C +150 (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Supply Voltage Input High Voltage Input Low Voltage Operating Temperature VCC VIH VIL TA TAI TAM min typ max 4.5 2.2 -0.3 0 -40 -55 5.0 - 5.5 5.8 0.8 70 85 125 V V V o C o C (I suffix) o C (M, MB suffix) DC Electrical Characteristics (VCC = 5.0V±10%, TA=-55°C to +125°C) Parameter Symbol Test Condition Input Leakage Current Output Leakage Current Average Supply Current Standby Supply Current -L Part ILI Il/O ICC1 ISB1 ISB2 VIH=0V to Vcc Output Voltage VOL VOH IOL = 2.1 mA CS1=VIH, CS2 =VIL, VI/O=0V to Vcc ,OE=VIH Min. Cycle, VIN=VIL or VIH CS1=VIH,CS2 = VIL , I/P's static CS1≥VCC-0.2V, 0.2V≥CS2≥VCC-0.2V , VIN ≥0.2V IOH = -1.0 mA min typ -2 -2 - - 2 2 110 4 450 µA µA mA mA uA 2.4 - 0.4 - V V Capacitance (VCC=5V±10%,TA=25oC) Parameter I/P Capacitance I/O Capacitance Symbol Test Condition typ max Unit CIN CI/O VIN=0V VI/O=0V - 9 11 pF pF Note: This parameter is not 100% tested. max Unit MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 Operating Modes The table below shows the logic inputs required to control the MSM8128 SRAM. Mode CS1 CS2 OE Not Selected 1 X X Not Selected X 0 Output Disable 0 Read Write VCC Current I/O Pin Reference Cycle X ISB1,ISB2 High Z Power Down X X ISB,ISB1 High Z Power Down 1 1 1 ICC High Z 0 1 0 1 ICC DOUT Read Cycle 0 1 X 0 ICC DIN Write Cycle 1 = VIH, WE 0 = VIL, X = Don't Care Low Vcc Data Retention Characteristics - L Version Only (TA=-55°C to +125oC) Parameter VCC for Data Retention Symbol Test Condition VDR ICCDR max 2.0 - - 0 5 - 660 - Unit V VCC=3.0V,VIN ≥0V, CS1 ≥VCC-0.2V, CS2≥VCC-0.2V or 0V≤ CS2 ≤ 0.2V. Chip Deselect to Data Retention tCDR Operation Recovery Time tR typ CS1≥ VCC-0.2V, CS2≥VCC-0.2V or 0V≤CS2≤ 0.2V. VIN≥0V Data Retention Current min See Retention Waveform See Retention Waveform µA ns ms Notes (1) CS2 controls address buffer, WE buffer, CS1 buffer and OE buffer. If CS2 controls data retention mode, Vin levels (WE,OE,CS1,I/O) can be in the high impedance state. If CS1 controls Data Retention mode, CS2 must be≥VCC - 0.2V or 0V ≤ CS2≤ 0.2V. The other input levels (address, WE,OE,I/O) can be in the high impedance state. AC Test Conditions Output Load I/O Pin * Input pulse levels: 0V to 3.0V * Input rise and fall times: 5ns * Input and Output timing reference levels: 1.5V * Output load: See Load Diagram * Vcc=5V±10% 166 Ω 1.76V 30pF ! MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 AC OPERATING CONDITIONS Read Cycle Parameter Read Cycle Time Address Access Time Chip Select (CS1) Access Time(2) Chip Select (CS2) Access Time(2) Output Enable to Output Valid Output Hold from Address Change Chip Selection (CS1) to Output in Low Z Chip Selection (CS2) to Output in Low Z Output Enable to Output in Low Z Chip Disable (CS1) to Output in High Z(3) Chip Disable (CS2) to Output in High Z(3) Output Disable to Output in High Z(3) Symbol min tRC tAA tACS1 tACS2 tOE tOH tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ 70 5 10 10 5 0 0 0 Symbol min 70 max 70 70 70 35 35 35 30 min 85 5 10 10 5 0 0 0 85 max 85 85 85 45 35 35 30 min 10 max min 12 max 100 10 10 10 5 0 0 0 100 100 100 50 35 35 35 120 10 10 10 5 0 0 0 120 120 120 60 45 45 45 min 10 max Unit ns ns ns ns ns ns ns ns ns ns ns ns Write Cycle Parameter Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time (WE, CS1) (CS2) Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write tWC tCW tAW tAS tWP tWR1 tWR2 tWHZ tDW tDH tOW 70 max 70 60 60 0 50 5 5 0 30 0 5 " 30 - min 85 75 75 0 60 5 5 0 35 0 5 85 max 30 - 100 85 85 0 70 5 5 0 40 0 5 35 - 12 min max 120 100 100 0 70 5 5 0 45 0 5 40 - Unit ns ns ns ns ns ns ns ns ns ns ns MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 Read Cycle Timing Waveform (1,2 ) t RC Address t AA OE t OE t OH t OLZ CS1 t CLZ1 t ACS1 (2) t CHZ1 (3) CS2 t ACS2 (2) t t OHZ (3) CLZ2 Data Valid Dout t CHZ2 (3) Notes: (1) WE is High for Read Cycle. (2) Address valid prior to or coincident with CS1 transition low or CS2 high. (3) tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. At any given temperature and voltage condition, tCHZ max is less than tCLZ min both for a given device and from device to device. This parameter is sampled and not 100% tested. # MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 Write Cycle No.1 Timing Waveform t WC Address tWR1,2 (2) t AW t AS (3) (6) CS1 t CW (4) (6) CS2 OE WE t OHZ(3,9) t WP(1) High - Z Dout t DH t DW Data Valid Din Write Cycle No.2 Timing Waveform (5) t WC Address t AW t WR1,2 (2) (6) CS1 t CW (4) CS2 (6) t AS (3) t WP (1) t OH WE t OW t WHZ(3,9) (8) High - Z Dout t DW High - Z Data Valid Din $ t DH (7) MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 Low VCC Data Retention Timing Waveform 1 (CS1 controlled) Vcc DATA RETENTION MODE 4.5V 4.5V t CDR tR 2.2V 2.2V V DR CS1 CS1≥Vcc-0.2V 0V Low VCC Data Retention Timing Waveform 2 (CS2 controlled) Vcc DATA RETENTION MODE 4.5V tR tCDR 4.5V CS2 V DR2 0.4V CS2 ≤ 0.2V 0V AC Characteristics Notes (1) A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 going low, CS2 going high and WE going low. A write ends at the earliest transition among CS1 going high, CS2 going low and WE going high. tWP is measured from the beginning of write to the end of write. (2) tWR is measured from the earlier of CS1 or WE going high or CS2 going high to the end of write cycle. (3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied. (4) If CS1 goes low simultaneously with WE going low or after WE going low, outputs remain in high impedance state. (5) OE is continuously low. (OE=VIL) (6) Dout is in the same phase as written data of this write cycle. (7) Dout is the read data of next address. (8) If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Input signals out of phase must not be applied to I/O pins. (9) tWHZ is defined as the time at which the outputs achieve the open circuit conditions and is not referenced to output voltage levels. These parameters are sampled and not 100% tested. % MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 Package Details 32 pin 0.1" Vertical-in-Line (VILTM) - 'V' Package 40.26 (1.585) 2.67 (0.105) 10.41 (0.410) 3.18 (0.125) 11.43 (0.450) 41.02 (1.615) 4.00 (0.157) 3.00 (0.117) 1.54 (0.060) 2.67 (0.105) 0.51 (0.020) 1.02 (0.040) 2.41 (0.095) 0.41 (0.016) 2.54 (0.100) All dimensions in mm (inches). & MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 Alternate Pin Definition NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 TOP VIEW VX,SX 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 NC WE A13 A8 A9 A11 OE A10 CS D7 D6 D5 D4 D3 Military Screening Procedure Component Screening Flow for high reliability product is in accordance with Mil-883 method 5004 MB COMPONENT SCREENING FLOW SCREEN TEST METHOD LEVEL Visual and Mechanical Internal visual Temperature cycle Constant acceleration Pre-Burn-in electrical Burn-in 2010 Condition B or manufacturers equivalent 1010 Condition C (10 Cycles,-65oC to +150oC) 2001 Condition E (Y, only) (30,000g) Per applicable device specifications at TA=+25oC Method 1015,Condition D,TA=+125oC,160hrs min Final Electrical Tests Per applicable Device Specification Static (dc) a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes 100% 100% Functional a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes 100% 100% Switching (ac) a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes 100% 100% Percent Defective allowable (PDA) Calculated at post-burn-in at TA=+25oC 5% Hermeticity 1014 Fine Gross Condition A Condition C 100% 100% External Visual 2009 Per vendor or customer specification 100% ' 100% 100% 100% 100% 100% MSM8128 - 70/85/10/12 Issue 4.5 : April 2001 Ordering Information MSM8128VLMB - 70 Speed 70 85 10 12 = = = = 70 ns 85 ns 100 ns 120 ns Temp. range/screening Blank I M MB = = = = Commercial Industrial Military Screened in accordance with MIL-STD-883. Power Consumption Blank = Standard Power L = Low Power Package V = 32 pin 0.1" VIL VX = 32 pin 0.6" VIL (Single CS Organisation 8128 = 128K x 8 SRAM THE ABOVE PARTS ARE NOT RECOMMENDED FOR NEW DESIGNS AND MAY BE MADE OBSOLETE WITHOUT NOTICE. Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subjected to a constant process of development. Data may be changed at any time without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director.