CY29948 2.5 V or 3.3 V, 200-MHz, 1:12 Clock Distribution Buffer 2.5 V or 3.3 V, 200-MHz, 1:12 Clock Distribution Buffer Features Description ■ 2.5 V or 3.3 V operation ■ 200-MHz clock support ■ LVPECL or LVCMOS/LVTTL clock input ■ LVCMOS-/LVTTL-compatible inputs ■ 12 clock outputs: drive up to 24 clock lines ■ Synchronous Output Enable ■ Output three-state control ■ 150 ps typical output-to-output skew ■ Pin compatible with MPC948, MPC948L, MPC9448 ■ Available in Commercial and Industrial temp. range ■ 32-pin TQFP package The CY29948 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The 12 outputs are LVCMOS or LVTTL compatible and can drive 50 series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:24. The outputs can also be three-stated via the three-state input TS#. Low output-to-output skews make the CY29948 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. The CY29948 also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. Block Diagram VDD PECL_CLK PECL_CLK# 0 TCLK 1 VDDC 12 Q0-Q11 TCLK_SEL SYNC_OE TS# Cypress Semiconductor Corporation Document Number: 38-07288 Rev. *E • VSS Q0 VDDC Q1 VSS Q2 VDDC Q3 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 VSS Q9 VDDC Q8 VSS CY29948 Q11 1 2 3 4 5 6 7 8 VDDC Q10 TCLK_SEL TCLK PECL_CLK PECL_CLK# SYNC_OE TS# VDD VSS 32 Pin Configuration 198 Champion Court 24 23 22 21 20 19 18 17 • VSS Q4 VDDC Q5 VSS Q6 VDDC Q7 San Jose, CA 95134-1709 • 408-943-2600 Revised May 2, 2011 [+] Feedback CY29948 Pin Description[1] Pin Name PWR I/O Description 3 PECL_CLK – I, PU PECL Input Clock 4 PECL_CLK# – I, PD PECL Input Clock I, PU External Reference/Test Clock Input 2 TCLK – 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 Q(11:0) VDDC 1 TCLK_SEL – I, PU Clock Select Input. When LOW, PECL clock is selected. When HIGH TCLK is selected. 5 SYNC_OE – I, PU Output Enable Input. When asserted HIGH, the outputs are enabled. When set LOW the outputs are disabled in a LOW state. 6 TS# – I, PU Three-state Control Input. When asserted LOW, the output buffers are three-stated. When set HIGH, the output buffers are enabled. 10, 14, 18, 22, 26, 30 VDDC – – 7 VDD – – 2.5 V or 3.3 V Power Supply 8, 12, 16, 20, 24, 28, 32 VSS – – Common Ground O Clock Outputs 2.5 V or 3.3 V Power Supply for Output Clock Buffers Output Enable/Disable The CY29948 features a control input to enable or disable the outputs. This data is latched on the falling edge of the input clock. When SYNC_OE is asserted LOW, the outputs are disabled in a LOW state. When SYNC_OE is set HIGH, the outputs are enabled as shown in Figure 1. Figure 1. SYNC_OE Timing Diagram TCLK SYNC_OE Q Note 1. PD = Internal pull-down, PU = Internal pull-up. Document Number: 38-07288 Rev. *E Page 2 of 10 [+] Feedback CY29948 Maximum Ratings[2] Maximum Input Voltage Relative to VSS ............. VSS – 0.3 V Maximum Input Voltage Relative to VDD............. VDD + 0.3 V Storage Temperature ............................... –65 °C to + 150 °C Operating Temperature............................... –40 °C to +85 °C Maximum ESD protection............................................... 2 kV Maximum Power Supply................................................ 5.5 V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Maximum Input Current ............................................. ±20 mA DC Parameters VDD = VDDC = 3.3 V ± 10% or 2.5 V ± 5%, over the specified temperature range. Parameter VIL VIH Description Input Low Voltage Input High Voltage Conditions Min Typ Max Unit VDD = 3.3 V, PECL_CLK single ended 1.49 – 1.825 V VDD = 2.5 V, PECL_CLK single ended 1.10 – 1.45 All other inputs VSS – 0.8 VDD = 3.3 V, PECL_CLK single ended 2.135 – 2.42 VDD = 2.5 V, PECL_CLK single ended 1.75 – 2.0 All other inputs V 2.0 – VDD IIL Input Low Current[3] – – –100 IIH Input High Current[3] – – 100 VPP Peak-to-Peak Input Voltage PECL_CLK 300 – 1000 mV VCMR Common Mode Range[4] PECL_CLK VDD = 3.3 V VDD – 2.0 – VDD – 0.6 V VDD = 2.5 V VDD – 1.2 – VDD – 0.6 Voltage[5] VOL Output Low VOH Output High Voltage[5] IDDQ Quiescent Supply Current IDD Dynamic Supply Current Zout Cin Output Impedance Input Capacitance IOL = 20 mA µA – – 0.4 V IOH = –20 mA, VDD = 3.3 V 2.5 – – V IOH = –20 mA, VDD = 2.5 V 1.8 – – – 5 7 mA VDD = 3.3 V, Outputs @ 100 MHz, CL = 30 pF – 180 – mA VDD = 3.3 V, Outputs @ 160 MHz, CL = 30 pF – 270 – VDD = 2.5 V, Outputs @ 100 MHz, CL = 30 pF – 125 – VDD = 2.5 V, Outputs @ 160 MHz, CL = 30 pF – 190 – VDD = 3.3 V 12 15 18 VDD = 2.5 V 14 18 22 – 4 – pF Notes 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. 5. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines. Document Number: 38-07288 Rev. *E Page 3 of 10 [+] Feedback CY29948 AC Parameters[6] VDD = VDDC = 3.3 V ± 10% or 2.5 V ± 5%, over the specified operating range. Parameter Fmax Tpd Description Input Frequency Conditions [7] PECL_CLK to Q Delay [7] Min Typ Max Unit VDD = 3.3 V – – 200 MHz VDD = 2.5 V – – 170 VDD = 3.3 V TCLK to Q Delay[7] PECL_CLK to Q Delay[7] VDD = 2.5 V [7] TCLK to Q Delay Cycle[7, 8, 9] – 8.0 – 8.9 6.0 – 10.0 6.4 – 10.9 ns FoutDC Output Duty 45 – 55 % tpZL, tpZH Output Enable Time (all outputs) 2 – 10 ns tpLZ, tpHZ Output Disable Time (all outputs) 2 – 10 ns – 150 250 ps ns Tskew Tskew(pp) Ts Th Tr/Tf Output-to-Output Part-to-Part Skew[7, 9] Skew[10] Set-up Time[7, 11] Hold Measured at VDD/2 4.0 4.4 Time[7, 11] Output Clocks Rise/Fall Time[9] PECL_CLK to Q – – 1.5 TCLK to Q – – 2.0 SYNC_OE to PECL_CLK 1.0 – – SYNC_OE to TCLK 0.0 – – PECL_CLK to SYNC_OE 0.0 – – TCLK to SYNC_OE 1.0 – – 0.8 V to 2.0 V, VDD = 3.3 V 0.20 – 1.0 0.6 V to 1.8 V, VDD = 2.5 V 0.20 – 1.3 ns ns ns Figure 2. LVCMOS_CLK CY29948 Test Reference for VCC = 3.3 V and VCC = 2.5 V CY29948 DUT Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm R T = 50 ohm VTT R T = 50 ohm VTT Notes 6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 7. Outputs driving 50 transmission lines. 8. 50% input duty cycle. 9. See Figure 2 and Figure 3 on page 5. 10. Part-to-Part skew at a given temperature and voltage. 11. Setup and hold times are relative to the falling edge of the input clock. Document Number: 38-07288 Rev. *E Page 4 of 10 [+] Feedback CY29948 Figure 3. PECL_CLK CY29948 Test Reference for VCC = 3.3 V and VCC = 2.5 V CY29948 DUT Zo = 50 ohm Differential Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm R T = 50 ohm VTT R T = 50 ohm VTT Figure 4. Propagation Delay (tPD) Test Reference PEC L_C LK V CMR VPP PEC L_C LK VCC Q V C C /2 t PD GND Figure 5. LVCMOS Propagation Delay (tPD) Test Reference VCC LVCMOS_CLK VCC /2 GND VCC Q VCC /2 t PD GND Figure 6. Output Duty Cycle (FoutDC) VCC VCC /2 tP GND T0 DC = tP / T0 x 100% Document Number: 38-07288 Rev. *E Page 5 of 10 [+] Feedback CY29948 Figure 7. Output-to-Output Skew tsk(0) VCC VCC /2 GND VCC VCC /2 t SK(0) GND Ordering Information Part Number Package Type Production Flow CY29948AC 32-pin TQFP Commercial, 0 °C to +70 °C CY29948ACT 32-pin TQFP - Tape and Reel Commercial, 0 °C to +70 °C Pb-free CY29948AXC 32-pin TQFP Commercial, 0 °C to +70 °C CY29948AXCT 32-pin TQFP - Tape and Reel Commercial, 0 °C to +70 °C CY29948AXI 32-pin TQFP Industrial, –40 °C to +85 °C CY29948AXIT 32-pin TQFP - Tape and Reel Industrial, –40 °C to +85 °C Ordering Code Definitions CY 29948 A X X T T = Tape and Reel; blank = Tube Temperature: X = C or I C = Commercial; I = Industrial X = Pb-free Package: A = 32-pin TQFP Device part number Company ID: CY = Cypress Document Number: 38-07288 Rev. *E Page 6 of 10 [+] Feedback CY29948 Package Drawing and Dimensions 51-85063 *C Document Number: 38-07288 Rev. *E Page 7 of 10 [+] Feedback CY29948 Acronyms Document Conventions Acronym Description CMOS complementary metal oxide semiconductor ESD electrostatic Discharge I/O input/output LVCMOS low voltage complementary metal oxide semiconductor LVPECL Units of Measure Symbol °C Unit of Measure degree Celsius kV kilo Volts MHz Mega Hertz low voltage positive emitter coupled logic µA micro Amperes LVTTL low voltage transistor-transistor logic mA milli Amperes PLL phase locked loop mm milli meter thin quad flat pack mV milli Volts ns nano seconds ohms TQFP Document Number: 38-07288 Rev. *E % percent pF pico Farad ps pico seconds V Volts Page 8 of 10 [+] Feedback CY29948 Document Revision History Document Title: CY29948, 2.5 V or 3.3 V, 200-MHz, 1:12 Clock Distribution Buffer Document Number: 38-07288 Rev. ECN No. Submission Date Orig. of Change ** 111099 02/13/02 BRK *A 116782 08/14/02 HWT *B 122880 12/22/02 RBI *C 428221 See ECN RGL Added Lead-free devices *D 2904731 04/05/10 CXQ Removed inactive part numbers - CY29948AI and CY29948AIT. Updated package diagram. *E 3246222 05/02/2011 CXQ Added Ordering Code Definitions. Added Acronyms and Units of Measure. Updated in new template. Document Number: 38-07288 Rev. *E Description of Change New datasheet Added Commercial Temperature Range Added power up requirements to Maximum Ratings Page 9 of 10 [+] Feedback CY29948 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2002-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07288 Rev. *E Revised May 2, 2011 Page 10 of 10 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback