LINER LTC1705EGN Dual 550khz synchronous switching regulator controller with 5-bit vid and 150ma ldo Datasheet

LTC1705
Dual 550kHz Synchronous
Switching Regulator Controller with
5-Bit VID and 150mA LDO
DESCRIPTIO
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FEATURES
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The LTC®1705 is a complete power supply controller for
Intel Mobile Pentium processors. It includes two switching regulator controllers, each designed to drive a pair of
N-channel MOSFETs in a voltage mode feedback, synchronous buck configuration, to provide the core and I/O
supplies. The core controller includes a 5-bit DAC that
conforms to the Intel Mobile VID specification. The IC also
includes a low dropout linear regulator (LDO) that delivers
up to 150mA of output current to provide the CLK supply.
The LTC1705 uses a constant-frequency 550kHz PWM
architecture, minimizing external component size and
cost, as well as optimizing load transient performance. It
provides better than 1.25% DC accuracy at its core output,
and 2% at I/0 and CLK outputs. The high performance
feedback loops allow the circuit to keep total output
regulation within ±5% under all transient conditions. An
open-drain PGOOD flag indicates that all three outputs are
within ±10% of their regulated values. A shutdown circuit
disables all three outputs if the RUN/SS pin is pulled to
ground. In this mode, the LTC1705 supply current drops
to below 100µA.
Three Regulated Outputs: Core, I/O and CLK in One
Package
Integrated Intel Mobile 5-Bit VID DAC
No External Current Sense Resistors
All N-Channel External MOSFET Architecture
550kHz Switching Frequency Minimizes External
Component Size and Cost
Integrated 150mA LDO Linear Regulator
Excellent DC Accuracy: 1.25% for Core, 2% for I/O
and CLK Supplies
PGOOD Flag Monitors All Three Outputs
High Efficiency Over Wide Load Current Range
Low Shutdown Current: < 100µA
Switchers Run Out-of-Phase to Minimize CIN
Small 28-Pin Narrow SSOP Package
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APPLICATIO S
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Complete Power Supply Controller for Intel
Mobile Pentium® Processors
Intel Mobile Pentium Core, I/O, Clock Supplies
Multiple Logic Supply Generator
, LTC and LT are registered trademarks of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation.
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TYPICAL APPLICATIO
VIN
5V
CIN
330µF
10V
×3
+
Intel Mobile Pentium VRM Supply
1µF
QTCA
QTCB
LC
0.68µH
VOUTC
0.9V TO 2V
15A
1µF
+
COUTC
180µF
4V
×6
RPGOOD
5k
DCPC
MBR
0520LT1
CCPC
1µF
QBCB
2
22
PVCC
5
TGC
3
BOOSTC
PGOOD
6
19
DCPIO
MBR
0520LT1
VCC
26
TGIO
27
BOOSTIO
SWC
SWIO
BGC
BGIO
QTIO
4
RIMAXC, 27k
8
11
C11
R31
C31 1.8k 1800pF
1800pF
C21
330pF
9
R21, 11k
10k
10
CSS
0.1µF
7
12
IMAXC
SENSEC
FBC
COMPC
RUN/SS
25
IMAXIO
COMPIO
FBIO
VINCLK
28
RIMAXI0, 16k
1
GND
VID4:0
VOUTCLK
COUTIO
QBIO 100µF
10V
×2
R22, 11k
21
C22
100pF
20
24
+
PGND
14–18
5-BIT VID
LTC1705
LIO
3µH
CCPIO
1µF
QBCA
13
SHUTDOWN
CIN: KEMET T510X337K010AS
COUTC: PANASONIC EEFUE0G181R
COUTIO: AVX TPS0107M010R0065
LC: SUMIDA CEP125-4712-T007
LIO: SUMIDA CDRH6D28-3R0
QTCA, QTCB, QBCA, QBCB: FAIRCHILD FDS6670A
QTIO, QBIO: 1/2 FAIRCHILD NDS8926
10µF
10Ω
+
■
CVINCLK
10µF
10V
C12
2200pF
+
1µF
VOUTIO
1.5V
3A
R12
8.87k
1%
VINCLK
3.3V
23
CVOUTCLK
10µF
10V
RB2
10k
1%
+
1µF
VOUTCLK
2.5V
150mA
1705 TA01
1
LTC1705
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ABSOLUTE
AXI U RATI GS
(Note 1)
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
Supply Voltage
VCC, PVCC, VINCLK .................................................. 6V
BOOSTC, BOOSTIO ............................................. 12V
BOOSTC – SWC, BOOSTIO – SWIO ....................... 6V
Input Voltage
SWC, SWIO ................................................ –1V to 6V
SENSEC, FBC, FBIO, VIDn ....... – 0.3V to (VCC + 0.3V)
PGOOD, RUN/SS,
IMAXC, IMAXIO .................................. – 0.3V to (VCC + 0.3V)
Peak Output Current <10µs
TGC, BGC .............................................................. 5A
TGIO, BGIO ....................................................... 1.25A
Operating Temperature Range (Note 2) .. – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
IMAXIO
1
28 BGIO
PVCC
2
27 BOOSTIO
BOOSTC
3
26 TGIO
BGC
4
25 SWIO
TGC
5
24 VINCLK
SWC
6
23 VOUTCLK
PGND
7
22 PGOOD
IMAXC
8
21 COMPIO
RUN/SS
9
20 FBIO
COMPC 10
LTC1705EGN
19 VCC
FBC 11
18 VID4
GND 12
17 VID3
SENSEC 13
16 VID2
VID0 14
15 VID1
GN PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 80°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = PVCC = BOOST = 5V, VINCLK = 3.3V unless otherwise specified. (Note 3)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
3.15
5
5.5
V
(Note 4)
●
3.15
5
5.5
V
VBOOST – VSW (Note 4)
●
3.15
5
5.5
V
●
3
3.3
5.5
V
4.5
40
8
100
mA
µA
VSENSEC = VFBIO = 0V, No Load at Drivers (Note 5) ●
●
RUN/SS = 0V (Note 6)
2
1
6
50
mA
µA
IBOOSTC + IBOOSTIO
VSENSEC = VFBIO = 0V, No Load at Drivers (Note 5) ●
RUN/SS = 0V (Note 6)
●
2
1
6
50
mA
µA
IVINCLK
VINCLK Supply Current
IVOUTCLK = 0mA
RUN/SS = 0V
●
●
1
4
1.5
30
mA
µA
VSHDN
RUN/SS Shutdown Threshold
VRUN/SS ↑ (Rising Edge)
●
ISS
RUN/SS Source Current
RUN/SS = 0V
VCC
VCC Supply Voltage
PVCC
PVCC Supply Voltage
BVCC
BOOST Pin Voltage
VINCLK
VINCLK Supply Voltage
IVCC
VCC Supply Current
Test Circuit 1
RUN/SS = 0V
IPVCC
PVCC Supply Current
IBOOST
●
●
0.2
0.5
V
–3
µA
Core, I/O Supply Control Loops
VSENSEC
Output Voltage Accuracy
Programmed from 0.9V to 2V
VFBC
Core Feedback Voltage
(Note 10)
VFBIO
I/O Feedback Voltage
dVFB
Feedback Voltage Line Regulation
VCC = 3.3V to 5.5V
●
dVOUT
Output Voltage Load Regulation
(Note 7)
●
IFBIO
I/O Feedback Input Current
2
●
–1.25
1.25
0.800
●
●
0.784
– 0.2
%
V
0.800
0.816
V
±0.01
±0.1
%/V
– 0.1
%
±1
µA
LTC1705
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = PVCC = BOOST = 5V, VINCLK = 3.3V unless otherwise specified. (Note 3)
SYMBOL PARAMETER
AFB
Feedback Amplifier DC Gain
GBW
Feedback Amplifier Gain Bandwidth Product
ICOMP
Feedback Amplifier Output Sink/Source Current
VPGOOD
Negative Power Good Threshold
Positive Power Good Threshold
AILIM
Current Limit Amplifier DC Gain
IIMAX
IMAX Source Current
CONDITIONS
MIN
TYP
●
74
85
dB
20
MHz
●
±3
±10
mA
●
●
–15
6
–10
10
●
40
60
VIMAXC = VIMAXIO = 0V
●
–12
–10
–8
●
460
550
650
f = 100kHz (Note 7)
Relative to Nominal Output Voltage
MAX
–6
15
UNITS
%
%
dB
µA
Core, I/O Supply Switching Characteristics
fOSC
Oscillator Frequency
Test Circuit 1
ΦOSC
Core and I/O Oscillator Phase Difference
(Note 7)
DCMAX
Maximum Duty Cycle
tNOV
Driver Nonoverlap
tr, tf
Driver Rise/Fall Time
180
kHz
DEG
●
87
90
93
%
Test Circuit 1, 50% to 50%
●
10
25
120
ns
Test Circuit 1, 10% to 90%
●
15
100
ns
IVOUTCLK = 0mA
●
2.50
2.55
V
VINCLK = 3.0V to 5.5V
●
±0.02
±0.1
%/V
Output Voltage Load Regulation
IVOUTCLK = 0mA to 150mA
●
CLK Output Short-Circuit Current
IVOUTCLK = 0V
●
– 240
–150
mA
VDROPOUT CLK Output Dropout Voltage
IVOUTCLK = 150mA, dVOUTCLK = –1% (Note 8)
●
0.3
0.5
V
VPGOOD
Relative to VOUTCLK
Relative to VOUTCLK
●
●
–10
10
–6
15
%
%
Clock Supply Output
VOUTCLK
CLK Output Voltage
dVOUTCLK Output Voltage Line Regulation
ILMCLK
Negative VOUTCLK Power Good Threshold
Positive VOUTCLK Power Good Threshold
2.45
– 0.1
–15
6
– 0.05
%
VID Inputs
R1
Resistance Across SENSEC and FBC
RVID
VID Input Pull-Up Resistance
VVID
VID Input Threshold
10
(Note 9)
kΩ
30
●
0.4
Power Good
Power Bad
●
●
10
IPGOOD = 1mA
●
VID Code Change
●
●
●
kΩ
1.6
V
10
µA
mA
0.03
0.1
V
4
20
20
8
40
40
µs
µs
µs
PGOOD
IPGOOD
VPGOOD Sink Current
VOLPG
PGOOD Output Low Voltage
TPGOOD
VPGOOD Falling Edge Delay
VPGOOD Rising Edge Delay
VPBAD Pulse
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC1705 is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: PVCC and BVCC (VBOOST – VSW) must be greater than VGS(ON) of
the external MOSFETs to ensure proper operation.
Note 5: Supply current in normal operation is dominated by the current
needed to charge and discharge the capacitance of the external MOSFET
2
10
10
gates. This current varies with supply voltage and the choice of external
MOSFETs.
Note 6: Supply current in shutdown is dominated by external MOSFET
leakage and may be significantly higher than the quiescent current drawn
by the LTC1705, especially at elevated temperature.
Note 7: Guaranteed by design, not subject to test.
Note 8: Dropout voltage is the minimum input-to-output voltage
differential required to maintain regulation at the specified output current.
In dropout, the output voltage will be equal to VINCLK – VDROPOUT.
Note 9: Each internal pull-up resistor attached to the VID inputs has a
series diode connected to VCC to allow input voltages higher than the VCC
supply without damage or clamping. (See Block Diagram.)
Note 10: The core feedback voltage accuracy is guaranteed by the VSENSE
output voltage accuracy test.
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LTC1705
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TYPICAL PERFOR A CE CHARACTERISTICS
VSENSEC vs Temperature
VSENSEC Line Regulation
1.315
1.30
VCC = 5V
VOUT = 1.3V
1.310
∆VSENSEC (mV)
VSENSEC (V)
1.300
1.295
1.290
0.08
0.78
0.06
0.52
0.04
0.26
0.02
0
0
–0.26
–0.02
–0.52
–0.04
–0.78
–0.06
–1.04
–0.08
–1.30
–25
0
25
50
75
TEMPERATURE (°C)
100
125
–0.10
3
3.5
4
4.5
VCC (V)
5
5.5
1705 G01
6
1705 G02
VSENSEC Load Regulation
Core Supply Efficiency
0.8
100
0.05
TA = 25°C
VOUT = 1.6V
0
∆VSENSE (%)
1.305
1.285
–50
0.10
TA = 25°C
1.04
VOUT = 2V
90
0
EFFICIENCY (%)
∆VSENSE (%)
∆VSENSEC (mV)
VOUT = 1.6V
80
–0.8
–0.05
–1.6
–0.10
–2.4
–0.15
60
–0.20
15
50
–3.2
0
3
6
9
ILOAD (A)
12
VOUT = 0.9V
70
VIN = 5V, TA = 25°C, I/O DISABLED
QTC = QBC = 2× FDS6670A
0
3
6
9
ILOAD (A)
12
1705 G04
1705 G03
VFBIO vs Temperature
VFBIO Line Regulation
0.810
0.80
VCC = 5V
∆VFBIO (mV)
VFBIO (V)
0.798
0.08
0.48
0.06
0.32
0.04
0.16
0.02
0
0
–0.16
–0.02
–0.32
–0.04
–0.48
–0.06
–0.64
–0.08
–0.80
–25
0
25
50
75
TEMPERATURE (°C)
100
125
1705 G05
–0.10
3
3.5
4
4.5
VCC (V)
5
5.5
6
1705 G06
∆VFBIO (%)
0.802
0.794
4
0.10
TA = 25°C
0.64
0.806
0.790
–50
15
LTC1705
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TYPICAL PERFOR A CE CHARACTERISTICS
Current Limit Threshold vs
Temperature
VOUTC 0A To 10A Load Step
I/O Supply Efficiency
100
24
VIN = 5V, VOUT = 1.5V, TA = 25°C,
CORE DISABLED, QTIO = QBIO = NDS8926
EFFICIENCY (%)
90
CURRENT LIMIT THRESHOLD (A)
0A TO 10A
LOAD
5A/DIV
VOUT = 1.6V
AC 50mV/
DIV
80
70
60
5ms/DIV
1705 G08
50
0.5
0
1
1.5
ILOAD (A)
2
VIN = 5V, VOUT = 1.6V, ∆VOUT = –1%,
RIMAXC = 24.9k, QTC = QBC = 2× FDS6670A
22
20
18
16
14
12
10
–50
2.5
–25
0
25
50
75
TEMPERATURE (°C)
100
1705 G07
125
1705 G09
VOUTC vs Load Current
VOUTCLK vs Temperature
2.0
VOUTCLK Line Regulation
2.55
2.5
VINCLK = 3.3V
2.54
0.10
TA = 25°C
2.0
0.08
2.53
1.5
0.06
2.52
1.0
0.04
0.5
0.02
TA = 25°C, VIN = 5V,
VOUT = 1.6V,
QBC = 2× FDS6670A,
RIMAXC = 24.9k,
CRUNSS = 0.01µF
0.5
0
4
0
8
12
LOAD CURRENT (A)
16
20
∆VOUTCLK (mV)
VOUTCLK (V)
1.0
2.51
2.50
2.49
0
0
–0.5
–0.02
2.48
–1.0
–0.04
2.47
–1.5
–0.06
2.46
–2.0
–0.08
2.45
–50
–2.5
–25
0
25
50
75
TEMPERATURE (°C)
1705 G10
100
125
–0.10
3
3.5
4
4.5
0
450
0
6
VOUTCLK Short-Circuit Current vs
Temperature
500
0.02
TA = 25°C
5.5
1705 G12
VOUTCLK Dropout Voltage vs
Temperature
0.5
5
VINCLK (V)
1705 G11
VOUTCLK Load Regulation
∆VOUTCLK (%)
VOUTC (V)
1.5
–150
IOUTCLK = –150mA
VINCLK = 3.3V
–190
–1.0
–0.04
–1.5
–0.06
–2.0
–0.08
350
ILMCLK (mA)
–0.02
VDROPOUT (mV)
–0.5
∆VOUTCLK (%)
∆VOUTCLK (mV)
400
300
250
–230
–270
200
–2.5
–150
–0.10
–125
–100 –75
–50
IOUTCLK (mA)
–25
0
1705 G13
–310
150
100
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
1705 G14
–350
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
1705 G15
5
LTC1705
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TYPICAL PERFOR A CE CHARACTERISTICS
VOUTCLK Short-Circuit Current vs
VINCLK
VOUTCLK 10mA To 150mA Load
Step
fOSC vs Temperature
–150
650
TA = 25°C
VCC = 5V
630
VOUTCLK
AC 5mV/DIV
–190
610
fOSC (kHz)
ILMCLK (mA)
590
–230
10mA TO
150mA LOAD
100mA/DIV
–270
570
550
530
510
–310
2ms/DIV
490
1705 G18.tif
470
–350
3
3.5
4
4.5
5
5.5
450
–50
6
–25
VINCLK (V)
0
25
50
75
TEMPERATURE (°C)
1705 G16
fOSC vs VCC
IIMAX vs Temperature
IIMAX vs VCC
–8.0
–8.0
TA = 25°C
VCC = 5V
–8.5
450
3
3.5
4
4.5
VCC (V)
5
5.5
6
–9.0
–9.0
–9.5
–9.5
IIMAX (µA)
IIMAX (µA)
fOSC (kHz)
490
–10.0
–10.5
–11.5
–11.5
–12.0
–25
0
25
50
75
TEMPERATURE (°C)
100
1.4
SUPPLY CURRENT (mA)
VID INPUT THRESHOLD (V)
0.6
1.2
1.0
0.8
4.5
0
25
50
75
TEMPERATURE (°C)
100
125
1705 G23
5.5
6
IVCC
3.0
IPVCC, IBOOST
1.5
0.6
–25
5
VCC = PVCC = BVCC = 5V, VINCLK = 3.3V,
TGC, BGC, TGIO, BGIO FLOAT
1.4
0.8
4.5
VCC (V)
6.0
TA = 25°C
1.0
4
Supply Current vs Temperature
1.6
VCC = 5V
1.2
3.5
1705 G22
VID Input Threshold vs VCC
1.6
VID INPUT THRESHOLD (V)
3
125
1705 G21
VID Input Threshold vs
Temperature
6
–10.5
–11.0
1705 G20
0.4
–50
–10.0
–11.0
–12.0
–50
TA = 25°C
–8.5
610
530
125
1705 G19
650
570
100
IVINCLK
0.4
3
3.5
4
4.5
VCC (V)
5
5.5
6
1705 G24
0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
1705 G25
LTC1705
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TYPICAL PERFOR A CE CHARACTERISTICS
Drivers Rise and Fall Time vs
Load
IPVCC, IBOOST vs Driver Load
12
2
12
6
TA = 25°C, PVCC = BOOST = 5V
0
0
2000
4000
6000
TG, BG LOAD (pF)
8000
0
10000
0.56
I/O DRIVERS
VSHDN (V)
18
0.68
40
t r, t f (ns)
24
CORE
DRIVERS
SUPPLY
CURRENT
WITH I/O
DISABLED
4
50
30
8
6
VCC = 5V
MEASURED AT RUN/SS
TA = 25°C, PVCC = BOOST = 5V
CORE IPVCC, IBOOST (mA)
I/O IPVCC, IBOOST (mA)
10
0.80
60
36
I/O DRIVERS
SUPPLY CURRENT
WITH CORE DISABLED
VSHDN vs Temperature
CORE
DRIVERS
30
0.44
20
0.32
10
0
0
2000
4000
6000
TG, BG LOAD (pF)
1705 G26
8000
10000
1705 G27
0.20
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
1705 G28
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PI FU CTIO S
IMAXIO (Pin 1): I/O Supply Current Limit Set. The IMAXIO pin
sets the current limit comparator threshold for the I/O
controller. If the voltage drop across the bottom MOSFET,
QBIO, exceeds the magnitude of the voltage at IMAXIO, the
I/O controller enters current limit. The IMAXIO pin has an
internal 10µA current source pull-up, allowing the current
threshold to be set with a single external resistor to PGND.
Kelvin connect this current setting resistor to the source of
QBIO. Refer to the Current Limit Programming section for
more information on choosing the value of RIMAX.
PVCC (Pin 2): Driver Power Supply Input. PVCC provides
power to the BGC and BGIO output drivers. PVCC must be
connected to a voltage high enough to fully turn on the
external MOSFETs QBC and QBIO. PVCC should generally
be connected directly to VIN, the main system 5V supply.
PVCC requires at least a 10µF bypass capacitor directly to
PGND.
BOOSTC (Pin 3): Core Controller Top Gate Driver Supply.
The BOOSTC pin supplies power to the floating TGC driver.
Bypass BOOSTC to SWC with a 1µF capacitor. An external
schottky diode from VIN to BOOSTC creates a complete
floating charge-pumped supply at BOOSTC. No other
external supplies are required.
BGC (Pin 4): Core Supply Bottom Gate Drive. The BGC pin
drives the gate of the bottom N-channel synchronous
switch MOSFET, QBC. BGC is designed to typically drive
up to 10,000pF of gate capacitance. If RUN/SS goes low,
BGC goes low, turning off QBC.
TGC (Pin 5): Core Supply Top Gate Drive. The TGC pin
drives the gate of the top N-channel MOSFET, QTC. The
TGC driver draws power from the BOOSTC pin and returns
it to the SWC pin, providing true floating drive to QTC. TGC
is designed to typically drive up to 10,000pF of gate
capacitance. If RUN/SS goes low, TGC goes low, turning
off QTC.
SWC (Pin 6): Core Supply Switching Node. Connect SWC
to the switching node of the core converter. The TGC driver
ground returns to SWC, providing floating gate drive to the
top N-channel MOSFET switch, QTC. The voltage at SWC
is compared to IMAXC by the current limit comparator while
the bottom MOSFET, QBC, is on.
PGND (Pin 7): Power Ground. The BGC and BGIO drivers
return to this pin. Connect PGND to a high-current ground
node in close proximity to the sources of external MOSFETs
QBC and QBIO, and the VIN and VOUT bypass capacitors.
IMAXC (Pin 8): Core Supply Current Limit Set. See IMAXIO.
7
LTC1705
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RUN/SS (Pin 9): SoftStart. Pulling RUN/SS to GND externally shuts down the LTC1705 and turns off all the external
MOSFET switches. The quiescent supply current drops
below 100µA. A capacitor from RUN/SS to GND controls
the turn on time and rate of rise of the core and I/O output
voltages at power up. An internal 3µA current source pullup at RUN/SS sets the turn-on time at approximately
300ms/µF.
COMPC (Pin 10): Core Controller Loop Compensation.
The COMPC pin is connected directly to the output of the
Core controller’s error amplifier and the input of the PWM
comparator. Use an RC network between the COMPC pin
and the FBC pin to compensate the feedback loop for
optimum transient response.
FBC (Pin 11): Core Controller Feedback Input. Connect the
loop compensation network for the core controller to FBC.
FBC internally connects to the VID resistor network to set
the Core output voltage.
GND (Pin 12): Signal Ground. All internal low power
circuitry returns to the GND pin. Connect to a low impedance ground, separated from the PGND node. All feedback, compensation and softstart connections should
return to GND. GND and PGND should connect only at a
single point, near the PGND pin and the negative plate of
the VIN bypass capacitor.
FBIO (Pin 20): I/O Controller Feedback Input. Connect
FBIO through a resistor divider network to VOUTIO to set the
output voltage. Also, connect the loop compensation
network for the I/O controller to FBIO.
COMPIO (Pin 21): I/O Controller Loop Compensation. See
COMPC.
PGOOD (Pin 22): Power Good. PGOOD is an open-drain
logic output. PGOOD pulls low if any of the three supply
outputs are out of regulation (see Electrical Characteristics table for Core, I/O and CLK thresholds). An external
pull-up resistor is required at PGOOD to allow it to swing
positive.
VOUTCLK (Pin 23): Clock Supply Output. VOUTCLK is the
output node of the internal linear clock supply regulator.
VOUTCLK provides up to 150mA at the 2.5V output to power
the CPU CLK supply. Bypass VOUTCLK with at least a 2.2µF
capacitor to GND (refer to the VCLK Linear Regulator
section). If RUN/SS goes low, the VOUTCLK regulator shuts
down.
VINCLK (Pin 24): Clock Supply Input. VINCLK is the input
terminal to the internal linear CLK supply regulator. Connect VINCLK to a 3.3V supply to maximize efficiency. VINCLK
can be connected to the 5V supply, but the efficiency of the
VOUTCLK regulator is reduced. Bypass VINCLK with a 10µF
capacitor to GND.
SENSEC (Pin 13): Core Controller Output Sense. Connect
to VOUTC.
SWIO (Pin 25): I/O Controller Switching Node. See SWC.
VID0 to VID4 (Pins 14 to 18): VID Programming Inputs.
These are logic inputs that set the output voltage at the
Core supply to a preprogrammed value (see Table 1). VID4
is the MSB, VID0 is the LSB. The codes selected by the VID
inputs correspond to the Intel Mobile VID specification.
Any VID code transition forces PGOOD to go low for 20µs.
Each VID pin includes an on-chip 30k pull-up resistor in
series with a diode (see Block Diagram).
BOOSTIO (Pin 27): I/O Controller Top Gate Driver Power.
See BOOSTC.
VCC (Pin 19): Power Supply Input. All internal circuits
except the output drivers are powered from this pin.
Connect VCC to a low-noise 5V supply and bypass the pin
to GND with at least a 10µF capacitor in close proximity to
the LTC1705.
8
TGIO (Pin 26): I/O Controller Top Gate Drive. See TGC.
TGIO is designed to typically drive up to 2,000pF of gate
capacitance.
BGIO (Pin 28): I/O Controller Bottom Gate Drive. See BGC.
BGIO is designed to typically drive up to 2,000pF of gate
capacitance.
SENSEC 13
FBC 11
COMPC 10
BGC 4
PVCC
SWC 6
TGC 5
BOOSTC 3
IMAXC 8
RB
R1
10k
0.8V
10µA
FBC
10k
–
+
CORE
DRIVER
LOGIC
ILMC
15
VID1
14
30k
16
30k
VID2
VCC
VID0
30k
0.84V
MINC
VID3
30k
18
VID4
30k
0.88V
CORE
SOFTSTART
9
RUN/SS
0.72V
0.76V
PWMC
17
19
MAXC
VCC
2
BANDGAP
REFERENCE
TO INTERNAL
CIRCUITRY
PPGC
NPGC
MPG
22
PGOOD
PWRGD
DELAY
OSC
550kHz
PWRBAD CORE
PGND
7
PWRBAD CLK
PVCC
PPGCLK
NPGCLK
PPGIO
NPGIO
GND
12
1.32V
1.08V
0.88V
+
–
FBIO
+
–
0.8V
AMP
0.76V
MAXIO
0.84V
POWER DOWN ENTIRE CHIP
PWMIO
MINIO
SCMP
1.2V
IO
SOFTSTART
0.72V
0.5V
3µA
IO
DRIVER
LOGIC
ILMIO
25 SWIO
26 TGIO
27 BOOSTIO
1 IMAXIO
1705 BD
23 VOUTCLK
24 VINCLK
21 COMPIO
20 FBIO
28 BGIO
PVCC
10µA
LTC1705
BLOCK DIAGRA
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PWRBAD IO
LTC1705
TEST CIRCUIT
Test Circuit 1
5V
IBOOSTC
IVCC
IPVCC
VCC
2000pF
2000pF
2k
TGIO
BGC
BGIO
LTC1705
IMAXC
0.1µF
IMAXIO
fOSCIO
1000pF
2k
1000pF
COMPIO
FBC
RUN/SS
100µF
BOOSTIO
TGC
COMPC
VFBC
+
VINCLK
PVCC
BOOSTC
fOSCC
IBOOSTIO
IVINCLK
FBIO
SENSEC
PGOOD
VIDO:4
VOUTCLK
VFBIO
VOUTCLK
+
RUN/SS
10µF
SWC
PGND
GND
SWIO
1705 TC
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I G CODES
Table 1. VID Inputs and Corresponding Core Output Voltages
VOUTC
CODE
VID4
VID3
VID2
VID1
Gnd
2.00V
10000
Float
Gnd
Gnd
Gnd
Gnd
1.275V
Float
1.95V
10001
Float
Gnd
Gnd
Gnd
Float
1.250V
1.90V
10010
Float
Gnd
Gnd
Float
Gnd
1.225V
CODE
VID4
VID3
VID2
VID1
VID0
00000
Gnd
Gnd
Gnd
Gnd
00001
Gnd
Gnd
Gnd
Gnd
00010
Gnd
Gnd
Gnd
Float
Gnd
VID0
VOUTC
00011
Gnd
Gnd
Gnd
Float
Float
1.85V
10011
Float
Gnd
Gnd
Float
Float
1.200V
00100
Gnd
Gnd
Float
Gnd
Gnd
1.80V
10100
Float
Gnd
Float
Gnd
Gnd
1.175V
00101
Gnd
Gnd
Float
Gnd
Float
1.75V
10101
Float
Gnd
Float
Gnd
Float
1.150V
00110
Gnd
Gnd
Float
Float
Gnd
1.70V
10110
Float
Gnd
Float
Float
Gnd
1.125V
00111
Gnd
Gnd
Float
Float
Float
1.65V
10111
Float
Gnd
Float
Float
Float
1.100V
01000
Gnd
Float
Gnd
Gnd
Gnd
1.60V
11000
Float
Float
Gnd
Gnd
Gnd
1.075V
01001
Gnd
Float
Gnd
Gnd
Float
1.55V
11001
Float
Float
Gnd
Gnd
Float
1.050V
01010
Gnd
Float
Gnd
Float
Gnd
1.50V
11010
Float
Float
Gnd
Float
Gnd
1.025V
01011
Gnd
Float
Gnd
Float
Float
1.45V
11011
Float
Float
Gnd
Float
Float
1.000V
01100
Gnd
Float
Float
Gnd
Gnd
1.40V
11100
Float
Float
Float
Gnd
Gnd
0.975V
01101
Gnd
Float
Float
Gnd
Float
1.35V
11101
Float
Float
Float
Gnd
Float
0.950V
01110
Gnd
Float
Float
Float
Gnd
1.30V
11110
Float
Float
Float
Float
Gnd
0.925V
1.25V
11111*
Float
Float
Float
Float
Float
0.900V
01111*
Gnd
Float
Float
Float
Float
*01111 and 11111 are defined by Intel to signify “no CPU.” The LTC1705
generates the output voltages shown if these codes are selected.
10
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The LTC1705 includes two, step-down (buck), voltage
mode feedback switching regulator controllers and a low
dropout linear regulator. The three outputs are designed to
power the core, I/O and CLK supplies of an Intel Mobile
Pentium system. Each switching regulator controller employs a synchronous switching architecture with two
external N-channel MOSFETs per channel. The chip operates from a low voltage input supply (6V maximum) and
provides high power, high efficiency, precisely regulated
output voltages. Several features make the LTC1705 particularly suited for microprocessor supply regulation.
Output regulation at the core supply is extremely tight,
with initial accuracy and DC line and load regulation better
than 1.25%. Total regulation including transient response
is inside of 3.5% with a properly designed circuit. The
550kHz switching frequency and the high speed internal
feedback amplifiers allow the use of physically small, low
value external components without compromising performance. An onboard 5-bit DAC sets the core output voltage,
consistent with the Intel Mobile VID specification (Table␣ 1).
The 800mV internal reference allows regulated output
voltages as low as 800mV without external level shifting
amplifiers. The linear regulator controls an internal Pchannel MOSFET that can provide more than 150mA of
current at an output voltage of 2.5V. A power good
(PGOOD) flag goes high when all the three outputs are in
regulation.
2-Step Conversion
“2-step” architectures use a primary regulator to convert
the input power source (batteries or AC line voltage) to an
intermediate supply voltage, often 5V. This intermediate
voltage is then converted to the low voltage, high current
supplies required by the system using a secondary regulator, such as the LTC1705. 2-step conversion eliminates the
need for a single converter to convert a high input voltage
to a very low output voltage, often an awkward design
challenge. It also fits naturally into systems that continue to
use the 5V supply to power portions of their circuitry or have
excess 5V capacity available as newer circuit designs shift
the current load to lower voltage supplies.
Each regulator in a typical 2-step system maintains a
relatively low step-down ratio (5:1 or less), running at high
efficiency while maintaining reasonable duty cycle. In
contrast, a regulator converting in a single step from a high
input voltage to a 1.xV output must operate at a very
narrow duty cycle, mandating trade-offs in external component values while compromising efficiency and transient response. The efficiency loss can exceed that of a
2-step solution. Further complicating the calculation is the
fact that many systems draw a significant fraction of their
total power off the intermediate 5V supply, bypassing the
low voltage supply. 2-step solutions using the LTC1705
usually match or exceed the total system efficiency of
single-step solutions and provide the additional benefits
of improved transient response, reduced PCB area and
simplified power trace routing.
2-step regulation can also buy advantages in thermal
management. Power dissipation in the LTC1705 portion
of a 2-step circuit is lower than it would be in a typical
1-step converter, even in cases where the 1-step converter
has higher total efficiency than the 2-step system. In a
typical microprocessor core supply regulator, for example, the regulator is usually located directly next to the
CPU. In a 1-step design, all of the power dissipated by the
core regulator is located next to the already hot CPU,
aggravating thermal management. In a 2-step LTC1705
design, a significant percentage of the power lost in the
core regulation system happens in the 5V supply, which is
usually located away from the CPU. The power lost to heat
in the LTC1705 section of the system is relatively low,
minimizing the added heat near the CPU.
Fast Transient Response
The LTC1705 core and I/O supplies use fast 20MHz GBW
op amps as error amplifiers. This allows the compensation
network to be designed with several poles and zeros in a
more flexible configuration than with typical gm feedback
amplifiers. The high bandwidth of the amplifier, coupled
with the high 550kHz switching frequency and the low
values of the external inductor and output capacitor, allow
very high loop cross-over frequencies. Additionally, a
typical LTC1705 circuit uses an inductor value on the
order of 1µH, allowing very fast di/dt slew rates. The result
is superior transient response compared with conventional solutions.
11
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High Efficiency
The LTC1705 core and I/O supplies use a synchronous
step-down (buck) architecture, with two external N-channel MOSFETs per output. A floating topside driver and a
simple external charge pump provide full gate drive to
each upper MOSFET. The voltage mode feedback loops
and MOSFET VDS current limit sensing circuits remove the
need for external current sense resistors, eliminating
external components and the corresponding power losses
in the high current paths. Properly designed circuits using
low gate charge MOSFETs are capable of efficiencies
exceeding 90% over a wide range of output voltages and
load currents.
VID Programming
The LTC1705 includes an onboard feedback network that
programs the core output voltage in accordance with the
Intel Mobile VID specification (Table 1). This network
includes a 10k resistor connected between SENSEC and
FBC and a variable value resistor connected between FBC
and GND, with the value set by the digital code present at
the VID4:0 pins. Connect SENSEC to VOUTC to allow the
network to monitor the output voltage. No additional
feedback components are required to set the output voltage of the core controller, although loop compensation
components are still required. Each VIDn pin includes an
internal 30k pull-up resistor, allowing it to float high if left
unconnected. The pull-up resistors connect to VCC through
diodes (see Block Diagram), allowing the VIDn pins to be
pulled above VCC without damage.
Note that codes 01111 and 11111, defined by Intel to
indicate “no CPU present, ” do generate output voltages at
VOUTC (1.25V and 0.9V, respectively). Also, note that the
I/O and CLK outputs on the LTC1705 are not connected to
the VID circuitry and work independently from the core
controller.
Linear Regulator and Thermal Shutdown
The LTC1705 CLK output is an easy to use monolithic LDO.
The VINCLK pin powers the regulator and an internal
P-channel MOS transistor provides the output current at
the 2.5V output. An external 10µF capacitor frequency
12
compensates the linear regulator feedback loop. The CLK
output is short-circuit protected and the built-in thermal
shutdown circuit turns off all three regulator outputs
should the LTC1705 junction temperature exceed 155°C.
SWITCHING ARCHITECTURE DETAILS
The LTC1705 dual switching regulator controller includes
two independent regulator channels. The two switching
regulator controllers and their corresponding external
components act independently of each other with the
exception of the common input bypass capacitor. The
RUN/SS and PGOOD pins also affect both channels. In the
following discussions, when a pin is referred to without
mentioning which side is involved, that discussion applies
equally to both sides.
Switching Architecture
Each half of the LTC1705 is designed to operate as a
synchronous buck converter (Figure 1). Each channel
includes two high power MOSFET gate drivers to control
external N-channel MOSFETs QT and QB. The core drivers
have 0.5Ω output impedances and can carry well over an
amp of continuous current with peak currents up to 5A to
slew large MOSFET gates quickly. The I/O drivers have 2Ω
output impedances. The external MOSFETs are connected
with the drain of QT attached to the input supply and the
source of QT at the switching node SW. QB is the synchronous rectifier with its drain at SW and its source at PGND.
SW is connected to one end of the inductor, with the other
end connected to VOUT. The output capacitor is connected
from VOUT to PGND.
When a switching cycle begins, QB is turned off and QT is
turned on. SW rises almost immediately to VIN and the
inductor current begins to increase. When the PWM pulse
finishes, QT turns off and one nonoverlap interval later, QB
turns on. Now SW drops to PGND and the inductor current
decreases. The cycle repeats with the next tick of the
master clock. The percentage of time spent in each mode
is controlled by the duty cycle of the PWM signal, which in
turn is controlled by the feedback amplifier. The master
clock runs at a 550kHz rate and turns QT on once every
1.8µs. In a typical application with a 5V input and a 1.5V
LTC1705
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output, the duty cycle will be set at 1.5/5 • 100% or 30%
by the feedback loop. This will give roughly a 540ns ontime for QT and a 1.26µs on-time for QB.
This constant frequency operation brings with it a couple
of benefits. Inductor and capacitor values can be chosen
with a precise operating frequency in mind and the feedback loop components can be similarly tightly specified.
Noise generated by the circuit will always be in a known
frequency band with the 550kHz frequency designed to
leave the 455kHz IF band free of interference. Subharmonic
oscillation and slope compensation, common headaches
with constant frequency current mode switchers, are
absent in voltage mode designs like the LTC1705.
During the time that QT is on, its source (the SW pin) is at
VIN. VIN is also the power supply for the LTC1705. However, QT requires VIN+VGS(ON) at its gate to achieve minimum RON. This presents a problem for the LTC1705—it
needs to generate a gate drive signal at TG higher than its
highest supply voltage. To accomplish this, the TG driver
runs from floating supplies, with its negative supply
attached to SW and its power supply at BOOST. This
allows it to slew up and down with the source of QT. In
VIN
+
CIN
QT
TG
L
SW
LTC1705
VOUT
+
QB
BG
COUT
PGND
1705 F01
Figure 1. Synchronous Buck Architecture
combination with a simple external charge pump (Figure
2), this allows the LTC1705 to completely enhance the
gate of QT without requiring an additional, higher supply
voltage.
The two channels of the LTC1705 run from a common
clock, with the phasing chosen to be 180° from the core
side to the I/O side. This has the effect of doubling the
frequency of the switching pulses seen by the input
bypass capacitor, lowering the RMS current seen by the
capacitor and reducing the value required.
Feedback Amplifier
Each side of the LTC1705 senses the output voltage at
VOUT with an internal feedback op amp (see Block Diagram). This is a real op amp with a low impedance output,
85dB open-loop gain and 20MHz gain bandwidth product.
The positive input is connected internally to an 800mV
reference, while the negative input is connected to the FB
pin. The output is connected to COMP, which is in turn
connected to the soft-start circuitry and from there to the
PWM generator.
Unlike many regulators that use a resistor divider connected to a high impedance feedback input, the LTC1705
is designed to use an inverting summing amplifier topology with the FB pin configured as a virtual ground. This
allows flexibility in choosing pole and zero locations not
available with simple gm configurations. In particular, it
allows the use of “Type 3” compensation, which provides
a phase boost at the LC pole frequency and significantly
improves loop phase margin (see Figure 3). Note that the
core side of the LTC1705 includes R1 and RB internally as
part of the VID DAC circuitry.
VIN
LTC1705
PVCC
BOOST
TG
+
DCP
CCP
CIN
+
BG
COMP
QT
SW
FB
–
L
QB
+
VOUT
R3
C3
R1
VOUT
RB
C2
PGND
R2
Figure 2. Floating TG Driver Supply
FB
LTC1705
COUT
1705 F02
0.8V
C1
1705 F03
Figure 3. "Type 3" Feedback Loop (I/O Channel)
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MIN/MAX Comparators
PGOOD Flag
Two additional feedback loops keep an eye on the main
feedback amplifier and step in if the feedback node moves
±5% from its nominal 800mV value. The MAX comparator
(see Block Diagram) activates if FB rises more than 5%
above 800mV. It immediately turns the top MOSFET (QT)
off and the bottom MOSFET (QB) on and keeps them that
way until FB falls back within 5% of its nominal value. This
pulls the output down as fast as possible, preventing
damage to the (often expensive) load. If FB rises because
the output is shorted to a higher supply, QB will stay on
until the short goes away, the higher supply current limits
or QB dies trying to save the load. This behavior provides
maximum protection against overvoltage fault at the output, while allowing the circuit to resume normal operation
when the fault is removed.
The LTC1705 incorporates a power good pin (PGOOD).
PGOOD is an open-drain output and requires an external
pull-up resistor. If all three regulators are typically within
±10% of their nominal value, transistor MPG shuts off (see
Block Diagram) and PGOOD is pulled high by the external
pull-up resistor. If any of the three outputs is more than
10% outside the nominal value for more than 4µs, PGOOD
pulls low, indicating that an output is out of regulation. For
PGOOD to pull high, all three outputs must be in regulation
for more than 20µs. PGOOD remains active during soft
start and current limit. On power up, PGOOD pulls low. As
soon as the RUN/SS pin rises above the shutdown threshold, the three pair of power good comparators take over
and control the transistor MPG directly. The 4µs and 20µs
delay ensure that short output transient glitches, that are
successfully “caught” by the power good comparators,
don’t cause momentary glitches at the PGOOD pin.
The MIN comparator (see Block Diagram) trips if FB is
more than 5% below 800mV and immediately forces the
switch duty cycle to 90% to bring the output voltage back
into range. It releases when FB is within the 5% window.
MIN is disabled when the soft-start or current limit circuits
are active—the only two times that the output should
legitimately be below its regulated value.
Notice that the FB pin is the virtual ground node of the
feedback amplifier. A typical compensation network does
not include local DC feedback around the amplifier, so that
the DC level at FB will be an accurate replica of the output
voltage, divided down by R1 and RB (Figure 3). However, the
compensation capacitors will tend to attenuate AC signals
at FB, especially with low bandwidth Type 1 feedback loops.
This can create a situation where the MIN, MAX and PGOOD
comparators do not respond immediately to shifts in the
output voltage, if they monitor the output at FB. With VID
code switching on the fly, this problem is aggravated.
To overcome this, a second resistor divider is used (see
Block Diagram) to provide the MIN, MAX and PGOOD
comparators with an accurate replica of the output voltage.
This ensures that the comparators react rapidly to code
changes. For the I/O channel, the output voltage is independent of VID codes and therefore the change in VOUT is
minimized. Maximizing I/O feedback loop bandwidth will
minimize these delays and allow MIN and MAX to operate
properly. See the Feedback Loop/Compensation section.
14
For the core channel, if there is a VID code change, the
internal DAC responds by switching its output voltage
immediately. However, the switching power supply output
slew rate is limited by the output filter. If the VID code step
change is small, the power good comparator might not
register any transition. To acknowledge the code transition command , the LTC1705 forces PGOOD to pull low for
20µs once there is a VID code change. After this short
interval, the power good comparators decide the PGOOD
status.
Shutdown/Soft-Start
The RUN/SS pin performs two functions: if pulled to
ground, it shuts down the LTC1705 and it acts as a
conventional soft-start pin, enforcing a maximum duty
cycle limit proportional to the voltage at RUN/SS. An
internal 3µA current source pull-up is connected to the
RUN/SS pin, allowing a soft-start ramp to be generated
with a single external capacitor to ground. The 3µA current
source is active even if the LTC1705 is shut down, ensuring the device will start when any external pull-down at
RUN/SS is released. In shutdown, the LTC1705 enters
micropower sleep mode and quiescent current drops
typically below 50µA.
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The RUN/SS pin shuts down the LTC1705 if it falls below
0.5V (Figure 4). Between 0.5V and about 1V, the LTC1705
wakes up and the duty cycle is kept to a miminum. As the
potential at RUN/SS increases, the duty cycle increases
linearly between 1V and 2V, reaching its final value of 90%
when RUN/SS is above 2V. Somewhere before this point,
the feedback amplifier will assume control of the loop and
the output will come into regulation. When RUN/SS rises
to 1V below VCC , the MIN feedback comparator is enabled
and the LTC1705 is in full operation.
VOUT
0V
NORMAL
OPERATION
START UP
CURRENT
LIMIT
5V
4V
COMP CONTROLS
DUTY CYCLE
2V
MIN
COMPARATOR
ENABLE
RUN/SS CONTROLS
DUTY CYCLE
1V
0.5V
0V
MINIMUM DUTY CYCLE
POWER-DOWN MODE
LTC1705 ENABLE
1705 F04
Figure 4. Soft-Start Operation in Start Up and Current Limit
Current Limit
The LTC1705 includes an onboard current limit circuit that
limits the maximum output current to a user-programmed
level. It works by sensing the voltage drop across QB
during the time that QB is on and comparing that voltage
to a user-programmed voltage at IMAX. Since QB looks like
a low value resistor during its on-time, the voltage drop
across it is proportional to the current flowing in it. In a
buck converter, the average current in the inductor is equal
to the output current. This current also flows through QB
during its on-time. Thus, by watching the voltage across
QB, the LTC1705 can monitor the output current.
Any time QB is on and the current flowing to the output is
reasonably large, the SW node at the drain of QB will be
somewhat negative with respect to PGND. The LTC1705
senses this voltage, inverts it and compares the sensed
voltage with a positive voltage at the IMAX pin. The IMAX pin
includes a trimmed 10µA pull-up, enabling the user to set
the voltage at IMAX with a single resistor, RIMAX, to ground.
The LTC1705 compares the two inputs and begins limiting
the output current when the magnitude of the negative
voltage at the SW pin is greater than the voltage at IMAX .
When the load current increases abruptly, the voltage
feedback loop forces the duty cycle to increase rapidly and
the on-time of QB will be small momentarily. The RDS(ON)
of QB must be low enough to ensure that the SW node is
pulled low within the QB on-time for proper current
sensing.
The current limit detector is connected to an internal gm
amplifier that pulls a current from the RUN/SS pin proportional to the difference in voltage magnitudes between the
SW and IMAX pins. The maximum value of this current is
250µA (typically). It begins to discharge the soft-start
capacitor at RUN/SS, reducing the duty cycle and controlling the output voltage until the current drops below the
limit. The soft-start capacitor needs to move a fair amount
before it has any effect on the duty cycle, adding a delay
until the current limit takes effect (Figure 4). This allows
the LTC1705 to experience brief overload conditions without affecting the output voltage regulation. The delay also
acts as a pole in the current limit loop to enhance loop
stability. While the soft-start capacitor is being discharged,
the top MOSFET must withstand the high power dissipation due to the high current especially if the regulator is
powered by a high current supply. Larger overloads cause
the soft-start capacitor to pull down quickly, protecting the
output components from damage. The current limit gm
amplifier includes a clamp to prevent it from pulling RUN/
SS below 0.5V and shutting off the LTC1705.
Power MOSFET RDS(ON) varies from MOSFET to MOSFET,
limiting the accuracy obtainable from the LTC1705 current
limit loop. Additionally, ringing on the SW node due to
parasitics can add to the apparent current, causing the
loop to engage early. The LTC1705 current limit is designed primarily as a disaster prevention, “no blow up”
circuit and is not useful as a precision current regulator. It
should typically be set around 50% above the maximum
expected normal output current to prevent component
tolerances from encroaching on the normal current range.
See the Current Limit Programming section for advice on
choosing a valve for RIMAX .
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EXTERNAL COMPONENT SELECTION
Gate Charge
Power MOSFETs
Gate charge is amount of charge (essentially, the number
of electrons) that the LTC1705 needs to put into the gate
of an external MOSFET to turn it on. The easiest way to
visualize gate charge is to think of it as a capacitance from
the gate pin of the MOSFET to SW (for QT) or to PGND (for
QB). This capacitance is composed of MOSFET channel
charge, actual parasitic drain-source capacitance and
Miller-multiplied gate-drain capacitance, but can be approximated as a single capacitance from gate to source.
Regardless of where the charge is going, the fact remains
that it all has to come out of PVCC to turn the MOSFET gate
on and when the MOSFET is turned back off, that charge
all ends up at ground. In the meanwhile, it travels through
the LTC1705’s gate drivers, heating them up. More power
lost!
Getting peak efficiency out of the LTC1705 depends strongly
on the external MOSFETs used. The LTC1705 requires at
least two external MOSFETs per side—more if one or
more of the MOSFETs are paralleled to lower on-resistance. To work efficiently, these MOSFETs must exhibit
low RDS(ON) at 5V VGS to minimize resistive power loss
while they are conducting current. They must also have
low gate charge to minimize transition losses during
switching. On the other hand, voltage breakdown requirements in a typical LTC1705 circuit are pretty tame: the 6V
maximum input voltage limits the VDS and VGS the MOSFETs
can see to safe levels for most devices.
Low RDS(ON)
RDS(ON) calculations are pretty straightforward. RDS(ON) is
the resistance from the drain to the source of the
MOSFETwhen the gate is fully on. Many MOSFETs have
RDS(ON) specified at 4.5V gate drive—this is the right
number to use in LTC1705 circuits running from a 5V
supply. As current flows through this resistance while the
MOSFET is on, it generates I2R watts of heat, where I is the
current flowing (usually equal to the output current) and R
is the MOSFET RDS(ON) . This heat is only generated when
the MOSFET is on. When it is off, the current is zero and the
power lost is also zero (and the other MOSFET is busy
losing power).
This lost power does two things: it subtracts from the
power available at the output, costing efficiency, and it
makes the MOSFET hotter—both bad things. The effect is
worst at maximum load when the current in the MOSFETs
and thus the power lost are at a maximum. Lowering
RDS(ON) improves heavy load efficiency at the expense of
additional gate charge (usually) and more cost (usually).
Proper choice of MOSFET RDS(ON) becomes a trade-off
between tolerable efficiency loss, power dissipation and
cost. Note that while the lost power has a significant effect
on system efficiency, it only adds up to a watt or two in a
typical LTC1705 circuit, allowing the use of small, surface
mount MOSFETs without heat sinks.
16
In this case, the power is lost in little bite-sized chunks, one
chunk per switch per cycle, with the size of the chunk set
by the gate charge of the MOSFET. Every time the MOSFET
switches, another chunk is lost. Clearly, the faster the
clock runs, the more important gate charge becomes as a
loss term. Old-fashioned switchers that ran at 20kHz could
pretty much ignore gate charge as a loss term; in the
550kHz LTC1705, gate charge loss can be a significant
efficiency penalty. Gate charge loss can be the dominant
loss term at medium load currents, especially with large
MOSFETs. Gate charge loss is also the primary cause of
power dissipation in the LTC1705 itself.
TG Charge Pump
There’s another nuance of MOSFET drive that the LTC1705
needs to get around. The LTC1705 is designed to use
N-channel MOSFETs for both QT and QB, primarily because N-channel MOSFETs generally cost less and have
lower RDS(ON) than similar P-channel MOSFETs. Turning
QB on is simple since the source of QB is attached to
PGND; the LTC1705 just switches the BG pin between
PGND and PVCC . Driving QT is another matter. The source
of QT is connected to SW which rises to PVCC when QT is
on. To keep QT on, the LTC1705 must get TG one MOSFET
VGS(ON) above PVCC . It does this by utilizing a floating
driver with the negative lead of the driver attached to SW
(the source of QT) and the PVCC lead of the driver coming
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out separately at BOOST. An external 1µF capacitor (CCP)
connected between SW and BOOST (Figure 2) supplies
power to BOOST when SW is high and recharges itself
through DCP when SW is low. This simple charge pump
keeps the TG driver alive even as it swings well above
PVCC. The value of the bootstrap capacitor CCP needs to
be at least 100 times that of the total “effective” gate
capacitance of the topside MOSFET(s). For very large
external MOSFETs (or multiple MOSFETs in parallel), CCP
may need to be increased beyond the 1µF value.
Input Supply
The BiCMOS process that allows the LTC1705 to include
large MOSFET drivers on-chip also limits the maximum
input voltage to 6V. This limits the practical maximum
input supply to a loosely regulated 5V rail. The LTC1705
operates properly with input supplies down to about 3.3V,
so a typical 3.3V supply can also be used if the external
MOSFETs are appropriately chosen (see the Power
MOSFETs section).
At the same time, the input supply needs to supply several
amps of current without excessive voltage drop. The input
supply must have regulation adequate to prevent sudden
load changes from causing the LTC1705 input voltage to
dip. In typical applications where the LTC1705 is generating a secondary low voltage logic supply, all of these input
conditions are met by the main system logic supply when
fortified with an input bypass capacitor.
Input Bypass Capacitor
A typical LTC1705 circuit running from a 5V logic supply
might provide 1.6V at 15A at its core output. 5V to 1.6V
implies a duty cycle of 32%, which means QTC is on 32%
of each switching cycle. During QTC’s on-time, the current
drawn from the input equals the load current and during the
rest of the cycle, the current drawn from the input is near
zero. This 0A to 15A, 32% duty cycle pulse train adds up to
7ARMS at the input. At 550kHz, switching cycles last about
1.8µs—most system logic supplies have no hope of regulating output current with that kind of speed. A local input
bypass capacitor is required to make up the difference and
prevent the input supply from dropping drastically when
QTC kicks on. This capacitor is usually chosen for RMS
ripple current capability and ESR as well as value. The
LTC1705 I/O channel typically operates at a much smaller
output current, hence the input bypass capacitor in an
LTC1705 circuit should be chosen primarily to meet the
core output requirement.
Consider our 15A example. The input bypass capacitor
gets exercised in three ways: its ESR must be low enough
to keep the initial drop as QT turns on within a reasonable
value (100mV or so); its RMS current capability must be
adequate to withstand the 7ARMS ripple current at the
input and the capacitance must be large enough to maintain the input voltage until the input supply can make up
the difference. Generally, a capacitor that meets the first
two parameters will have far more capacitance than is
required to keep capacitance-based droop under control.
In our example, we need 0.006Ω ESR to keep the input
drop under 100mV with a 15A current step and 7ARMS
ripple current capacity to avoid overheating the capacitor.
These requirements can be met with multiple low ESR
tantalum or electrolytic capacitors in parallel or with a
large monolithic ceramic capacitor.
Tantalum capacitors are a popular choice as input capacitors for LTC1705 applications, but they deserve a special
caution here. Generic tantalum capacitors have a destructive failure mechanism if they are subjected to large RMS
currents (like those seen at the input of a LTC1705). At
some random time after they are turned on, they can blow
up for no apparent reason. The capacitor manufacturers
are aware of this and sell special “surge tested” tantalum
capacitors specifically designed for use with switching
regulators. When choosing a tantalum input capacitor,
make sure that it is rated to carry the RMS current that the
LTC1705 will draw. If the data sheet doesn’t give an RMS
current rating, chances are the capacitor isn’t surge tested.
Don’t use it!
Output Bypass Capacitor
The output bypass capacitor has quite different requirements from the input capacitor. The ripple current at the
output of a buck regulator like the LTC1705 is much lower
than at the input, due to the fact that the inductor current
is constantly flowing at the output. The primary concern at
the output is capacitor ESR. Fast load current transitions
at the output appear as voltage across the ESR of the
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Usually the solution is to parallel several capacitors at the
output. For example, to keep the transient response in side
of 3.5% with the previous design, we’d need an output
ESR better than 0.004Ω. This can be met with six 0.025Ω,
180µF special polymer capacitors in parallel.
Inductor
The inductor in a typical LTC1705 circuit is chosen primarily for value and saturation current. The inductor value
sets the ripple current, which is commonly chosen between 20% to 40% of the anticipated full load current.
Ripple current is set by:
tON(QB) (VOUT )
L
In our 1.6V, 15A example, we’d set the ripple to 20% of
15A or 3A and the inductor value would be:
The external inductor/output capacitor combination makes
a more significant contribution to loop behavior. These
components cause a second order LC roll off at the output,
with the attendant 180° phase shift. This rolloff is what
filters the PWM waveform, resulting in the desired DC
output voltage, but the phase shift complicates the loop
compensation if the gain is still higher than unity at the
pole frequency. Eventually (usually well above the LC pole
frequency), the reactance of the output capacitor will
approach its ESR and the rolloff due to the capacitor will
stop, leaving 6dB/octave and 90° of phase shift (Figure 5).
PHASE (DEG)
IRIPPLE =
and the feedback amplifier with its compensation network.
All of these components affect loop behavior and must be
accounted for in the loop compensation. The modulator
consists of the internal PWM generator, the output MOSFET
drivers and the external MOSFETs themselves. From a
feedback loop point of view, it looks like a linear voltage
transfer function from COMP to SW and has a gain roughly
equal to the input voltage. It has fairly benign AC behavior
at typical loop compensation frequencies with significant
phase shift appearing at half the switching frequency.
GAIN (dB)
output bypass capacitor until the feedback loop in the
LTC1705 can change the inductor current to match the
new load current value. This ESR step at the output is often
the single largest budget item in the load regulation
calculation. As an example, our hypothetical 1.6V, 15A
switcher with a 0.006Ω ESR output capacitor would
experience a 90mV step at the output with a 0A to 15A load
step—a 5.6% output change!
AV
GAIN
–12dB/OCT
(1.2µs)(1.6V)
L=
=
= 0.67µH
IRIPPLE
3A
 1.6V 
with tON(QB) =  1 −
 / 550kHz = 1.2µs
5V 

tON(QB) (VOUT )
The inductor must not saturate at the expected peak
current. In this case, if the current limit was set to 22.5A,
the inductor should be rated to withstand 22.5A + (0.5 •
IRIPPLE) or 24A without saturating.
FEEDBACK LOOP/COMPENSATION
Feedback Loop Types
In a typical LTC1705 circuit, the feedback loop consists of
the modulator, the external inductor, the output capacitor
18
0
FREQ
–90
PHASE
–6dB/OCT
–180
–270
–360
1705 F05
Figure 5. Transfer Function of Buck Modulator
So far, the AC response of the loop is pretty well out of the
user’s control. The modulator is a fundamental piece of the
LTC1705 design and the external L and C are usually
chosen based on the regulation and load current requirements without considering the AC loop response. The
feedback amplifier, on the other hand, gives us a handle
with which to adjust the AC response. The goal is to have
180° phase shift at DC (so the loop regulates) and something less than 360° phase shift at the point that the loop
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GAIN (dB)
R1
FB
GAIN
–
–6dB/OCT
OUT
RB
VREF
PHASE (DEG)
C1
IN
0
FREQ
+
–90
–180
PHASE
–270
–360
1705 F06
Figure 6. Type 1 Schematic and Transfer Function
R2
R1
FB
C1
–6dB/OCT
GAIN
–
OUT
RB
VREF
GAIN (dB)
IN
PHASE (DEG)
C2
–6dB/OCT
0
FREQ
+
–90
PHASE
–180
–270
–360
1705 F07
Figure 7. Type 2 Schematic and Transfer Function
IN
C2
C3
R1
R2
C1
R3
FB
–
VREF
–6dB/OCT
GAIN
OUT
RB
PHASE (DEG)
Figure 7 shows an improved “Type 2” circuit that uses an
additional pole-zero pair to temporarily remove 90° of
phase shift. This allows the loop to remain stable with 90°
more phase shift in the LC section, provided the loop
reaches 0dB gain near the center of the phase “bump.”
Type 2 loops work well in systems where the ESR zero in
the LC roll-off happens close to the LC pole, limiting the
total phase shift due to the LC. The additional phase
compensation in the feedback amplifier allows the 0dB
point to be at or above the LC pole frequency, improving
loop bandwidth substantially over a simple Type 1 loop. It
has limited ability to compensate for LC combinations
where low capacitor ESR keeps the phase shift near 180°
for an extended frequency range. LTC1705 circuits using
conventional switching grade electrolytic output capacitors can often get acceptable phase margin with Type 2
compensation.
“Type 3” loops (Figure 8) use two poles and two zeros to
obtain a 180° phase boost in the middle of the frequency
band. A properly designed Type 3 circuit can maintain
acceptable loop stability even when low output capacitor
ESR causes the LC section to approach 180° phase shift
well above the initial LC roll-off. As with a Type 2 circuit,
the loop should cross through 0dB in the middle of the
phase bump to maximize phase margin. Many LTC1705
circuits using low ESR tantalum or OS-CON output capacitors need Type 3 compensation to obtain acceptable phase
margin with a high bandwidth feedback loop.
GAIN (dB)
gain falls to 0dB. The simplest strategy is to set up the
feedback amplifier as an inverting integrator, with the 0dB
frequency lower than the LC pole (Figure 6). This “Type 1”
configuration is stable but transient response is less than
exceptional if the LC pole is at a low frequency.
+6dB/OCT
–6dB/OCT
0
FREQ
+
–90
–180
PHASE
–270
–360
1705 F08
Figure 8. Type 3 Schematic and Transfer Function
Feedback Component Selection
Selecting the R and C values for a typical Type 2 or Type␣ 3
loop is a nontrivial task. The applications shown in this
data sheet show typical values, optimized for the power
components shown. They should give acceptable performance with similar power components, but can be way off
if even one major power component is changed significantly. Applications that require optimized transient response will need to recalculate the compensation values
specifically for the circuit in question. The underlying
mathematics are complex, but the component values can
be calculated in a straightforward manner if we know the
gain and phase of the modulator at the crossover frequency.
Modulator gain and phase can be measured directly from
a breadboard or can be simulated if the appropriate
parasitic values are known. Measurement will give more
accurate results, but simulation can often get close enough
to give a working system. To measure the modulator gain
and phase directly, wire up a breadboard with an LTC1705
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and the actual MOSFETs, inductor and input and output
capacitors that the final design will use. This breadboard
should use appropriate construction techniques for high
speed analog circuitry: bypass capacitors located close to
the LTC1705, no long wires connecting components,
appropriately sized ground returns, etc. Wire the feedback
amplifier as a simple Type 1 loop, with a 10k resistor from
VOUT to FB and a 0.1µF feedback capacitor from COMP to
FB. Choose the bias resistor (RB) as required to set the
desired output voltage. Disconnect RB from ground and
connect it to a signal generator or to the source output of
a network analyzer (Figure 9) to inject a test signal into the
loop. Measure the gain and phase from the COMP pin to
the output node at the positive terminal of the output
capacitor. Make sure the analyzer’s input is AC coupled so
that the DC voltages present at both the COMP and VOUT
nodes don’t corrupt the measurements or damage the
analyzer.
5V
10Ω
+
10µF
MBR0530T
VCC
VCOMP TO
ANALYZER
0.1µF
COMP
QT
TG
BOOST
1µF
FB
RB
PVCC
LTC1705
L
SW
10k
QB
BG
AC SOURCE
FROM
ANALYZER
RUN/SS
GND
NC
+
VOUT TO
ANALYZER
COUT
PGND
1705 F09
Figure 9. Modulator Gain/Phase Measurement Set Up
If breadboard measurement is not practical, a SPICE
simulation can be used to generate approximate gain/
phase curves. Plug the expected capacitor, inductor and
MOSFET values into the following SPICE deck and generate an AC plot of V(VOUT )/V(COMP) in dB and phase of
VOUT in degrees. Refer to your SPICE manual for details of
how to generate this plot.
20
*1705 modulator gain/phase
*2000 Linear Technology
*this file written to run with PSpice 8.0
*may require modifications for other
SPICE simulators
*MOSFETs
rfet mod sw 0.02
;MOSFET rdson
*inductor
lext sw out1 1u
rl out1 out 0.005
;inductor value
;inductor series R
*output cap
cout out out2 1000u
resr out2 0 0.01
;capacitor value
;capacitor ESR
*1705 internals
emod mod 0 comp 0 5
vstim comp 0 0 ac 1
.ac dec 100 1k 1meg
.probe
.end
;3.3 for 3.3V supply
;ac stimulus
With the gain/phase plot in hand, a loop crossover frequency can be chosen. Usually the curves look something
like Figure 5. Choose the crossover frequency in the rising
or flat parts of the phase curve, beyond the external LC
poles. Frequencies between 10kHz and 50kHz usually
work well. Note the gain (GAIN, in dB) and phase (PHASE,
in degrees) at this point. The desired feedback amplifier
gain will be -GAIN to make the loop gain at 0dB at this
frequency. Now calculate the needed phase boost, assuming 60° as a target phase margin:
BOOST = – (PHASE + 30°)
If the required BOOST is less than 60°, a Type 2 loop can
be used successfully, saving two external components.
BOOST values greater than 60° usually require Type 3
loops for satisfactory performance.
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Finally, choose a convenient resistor value for R1 (10k is
usually a good value). Now calculate the remaining values:
(K is a constant used in the calculations)
f = chosen crossover frequency
G = 10(GAIN/20) (this converts GAIN in dB to G in
absolute gain)
TYPE 2 Loop:
 BOOST

K = Tan
+ 45°
 2

1
2πfGKR1
C1 = C 2 K2 − 1
C2 =
(
)
K
2πfC1
VREF (R1)
RB =
VOUT − VREF
R2 =
TYPE 3 Loop:
 BOOST

K = Tan2 
+ 45°
 4

1
2πfGR1
C1 = C 2 K − 1
C2 =
( )
K
2πfC1
R1
R3 =
K −1
1
C3 =
2πf KR3
VREF (R1)
RB =
VOUT − VREF
R2 =
CURRENT LIMIT PROGRAMMING
Programming current limit on the LTC1705 is straightforward. The IMAX pin sets the current limit by setting the
maximum allowable voltage drop across QB (the bottom
MOSFET) before the current limit circuit engages. The
voltage across QB is set by its on-resistance and the
current flowing in the inductor, which is the same as the
output current. The LTC1705 current limit circuit inverts
the negative voltage across QB before comparing it with
the voltage at IMAX, allowing the current limit to be set with
a positive voltage.
To set the current limit, calculate the expected voltage
drop across QB at the maximum desired current:
VPROG = (ILIMIT) (RDS(ON))
ILIMIT should be chosen to be quite a bit higher than the
expected operating current, to allow for MOSFET RDS(ON)
changes with temperature. Setting ILIMIT to 150% of the
maximum normal operating current is usually safe and will
adequately protect the power components if they are
chosen properly. Note that the ringing on the switch node
can cause error for the current limit threshold. This factor
will change depending on the layout and the components
used. VPROG is then programmed at the IMAX pin using the
internal 10µA pull-up and an external resistor:
RIMAX = VPROG/10µA
The resulting value of RIMAX should be checked in an
actual circuit to ensure that the current circuit kicks in as
expected. MOSFET RDS(ON) specs are like horsepower
ratings in automobiles and should be taken with a grain of
salt. Circuits that use very low values for RIMAX (<10k)
should be checked carefully, since small changes in RIMAX
can cause large ILIMIT changes when the switch node
ringing makes up a large percentage of the total VPROG
value. If VPROG is set too low, the LTC1705 may fail to start
up.
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Accuracy Trade-Offs
OPTIMIZING PERFORMANCE
The VDS sensing scheme used in the LTC1705 is not
particularly accurate, primarily due to uncertainty in the
RDS(ON) from MOSFET to MOSFET. A second error term
arises from the ringing present at the SW pin, which
causes the VDS to look larger than (ILOAD)(RDS(ON)) at the
beginning of QB’s on-time. These inaccuracies do not
prevent the LTC1705 current limit circuit from protecting
itself and the load from damaging overcurrent conditions,
but they do prevent the user from setting the current limit
to a tight tolerance if more than one copy of the circuit is
being built. The 50% factor in the current setting equation
above reflects the margin necessary to ensure that the
circuit will stay out of current limit at the maximum normal
load, even with a hot MOSFET that is running quite a bit
higher than its RDS(ON) spec.
2-Step Conversion
VCLK LINEAR REGULATOR
The LTC1705 monolithic LDO linear regulator is easy to
use. Input and output supply bypass capacitors are the
only two external components required for this LDO. The
VINCLK pin powers up the regulator and an internal P-channel
MOS transistor sources at least 150mA of current at a
fixed output voltage of 2.5V. This device is short-circuit
protected and includes thermal shutdown to turn off all
three regulator outputs should the junction temperature
exceed about 155°C.
The circuit design in the LTC1705 requires the use of an
output capacitor as part of the frequency compensation. A
minimum output capacitor of 2.2µF and ESR larger than
100mΩ is recommended to prevent oscillations. Larger
values of output capacitance decrease the peak deviations
and provide improved transient response for large load
current changes. Many different types of capacitors are
available and have widely varying characteristics. These
capacitors differ in capacitor tolerance (sometimes ranging up to ±100%), equivalent series resistance, equivalent
series inductance and capacitance temperature coefficient. In a typical operating condition, a 10µF solid tantalum at the VOUTCLK pin ensures stability. The AVX
TPSD106M035R0300 or equivalent works well in this
application.
22
The LTC1705 is ideally suited for use in 2-step conversion
systems. 2-step systems use a primary regulator to convert the input power source (batteries or AC line voltage)
to an intermediate supply voltage, often 5V. The LTC1705
then converts the intermediate voltage to the lower voltage, high current supplies required by the system. Compared to a 1-step converter that converts a high input
voltage directly to a very low output voltage, the 2-step
converter exhibits superior transient response, smaller
component size and equivalent efficiency. Thermal management and layout complexity are also improved with a
2-step approach.
A typical notebook computer supply might use a 4-cell LiIon battery pack as an input supply with a 15V nominal
terminal voltage. The logic circuits require 5V/3A and
3.3V/5A to power system board logic and 2.5V/0.15A,
1.5V/2A and 1.3V/15A to power the CPU. A typical 2-step
conversion system would use a step-down switcher (perhaps an LTC1628 or two LTC1625s) to convert 15V to 5V
and another to convert 15V to 3.3V (Figure 10). The 3.3V
input supply can power the 1.3V output at the LTC1705
core channel and the 2.5V LDO. The 5V input supply can
power the 1.5V I/O channel. The corresponding 1-step
system would use four similar step-down switchers plus
an LDO, each switcher using 15V as the input supply and
generating one of the four output voltages.
Clearly, the 5V and 3.3V sections of the two schemes are
equivalent. The 2-step system draws additional power
from the 5V and 3.3V outputs, but the regulation techniques and trade-offs at these outputs are similar. The
difference lies in the way the 1.5V and 1.3V supplies are
generated. For example, the 2-step system converts 3.3V
to 1.3V with a 39% duty cycle. During the QT on-time, the
voltage across the inductor is 2V and during the QB ontime, the voltage is 1.3V, giving roughly symmetrical
transient response to positive and negative load steps. The
2V maximum voltage across the inductor allows the use of
a small 0.47µH inductor while keeping ripple current to 3A
(20% of the 15A maximum load). By contrast, the 1-step
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converter is converting 15V to 1.3V, requiring just a 9%
duty cycle. Inductor voltages are now 13.7V when QT is on
and 1.3V when QB is on, giving vastly different di/dt values
and correspondingly skewed transient response with positive and negative current steps. The narrow 9% duty cycle
usually requires a lower switching frequency, which in
turn requires a higher value inductor and larger output
capacitor. Parasitic losses due to the large voltage swing
at the source of QT cost efficiency, eliminating any advantage the 1-step conversion might have had.
Note that power dissipation in the LTC1705 portion of a
2-step circuit is lower than it would be in a typical 1-step
converter, even in cases where the 1-step converter has
higher total efficiency than the 2-step system. In a typical
microprocessor core supply regulator, for example, the
regulator is usually located right next to the CPU. In a
1-step design, all of the power dissipated by the core
regulator is right there next to the hot CPU, aggravating
thermal management. In a 2-step LTC1705 design, a
significant percentage of the power lost in the core regulation system happens in the 5V or 3.3V supply, which is
usually away from the CPU. The power lost to heat in the
LTC1705 section of the system is relatively low, minimizing the heat near the CPU.
Additionally, with a 1-step converter, the high input battery
voltage requires the MOSFET to operate at high voltage
levels. This imposes stringent requirements on the
MOSFETs selection. Most of the MOSFETs that meet the
high voltage and high current requirements are expensive
and bulky. This makes for an awkward power supply
design, especially in portable applications. The high input
voltage also necessitates higher gate drive, which aggravate switching losses.
LTC1628*
5V/3A LOGIC SUPPLY
3.3V/5A LOGIC SUPPLY
I/O
CORE
LDO
LTC1705
CPU SUPPLY CONTROLLER
1.5V/2A CPU I/O SUPPLY
1.3V/15A CPU CORE SUPPLY
2.5V/0.15A CPU CLOCK SUPPLY
*OR TWO LTC1625s
2-STEP CONVERSION OFFERS
• BETTER TRANSIENT RESPONSE
• SMALLER COMPONENT SIZE
• BETTER THERMAL MANAGEMENT
• LOWER VOLTAGE REQUIREMENT FOR MOSFETS
• SMALLER SWITCHING LOSS
• EQUIVALENT EFFICIENCY
1705 F10
Figure 10. 2-Step Conversion Block Diagram
23
LTC1705
U
W
U
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APPLICATIO S I FOR ATIO
2-Step Efficiency Calculation
Calculating the efficiency of a 2-step converter system
involves some subtleties. Simply multiplying the efficiency of the primary 5V or 3.3V supply by the efficiency
of the 1.5V or 1.3V supply under estimates the actual
efficiency, since a significant fraction of the total power is
drawn from the 3.3V and 5V rails in a typical system. The
correct way to calculate system efficiency is to calculate
the power lost in each stage of the converter and divide the
total output power from all outputs by the sum of the
output power plus the power lost:
Efficiency =
Total Output Power
(100%)
Total Output Power + Total Output Lost
In our example 2-step system, the total output power is:
Total Output Power =
15W + 16.5W + 0.375W + 3W + 19.5W = 54.375W
(corresponding to 5V, 3.3V, 2.5V, 1.5V and
1.3V output voltages)
Assuming the LTC1705 provides 90% efficiency at the
core and I/O channels, and 75% efficiency at the LDO, the
additional loads on the 5V and 3.3V supplies are:
1.3V: 19.5W/90% =21.67W
⇒ 6.6A from 3.3V
1.5V: 3W/90% =3.3W
⇒ 0.66A from 5V
2.5V: 0.375W/75% =0.5W
⇒ 0.152A from 3.3V
24
If the 5V and 3.3V supplies are each 94% efficient, the
power lost in each supply is:
1.3V: 21.67W – 19.5W
= 2.17W
1.5V: 3.3W – 3W
= 0.3W
2.5V: 0.5W – 0.375W
= 0.125W
3.3V: 16.5W + 3.3V(6.6A + 0.152A) = 38.78W Load
(38.78W/94%) – 38.78W
= 2.48W Lost
5V: 15W + 5V(0.66A)
(18.3W/94%) – 18.3W
= 18.3W Load
= 1.17W Lost
Total Loss
= 6.25W
Total System Efficiency =
54.375W/(54.375W + 6.25W) = 89.7%
Maximizing High Load Current Efficiency
Efficiency at high load currents is primarily controlled by
the resistance of the components in the power path (QT,
QB, LEXT ) and power lost in the gate drive circuits due to
MOSFET gate charge. Maximizing efficiency in this region
of operation is as simple as minimizing these terms.
The behavior of the load over time affects the efficiency
strategy. Parasitic resistances in the MOSFETs and the
inductor set the maximum output current the circuit can
supply without burning up. A typical efficiency curve
shows that peak efficiency occurs near 30% of this maximum current. If the load current will vary around the
efficiency peak and will spend relatively little time at the
maximum load, choosing components so that the average
load is at the efficiency peak is a good idea. This puts the
maximum load well beyond the efficiency peak, but usually gives the greatest system efficiency over time, which
translates to the longest run time in a battery-powered
system. If the load is expected to be relatively constant at
the maximum level, the components should be chosen so
that this load lands at the peak efficiency point, well below
the maximum possible output of the converter.
LTC1705
U
W
U
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APPLICATIO S I FOR ATIO
REGULATION OVER COMPONENT TOLERANCE/
TEMPERATURE
DC Regulation Accuracy
The LTC1705 initial DC output accuracy depends mainly
on internal reference accuracy, op amp offset and internal
or external resistor accuracy. Two LTC1705 specs come
into play: VSENSEC voltage and feedback voltage line regulation. The VSENSEC voltage spec is within ±1.25% for all
VID codes over the full temperature range, which encompasses reference accuracy, error amplifier offset and the
input resistor divider mismatch. The feedback voltage line
regulation spec adds an additional 0.1%/V term that
accounts for change in reference output with change in
input supply voltage. With a 5V supply, the errors contributed by the LTC1705 itself add up to less than 1.5% DC
error at the output.
At the I/O side, the output voltage setting resistors (R1 and
RB in Figure 3) are the other major contributor to DC error.
At a typical 1.xV output voltage, the resistors are of
roughly the same value, which tends to halve their error
terms, improving accuracy. Still, using 1% resistors for
R1 and RB will add 1% to the total output error budget.
Using 0.1% resistors in just those two positions can nearly
halve the DC output error for very little additional cost.
Load Regulation
Load regulation is affected by feedback amplifier gain and
external ground drops in the feedback path. A full-range
load step might require a 10% duty cycle change to keep
the output constant, requiring the COMP pin to move
about 100mV. With amplifier gain at 85dB, this adds up to
only a 10µV shift at FB, negligible compared to the reference accuracy terms.
External ground drops aren’t so negligible. The LTC1705
can sense the positive end of the output voltage by
attaching the feedback resistor directly at the load, but it
cannot do the same with the ground lead. Just 0.001Ω of
resistance in the ground lead at 15A load will cause a 15mV
error in the output voltage—as much as all the other DC
errors put together. Proper layout becomes essential to
achieving optimum load regulation from the LTC1705. A
properly laid out LTC1705 circuit should move not more
than one to two millivolts at the output from zero to full
load.
Transient Response
Transient response is the other half of the regulation
equation. The LTC1705 can keep the DC output voltage
constant to within 1% when averaged over hundreds of
cycles. Over just a few cycles, however, the external
components conspire to limit the speed that the output
can move. Consider our typical 5V to 1.5V circuit, subjected to a 1A to 5A load transient. Initially, the loop is in
regulation and the DC current in the output capacitor is
zero. Suddenly, an extra 4A start flowing out of the output
capacitor while the inductor is still supplying only 1A. This
sudden change will generate a (4A)(RESR )voltage step at
the output; with a typical 0.015Ω output capacitor ESR,
this is a 60mV or 4% (for a 1.5V output voltage) step at the
output!
Very quickly, the feedback loop will realize that something
has changed and will move at the bandwidth allowed by
the external compensation network towards a new duty
cycle. If the bandwidth is set to 50kHz, the COMP pin will
get to 60% of the way to 90% duty cycle in 3µs. Now the
inductor is seeing 3.5V across itself for a large portion of
the cycle and its current will increase from 1A at a rate set
by di/dt = V/L. If the inductor value is 0.5µH, the peak di/dt
will be 3.5V/0.5µH or 7A/µs. Sometime in the next few
micro-seconds after the switch cycle begins, the inductor
current will have risen to the 5A level of the load current
and the output voltage will stop dropping. At this point, the
inductor current will rise somewhat above the level of the
output current to replenish the charge lost from the output
capacitor during the load transient. During the next couple
of cycles, the MIN comparator may trip on and off,
preventing the output from falling below its -5% threshold
until the time constant of the compensation loop runs out
and the main feedback amplifier regains control. With a
properly compensated loop, the entire recovery time will
be inside of 10µs.
25
LTC1705
U
TYPICAL APPLICATIO S
Most loads care only about the maximum deviation from
ideal, which occurs somewhere in the first two cycles after
the load step hits. During this time, the output capacitor
does all the work until the inductor and control loop regain
control. The initial drop (or rise if the load steps down) is
entirely controlled by the ESR of the capacitor and amounts
to most of the total voltage drop. To minimize this drop,
reduce the ESR as much as possible by choosing low ESR
capacitors and/or paralleling multiple capacitors at the
output. The capacitance value accounts for the rest of the
voltage drop until the inductor current rises. With most
output capacitors, several devices paralleled to get the
ESR down will have so much capacitance that this drop
term is negligible. Ceramic capacitors are an exception; a
small ceramic capacitor can have suitably low ESR with
relatively small values of capacitance, making this second
drop term significant.
Optimizing Loop Compensation
Loop compensation has a fundamental impact on transient recovery time, the time it takes the LTC1705 to
recover after the output voltage has dropped due to output
capacitor ESR. Optimizing loop compensation entails
maintaining the highest possible loop bandwidth while
ensuring loop stability. The feedback component selection
section describes in detail the techniques used to design
an optimized Type 3 feedback loop, appropriate for most
LTC1705 systems.
doesn’t cause a bigger spike than the transient signal
being measured. Conveniently, the typical probe tip ground
clip is spaced just right to span the leads of a typical output
capacitor.
Now that we know how to measure the signal, we need to
have something to measure. The ideal situation is to use
the actual load for the test and switch it on and off while
watching the output. If this isn’t convenient, a current step
generator is needed. This generator needs to be able to
turn on and off in nanoseconds to simulate a typical
switching logic load, so stray inductance and long clip
leads between the LTC1705 and the transient generator
must be minimized.
Figure 11 shows an example of a simple transient generator. Be sure to use a noninductive resistor as the load
element—many power resistors use an inductive spiral
pattern and are not suitable for use here. A simple solution
is to take ten 1/4W film resistors and wire them in parallel
to get the desired value. This gives a noninductive resistive
load which can dissipate 2.5W continuously or 50W if
pulsed with a 5% duty cycle, enough for most LTC1705
circuits. Solder the MOSFET and the resistor(s) as close to
the output of the LTC1705 circuit as possible and set up
the signal generator to pulse at a 100Hz rate with a 5% duty
cycle. This pulses the LTC1705 with 500µs transients10ms
apart, adequate for viewing the entire transient recovery
time for both positive and negative transitions while keeping the load resistor cool.
Measurement Techniques
Measuring transient response presents a challenge in two
respects: obtaining an accurate measurement and generating a suitable transient to use to test the circuit. Output
measurements should be taken with a scope probe directly across the output capacitor. Proper high frequency
probing techniques should be used. In particular, don’t
use the 6" ground lead that comes with the probe! Use an
adapter that fits on the tip of the probe and has a short
ground clip to ensure that inductance in the ground path
26
LTC1705
VOUT
RLOAD
IRFZ44 OR
EQUIVALENT
PULSE
GENERATOR
50Ω
0V TO 10V
100Hz, 5%
DUTY CYCLE
1705 F11
LOCATE CLOSE TO THE OUTPUT
Figure 11. Transient Load Generator
LTC1705
U
PACKAGE DESCRIPTIO
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
0.386 – 0.393*
(9.804 – 9.982)
28 27 26 25 24 23 22 21 20 19 18 17 1615
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
0.015 ± 0.004
× 45°
(0.38 ± 0.10)
0.0075 – 0.0098
(0.191 – 0.249)
0.033
(0.838)
REF
2 3
4
5 6
7
8
9 10 11 12 13 14
0.053 – 0.069
(1.351 – 1.748)
0.004 – 0.009
(0.102 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.008 – 0.012
(0.203 – 0.305)
0.0250
(0.635)
BSC
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
GN28 (SSOP) 1098
27
LTC1705
U
TYPICAL APPLICATIO
Complete 2-Step Notebook Power Supply
STDBY5V
+
0.22µF
D5
MBRD
835L
+
23
Q3
10Ω
1000pF
105k
1%
20k
1%
180pF
0.1µF
330pF
LTC1628
SENSE2–
EXTVCC
PGND
VOSENSE1
VOSENSE2
RUN/SS1
RUN/SS2
ITH1
ITH2
33k
9
L5, 0.33µH
D03316P-331HC
QT1B
L3
0.68µH
10µF
6.3V
+
1000pF
13
10Ω
20
63.4k
1%
100pF
12
15
11
180µF
4V
VOUT2
3.3V
5A
20k
1%
47pF
3.3VENABLE
180pF
0.1µF
SGND
3.3VOUT
STBYMD
10
STDBY3.3V
0.1µF
6
STDBYMD
180µF
4V
×6
1µF
D5
MBRD
835L
QB1A
2
22
PVCC
5
TGC
3
BOOSTC
PGOOD
6
19
VCC
26
TGIO
27
BOOSTIO
SWC
SWIO
BGC
BGIO
1µF
D7
MBR
0520LT1
QT2
L4
3µH
1µF
25
QB1B
4
27k
8
11
1.8k
10µF
10Ω
5k
13
1800pF
D4
MBRS
130T3
Q4
10Ω
330pF
D6
MBR0520LT1
QT1A
1µF
19
10mΩ
0.01µF
1µF
+
L2
4.6µH
0.1µF
17
33k
+
VOUTC
0.9V TO 2V
15A
Q5
14
SENSE2+
5
FREQSET
7
FCB
28
FLTCPL
0.1µF
150µF
6.3V
×2
BG2
SENSE1 –
8
5VENABLE
BG1
SENSE1+
1
47pF
SW2
3
4
16
TG2
18
BOOST2
SW1
2
22
10Ω
100pF
24
+
150µF
6.3V
×2
26
VIN
7V TO 20V
CIN
22µF
50V
VIN
INTVCC
27
TG1
25
BOOST1
10µF
6.3V
VOUT1
5V
4A
21
Q2
L1
2.9µH
0.1µF
D2
50V CMDSH-3
10Ω
D1
CMDSH-3
Q1
4mΩ
1µF
4.7µF
0.1µF
50V
+
0.1µF
50V
1800pF
330pF
9
11k
Q1, Q2, Q3: IRF7805
COREENABLE
Q4, Q5: IRF7807
L1: ETQP6F2R9L
L2: ETQP6F4R6H
QT1A, QT1B, QB1A, QB1B: FAIRCHILD FDS6670A
QT2, QB2: NDS8926
L3: SUMIDA CEP125-4712-T007
L4: SUMIDA CDRH6D28-3R0
10
0.1µF
7
12
LTC1705
IMAXC
IMAXIO
SENSEC
COMPIO
FBC
FBIO
COMPC
RUN/SS
VINCLK
28
QB2
16k
1
VID0
VOUTCLK
VID1
VID2
VID3
VID4
14
15
16
17
18
VID0 VID1 VID2 VID3 VID4
+
1µF
VOUTIO
1.5V
3A
11k
21
100pF
20
2200pF
10k
1%
8.87k
1%
24
+
PGND
GND
100µF
4V
×2
10µF
10V
23
+
10µF
1µF
VOUTCLK
2.5V
150mA
10V
1705 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1628/LTC1628-PG Dual High Efficiency 2-Phase Synchronous Step-Down Controller
Constant Frequency, Standby 5V and 3.3V LDOs,
3.5V ≤ VIN ≤ 36V
LTC1703
Dual 550kHz Synchronous 2-Phase Switching Regulator
Controller with VID
Mobile VID Control with 25MHz GBW Voltage Mode, VIN ≤ 7V
LTC1708
Dual, 2-Phase Synchronous Step-Down Controller with 5-Bit VID
Mobile CPU VID, Dual Output 3.5V ≤ VIN ≤ 36V,
Minimum CIN and COUT
LTC1736
Synchronous Step-Down Controller with 5-Bit VID Control
Output Fault Protection, Power Good Output, 3.5V to 36V Input
28
Linear Technology Corporation
1705fa LT/TP 0801 1.5K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2001