EMC EM73866 4-bit micro-controller for lcd product Datasheet

EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
GENERAL DESCRIPTION
EM73866 is an advanced single chip CMOS 4-bit micro-controller. It contains 8K-byte ROM, 500-nibble RAM,
4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel function.
EM73866 also contains 6 interrupt sources, 2 input port, 7 bidirection ports, Max LCD display (32x4), built-in
watch-dog-timer and high speed Timer/Counter.
EM73866 has plentiful operating modes (SLOW, IDLE, STOP) intended to reduce the power consumption.
FEATURES
• Operation voltage
• Clock source
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
: 2.2V ~ 6V.
: Dual clock system. Low-frequency oscillator is Crystal or RC oscillator (32K Hz,
connect an external resistor) by mask option and high-frequency oscillator is RC
(Connect an external resistor) or Crystall oscillator.
Instruction set
: 107 powerful instructions.
Instruction cycle time : Up to 2us for 4 MHz (high speed clock).
244 µs for 32768 Hz (low speed clock).
122 µs for 32768 Hz (low speed clock with frequency Double)
ROM capacity
: 8192 X 8 bits.
RAM capacity
: 500 X 4 bits.
Input port
: 2 ports (P0, P2), P0(0..3), P2 (0..3), IDLE/STOP releasing function are available
by mask option.
Bidirection port
: 7 ports (P1, P3, P4, P5, P6, P7, P8). P4.1 is shared with HTC external input.
IDLE/STOP releasing function are available by mask option for P8(0..3).
12-bit timer/counter : Two 12-bit timer/counters are programmable for timer, event counter and pulse width
measurement.
Built-in watch-dog-timer : It is available by mask option.
Built-in time base counter : 22 stages.
Built-in high Speed Timer/Counter : Could be timer, melody out or pulse width measurement.
Subrountine nesting : Up to 13 levels.
Interrupt
: External . . . . . 2 input interrupt sources.
Internal . . . . . . 2 Timer overflow interrupts, 1 time base interrupt.
1 high speed counter overflow interrupt.
LCD driver
: Max 32 X 4 dots, 1/4, 1/3, 1/2 static four kinds of duty selectable, 1/2 or 1/3 bias choice
and dynamic resistor available.
Power saving function :SLOW, IDLE, STOP operation mode.
Package type
: Chip form 76 pins.
APPLICATIONS
EM73866 is suitable for application in family applicance, consumer products, hand held games, calculator and
the toy controller.
* This specification are subject to be changed without notice.
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FUNCTION BLOCK DIAGRAM
VDD
RESET
XOUT XIN
LXOUT LXIN
Sleep Mode
Control
Timing
Generator
Clock
Generator
(slow)
Clock
Generator
Reset
Control
System Control
Data pointer
Time
Base
Timer/Counter
(TA,TB)
TEST
V1
V2
V3
Instruction Decoder
Instruction Register
ROM
Stack pointer
ACC
Data Bus
Interrupt
Control
Stack
ALU
RAM
Flag
Z
C
S
HR
LR
P0(0..3)/WAKEUP(0..3)
PC
P2(0..3)/WAKEUP(4..7)
I/O Control
LCD
P4(0..3) /WAKEUP(P8..11)
VRLC
VSS
P8(0,2)(INT1,0)/
WAKEUPA,C
P6.0 - P6.1
P3.0 - P3.3
P1.0 - P1.1
SEG0~SEG29
COM0~COM3
P5(0..3) /WAKEUP(P12..15)
P7.0 /WAKEUPD
PIN DESCRIPTIONS
Symbol
Pin-type
Function
V DD
VSS
RESET
Power supply (+)
Power supply (-)
RESET-A
System reset input signal, low active
mask option : none
pull-up
XIN/RCOSC
OSC-A/OSC-H1 Crystal/RC clock source connecting pin
XOUT
OSC-A
Crystal connecting pin
LXIN
OSC-B/OSC-H2 Crystal/RC connecting pin for low speed clock source
LXOUT
OSC-B
Crystal connecting pin for low speed clock source
P0(0..3)/WAKEUP(0..3) INPUT-K
8-bit input pins with IDLE/STOP releasing function
P2(0..3)/WAKEUP(4..7)
mask option : wakeup enable, negative edge release, pull-up
wakeup enable, negative edge release, none
wakeup enable, positive edge release, pull-down
wakeup enable, positive edge release, none
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none
P1(0..1)
I/O-Z
2-bit bidirection I/O pins with high current function source
mask option 1: initial low
initial high
mask option 2: low current push-pull
normal current push-pull
high current push-pull
NMOS open-drain
PMOS open-drain
* This specification are subject to be changed without notice.
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PIN DESCRIPTIONS
Symbol
Pin-type
P3(0,1)/SEG(30,31)
I/O-O
P3(2,3), P6(0,1)
I/O-N
P4.0/SOUND/WAKEUP8 I/O-R1
P4.1(TRGH)/WAKEUP9 I/O-R1
P4(2,3)/WAKEUP(10,11) I/O-R1
P5(0..3)/WAKEUP(12..15) I/O-S
P7.0/TRGA/WAKEUPD
P8.1/TRGB/WAKEUPB
I/O-S
Function
2-bit bidirection I/O pins are shared with LCD segment pin
mask option : segment pin
low current push-pull
normal current push-pull
open-drain
4-bit bidirection I/O pins
mask option : low current push-pull
normal current push-pull
open-drain
1-bit bidirection I/O with inverse sound output and IDLE/STOP
releasing function.
mask option : wakeup disable, low current push-pull
wakeup disable, normal current push-pull
wakeup disable, high current push-pull
wakeup disable, open-drain
wakeup disable, SOUND
wakup enable, low current push-pull
wakeup enable, normal current push-pull
1-bit bidirection I/O with HTC output and IDLE/STOP releasing
function.
mask option : wakeup disble, low current push-pull
wakeup disable, normal current push-pull
wakeup disable, high current push-pull
wakeup disable, NMOS open-drain
wakeup disable, PMOS open-drain
wakeup enable, low current push-pull
wakeup enable, normal current push-pull
2-bit bidirection I/O pins with IDLE/STOP releasing function
mask option : wakeup disble, low current push-pull
wakeup disable, normal current push-pull
wakeup disable, high current push-pull
wakeup disable, NMOS open-drain
wakeup disable, PMOS open-drain
wakeup enable, low current push-pull
wakeup enable, normal current push-pull
4-bit bidirection I/O pins with IDLE/STOP releasing function
mask option : wakeup disable, low current push-pull
wakeup disable, normal current push-pull
wakeup disable, open-drain
wakeup enable, low current push-pull
wakeup enable, normal current push-pull
2-bit bidirection I/O pins with timer/counterA, B external intput and
IDLE/STOP releasing function
mask option : wakeup disable, low current push-pull
wakeup disable, normal current push-pull
wakeup disable, open-drain
wakeup enable, low current push-pull
wakeup enable, normal current push-pull
* This specification are subject to be changed without notice.
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PIN DESCRIPTIONS
Symbol
P8.0(INT1)/WAKEUPA
P8.2(INT0)/WAKEUPC
Pin-type
I/O-S
COM(0..3)
SEG(0..29)
V1, V2, V3, VRLC
----
Function
2-bit bidirection I/O pins with interrupt 0, 1 external intput and
IDLE/STOP releasing function
mask option : wakeup disable, low current push-pull
wakeup disable, normal current push-pull
wakeup disable, open-drain
wakeup enable, low current push-pull
wakeup enable, normal current push-pull
LCD common pins
LCD segment pins
LCD bias pins
FUNCTION DESCRIPTIONS
PROGRAM ROM ( 8K X 8 bits )
8 K x 8 bits program ROM contains user's program and some fixed data.
The basic structure of the program ROM may be categorized into 5 partitions.
1. Address 0000h: Reset start address.
2. Address 0002h - 000Ch : 6 kinds of interrupt service routine entry addresses.
3. Address 000Eh - 0086h : SCALL subroutine entry address, only available at 000Eh, 0016h, 001Eh, 0026h, 002Eh,
0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh, 0086h.
4. Address 0000h - 07FFh : LCALL subroutine entry address.
5. Address 0000h - 1FFFh : Except used as above function, the other region can be used as user's program and
data region.
* This specification are subject to be changed without notice.
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address
0000h
0002h
0004h
0006h
0008h
000Ah
000Ch
000Eh
0086h
8192 x 8 bits
Reset start address
INT0 ; External interrupt service routine entry address
HTCI; High speed counter interrupt service routine entry address
TRGA; Timer/counterA interrupt serice routine entry address
TRGB; Timer/counterA interrupt serice routine entry address
TBI; Time base interrupt serice routine entry address
INT1; External interrupt serice routine entry address
Subroutine call entry address
designated by [LCALL a]
instruction
SCALL, subroutine call entry address
..
.
07FFh
0800h
0FFFh
1000h
Data table for
[LDAX],[LDAXI]
instruction
1FFFh
DP is a 12-bit data register that stores the program ROM address as pointer for the ROM code data.
User has to initially load ROM address into DP with instructions "STADPL", and "STADPM, STADPH",
then then to obtain the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction
"LDAXI"
PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction.
LDIA #07h;
STADPL
STADPM
STADPH
:
LDL #00h;
LDH #03h;
LDAX
STAMI
LDAXI
STAM
;
ORG 1777h
DATA 56h;
; [DP]L ← 07h
; [DP]M ← 07h
; [DP]H ← 07h, Load DP=777h
; ACC ← 6h
; RAM[30] ← 6h
; ACC ← 5h
; RAM[31] ← 5h
DATA RAM ( 500-nibble )
A total 500-nibble data RAM is available from address 000 to 1FFh. DATA RAM includes the zero page region,
stacks and data areas.
* This specification are subject to be changed without notice.
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Increment
Address
Bank 0
Increment
Zero-page
000h - 00Fh
010h - 01Fh
020h - 02Fh
:
:
:
0C0h - 0CFh
0D0h - 0DFh
0E0h - 0EFh
0F0h - 0F3h
Bank 1
Level 0
Level 1
Level 2
Level 4
Level 5
Level 6
Level 7
Level 8
Level 9
Level 10
Level 11
Level 3
Level 12
100h - 10Fh
110h - 11Fh
:
:
:
:
:
:
1F0h - 1FFh
ZERO- PAGE:
From 000h to 00Fh is the zero-page location. It is used as the zero-page address mode pointer for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".
PROGRAM EXAMPLE: To write immediate data "07h" to RAM [03] and to clear bit 2 of RAM [0Eh].
STD
CLR
#07h, 03h
0Eh,2
; RAM[03] ← 07h
; RAM[0Eh]2 ← 0
STACK:
There are 13 (maximum) stack levels that user can use for subroutine (including interrupt and CALL).
User can assign any level be the starting stack by providing the level number to stack pointer (SP).
When an instruction (CALL or interrupt) is invoked, before enter the subroutine, the previous PC address
is saved into the stack until returned from those subroutines, the PC value is restored by the data saved in stack.
SPECIAL PURPOSE REGISTER:
The instruction concerning with "Timer/counter", "Data Pointer" and "Stack Pointer" at instruction table 14
be sure the RAM bank must be set in Bank0.
DATA AREA:
Except the area used by user's application, the whole RAM can be used as data area for storing and loading
general data.
ADDRESSING MODE
The 500 nibble data memory consists of two banks (bank 0 and bank 1). There are 244x4 bits (address
000h~0F3h) in bank 0 and 256x4 bits (address 100h~1FFh) in bank 1.
* This specification are subject to be changed without notice.
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The bank is selected by P9.3. When P9.3 is cleared to "0", the bank 0 is selected. When P9.3 is set to "1", the bank
1 is selected.
There are 3 addressing mode to access the data memory, namely (1) Indirect addressing mode:
The address in the certain bank is specified by the HL registers.
P9.3
HR
LR
RAM address
PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "032h".
SEP
LDL
LDH
LDAM
CLP
LDL
LDH
STAM
P9,3
#3h
#4h
P9,3
#2h
#3h
; P9.3← 1
; LR← 3
; HR← 4
; Acc← RAM[143h]
; P9.3← 0
; LR← 2
; HR← 3
; RAM[032h]← Acc
(2) Direct addressing mode:
The address in the bank is directly specified by 8 bits code of the second byte in the instruction field.
instruction field
xxxxxxxx
P9.3
xxxxxxxx
RAM address
PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h".
SEP
LDA
CLP
STA
P9,3
43h
P9,3
23h
; P9.3← 1
; Acc← RAM[143h]
; P9.3← 0
; RAM[023h]← Acc
(3) Zero-page addressing mode:
The address is the lower 4 bits code of the second byte in the instruction field.This kind of instructions are
only available for the zero page. Area in bank0, even the P9.3 is set.
instruction field
yyyy
RAM address 0
0000 yyyy
PROGRAM EXAMPLE: Write immediate "0Fh" to RAM address "005h".
STD
#0Fh, 05h
; RAM[05h]← 0Fh
* This specification are subject to be changed without notice.
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PROGRAM COUNTER (8K ROM)
Program counter ( PC ) is composed by a 13-bit counter, which indicates the next executed address for the
instruction of program ROM instruction.
For BRANCH and CALL instructions, PC is changed by instruction indicated. PC can only indicate the address
from 0000h-1FFFh.
(1) Branch instruction:
SBR a
Object code: 00aa aaaa
Condition: SF=1; PC ← PC 12-6.a ( branch condition satisified )
PC Hold original PC value+1
a
a
a
a
a
a
SF=0; PC← PC +1( branch condition not satisified)
PC
Original PC value + 1
LBR a
Object code: 1100 aaaa aaaa aaaa
Condition: SF=1; PC ← PC 12.a ( branch condition satisified )
PC
Hold
+2
a
a
a
a
a
a
a
a
a
a
a
a
SF=0; PC← PC +2( branch condition not satisified)
PC
Original PC value + 2
SLBR a
Object code: 0101 0101 1100 aaaa aaaa aaaa (a:1000h~1FFFh)
0101 0111 1100 aaaa aaaa aaaa (a:0000h~0FFFh)
Condition: SF=1; PC ← a ( branch condition satisified )
PC a
a
a
a
a
a
a
a
a
a
a
a
a
SF=0 ; PC ← PC + 3 ( branch condition not satisified )
PC
Original PC value + 3
(2) Subrountine instruction:
SCALL a
Object code: 1110 nnnn
Condition : PC ← a ; a=8n+6 ; n=1..Fh ; a=86h, n=0
PC 0
0
0
0
0
a
a
a
a
a
* This specification are subject to be changed without notice.
a
a
a
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LCALL a
Object code: 0100 0aaa aaaa aaaa
Condition: PC ← a
PC 0
0
a
a
a
a
a
a
a
a
a
a
a
RET
Object code: 0100 1111
Condition: PC ← STACK[SP]; SP + 1
PC
The return address stored in stack
RT I
Object code: 0100 1101
Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1
PC
The return address stored in stack
(3) Interrupt acceptance operation:
When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into
PC,The interrupt vectors are as following:
INT0 (External interrupt from P8.2)
PC 0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
TRGH (High speed counter interrupt)
PC 0
0
0
0
0
0
TRGA (Timer A overflow interrupt)
PC 0
0
0
0
0
TRGB (Time B overflow interrupt)
PC 0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
TBI (Time base interrupt)
PC 0
0
0
INT1 (External interrupt from P8.0)
PC 0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(4) Reset operation:
PC 0
* This specification are subject to be changed without notice.
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(5) Other operations:
For 1-byte instruction execution: PC + 1
For 2-byte instruction execution: PC + 2
For 3-byte instruction execution: PC + 3
ACCUMULATOR
Accumulator is a 4-bit data register for temporary data. For the arithematic, logic and comparative opertion
.., ACC plays a role which holds the source data and result.
FLAGS
There are 3 kinds of flag, CF ( Carry flag ), ZF ( Zero flag ), SF ( Status flag ), these 3 1-bit flags are affected
by the arithematic, logic and comparative .... operation.
All flags will be put into stack when an interrupt subrountine is served, and the flags will be restored after
RTI instruction executed.
(1) Carry Flag ( CF )
The carry flag is affected by following operation :
a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1", in
another word, if the operation has no carry-out, CF will be "0".
b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow-in, the CF
will be "0", in another word, if no borrow-in, CF will be "1".
c. Comparision : CF is as a borrow-in indicator for Comparision operation as the same as subtraction
operation.
d. Rotation : CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after
rotation.
e. CF test instruction : For TFCFC instruction, the content of CF sends into SF then clear itself "0".
For TTSFC instruction, the content of CF sends into SF then set itself "1".
(2) Zero Flag ( ZF )
ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1", otherwise,
the ZF will be "0".
(3) Status Flag ( SF )
The SF is affected by instruction operation and system status.
a. SF is initiated to "1" for reset condition.
b. Branch instruction is decided by SF, when SF=1, branch condition will be satisified, otherwise, branch
condition will not be satisified by SF = 0.
PROGRAM EXAMPLE:
Check following arithematic operation for CF, ZF, SF
* This specification are subject to be changed without notice.
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CF
-
LDIA #00h;
LDIA #03h;
ADDA #05h;
ADDA #0Dh;
ADDA #0Eh;
ZF
1
0
0
0
0
SF
1
1
1
0
0
ALU
The arithematic operation of 4-bit data is performed in ALU unit. There are 2 flags can be affected by the
result of ALU operation, ZF and SF. The operation of ALU can be affected by CF only.
ALU STRUCTURE
ALU supported user arithematic operation function, including : addition, subtraction and rotaion.
DATA BUS
ALU
ZF CF SF
ALU FUNCTION
(1) Addition:
For instruction ADDAM, ADCAM, ADDM #k, ADD #k,y .... ALU supports additional function.
The additional operation can affect CF and ZF. For additional operation, if the result is "0", ZF will be
"1", otherwise, not equal "0", ZF will be "0". When the addition operation has a carry-out, CF will be "1",
otherwise, CF will be "0".
EXAMPLE:
Operation
3+4=7
7+F=6
0+0=0
8+8=0
Carry
Zero
0
1
0
1
0
0
1
1
(2) Subtraction:
For instruction SUBM #k, SUBA #k, SBCAM, DECM... ALU supports user subtraction function. The
subtraction operation can affect CF and ZF, For subtraction operation, if the result is negative, CF will
be "0", it means a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result
of subtraction operation is "0", the ZF will be "1", otherwise, ZF will be "1".
* This specification are subject to be changed without notice.
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EXAMPLE:
Operation
8-4=4
7-F= -8(1000)
9-9=0
Carry
1
0
1
Zero
0
0
1
(3) Rotation:
There are two kinds of rotation operation, one is rotation left, the other is rotation right.
RLCA instruction rotates Acc value to left, shift the CF value into the LSB bit of Acc and the shift out data
will be hold in CF.
MSB LSB
ACC
CF
RRCA instruction operation rotates Acc value to right, shift the CF value into the MSB bit of Acc and the
shift out data will be hold in CF.
MSB LSB
ACC
CF
PROGRAM EXAMPLE: To rotate Acc right and shift a "1" into the MSB bit of Acc.
TTCFS; CF ← 1
RRCA; rotate Acc right and shift CF=1 into MSB.
HL REGISTER
HL register are two 4-bit registers, they are used as a pair of pointer for the address of RAM memory and also
2 independent temporary 4-bit data registers. For some instruction, L register can be a pointer to indicate the
pin number (Port4).
HL REGISTER STRUCTURE
3 2 1 0
3 2 1 0
H REGISTER L REGISTER
* This specification are subject to be changed without notice.
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HL REGISTER FUNCTION
(1) For instruction : LDL #k, LDH #k, THA, THL, INCL, DECL, EXAL, EXAH, HL register used as a
temporary register.
PROGRAM EXAMPLE: Load immediate data "5h" into L register, "Dh" into H register.
LDL #05h;
LDH #0Dh;
(2) For instruction LDAM, STAM, STAMI.., HL register used as a pointer for the address of RAM memory.
PROGRAM EXAMPLE: Store immediate data #Ah into RAM of address 35h.
LDL #5h;
LDH #3h;
STDMI #0Ah; RAM[35] ← Ah
(3) For instruction : SELP, CLPL, TFPL, L regieter be a pointer to indicate the bit of I/O port.
When LR = 0 indicate P4.0
PROGRAM EXAMPLE: To set bit 0 of Port4 to "1"
LDL #00h;
SEPL ; P4.0 ← 1
STACK POINTER (SP)
Stack pointer is a 4-bit register which stores the present stack level number.
Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition.
When a new subroutine is accepted, the SP will be decreased one automatically, in another word, if
returning from a subroutine, the SP will be increased one.
The data transfer between ACC and SP is by instruction of "LDASP" and "STASP". When "LDASP" and
"STASP" are used, Port 9.3 must be set to 0.
DATA POINTER (DP)
Data pointer is a 12-bit register which stores the address of ROM can indicate the ROM code data
specified by user (refer to data ROM).
When "LDADPL", "LDADPM" and "LDADPH" are used, Port 9.3 must be set to 0.
CLOCK AND TIMING GENERATOR
The clock generator is supported by a dual clock system, the clock source comes from crystal (resonator)
or RC oscillation for both high or low frequency osc. are decided by mask option.
CLOCK GENERATOR STRUCTURE
There are two clock generator for system clock control. P14 is the status register for the CPU status. P16,
P19 and P22 are the system clock mode control ports.
* This specification are subject to be changed without notice.
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Mask option for choose Crystal or RC oscillator
XIN
High-frequency
generator
XOUT
LXIN
Low-frequency
generator
LXOUT
fc
P14
P16
System clock
mode control
fs
P19
P22
Mask option for choose Crystal or RC oscillator
System control
Res
LXIN/XIN
LXIN/XIN
LXOUT/XOUT
LXOUT/XOUT
Crystal connection
or
RC connection
( Res=100K for high frequency osc / Res=1M for slow frequency osc)
SYSTEM CLOCK MODE CONTROL
The system clock mode controller can start or stop the high-frequency and low-frequency clock oscillator
and switch between these two basic clocks. EM73866 has four operation modes (NORMAL, SLOW, IDLE
and STOP operation modes).
STOP
operation
mode
I/O wakeup
High osc : stopped
Low osc : stopped
Command
(P16)
Reset
Reset
Command
(P16)
Command
(P22)
Command
(P22)
Reset release
RESET
operation
High osc : oscillating
Low osc : oscillating
NORMAL
operation
mode
Reset
SLOW
operation
mode
High osc : stopped
Low osc : oscillating
Command
(P19)
Reset
I/O or internal timer wakeup
IDLE
(CPU
stops)
High osc : stopped
Low osc : oscillating
Operation Mode
NORMAL
SLOW
IDLE
STOP
Oscillator
System Clock
High, Low frequency High frequency clock
Low frequency
Low frequency clock
Low frequency
None
CPU stops
CPU stops
* This specification are subject to be changed without notice.
Available function One instruction cycle
LCD, High speed timer
8 / fc
LCD, High speed timer
8 / fs
8 / fs x 2 (freq.Double)
LCD
All disable
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EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
NORMAL OPERATION MODE
The 4-bit µc is in the NORMAL operation mode when the CPU is reseted. This mode is a dual clock system
(high-frequency and low-frequency clocks oscillating). It can be changed to SLOW or STOP operation
mode by the command register (P22 or P16).
LCD display and high speed timer/counter with melody output are available for the NORMAL operation
mode.
SLOW OPERATION MODE
The SLOW operation mode is a single clock system (low-frequency clock oscillating). It can be changed to
the DUAL operation mode by the command register (P22), STOP operation mode by P16 and IDLE
operation mode by P19.
LCD display and high speed timer/counter with melody output are available for the SLOW operation
mode.
P22
3
*
2
SOM
000
001
010
011
1**
P14
3
*
1
SOM
0
Initial value : 0000
Low-frequency
2^3/LXIN RC solw to normal
2^4/LXIN RC solw to normal
2^11/LXIN X'tal slow to normal
2^12/LXIN X'tal slow to normal
normal to slow
2
WKS
1
0
LFS CPUS
With low-frequency double
2^3/LXIN RC solw to normal
2^4/LXIN RC solw to normal
2^11/LXIN X'tal slow to normal
2^12/LXIN X'tal slow to normal
normal to slow
Initial value : *000
LFS
0
1
Low-frequency status
LXIN source is not stable
LXIN source is stable
WKS
0
1
Wakeup status
Wakeup not by internal timer
Wakeup by internal timer
CPUS
0
1
CPU status
NORMAL operation mode
SLOW operation mode
Port14 is the status register for CPU. P14.0 (CPU status) and P14.1 (Low-frequency status) are read-only
bits. p14.2 (wakeup status) will be set to "1" when CPU is wake-up by internal timer. P14.2 will be cleared
to "0" when user out data to P14.
IDLE OPERATION MODE
The IDLE operation mode suspends all SLOW operations except for the low-frequency clock and LCD
driver. It retains the internal status with low power consumption without stopping the clock function and
LCD display.
LCD display is available for the IDLE operation mode. The IDLE operation mode will be wakeup and
return to the SLOW operation mode by the internal timing generator or I/O pins ( P0(0..3)/WAKEUP(0..3),
P2(0..3)/WAKEUP(4..7), P4(0..3)/WAKEUP(8..11), P5(0..3)/WAKEUP(12..15), P7.0/WAKEUPD or P8
(0..2)/WAKEUP(A..C) ).
* This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
P19
3
2
1
IDME
IDME
0 1
* *
Initial value : 0000
0
SIDR
Enable IDLE mode
Enable IDLE mode
Reserved
SIDR
0 0
0 1
1
0
1
1
Select IDLE releasing condition
P0(0..3), P2(0..3), P4(0..3), P5(0..3), P7.0, P8(0..2) pin input
P0(0..3), P2(0..3), P4(0..3), P5(0..3), P7.0, P8(0..2) pin input and 1 sec
signal (0.5 sec with frequency Double)
P0(0..3), P2(0..3), P4(0..3), P5(0..3), P7.0, P8(0..2) pin input and 0.5
sec signal (0.25 sec with frequency Double)
P0(0..3), P2(0..3), P4(0..3), P5(0..3), P7.0, P8(0..2) pin input and 15.
625 ms signal (7.8 ms with frequency Double)
STOP OPERATION MODE
The STOP operation mode suspends system operation and holds the internal status immediately before the
suspension with low power consumption. This mode will be released by reset or I/O pins (P0(0..3)/, P2 (0..
3), P4(0..3), P5(0..3), P7.0 or P8(0..2)).
LCD display and high speed timer/counter with melody output are disabled in STOP mode.
Initial value : 0000
P16 3 2 1 0
SWWT Set wake up
*
Stop wake up time ( go to NORMAL )
* 100
2^9/XIN for RC osc.
*
101
2^10/XIN for RC osc.
*
110
2^18/XIN for Crystal osc.
* 111
2^19/XIN for Crystal osc.
TIME BASE INTERRUPT (TBI )
The time base can be used to generate a fixed frequency interrupt. There are 8 kinds of frequencies can be
selected by setting P25.
P25 3
2
1
0
initial value : 0000
P25
0
0
0
0
0
1
1
1
1
1
0x
10
10
11
11
10
10
11
11
0x
x
0
1
0
1
0
1
0
1
x
Interrupt Rate
Low-frequency
NORMAL mode
SLOW mode
disable
disable
LXIN / 23 Hz
Reserved
LXIN / 24 Hz
Reserved
5
LXIN / 2 Hz
Reserved
LXIN / 214 Hz
LXIN / 214 Hz
LXIN / 21 Hz
Reserved
6
LXIN / 2 Hz
LXIN / 26 Hz
8
LXIN / 2 Hz
LXIN / 28 Hz
10
LXIN / 2 Hz
LXIN / 210 Hz
Reserved
Reserved
* This specification are subject to be changed without notice.
With low-frequency double
NORMAL mode
SLOW mode
disable
disable
LXIN / 22 Hz
Reserved
LXIN / 23 Hz
Reserved
4
LXIN / 2 Hz
Reserved
LXIN / 213 Hz
LXIN / 213 Hz
LXIN / 2 Hz
Reserved
5
LXIN / 2 Hz
LXIN / 25 Hz
7
LXIN / 2 Hz
LXIN / 27 Hz
9
LXIN / 2 Hz
LXIN / 29 Hz
Reserved
Reserved
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TIMER / COUNTER (TIMERA, TIMERB)
Timer/counters can support user three special functions:
1. Even counter
2. Timer.
3. Pulse-width measurement.
These three functions can be executed by 2 timer/counter independently.
For timerA, the counter data is saved in timer register TAH, TAM, TAL, which user can set counter initial
value and read the counter value by instruction "LDATAH(M,L), STATAH(M,L)" and timer register is
TBH, TBM, TBL and W/R instruction "LDATBH (M,L), STATBH (M,L)".
The basic structure of timer/counter is composed by two same structure counter, these two counters can be
set initial value and send counter value to timer register, P28 and P29 are the command ports for timerA
and timer B, user can choose different operation mode and different internal clock rate by setting these two
ports. When timer/counter overflow, it will generate a TRGA(B) interrupt request to interrupt control unit.
INTERRUPT CONTROL
TRGB request
TRGA request
DATA BUS
12 BIT COUNTER
P7.0/
TRGA
internal clock
12 BIT COUNTER
EVENT COUNTER CONTROL
EVENT COUNTER CONTROL
TIMER CONTROL
TIMER CONTROL
PULSE-WIDTH MEASUREMENT
CONTROL
PULSE-WIDTH MEASUREMENT
CONTROL
P28
IPSA
TMSA
P29
TMSB
P8.1/
TRGB
MUX
internal clock
high speed timer/counter
IPSB
TIMER/COUNTER CONTROL
P8.1/TRGB, P7.0/TRGA are the external timer inputs for timerB and timerA, they are used in event
counter and pulse-width measurement mode.
Timer/counter command port: P28 is the command port for timer/counterA and P29 is for the timer/
counterB.
Port 28
Port 29
3
2
1
0
TIMER/COUNTER MODE SELECTION
TMSA IPSA
TMSA (B)
Initial state: 0000
0 0
Stop
0 1
Event counter mode
1 0
Timer mode
1 1
Pulse width measurement mode
3
2
TMSB
1
0
Function description
IPSB
Initial state: 0000
* This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
IPSA
0
0
1
1
0
1
0
1
IPSB
0
0
1
1
0
1
0
1
INTERNAL PULSE-RATE SELECTION
Low-frequency
With low-frequency double
NORMAL mode
SLOW mode
NORMAL mode
SLOW mode
Reserved
LXIN/22 Hz
Reserved
LXIN/23 Hz
LXIN/27 Hz
LXIN/27 Hz
LXIN/26 Hz
LXIN/26 Hz
11
11
10
LXIN/2 Hz
LXIN/2 Hz
LXIN/2 Hz
LXIN/210 Hz
15
15
14
LXIN/2 Hz
LXIN/2 Hz
LXIN/214 Hz
LXIN/2 Hz
INTERNAL PULSE-RATE SELECTION
Low-frequency
With low-frequency double
NORMAL mode
SLOW mode
NORMAL mode
SLOW mode
Depend on high speed timer/counter
Depend on high speed timer/counter
LXIN/25 Hz
LXIN/24 Hz
LXIN/24 Hz
LXIN/25 Hz
9
9
8
LXIN/2 Hz
LXIN/2 Hz
LXIN/2 Hz
LXIN/28 Hz
13
13
12
LXIN/2 Hz
LXIN/2 Hz
LXIN/2 Hz
LXIN/212 Hz
TIMER/COUNTER FUNCTION
Timer/counter A can be programmable for timer, event counter and pulse width measurement. Each timer/
counter can execute any one of these functions independly.
EVENT COUNTER MODE
For event counter mode, timer/counter increases one at any rising edge of P8.1/TRGB for timerB (P7.0/
TRGA for timer A). When timerB (timerA) counts overflow, it will give interrupt control an interrupt request
TRGB (TRGA).
P8.1/TRGB (P7.0/TRGA)
TimerB (TimerA) value n
n+1
n+2
n+3
n+4
n+5
n+6
PROGRAM EXAMPLE: Enable timerA with P28
LDIA
OUTA
#0100B ;
P28
; Enable timerA with event counter mode
TIMER MODE
For timer mode, timer/counter increase one at any rising edge of internal pulse. User can choose 4 kinds of
internal pulse rate by setting IPSB for timerB (IPSA for timerA).
When timer/counter counts overflow, TRGB (TRGA) will be generated to interrupt control unit.
Internal pulse
TimerB (TimerA )value
n
n+1
* This specification are subject to be changed without notice.
n+2
n+3
n+4
n+5
n+6
n+7
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
PROGRAM EXAMPLE: To generate TRGA interrupt request after 60 ms with system clock LXlN=32KHz
LDIA
EXAE
EICIL
LDIA
STATAL
LDIA
STATAM
LDIA
STATAH
LDIA
OUTA
#0100B ;
; enable mask 2
110111B ; interrupt latch ←0, enable EI
#0AH ;
;
#00H
;
;
#0FH ;
;
#1000B ;
P28
; enable timerA with internal pulse rate: LXIN/23 Hz
NOTE:
The preset value of timer/counter register is calculated as following procedure.
Internal pulse rate: LXIN/23 ; LXIN = 32KHz
The time of timer counter count one = 23 /LXIN = 8/32768=0.244ms
The number of internal pulse to get timer overflow = 60 ms/ 0.244ms = 245.901= 0F6H
The preset value of timer/counter register = 1000H - 0F6H = 0F0AH
PULSE WIDTH MEASUREMENT MODE
For the pulse width measurement mode, the counter only incresed by the rising edge of internal pulse rate
as external timer/counter input (P8.1/TRGB, P7.0/TRGA ), interrupt request will be generated as soon as
timer/counter count overflow.
P8.1/TRGB(P8.3/TRGA)
Internal pulse
TimerB(TimerA) value
n
n+1
n+2
n+3
n+4
n+5
PROGRAM EXAMPLE: Enable timerA by pulse width measurement mode.
LDIA
OUTA
#1100b ;
P28
; Enable timerA with pulse width measurement mode.
HIGH SPEED TIMER/COUNTER
EM73866 has one 8-bit high speed timer/counter (HTC). It supports three special functions : auto load timer,
melody output and pulse width measurement modes. The HTC is available for the NORMAL and SLOW
operation mode.
The HTC can be set initial value and send counter value to counter registers (P11 and P10), P31 is the
command port for HTC, user can choose different operation mode and different internal clockrate by setting
the port. The timer/counter increase one at the rising edge of internal pulse. The HTC can generate an overflow
interrupt (HTCI) when it overflows. The HTCI cannot be generated when the HTC is in the melody mode
or disabled.
* This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Output data
Ö2
FHTC
P4.0/SOUND
P31(3,2)
8-bit binary counter
mask option
P31(1,0)
XIN
Overflow
HTCI interrupt
Timer/counter B
Reload
P11
P10
Input data
P4.1/TRGH
Data bus
P31 is the command register of the 8-bit high speed timer/counter.
2
1
0
Initial value : 0000
P31 3
HTMS
HTMS
0 0
0 1
1 0
1 1
HIPS
0
0
1
1
0
1
0
1
HIPS
Mode selection
Stop
Auto load timer mode
Melody mode
Pulse width measurement mode
CLOCK RATE SELECTION
Low-frequency
With low-frequency double
NORMAL mode
SLOW mode
NORMAL mode
SLOW mode
LXIN/20 Hz
LXIN/20 Hz
2xLXIN Hz
2xLXIN Hz
2
2
1
LXIN/2 Hz
LXIN/2 Hz
LXIN/2 Hz
LXIN/21 Hz
4
3
RCIN/2 Hz
Reserved
RCIN/2 Hz
Reserved
RCIN/26 Hz
Reserved
RCIN/25Hz
Reserved
P11 and P10 are the counter registers of the 8-bit high speed timer/counter. P10 is the lower nibble
register and P11 is the higher nibble register. (HT is the value of counter registers.)
P11 3
2
1
0
Higher nibble register
P10
3
2
1
0
Lower nibble register
* This specification are subject to be changed without notice.
Initial value : 0000 0000 (HT)
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
** FHTC=[(XIN/2X)/(100H-HT)]/2, HT=0~255
** Example : LXIN=32K Hz, HIPS=01, HT=11110000B=0F0H.
⇒FHTC=[(32K Hz/22)/(100H-0f0H)]/2=256 Hz.
LDIA
OUTA
LDIA
OUTA
LDIA
OUTA
#1111B
P11
#0000B
P10
#1001B
P31
The value of 8-bit binary up counter can be presetted by P10 and P11. The value of registers can loaded into
the HTC when the counter starts counting or occurs overflow. If user write value to the registers before the
next overflow occurs, the preset value can be changed.
The preset value will be changed when users output the different data to P10 and P11.
The count value of HTC can be read from P10 and P11. The value is unstable when user read the value during
counting. Thus, user must disable the counter before reading the value.
The P4.0/SOUND and SOUND pins will output the squre wave in the melody mode. When the CPU is not
in the melody mode, the P4.0/SOUND is high and SOUND is low.
The P4.1/RGH pin will be the input pin in the pulse width measurement mode. User must output high to P4.1/
TRGH and then it can be the HTC external input pin. When the HTC is disabled, the P4.1 pin is a normal I/
O pin.
INTERRUPTFUNCTION
There are 6 interrupt sources, 2 external interrupt sources, 4 internal interrupt sources. Multiple
interrupts are admitted according the priority.
Type
Interrupt source
External
Internal
Internal
Internal
Internal
External
Priority
External interrupt (INT0)
High speed timer overflow interrupt(HTCI)
TimerA overflow interrupt (TRGA)
TimerB overflow interrupt (TRGB)
Time base interrupt (TBI)
External interrupt(INT1)
Interrupt
Interrupt
Program ROM
Latch Enable condition entry address
1
2
3
4
5
6
IL5
IL4
IL3
IL2
IL1
IL0
EI=1
EI=1, MASK3=1
EI=1, MASK2=1
EI=1, MASK1=1
EI=1,MASK0=1
002H
004H
006H
008H
00AH
00CH
INTERRUPT STRUCTURE
MASK0 MASK1 MASK1 MASK2 MASK3
INT1
r0
Reset by system reset and program
instruction
TBI
r1
TRGB
r2
TRGA
r3
HTCI
r4
INT0
r5
IL1
IL2
IL3
IL4
IL5
IL0
Priority checker
Reset by system reset and program
instruction
Set by program instruction
EI
Interrupt request
* This specification are subject to be changed without notice.
Entry address generator
Interrupt entry address
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Interrupt controller:
IL0-IL5
: Interrupt latch. Hold all interrupt requests from all interrupt sources. ILr can not be
set by program, but can be reset by program or system reset, so IL only can decide
which interrupt source can be accepted.
MASK0-MASK3
EI
: Except INT0 ,MASK register can promit or inhibit all interrupt sources.
: Enable interrupt Flip-Flop can promit or inhibit all interrupt sources, when interrupt happened, EI is cleared to "0" automatically, after RTI instruction happened,
EI will be set to "1" again.
Priority checker: Check interrupt priority when multiple interrupts happened.
INTERRUPT FUNCTION
The procedure of interrupt operation:
1. Push PC and all flags to stack.
2. Set interrupt entry address into PC.
3. Set SF= 1.
4. Clear EI to inhibit other interrupts happened.
5. Clear the IL for which interrupt source has already be accepted.
6. To excute interrupt subrountine from the interrupt entry address.
7. CPU accept RTI, restore PC and flags from stack. Set EI to accept other interrupt requests.
PROGRAM EXAMPLE: To enable interrupt of "INT0, TRGA"
LDIA
EXAE
EICIL
#1100B
;
; set mask register "1100B"
111111B ; enable interrupt F.F.
LCD DRIVER
EM73866 can directly drive the liquid crystal display (LCD) and has max. 32 segment and 4 common output pins.
There are total 32 x 4 dots can be display. The VRLC pin is the LCD driver power input, there is the voltage
of (VCC-VRLC) to LCD.
CONTROL OF LCD DRIVER
The LCD driver control command register is P27. When LDC is 00, the LCD is disabled and changes the duty
only. When LDC is 01, the LCD is blanking, the COM pins are inactive and the SEG pins continuously output
the display data. When LDC is 11, the LCD driver enables, the power switch is turned on and it cannot off
forever except the CPU is reseted or sleeping. User must enable the LCD driver by self when the CPU is waked
up.
Port27
3
2
LDC
LDC
0
0
1
1
0
1
0
1
1
0
Initial value : 0000
DUTY
LCD display control
LCD display disable & change duty
Blanking
Reserved
LCD display enable
* This specification are subject to be changed without notice.
DUTY
0 0
0 1
1 0
1 1
Driving method select
1/4 duty (1/3 bias)
1/3 duty (1/3 bias)
1/2 duty (1/2 bias)
Static
Frame frequency
85 Hz
114 Hz
171 Hz
85 Hz
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EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
The storing region of data RAM for LCD display data.
RAM
COM3
COM2
address
bit3
bit2
SEG0
20H
SEG1
21H
SEG2
22H
:
:
SEG32
3FH
The relation between LCD display data and driving method
Driving method
bit3
bit2
1/4 duty
COM3
COM2
1/3 duty
COM2
1/2 duty
Static
-
bit1
COM1
COM1
COM1
-
COM1
bit1
COM0
bit0
bit0
COM0
COM0
COM0
COM0
PROGRAM EXAMPLE:
LDIA
OUTA
LDIA
OUTA
LDIA
STA
#0000B
P27
; Set LCD duty
#1100B
P27
; Enable LCD
#1010B
24H
LCD driving methods
There are four kinds of driving methods can be selected by DUTY (P27.0~P27.1). Ther are two waveform
types, but for the reason of the number of voltage transition point in type A is greater than type B, so type B
gets a better display performance. The driving waveforms type A and B of LCD driver are as below :
* This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TYPE A :
• 1/4 duty (1/3 bias)
COM0
• 1/3 duty (1/3 bias)
COM0
COM1
COM1
COM2
COM2
• 1/2 duty (1/2 bias)
COM0
• Static
COM0
COM1
COM3
SEG0
SEG0
SEG0
SEG0
OFF
ON
SEG0~COM0
SEG0~COM0
ON
SEG0~COM0
ON
SEG0~COM1
SEG0~COM1
OFF
ON
SEG0~COM1
OFF
Frame
SEG0~COM0
ON
SEG0~COM0
OFF
OFF
Frame
Frame
Frame
TYPE B :
(1) 1/4 duty (1/3 bias)
(2 ) 1/3 duty (1/3 bias)
(3) 1/2 duty (1/2 bias)
(4) static
V3
V2
V1
Vss
V3
V2
V1
Vss
V3
V1
Vss
COM1
V3
V2
V1
Vss
V3
V2
V1
Vss
V3
V1
Vss
COM2
V3
V2
V1
Vss
V3
V2
V1
Vss
COM3
V3
V2
V1
Vss
SEG0
V3
V2
V1
Vss
V3
V2
V1
Vss
V3
V1
Vss
V3
V2
V1
Vss
-V1
-V2
-V3
V3
V2
V1
Vss
-V1
-V2
-V3
V3
V1
Vss
-V1
-V3
V3
V3
V2
V1
Vss
-V1
-V2
-V3
V3
V2
V1
Vss
-V1
-V2
-V3
V3
V1
Vss
-V1
-V3
V3
COM0
SEG0-COM0
ON
SEG0-COM1
OFF
Frame
Frame
Frame
* This specification are subject to be changed without notice.
V3
V1
Vss
ON
OFF
V3
V1
Vss
Vss
-V3
Vss
-V3
Frame
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EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
WATCH-DOG-TIMER (WDT)
Watch-dog-timer can help user to detect the malfunction (runaway) of CPU and give system a timeup signal every
certain time. User can use the time up signal to give system a reset signal when system is fail.
This function is available by mask option. If the mask option of WDT is enabled, it will stop counting when CPU
is reseted or in the STOP operation mode.
The basic structure of Watch-Dog-Timer control is composed by a 4-stage binary counter and a control unit.
The WDT counter counts for a certain time to check the CPU status, if there is no malfunction happened, the
counter will be cleared and continue counting. Otherwise, if there is a malfunction happened, the WDT control
will send a WDT signal (low active) to reset CPU. The WDT checking period is assign by P21 (WDT command
port).
WDT counter
LXIN/213
0
1
2
3
RESET pin
counter clear request
mask option
WDT control
P21
WDT
command port
P21 is the control port of watch-dog-timer, and the WDT time up signal is connected to RESET.
Port 21
CWC
0
1
WDT
0
1
CWC
3
*
2
*
1
0
WDT
Initial value :0000
Clear watchdog timer counter
Clear counter then return to 1
Nothing
SET WATCH-DOG-TIMER DETECT TIME
Low-frequency
With low-frequency double
13
13
12
3 x 2 /LXIN = 3 x 212/32K Hz = 0.375 sec
3 x 2 /LXIN = 3 x 2 /32K Hz = 0.75 sec
13
13
7 x 2 /LXIN = 7 x 2 /32K Hz = 1.75 sec
7 x 212/LXIN = 7 x 212/32K Hz = 0.875 sec
* This specification are subject to be changed without notice.
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EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
PROGRAM EXAMPLE
To enable WDT with 7x213/LXIN detection time.
LDIA #0001B
OUTA P21
; set WDT detection time and clear WDT counter
:
:
RESETTING FUNCTION
When CPU in normal working condition and RESET pin holds in low level for three instruction cycles at least,
then CPU begins to initialize the whole internal states, and when RESET pin changes to high level, CPU begins
to work in normal condition.
The CPU internal state during reset condition is as following table :
Hardware condition in RESET state
Program counter
Status flag
Interrupt enable flip-flop ( EI )
MASK0 ,1, 2, 3
Interrupt latch ( IL )
P10, 11,14, 16, 19, 21, 22, 25, 27, 28, 29, 31
P1, 3, 4, 5, 6, 7, 8
Both oscillator
Initial value
0000h
01h
00h
00h
00h
00h
0Fh
Start oscillation
The RESET pin is a hysteresis input pin and it has a pull-up resistor available by mask option.
The simplest RESET circuit is connect RESET pin with a capacitor to VSS and a diode to VDD.
RESET
* This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
EM73866 I/O PORT DESCRIPTION :
Port
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
E
E
E
E
E
E
E
E
E
I
Input function
Input port , wakeup function
Input port
Input port , wakeup function
Input port
Input port , wakeup function
Input port , wakeup function
Input port
Input port, wakeup function
Input port, wakeup function
-----CPU status
--
Output function
Note
E Output port
-E Output port, shared with segment
E Output port
E Output port, P4.0/SOUND, P4.1(TRGH)
E Output port
E Output port, P7.0(TRGA)
E Output port,P8.0(INT1),P8.1(TRGB),P8.2(INT1)
-I High speed Timer/Counter Register
Low nibble
I High speed Timer/Counter Register
High nibble
--I Clear P14.0 to 0
-I STOP mode control register
--I IDLE mode control register
-I WDT control register
I Slow mode control register
--I Timebase control register
-I LCD control register
I Timer/counter A control register
I Timer/counter B control register
-I HTC control register
E : External port
I : Internal port
* This specification are subject to be changed without notice.
12.29.1999
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EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
ABSOLUTE MAXIMUM RATINGS
Items
Sym.
Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
Storage Temperature
VDD
VIN
VO
PD
T OPR
TSTG
Ratings
Conditions
-0.5V to 6V
-0.5V to VDD+0.5V
-0.5V to VDD+0.5V
300mW
0oC to 50oC
-55oC to 125oC
RECOMMANDED OPERATING CONDITIONS
Items
Supply Voltage
Input Voltage
schmitt circuit
Operating Frequency
Sym.
VDD
VIH
VIL
FC
Fs
Ratings
Min.
Normal
2.2V
Slow
2.2V
Idle
2.2V
Stop
2.0V
0.80xVDD to VDD
0V to 0.20 to VDD
4MHz
32KHz
* This specification are subject to be changed without notice.
TOPR=50oC
Condition
Max.
4MHz by RC osc
6.0V
VDD : 2.0~5.5V
Osc
LXIN, LXOUT (crystal osc)
12.29.1999
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EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
DC ELECTRICAL CHARACTERISTICS (VDD=5±0.5V, VSS=0V, TOPR=25oC)
Parameters
Supply current
Sym.
I DD_Xtal
I DD_RC
Hysteresis voltage
Input
current
V HYS+
V HYSI IH
High current
Normal current I IL
Low current
Output
Voltage
High current
Normal current
VOH1
VOH
VOL
IOH
Low current
Leakage current
ILO
Input resistor
RIN
High Frequency
Variation
Low Frequency
Variation
Min.
Typ.
Max.
Unit
-
1
2
mA
-
100
150
µA
-
80
100
µA
-
0.1
650
1
1000
µA
µA
-
80
120
µA
-
45
70
µA
-
0.1
1
µA
0.50VDD
16
550
24
11
460
22
150
150
70
20
0.75VDD
±1
±1
20
650
28
0.2
14
500
27
1
180
180
90
30
V
V
µA
µA
mA
µA
µA
V
V
V
mA
µA
µA
µA
KΩ
KΩ
KΩ
%
30
%
0.20VDD
12
450
20
3
2.2
9
420
18
120
120
50
20
0.40VDD
* This specification are subject to be changed without notice.
Conditions
VDD=5.5V,no load,NORMAL mode,
Fc=4MHz, Fs=32KHz (crystal)
VDD=5.5V,no load,SLOW mode,Fs=32KHz
(crystal)
VDD=5.5V,no load,RVRLC=68K,IDLE mode,
Fs=32KHz (crystal)
VDD=5.5V,STOP mode (crystal)
VDD=5.5V,no load,NORMAL mode,
Fc=4MHz,Fs=32KHz (RC, OSC)
VDD=5.5V,no load,SLOW mode,Fs=32KHz
(RC, OSC)
VDD=5.5V,no load,RVRLC=68K,IDLE mode,
Fs=32KHz (RC, OSC)
VDD=5.5V,STOP mode (RC, OSC)
RESET,all I/O ports except P3
RESET, P0,P2, VDD=5.5V,VIH=5.5/0V
Open-drain,VDD=5.5V,VIH=5.5/0V
P1,P4
I/O port acts as input(push-pull),
P1,P3~8 optional,VDD=4.5V,VIL=0.2V
P1,P3~8
VDD=4.5V,IOH=3mA for P1
VDD=4.5V,see IOH=typical. for P3~8
VDD=4.5V,IOL=0.5mA,P1,P3~8
P1,P4,optional
VDD=4.5V,VOH=2.2V
P1,P3~8,optional
P1,P3~8,optional
Open-drain,VDD=5.5V,Vo=5.5V
P0,P2,pull-up,optional
P0,P2,pull-down,optional
RESET
VDD=2.2~5.5V+10% RC OSC
R=100K+2%, fc=4MHz
VDD=2.2~5.5V+10% RC OSC
R=1MΩ+2%, fs=32KHz
12.29.1999
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EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
RESET PIN TYPE
TYPE RESET-A
RESET
mask option
OSCILLATION PIN TYPE
TYPE OSC-A
TYPE OSC-B
XIN
LXIN
Crystal
Osc.
Crystal
Osc.
XOUT
LXOUT
TYPE OSC-H1 (Low frequency)
TYPE OSC-H2 (High frequency)
VDD
VDD
1Mohm
LXIN
10Kohm
RC Osc.
OSC
RC Osc.
INPUT PIN TYPE
TYPE INPUT-K
positive
edge
input data detector
WAKEUP
mask option
: mask option
negative
edge
detector
I/O PIN TYPE
TYPE I/O-N
TYPE I/O-O
path B
Input
data
path A
TYPE I/O-N
: mask option
: mask option
* This specification are subject to be changed without notice.
Output
data
latch
Output
data
Special function
output
12.29.1999
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EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TYPE I/O-Q
TYPE I/O-R1
path B
Input
data
path A
Output
data
latch
TYPE I/O-Q
: mask option
TYPE I/O-S
Special function
output
WAKEUP function
mask option
TYPE I/O-Z
path B
SEL
path A
TYPE I/O-N
Special function
control input
path B
Input
data
Output
data
latch
Input
data
path A
TYPE I/O-Q
Output
data
WAKEUP function
mask option
Path A :
Path B :
Output
data
: mask option
Output S
R
data
latch
Power-on
reset
Output
data
Special function
output
For set and clear bit of port instructions, data goes through path A from output data latch to CPU.
For input and test instructions, data from output pin go through path B to CPU and the output data latch
will be set to high.
* This specification are subject to be changed without notice.
12.29.1999
31
EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
P5.2/W
P5.1/W
P5.0/W
P7.0/W/TRGA
P1.1
P1.0
VDD
P8.2/W/INT0
P8.1/W/TRGB
P8.0/W/INT1
P2.3/W
P2.2/W
P2.1/W
P2.0/W
P0.3/W
P0.2/W
P0.1/W
P0.0/W
PAD DIAGRAM
1 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60
12
EM73866
* This specification are subject to be changed without notice.
59
VSS
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
P5.3/W
P4.0/SOUND/W
P4.1/W
P4.2/W
P4.3/W
LXIN
LXOUT
COM3
COM2
COM1
COM0
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
SEG8
13
14
15
16
17
18
19
20
21
22
SEG5
VRLC
V1
V2
V3
VDD
SEG0
SEG1
SEG2
SEG3
SEG4
(0,0)
SEG7
VSS
2
3
4
5
6
7
8
9
10
11
SEG6
RESET
XOUT
XIN/OSC
TEST
P6.1
P6.0
P3.3
P3.2
P3.1/(SEG31)
P3.0/(SEG30)
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EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Symbol
P0.0/W
RESET
XOUT
XIN/OSC
TEST
P6.1
P6.0
P3.3
P3.2
P3.1/(SEG31)
P3.0/(SEG30)
VSS
VRLC
V1
V2
V3
VDD
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
X
-1056.5
-1030.3
-1030.3
-1030.3
-1030.3
-1030.3
-1030.3
-1030.3
-1030.3
-1030.3
-1030.3
-991.7
-1030.3
-1030.3
-1030.3
-1030.3
-1030.3
-1030.3
-1030.3
-1030.3
-1030.3
-1030.3
-839.4
-719.4
-599.4
-479.4
-359.4
-239.4
-119.4
0.6
120.6
240.6
360.6
480.6
600.6
720.6
840.6
1030.2
1030.2
1030.2
* This specification are subject to be changed without notice.
Y
1391.1
1186.6
1066.7
946.7
826.7
703.3
583.4
459.5
339.6
215.8
95.8
-105.5
-271.5
-391.5
-511.5
-631.5
-782.8
-902.8
-1022.8
-1142.8
-1262.8
-1382.8
-1390.2
-1390.2
-1390.2
-1390.2
-1390.2
-1390.2
-1390.2
-1390.2
-1390.2
-1390.2
-1390.2
-1390.2
-1390.2
-1390.2
-1390.2
-1390.7
-1270.7
-1150.7
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Pad No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
Symbol
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
COM0
COM1
COM2
COM3
LXOUT
LXIN
P4.3/W
P4.2/W
P4.1/W
P4.0/SOUND/W
P5.3/W
VSS
P5.2/W
P5.1/W
P5.0/W
P7.0/W/TRGA
P1.1
P1.0
VDD
P8.2/W/INT0
P8.1/WTRGB
P8.0/W/INT1
P2.3/W
P2.2/W
P2.1/W
P2.0/W
P0.3/W
P0.2/W
P0.1/W
X
1030.2
1030.2
1030.2
1030.2
1030.2
1030.2
1030.2
1030.2
1030.2
1030.2
1030.2
1030.2
1030.2
1030.2
1030.2
1030.2
1030.2
1030.2
1030.2
1061.1
941.0
817.2
697.2
573.4
453.4
332.0
180.7
56.9
-63.1
-189.5
-309.5
-438.5
-558.5
-687.5
-807.5
-936.5
Y
-1030.7
-910.7
-790.7
-670.7
-550.7
-430.7
-310.7
-190.7
-70.7
49.3
169.3
289.3
409.2
531.2
651.2
775.0
895.0
1018.8
1181.6
1391.1
1391.1
1391.1
1391.1
1391.1
1391.1
1391.1
1391.1
1391.1
1391.1
1391.1
1391.1
1391.1
1391.1
1391.1
1391.1
1391.1
Chip size : 2420 * 3140 UM
Unit : µm
For PCB layout, IC substrate must be floated or connected at Vss.
* This specification are subject to be changed without notice.
12.29.1999
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EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
INSTRUCTION TABLE
(1) Data Transfer
Mnemonic
Object code ( binary )
Operation description
LDA
x
LDAM
LDAX
LDAXI
LDH
#k
LDHL x
LDIA #k
LDL
#k
STA
x
STAM
STAMD
STAMI
STD
#k,y
STDMI #k
THA
TLA
0110 1010 xxxx xxxx
0101 1010
0110 0101
0110 0111
1001 kkkk
0100 1110 xxxx xx00
1101 kkkk
1000 kkkk
0110 1001 xxxx xxxx
0101 1001
0111 1101
0111 1111
0100 1000 kkkk yyyy
1010 kkkk
0111 0110
0111 0100
Acc←RAM[x]
Acc ←RAM[HL]
Acc←ROM[DP] L
Acc←ROM[DP] H,DP+1
HR←k
LR←RAM[x],HR←RAM[x+1]
Acc←k
LR←k
RAM[x]←Acc
RAM[HL]←Acc
RAM[HL]←Acc, LR-1
RAM[HL]←Acc, LR+1
RAM[y]←k
RAM[HL]←k, LR+1
Acc←HR
Acc←LR
Byte
2
1
1
1
1
2
1
1
2
1
1
1
2
1
1
1
Cycle
2
1
2
2
1
2
1
1
2
1
1
1
2
1
1
1
C
-
Flag
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C
Flag
Z
Z
Z
S
C'
C'
C
C
-
Flag
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
S
C'
C'
C'
C'
C'
C'
C'
C
C
C
C'
12.29.1999
35
S
1
1
1
1
1
1
1
1
1
1
C
C'
1
C'
1
1
(2) Rotate
Mnemonic
RLCA
RRCA
Object code ( binary ) Operation description
0101 0000
0101 0001
←CF←Acc←
→CF→Acc→
Byte
1
1
Cycle
1
1
(3) Arithmetic operation
Mnemonic
Object code ( binary )
Operation description
Byte
ADCAM
ADD
#k,y
ADDA #k
ADDAM
ADDH #k
ADDL #k
ADDM #k
DECA
DECL
DECM
INCA
0111
0100
0110
0111
0110
0110
0110
0101
0111
0101
0101
Acc←Acc + RAM[HL] + CF
RAM[y]←RAM[y] +k
Acc←Acc+k
Acc←Acc + RAM[HL]
HR←HR+k
LR←LR+k
RAM[HL]←RAM[HL] +k
Acc←Acc-1
LR←LR-1
RAM[HL]←RAM[HL] -1
Acc←Acc + 1
1
2
2
1
2
2
2
1
1
1
1
0000
1001 kkkk yyyy
1110 0101 kkkk
0001
1110 1001 kkkk
1110 0001 kkkk
1110 1101 kkkk
1100
1100
1101
1110
* This specification are subject to be changed without notice.
Cycle
1
2
2
1
2
2
2
1
1
1
1
EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
INCL
INCM
SUBA #k
SBCAM
SUBM #k
0111 1110
0101 1111
0110 1110 0111 kkkk
0111 0010
0110 1110 1111 kkkk
LR←LR + 1
RAM[HL]←RAM[HL]+1
Acc←k-Acc
Acc←RAM[HLl - Acc - CF'
RAM[HL]←k - RAM[HL]
1
1
2
1
2
1
1
2
1
2
C
-
Z
Z
Z
Z
Z
C'
C'
C
C
C
(4) Logical operation
Object code ( binary )
Operation description
Byte
ANDA #k
ANDAM
ANDM #k
ORA
#k
ORAM
ORM #k
XORAM
0110
0111
0110
0110
0111
0110
0111
Acc←Acc&k
Acc←Acc & RAM[HL]
RAM[HL]←RAM[HL]&k
Acc←Acc k
Acc ←Acc RAM[HL]
RAM[HL]←RAM[HL] k
Acc←Acc^RAM[HL]
2
1
2
2
1
2
1
--
1110 0110 kkkk
1011
1110 1110 kkkk
1110 0100 kkkk
1000
1110 1100 kkkk
1001
----
Mnemonic
Cycle
2
1
2
2
1
2
1
C
-
Flag
Z
Z
Z
Z
Z
Z
Z
Z
S
Z'
Z'
Z'
Z'
Z'
Z'
Z'
(5) Exchange
Mnemonic
Object code ( binary )
Operation description
Byte
Cycle
EXA x
EXAH
EXAL
EXAM
EXHL x
0110 1000 xxxx xxxx
0110 0110
0110 0100
0101 1000
0100 1100 xxxx xx00
Acc↔RAM[x]
Acc↔HR
Acc↔LR
Acc↔RAM[HL]
LR↔RAM[x],
HR↔RAM[x+1]
2
1
1
1
2
2
2
1
2
2
Mnemonic
Object code ( binary )
Operation description
Byte
SBR a
00aa aaaa
1
1
LBR a
SLBR a
1100 aaaa aaaa aaaa
0101 0101 1100 aaaa
If SF=1 then PC←PC12-6.a5-0
else null
If SF= 1 then PC←a else null
If SF=1 then PC←a else null
2
3
2
3
Operation description
Byte
k-RAM[y]
RAM[x]-Acc
2
2
Flag
C
Z
S
-
Z
Z
Z
Z
1
1
1
1
-
-
1
Flag
C
Z
-
-
S
-
-
1
1
(6) Branch
aaaa aaaa (a:1000~1FFFh)
Cycle
1
0101 0111 1100 aaaa
aaaa aaaa (a:0000~0FFFh)
(7) Compare
Mnemonic
Object code ( binary )
CMP #k,y 0100 1011 kkkk yyyy
CMPA x
0110 1011 xxxx xxxx
* This specification are subject to be changed without notice.
Cycle
2
2
Flag
C
Z
C
C
Z
Z
12.29.1999
S
Z'
Z'
36
EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Mnemonic
Object code ( binary )
CMPAM
CMPH #k
CMPIA #k
CMPL #k
0111 0011
0110 1110 1011 kkkk
1011 kkkk
0110 1110 0011 kkkk
Operation description
Byte
RAM[HL] - Acc
k - HR
k - Acc
k-LR
1
2
1
2
Cycle
1
2
1
2
C
Flag
Z
C
-
Flag
Z
-
S
1
1
1
1
1
1
1
1
*
*
*
*
*
*
*
Flag
Z
-
S
-
C
C
-
Z
Z
Z
Z
S
Z'
C
Z'
C
(8) Bit manipulation
Mnemonic
Object code ( binary )
Operation description
Byte
CLM
CLP
CLPL
CLR
SEM
SEP
SEPL
SET
TF
TFA
TFM
TFP
TFPL
TT
TTP
1111 00bb
0110 1101 11bb pppp
0110 0000
0110 1100 11bb yyyy
1111 01bb
0110 1101 01bb pppp
0110 0010
0110 1100 01bb yyyy
0110 1100 00bb yyyy
1111 10bb
1111 11bb
0110 1101 00bb pppp
0110 0001
0110 1100 10bb yyyy
0110 1101 10bb pppp
RAM[HL]b←0
PORT[p]b←0
PORT[LR3-2+4]LR1-0←0
RAM[y]b←0
RAM[HL]b←1
PORT[p]b←1
PORT[LR3-2+4]LRl-0←1
RAM[y]b←1
SF←RAM[y]b'
SF←Acc b'
SF←RAM[HL]b'
SF←PORT[p]b'
SF←PORT[LR 3-2 +4]LR1-0'
SF←RAM[y]b
SF←PORT[p]b
1
2
1
2
1
2
1
2
2
1
1
2
1
2
2
Mnemonic
Object code ( binary )
Operation description
Byte
LCALL a
0100 0aaa aaaa aaaa
2
2
SCALL a
1110 nnnn
1
2
-
-
-
RET
0100 1111
STACK[SP]←PC,
SP←SP -1, PC←a
STACK[SP]←PC,
SP←SP - 1, PC←a, a = 8n + 6
(n =1∼15),0086h (n = 0)
SP←SP + 1, PC←STACK[SP]
C
-
1
2
-
-
-
Mnemonic
Object code ( binary )
Operation description
Byte
INA
INM
OUT
OUTA
OUTM
0110 1111 0100 pppp
0110 1111 1100 pppp
0100 1010 kkkk pppp
0110 1111 000p pppp
0110 1111 100p pppp
Acc←PORT[p]
RAM[HL]←PORT[p]
PORT[p]←k
PORT[p]←Acc
PORT[p]←RAM[HL]
2
2
2
2
2
b
p,b
y,b
b
p,b
y,b
y,b
b
b
p,b
y,b
p,b
Cycle
1
2
2
2
1
2
2
2
2
1
1
2
2
2
2
(9) Subroutine
Cycle
(10) Input/output
p
p
#k,p
p
p
* This specification are subject to be changed without notice.
Cycle
2
2
2
2
2
C
-
Flag
Z
Z
-
12.29.1999
S
Z'
Z'
1
1
1
37
EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
(11) Flag manipulation
Mnemonic
TFCFC
TTCFS
TZS
Object code ( binary ) Operation description
0101 0011
0101 0010
0101 1011
Byte
Cycle
SF←CF', CF←0
SF←CF, CF←1
SF←ZF
1
1
1
1
1
1
C
0
1
-
Flag
Z
-
S
*
*
*
C
*
Flag
Z
*
S
1
1
1
1
*
C
-
Flag
Z
-
S
-
C
-
Flag
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
S
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(12) Interrupt control
Mnemonic
Object code ( binary )
Operation description
Byte
CIL
r
DICIL r
EICIL r
EXAE
RTI
0110 0011 11rr rrrr
0110 0011 10rr rrrr
0110 0011 01rr rrrr
0111 0101
0100 1101
IL←IL & r
EIF←0,IL←IL&r
EIF←1,IL←IL&r
MASK↔Acc
SP←SP+1,FLAG.PC
←STACK[SP],EIF ←1
2
2
2
1
1
Mnemonic
Object code ( binary )
Operation description
Byte
NOP
0101 0110
no operation
1
Cycle
2
2
2
1
2
(13) CPU control
Cycle
1
(14) Timer/Counter & Data pointer & Stack pointer control
Mnemonic
Object code ( binary )
Operation description
LDADPL
0110 1010 1111 1100
Acc←[DP]L
LDADPM
0110 1010 1111 1101
Acc←[DP] M
LDADPH
0110 1010 1111 1110
Acc←[DP] H
LDASP
0110 1010 1111 1111
Acc←SP
LDATAL
0110 1010 1111 0100
Acc←[TA] L
LDATAM
0110 1010 1111 0101
Acc←[TA]M
LDATAH
0110 1010 1111 0110
Acc←[TA] H
LDATBL
0110 1010 1111 1000
Acc←[TB] L
LDATBM
0110 1010 1111 1001
Acc←[TB]M
LDATBH
0110 1010 1111 1010
Acc←[TB]H
STADPL
0110 1001 1111 1100
[DP] L←Acc
STADPM
0110 1001 1111 1101
[DP] M ←Acc
STADPH
0110 1001 1111 1110
[DP] H←Acc
STASP
0110 1001 1111 1111
SP←Acc
STATAL
0110 1001 1111 0100
[TA] L←Acc
STATAM
0110 1001 1111 0101
[TA]M ←Acc
STATAH
0110 1001 1111 0110
[TA] H←Acc
STATBL
0110 1001 1111 1000
[ TB] L←Acc
STATBM
0110 1001 1111 1001
[TB] M←Acc
STATBH
0110 1001 1111 1010
[TB] H←Acc
* This specification are subject to be changed without notice.
Byte
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Cycle
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
12.29.1999
38
EM73866
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
**** SYMBOL DESCRIPTION
Symbol
HR
PC
SP
ACC
CF
SF
IL
PORT[p]
ΤΒ
RAM[x]
ROM[DP]H
[DP]M
[TA]L([TB]L)
[TA]H([TB]H)
LR3-2
PC12-6
↔
--
#k
y
b
Description
Symbol
H register
Program counter
Stack pointer
Accumulator
Carry flag
Status flag
Interrupt latch
Port ( address : p )
Timer/counter B
Data memory (address : x )
High 4-bit of program memory
Middle 4-bit of data pointer register
Low 4-bit of timer/counter A
(timer/counter B) register
High 4-bit of timer/counter A
(timer/counter B) register
Bit 3 to 2 of LR
LR
DP
STACK[SP]
FLAG
ZF
EI
MASK
ΤΑ
RAM[HL]
ROM[DP]L
[DP]L
[DP]H
[TA]M([TB]M)
Bit 12 to 6 of program counter
Exchange
Substraction
Logic OR
Inverse operation
4-bit immediate data
4-bit zero-page address
Bit address
←
+
&
^
.
x
p
r
LR 1-0
a5-0
* This specification are subject to be changed without notice.
Description
L register
Data pointer
Stack specified by SP
All flags
Zero flag
Enable interrupt register
Interrupt mask
Timer/counter A
Data memory (address : HL )
Low 4-bit of program memory
Low 4-bit of data pointer register
High 4-bit of data pointer register
Middle 4-bit of timer/counter A
(timer/counter B) register
Contents of bit assigned by bit
1 to 0 of LR
Bit 5 to 0 of destination address for
branch instruction
Transfer
Addition
Logic AND
Logic XOR
Concatenation
8-bit RAM address
4-bit or 5-bit port address
6-bit interrupt latch
12.29.1999
39
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