TI BQ24157YFFT Fully integrated switch-mode charger with usb compliance and usb-otg support Datasheet

bq24157
www.ti.com
SLUSB80 – SEPTEMBER 2012
Fully Integrated Switch-Mode Charger
With USB Compliance and USB-OTG Support
Check for Samples: bq24157
FEATURES
1
•
•
•
23
•
•
•
•
•
•
•
•
•
Power Up System without Battery
Charge Faster than Linear Chargers
High-Accuracy Voltage and Current Regulation
– Input Current Regulation Accuracy: ±5%
(100 mA and 500 mA)
– Charge Voltage Regulation Accuracy:
±0.5% (25°C), ±1% (0°C to 125°C)
– Charge Current Regulation Accuracy: ±5%
Input Voltage Based Dynamic Power
Management (VIN DPM)
Bad Adaptor Detection and Rejection
Safety Limit Register for Maximum Charge
Voltage and Current Limiting
High-Efficiency Mini-USB/AC Battery Charger
for Single-Cell Li-Ion and Li-Polymer Battery
Packs
20-V Absolute Maximum Input Voltage Rating
6.5-V Maximum Operating Input Voltage
Built-In Input Current Sensing and Limiting
Integrated Power FETs for Up To 1.25-A
Charge Rate
Programmable Charge Parameters through
I2C™ Compatible Interface (up to 3.4 Mbps):
– Input Current Limit
– VIN DPM Threshold
– Fast-Charge/Termination Current
– Charge Regulation Voltage (3.5 V to 4.44 V)
– Low Charge Current Mode Enable/Disable
– Termination Enable/Disable
•
Synchronous Fixed-Frequency PWM
Controller Operating at 3 MHz With 0% to
99.5% Duty Cycle
Automatic High Impedance Mode for Low
Power Consumption
Robust Protection
– Reverse Leakage Protection Prevents
Battery Drainage
– Thermal Regulation and Protection
– Input/Output Overvoltage Protection
Status Output for Charging and Faults
USB Friendly Boot-Up Sequence
Automatic Charging
Boost Mode Operation for USB OTG
– Input Voltage Range (from Battery): 3.2 V to
4.5 V
2.1 mm x 2 mm 20-Pin WCSP Package
•
•
•
•
•
•
•
APPLICATIONS
•
•
•
Mobile and Smart Phones
MP3 Players
Handheld Devices
Figure 1. Typical Application Circuit
LO 1.0 mH
VBUS
VBUS
CIN
1 mF
RSNS
SW
U1
bq24157
C IN 4.7 mF
33 mF
+
CSIN
10 kW
2
I C BUS
SCL
SCL
SDA
PACK–
CSOUT
SDA
STAT
STAT
OTG
10 kW
PACK+
CCSIN
0.1 mF
10 kW 10 kW
HOST
BOOT
PGND
VAUX
CO2
22 mF
33 nF
PMID
VBAT
CO1
CBOOT
CD
OTG
CD
CCSOUT
VREF
CVREF
0.1 mF
1 mF
10 kW
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
I2C is a trademark of NXP B.V. Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
bq24157
SLUSB80 – SEPTEMBER 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The bq24157 is a compact, flexible, high-efficiency, USB-friendly switch-mode charge management device for
single-cell Li-ion and Li-polymer batteries used in a wide range of portable applications. The charge parameters
can be programmed through an I2C interface. The IC integrates a synchronous PWM controller, power
MOSFETs, input current sensing, high-accuracy current and voltage regulation, and charge termination, into a
small WCSP package.
The IC charges the battery in three phases: conditioning, constant current and constant voltage. The input
current is automatically limited to the value set by the host. Charge is terminated based on battery voltage and
user-selectable minimum current level. A safety timer with reset control provides a safety backup for I2C
interface. During normal operation, The IC automatically restarts the charge cycle if the battery voltage falls
below an internal threshold and automatically enters sleep mode or high impedance mode when the input supply
is removed. The charge status can be reported to the host using the I2C interface. During the charging process,
the IC monitors its junction temperature (TJ) and reduces the charge current once TJ increases to about 125°C.
To support USB OTG device, bq24157 can provide VBUS (5.05V) by boosting the battery voltage. The IC is
available in 20-pin WCSP package.
DEVICE SPINS AND COMPARISONS
PART NUMBER
bq24157
VOVP (V)
6.5
D4 Pin Definition
OTG
ICHARGE(MAX) at POR in default mode with R(SNS) = 68 mΩ and OTG=High on bq24157(mA)
325
ICHARGE(MAX) in HOST mode with R(SNS) = 68 mΩ and Safety Limit Register increased from default (A)
1.25
Output regulation voltage at POR (V)
3.54
Boost Function
Yes
100mA (OTG=LOW);
500mA (OTG=High)
Input Current Limit in Default Mode
Battery Detection at Power Up
No
I2C Address
6AH
PN1 (bit4 of 03H)
1
PN0 (bit3 of 03H)
0
Safety Timer and WD Timer
Disabled
100 ms Power Up Delay
2
No
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SLUSB80 – SEPTEMBER 2012
PIN LAYOUT (20-Bump YFF Package)
bq24157
(Top View)
A1
A2
A3
A4
VBUS
VBUS
BOOT
SCL
B3
B4
PMID
B1
PMID
B2
PMID
SDA
C1
C2
C3
C4
SW
SW
SW
STAT
D1
D2
D3
D4
PGND
PGND
PGND
OTG
E1
E2
E3
E4
CD
VREF
CSOUT
CSIN
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
CSOUT
E4
I
Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1 μF) to PGND if there are
long inductive leads to battery.
VBUS
A1, A2
I/O
Charger input voltage. Bypass it with a 1-μF ceramic capacitor from VBUS to PGND. It also provides power to the
load during boost mode .
PMID
B1, B2, B3
I/O
Connection point between reverse blocking FET and high-side switching FET. Bypass it with a minimum of 3.3-μF
capacitor from PMID to PGND.
SW
C1, C2, C3
O
Internal switch to output inductor connection.
BOOT
A3
I/O
Bootstrap capacitor connection for the high-side FET gate driver. Connect a 10-nF ceramic capacitor (voltage rating ≥
10 V) from BOOT pin to SW pin.
PGND
D1, D2, D3
CSIN
E1
I
Charge current-sense input. Battery current is sensed across an external sense resistor. A 0.1-μF ceramic capacitor
to PGND is required.
SCL
A4
I
I2C interface clock. Connect a 10-kΩ pullup resistor to 1.8V rail (VAUX= VCC_HOST)
SDA
B4
I/O
I2C interface data. Connect a 10-kΩ pullup resistor to 1.8V rail (VAUX= VCC_HOST)
STAT
C4
O
Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a 128-μs pulse is
sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can be used to drive a LED or
communicate with a host processor.
VREF
E3
O
Internal bias regulator voltage. Connect a 1µF ceramic capacitor from this output to PGND. External load on VREF is
not recommended.
CD
E2
I
Charge disable control pin. CD=0, charge is enabled. CD=1, charge is disabled and VBUS pin is high impedance to
GND.
I
Boost mode enable control or input current limiting selection pin. When OTG is in active status, the device is forced to
operate in boost mode. It has higher priority over I2C control and can be disabled using the control register. At POR
while in default mode, the OTG pin is used as the input current limiting selection pin. The I2C register is ignored at
startup. When OTG=High, IIN_LIMIT = 500mA and when OTG = Low, IIN_LIMIT = 100mA.
OTG
D4
Power ground
ORDERING INFORMATION (1)
(1)
PART NUMBER
MARKING
MEDIUM
QUANTITY
bq24157YFFR
bq24157A
Tape and Reel
3000
bq24157YFFT
bq24157A
Tape and Reel
250
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS (1)
(2)
over operating free-air temperature range (unless otherwise noted)
Supply voltage range (with respect to PGND
(3)
)
(3)
Input voltage range (with respect to PGND )
(3)
Output voltage range (with respect to PGND )
bq24157
UNIT
VBUS; VPMID ≥ VBUS –0.3 V
–2 to 20
V
SCL, SDA, OTG, SLRST, CSIN, CSOUT,
CD
–0.3 to 7
V
PMID, STAT
–0.3 to 20
V
VREF
7
V
–0.7 to 20
V
±7
V
Voltage difference between BOOT and SW inputs (V(BOOT) – V(SW) )
-0.3 to 7
V
Voltage difference between VBUS and PMID inputs (V(VBUS) – V(PMID) )
-7 to 0.7
V
Voltage difference between PMID and SW inputs (V(PMID) – V(SW) )
-0.7 to 20
V
10
mA
SW, BOOT
Voltage difference between CSIN and CSOUT inputs (V(CSIN) – V(CSOUT) )
Output sink
STAT
Output Current (average)
SW
1.55 (2)
A
TA
Operating free-air temperature range
–30 to 85
°C
TJ
Junction temperature
–40 to 125
°C
Tstg
Storage temperature
–45 to 150
°C
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
Duty cycle for output current should be less than 50% for 10- year life time when output current is above 1.25A.
All voltages are with respect to PGND if not specified. Currents are positive into, negative out of the specified terminal, if not specified.
Consult Packaging Section of the data sheet for thermal limitations and considerations of packages.
THERMAL INFORMATION
THERMAL METRIC (1)
bq24157
UNITS
YFF (20 PINS)
θJA
Junction-to-ambient thermal resistance
85
θJCtop
Junction-to-case (top) thermal resistance
25
θJB
Junction-to-board thermal resistance
55
ψJT
Junction-to-top characterization parameter
4
ψJB
Junction-to-board characterization parameter
50
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
°C/W
spacer
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
MIN
VBUS
Supply voltage, bq24157
TJ
Operating junction temperature range
(1)
4
NOM
MAX
UNIT
4
6 (1)
V
–40
125
°C
The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOST or SW pins. A tight
layout minimizes switching noise.
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SLUSB80 – SEPTEMBER 2012
ELECTRICAL CHARACTERISTICS
Circuit of Figure 2, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical values
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
VBUS > VBUS(min), PWM switching
I(VBUS)
VBUS supply current control
10
VBUS > VBUS(min), PWM NOT switching
0°C < TJ < 85°C, CD=1 or HZ_MODE=1
Ilgk
Leakage current from battery to VBUS pin
0°C < TJ < 85°C, V(CSOUT) = 4.2 V,
High Impedance mode, VBUS = 0 V
Battery discharge current in High Impedance
mode, (CSIN, CSOUT, SW pins)
0°C < TJ < 85°C, V(CSOUT) = 4.2 V,
High Impedance mode, V = 0 V, SCL, SDA,
OTG = 0 V or 1.8 V
mA
5
15
23
μA
5
μA
23
μA
V
VOLTAGE REGULATION
V(OREG)
Output regulation voltage programable range
Operating in voltage regulation, programmable
TA = 25°C
Voltage regulation accuracy
3.5
4.44
–0.5%
0.5%
–1%
1%
550
1250
mA
350
mA
CURRENT REGULATION (FAST CHARGE)
IO(CHARGE)
Output charge current programmable range
V(LOWV) ≤ V(CSOUT) < V(OREG),
VBUS > V(SLP), R(SNS) = 68 mΩ, LOW_CHG=0,
Programmable
Low charge current
VLOWV ≤ VCSOUT < VOREG, VBUS >VSLP, RSNS= 68
mΩ,
LOW_CHG=1, OTG=High
Regulation accuracy of the voltage across R(SNS)
(for charge current regulation)
V(IREG) = IO(CHARGE) × R(SNS)
37.4 mV ≤ V(IREG)< 44.2mV
44.2 mV ≤ V(IREG)
325
–3.5%
3.5%
-3%
3%
3.4
3.7
WEAK BATTERY DETECTION
V(LOWV)
Weak battery voltage threshold programmable
range2 (1)
Adjustable using I2C control
Weak battery voltage accuracy
–5%
Hysteresis for V(LOWV)
Battery voltage falling
Deglitch time for weak battery threshold
Rising voltage, 2-mV over drive, tRISE = 100 ns
V
5%
100
mV
30
ms
CD, OTG and SLRST PIN LOGIC LEVEL
VIL
Input low threshold level
VIH
Input high threshold level
I(bias)
Input bias current
0.4
V
1.0
µA
1.3
V
Voltage on control pin is 5 V
CHARGE TERMINATION DETECTION
I(TERM)
Termination charge current programmable range
V(CSOUT) > V(OREG) – V(RCH), VBUS > V(SLP),
R(SNS) = 68 mΩ, Programmable
Deglitch time for charge termination
Both rising and falling, 2-mV overdrive,
tRISE, tFALL = 100 ns
Regulation accuracy for termination current
across R(SNS)
V(IREG_TERM) = IO(TERM) × R(SNS)
(1)
50
400
30
mA
ms
3.4 mV ≤ V(IREG_TERM) ≤ 6.8 mV
–15%
6.8 mV < V(IREG_TERM) ≤ 17 mV
–10%
10%
17 mV < V(IREG_TERM) ≤ 27.2 mV
–5.5%
5.5%
15%
While in 15-min mode, if a battery that is charged to a voltage higher than this voltage is inserted, the charger enters Hi-Z mode and
awaits I2C commands.
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ELECTRICAL CHARACTERISTICS (continued)
Circuit of Figure 2, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical values
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.6
3.8
4.0
UNIT
BAD ADAPTOR DETECTION
VIN(min)
Input voltage lower limit
BAD ADAPTOR DETECTION
Deglitch time for VBUS rising above VIN(min)
Rising voltage, 2-mV overdrive, tRISE = 100 ns
Hysteresis for VIN(min)
Input voltage rising
ISHORT
Current source to GND
During bad adaptor detection
tINT
Detection Interval
Input power source detection
30
100
20
30
V
ms
200
mV
40
mA
2
s
INPUT BASED DYNAMIC POWER MANAGEMENT
Input Voltage DPM threshold programmable
range
VIN_DPM
VIN DPM threshold accuracy
4.2
4.76
–3%
1%
V
INPUT CURRENT LIMITING
TJ = 0°C – 125°C
88
93
98
TJ = –40°C –125°C
86
93
98
TJ = 0°C – 125°C
450
475
500
TJ = –40°C –125°C
440
475
500
VBUS >VIN(min) or V(CSOUT) > VBUS(min),
I(VREF) = 1 mA, C(VREF) = 1 μF
2
IIN = 100 mA
IIN_LIMIT
Input current limiting threshold
IIN = 500 mA
mA
mA
VREF BIAS REGULATOR
VREF
Internal bias regulator voltage
VREF output short current limit
6.5
30
V
mA
BATTERY RECHARGE THRESHOLD
V(RCH)
Recharge threshold voltage
Below V(OREG)
Deglitch time
V(CSOUT) decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive
100
120
150
130
mV
ms
STAT OUTPUTS
VOL(STAT)
Low-level output saturation voltage, STAT pin
IO = 10 mA, sink current
High-level leakage current for STAT
Voltage on STAT pin is 5 V
0.55
V
1
μA
I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS
VOL
Output low threshold level
IO = 10 mA, sink current
0.4
V
VIL
Input low threshold level
V(pull-up) = 1.8 V, SDA and SCL
0.4
V
VIH
Input high threshold level
V(pull-up) = 1.8 V, SDA and SCL
I(BIAS)
Input bias current
V(pull-up) = 1.8 V, SDA and SCL
1
μA
f(SCL)
SCL clock frequency
1.2
V
3.4
MHz
BATTERY DETECTION
I(DETECT)
Battery detection current before charge done
(sink current) (2)
tDETECT
Battery detection time
Begins after termination detected,
V(CSOUT) ≤ V(BATREG)
–0.5
mA
262
ms
SLEEP COMPARATOR
V(SLP)
Sleep-mode entry threshold,
VBUS – VCSOUT
2.3 V ≤ V(CSOUT) ≤ V(BATREG), VBUS falling
V(SLP_EXIT)
Sleep-mode exit hysteresis
2.3 V ≤ V(CSOUT) ≤ V(BATREG)
Deglitch time for VBUS rising above
V(SLP) + V(SLP_EXIT)
Rising voltage, 2-mV overdrive,
tRISE = 100 ns
0
40
100
mV
140
200
260
mV
30
ms
UNDERVOLTAGE LOCKOUT (UVLO)
UVLO
IC active threshold voltage
VBUS rising - Exits UVLO
3.05
3.3
UVLO(HYS)
IC active hysteresis
VBUS falling below UVLO - Enters UVLO
120
150
mV
140
ms
Power up delay
(2)
6
3.55
V
Bottom N-channel FET always turns on for ~30 ns and then turns off if current is too low.
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ELECTRICAL CHARACTERISTICS (continued)
Circuit of Figure 2, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical values
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PWM
f(OSC)
Voltage from BOOT pin to SW pin
During charge or boost operation
Internal top reverse blocking MOSFET onresistance
6.5
IIN(LIMIT) = 500 mA, Measured from VBUS to PMID
180
250
Internal top N-channel Switching MOSFET onresistance
Measured from PMID to SW,
VBOOT – VSW= 4V
120
250
Internal bottom N-channel MOSFET onresistance
Measured from SW to PGND
110
210
Oscillator frequency
Maximum duty cycle
D(MIN)
Minimum duty cycle
mΩ
3.0
Frequency accuracy
D(MAX)
V
–10%
MHz
10%
99.5%
0
Synchronous mode to non-synchronous mode
transition current threshold (3)
Low-side MOSFET cycle-by-cycle current sensing
100
mA
CHARGE MODE PROTECTION
VOVP_IN_USB
VOVP
ILIMIT
VSHORT
ISHORT
Input VBUS OVP threshold voltage
VBUS threshold to turn off converter during charge
6.3
6.5
6.7
Output OVP threshold voltage
V(CSOUT) threshold over V(OREG) to turn off charger
during charge
110
117
121
V(OVP) hysteresis
Lower limit for V(CSOUT) falling from above V(OVP)
Cycle-by-cycle current limit for charge
Charge mode operation
1.8
Trickle to fast charge threshold
V(CSOUT) rising
2.0
VSHORT hysteresis
V(CSOUT) falling below VSHORT
Trickle charge charging current
V(CSOUT) ≤ VSHORT)
V
%VOREG
11
2.4
3.0
2.1
2.2
100
20
30
A
V
mV
40
mA
BOOST MODE OPERATION FOR VBUS (OPA_MODE = 1, HZ_MODE = 0)
VBUS_B
Boost output voltage (to VBUS pin)
2.5V < V(CSOUT) < 4.5 V
Boost output voltage accuracy
Including line and load regulation
IBO
Maximum output current for boost
VBUS_B = 5.05 V, 2.5 V < V(CSOUT) < 4.5 V,
TJ= 0°C – 125°C
IBLIMIT
Cycle by cycle current limit for boost
VBUS_B = 5.05 V, 2.5 V < V(CSOUT) < 4.5 V
VBUSOVP
Overvoltage protection threshold for boost (VBUS Threshold over VBUS to turn off converter during
pin)
boost
VBATMAX
VBATMIN
5.05
–3%
200
mA
1.0
5.8
6.0
VBUSOVP hysteresis
VBUS falling from above VBUSOVP
Maximum battery voltage for boost (CSOUT pin)
V(CSOUT) rising edge during boost
VBATMAX hysteresis
V(CSOUT) falling from above VBATMAX
200
During boosting
2.5
Before boost starts
2.9
Minimum battery voltage for boost (CSOUT pin)
Boost output resistance at high-impedance mode
(From VBUS to PGND)
CD = 1 or HZ_MODE = 1
V
3%
A
6.2
162
4.75
4.9
V
mV
5.05
V
mV
V
3.05
217
V
kΩ
PROTECTION
TSHTDWN)
Thermal trip
165
Thermal hysteresis
10
TCF
Thermal regulation threshold
Charge current begins to reduce
t15M
15 minute safety timer
15 Minute mode
(3)
°C
120
12
15
m
Bottom N-channel FET always turns on for ~30 ns and then turns off if current is too low.
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TYPICAL APPLICATION CIRCUITS
VBUS = 5 V, ICHARGE = 1250 mA, VBAT = 3.5 V to 4.44 V (Adjustable).
LO 1.0 mH
VBUS
VBUS
CIN
SW
PMID
33 mF
BOOT
PACK+
+
CCSIN
PGND
VAUX
CO2
22 mF
33 nF
C IN 4.7 mF
VBAT
CO1
CBOOT
U1
bq24157
1 mF
RSNS
0.1 mF
CSIN
10 kW
10 kW 10 kW 10 kW
2
I C BUS
SCL
SCL
SDA
STAT
SLRST
10 kW
SDA
STAT
SLRST
CD
10 kW
CD
PACK–
CSOUT
CCSOUT
VREF
CVREF
0.1 mF
1 mF
HOST
Figure 2. I2C Controlled 1-Cell USB Charger Application Circuit with USB OTG Support.
8
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SLUSB80 – SEPTEMBER 2012
TYPICAL PERFORMANCE CHARACTERISTICS
Using circuit shown in Figure 2, TA = 25°C, unless otherwise specified.
vertical spacer
ADAPTER INSERTION
CYCLE BY CYCLE CURRENT LIMITING IN CHARGE MODE
VBUS
2 V/div
VSW
2 V/div
IL
0.5 A/div
VSW
5 V/div
IBAT
0.5 A/div
10 ms/div
2 ms/div
Figure 3. VBUS = 0-5V, Iin_limit = 500mA, Voreg = 4.2V
VBAT = 3.5V, ICHG = 550mA, 32S mode
Figure 4. VBUS = 5V, VBAT = 3.5V
Charge Mode Overload Operation
PWM CHARGING WAVEFORMS
POOR SOURCE DETECTION
VBUS
2 V/div
VSW
2 V/div
VSW
2 V/div
IL
0.5 A/div
IBUS
20 mA/div
10 mS/div
100 nS/div
Figure 5. VBUS = 5 V, VBAT = 2.6 V, Voreg = 4.2 V,
ICHG = 1550 mA
Figure 6. VBUS = 5 V at 8 mA, VBAT = 3.2V,
Iin_limit = 100 mA, ICHG = 550 mA
CHARGE CURRENT RAMP UP
INPUT CURRENT CONTROL
VSW
5 V/div
OTG
2 V/div
15 Minute Mode
32 S Mode
IBAT
0.1 A/div
IBAT
200 mA/div
Write Command
1 S/div
500 mS/div
Figure 7. Vin = 5 V, VBAT = 3. 2V, No Input Current Limit,
ICHG = 1550mA
Figure 8. VBUS = 5 V, VBAT = 3.1V, Iin_limit = 100/500 mA,
(OTG Control, 15 Minute Mode), Iin_limit = 100 mA
(I2C Control, 32 Second Mode)
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN BASED DPM
CHARGER EFFICIENCY
94
93
VBUS
1 V/div
Vbat = 4.2 V
92
Vbat = 3.6 V
91
Efficiency - %
90
IBUS
0.2 A/div
89
88
87
86
85
Vbat = 3 V
84
83
82
81
80
0.5 mS/div
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Charge Current - A
Figure 9. VBUS = 5 V at 500 mA, VBAT = 3.5V,
ICHG = 1550 mA,
VIN_DPM = 4.52 V
Figure 10.
BOOST WAVEFORM (PWM MODE)
VBUS
10 mV/div,
5.05 V Offset
1.1 1.2 1.3 1.4 1.5
BOOST WAVEFORM (PFM MODE)
VBUS
100 mV/div,
5.05 V Offset
VBAT
10 mV/div,
3.5 V Offset
VBAT
100 mV/div,
3.5 V Offset
VSW
2V/div
VSW
2 V/div
IL
100 mA/div
IL
0.2 A/div
100 nS/div
5 mS/div
Figure 11. VBUS = 5.05 V, VBAT = 3.5V, IBUS = 217 mA
VBUS OVERLOAD WAVEFORMS (BOOST MODE)
Figure 12. VBUS = 5.05 V, VBAT = 3.5V, IBUS = 42 mA
LOAD STEP UP RESPONSE (BOOST MODE)
VBUS
2 V/div
VBUS
200 mV/div,
5.05 V Offset
VPMID
200 mV/div,
5.02 V Offset
VBAT
200 mV/div,
3.5 V Offset
VSW
5 V/div
VSW
5 V/div
IBAT
500 mV/div
IBUS
0.2 A/div
100 mS/div
5 mS/div
Figure 13. VBUS = 5.05 V, VBAT = 3.5V, RLOAD (at VBUS) =
1KΩ to 0.5Ω
10
Figure 14. VBUS = 5.05, VBAT = 3.5V, IBUS = 0-360 mA
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
LOAD STEP UP RESPONSE (BOOST MODE)
LOAD STEP DOWN RESPONSE (BOOST MODE)
VBUS
200 mV/div,
5.05 V Offset
VBUS
100 mV/div,
5.05 V Offset
VBAT
200 mV/div,
3.5 V Offset
VBAT
0.2 V/div,
3.5 V Offset
VSW
5 V/div
VSW
5 V/div
IBAT
500 mV/div
IBAT
0.1 A/div
100 mS/div
100 mS/div
Figure 15. VBUS = 5.05 V, VBAT = 3.5V, IBUS = 0-217 mA
Figure 16. VBUS = 5.05, VBAT = 3.5V, IBUS = 360-0 mA
LOAD STEP DOWN RESPONSE (BOOST MODE)
BOOST TO CHARGE MODE TRANSITION (OTG CONTROL)
VBUS
0.5 V/div,
4.5 V Offset
VBUS
100 mV/div,
5.05 V Offset
OTG
2 V/div
VBAT
0.2 V/div,
3.5 V Offset
VSW
5 V/div
VSW
5 V/div
IBAT
0.1 A/div
IL
0.5 A/div
100 mS/div
10 mS/div
Figure 17. VBUS = 5.05 V, VBAT = 3.5V, IBUS = 217 mA
Figure 18. VBUS = 4.5 V (Charge Mode) / 5.1 V
(Boost Mode), VBAT = 3.5V, IIN_LIM = 500 mA, (32S mode)
BOOST EFFICIENCY
LINE REGULATION FOR BOOST
5.09
95
VBAT = 2.7 V
VBAT = 3.6 V
IBUS = 100 mA
IBUS = 200 mA
5.08
VBAT = 4.2 V
90
85
5.06
VBUS - V
Efficiency - %
5.07
80
5.05
IBUS = 50 mA
5.04
75
5.03
5.02
70
0
50
100
150
Load Current at VBUS - mA
200
5.01
2.6
2.8
3
3.2
3.4
3.6
3.8
4
4.2
VBAT - V
Figure 19.
Figure 20.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
LOAD REGULATION FOR BOOST
5.09
VBAT = 2.7 V
VBAT = 3.6 V
5.08
5.07
VBUS
5.06
5.05
VBAT = 4.2 V
5.04
5.03
5.02
5.01
5
0
50
100
150
Load Current at VBUS - mA
200
Figure 21.
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FUNCTIONAL BLOCK DIAGRAM (Charge Mode)
PMID
bq24157
PMID
V PMID
PMID
NMOS
VBUS
NMOS
SW
VBUS
VBUS
SW
Q2
Q1
VREF 1
PWM
Controller
OSC
Charge
Pump
-
CBC
Current
Limiting
Q3
I LIMIT
-
+
V IN _ DPM
-
T CF
+
TJ
-
-
VREF
PWM _ CHG
V UVLO
-
V BUS
+
V IN(MIN)
-
Poor Input
Source
VBUS
+
VBUS OVP
V OVP_IN
-
TJ
+
VBUS UVLO
LINEAR
V OVP
-
*
_CHG
VREF
REFERNCES
& BIAS
CHARGE CONTROL
TIMER and DISPLAY
LOGIC
Thermal
Shutdown
+
CSIN
IOCHARGE
I SHORT
+
VOUT
CSOUT
V OREG
V CSIN
+
V BUS
T SHTDWN
V OUT
-
-
I IN _ LIMIT
NMOS
+
+
SW
VREF
BOOT
VREF 1
V PMID
VOUT
Battery OVP
STAT
V BAT
VBUS
VOREG - VRCH
PGND
PGND
VOUT
VOUT
VCSIN
I TERM
+
-
*
Sleep
CD
+
-
+
-
* Recharge
*
( I2 C Control )
Decoder
DAC
PGND
VBAT
VSHORT
+
-
OTG (bq 24153 /8)
SLRST(bq24156)
Termination
SCL
SDA
Charge
* PWMMode
* Signal Deglitched
Figure 22. Function Block Diagram of bq2415x in Charge Mode
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FUNCTIONAL BLOCK DIAGRAM (Boost Mode)
PMID
bq24157
PMID
V PMID
PMID
NMOS
VBUS
NMOS
SW
SW
SW
V BUS
VBUS
Q2
Q1
VREF 1
Charge
Pump
OSC
PWM
Controller
CBC
Current
Limiting
Q3
PFM Mode
I BO
-
NMOS
-
75 mA
+
+
VBUS_B
+
I BLIMIT
-
VREF
REFERNCES
& BIAS
PWM _ BOOST
V BUS
+
V BUSOVP
-
TJ
+
TSHTDWN
-
VOUT
+
VBATMAX
-
VBUS OVP
VREF
BOOT
VREF 1
VPMID
CSIN
Thermal
Shutdown
*
Battery OVP
V OUT
CHARGE CONTROL,
TIMER and DISPLAY
LOGIC
CSOUT
STAT
CD
PGND
PGND
V BAT
+
VBATMIN
-
*
*
Low Battery
OTG
( I2 C Control)
Decoder
DAC
Signal Deglitched
PGND
SCL
SDA
Figure 23. Function Block Diagram of bq2415x in Boost Mode
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OPERATIONAL FLOW CHART
Power Up
V BUS > V UVLO
V
POR
Load I 2 C Registers
with Default Value
CSOUT
< V LOWV
High Impedance Mode or Host
No
Controlled Operation Mode
Yes
Reset and Start
15-M inute T imer
Disable Charge
/CE = LOW
/CE = HIGH
Charge Configure
Mode
Any Charge State
Disable Charge
Wait Mode
Delay TINT
Indicate Power
not Good
Yes
No
Enable I SHORT
V CSOPUT <V SHORT ?
Yes
V BUS < V IN ( MIN ) ?
Indicate Short
Circuit condition
No
15- Minute
Timer Expired ?
No
Regulate
Input Current , Charge
Current or Voltage
Yes
Indicate Charge- In Progress
VBUS < V IN ( MIN ) ?
Yes
Yes
Turn Off Charge
Indicate Fault
Yes
/CE =HIGH
No
Turn Off Charge
No
Enable I DETECT for
t DETECT
15-Minute
Timer Expired ?
Battery Removed
No
V CSOUT < VOREG V RCH ?
Yes
Wait Mode
Delay T INT
Reset Charge
Parameters
Yes
No
VCSOUT < V SHORT ?
No
Charge Complete
15-Minute Timer
Active ?
No
Yes
Termination Enabled
I TERM detected
and VCSOUT >V OREG -V RCH
?
Indicate DONE
No
Yes
Charge Complete
V CSOUT < V OREG VRCH ?
High Impedance
Mode
Yes
Figure 24. Operational Flow Chart of bq2415x in Charge Mode
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DETAILED FUNCTIONAL DESCRIPTION
For a current restricted power source, such as a USB host or hub, a high efficiency converter is critical to fully
use the input power capacity for quickly charging the battery. Due to the high efficiency for a wide range of input
voltages and battery voltages, the switch mode charger is a good choice for high speed charging with less power
loss and better thermal management than a linear charger.
The bq24157 are highly integrated synchronous switch-mode chargers, featuring integrated FETs and small
external components, targeted at extremely space-limited portable applications powered by 1-cell Li-Ion or Lipolymer battery pack. Furthermore, bq24157 also has bi-directional operation to achieve boost function for USB
OTG support.
The bq24157 have three operation modes: charge mode, boost mode, and high impedance mode. In charge
mode, the IC supports a precision Li-ion or Li-polymer charging system for single-cell applications. In boost
mode, the IC boosts the battery voltage to VBUS for powering attached OTG devices. In high impedance mode,
the IC stops charging or boosting and operates in a mode with very low current from VBUS or battery, to
effectively reduce the power consumption when the portable device is in standby mode. Through I2C
communication with a host, referred to as "HOST" control/mode, the IC achieves smooth transition among the
different operation modes. Even when no I2C communication is available, the IC starts in default mode. During
default mode operation, the charger will still charge the battery but using each register's default values.
Input Voltage Protection
Input Overvoltage Protection
The IC provides a built-in input overvoltage protection to protect the device and other components against
damage if the input voltage (Voltage from VBUS to PGND) goes too high. When an input overvoltage condition is
detected, the IC turns off the PWM converter, sets fault status bits, and sends out a fault pulse from the STAT
pin. Once VBUS drops below the input overvoltage exit threshold, the fault is cleared and charge process
resumes.
Bad Adaptor Detection/Rejection
Although not shown in Figure 24, at power-on-reset (POR) of VBUS, the IC performs the bad adaptor detection
by applying a current sink to VBUS. If the VBUS is higher than VIN(MIN) for 30ms, the adaptor is good and the
charge process begins. Otherwise, if the VBUS drops below VIN(MIN), a bad adaptor is detected. Then, the IC
disables the current sink, sends a send fault pulse in FAULT pin and sets the bad adaptor flag (B2 - B0 = 011 for
Register 00H). After a delay of TINT, the IC repeats the adaptor detection process, as shown in Figure 25 and
Figure 26.
Adpator
V BUS
VBUS
ISHORT
(30 mA)
Adaptor Detection Control
VIN_GOOD
Deglitch
30ms
PGND
GND
START
VIN
VIN(MIN)
VIN_POOR
Delay
TINT
Figure 25. Bad Adaptor Detection Circuit
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Charge Command
(Host Control or VBUS
Ramps Up)
Delay 10mS
Enable Adaptor Detection
Start 30ms Timer
Enable Input Current Sink
(30mA, to GND)
No
VBUS>VIN(MIN)?
Yes
30ms Timer
Expired?
No
Yes
Bad Adaptor Detected
Good Adaptor Detected
Pulsing STAT Pin
Set Bad Adaptor Flag
Disable Adaptor Detection
Charge Start
Enable VIN Based DPM
Delay TINT
(2 Seconds)
Figure 26. Bad Adaptor Detection Scheme Flow Chart
Sleep Mode
The IC enters the low-power sleep mode if the VBUS pin voltage falls below the sleep-mode entry threshold,
VCSOUT+VSLP, and VBUS is higher than the bad adaptor detection threshold, VIN(MIN). This feature prevents
draining the battery during the absence of VBUS. During sleep mode, both the reverse blocking switch Q1 and
PWM are turned off.
Input Voltage Based DPM (Special Charger Voltage Threshold)
During the charging process, if the input power source is not able to support the programmed or default charging
current, the VBUS voltage will decrease. Once the VBUS drops to VIN_DPM (default 4.52V), the charge current
begins to taper down to prevent any further drop of VBUS. When the IC enters this mode, the charge current is
lower than the set value and the special charger bit is set (B4 in Register 05H). This feature makes the IC
compatible with adapters having different current capabilities.
BATTERY PROTECTION
Output Overvoltage Protection
The IC provides a built-in overvoltage protection to protect the device and other components against damage if
the battery voltage goes too high, as when the battery is suddenly removed. When an overvoltage condition is
detected, the IC turns off the PWM converter, sets fault status bits, and sends out a fault pulse from the STAT
pin. Once V(CSOUT) drops to the battery overvoltage exit threshold, the fault is cleared and charge process
resumes.
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Battery Short Protection
During the normal charging process, if the battery voltage is lower than the short-circuit threshold, VSHORT, the
charger operates in short circuit mode with a lower charge rate of ISHORT.
Battery Detection in Host Mode
For applications with removable battery packs, the IC provides a battery absent detection scheme to reliably
detect insertion or removal of battery packs.
During the normal charging process with host control, once the voltage at the CSOUT pin is above the battery
recharge threshold, VOREG- VRCH, and the termination charge current is detected, the IC turns off the PWM
charge and enables a discharge current, IDETECT, for a period of tDETECT, (262 ms typical) then checks the battery
voltage. If the battery voltage is still above the recharge threshold after tDETECT, the battery is present. On the
other hand, if the battery voltage is below the battery recharge threshold, the battery is absent. Under this
condition, the charge parameters (such as input current limit) are reset to the default values and charge resumes
after a delay of TINT. This function ensures that the charge parameters are reset whenever the battery is
replaced.
15-MINUTE SAFETY TIMER
The bq24157 stays in 15-minute (default) mode indefinitely until I2C communication begins. When I2C
communication begins, the host processor does not need to reset this 15 minutes timer while charging the
battery.
USB FRIENDLY POWER UP
The default control bits set the charging current and regulation voltage low as a safety feature to avoid violating
USB spec and over-charging any of the Li-Ion chemistries, while the host has lost communication. The input
current limiting is described below.
INPUT CURRENT LIMITING AT POWER UP
The input current sensing circuit and control loop are integrated into the IC. When operating in default mode, the
OTG pin logic level sets the input current limit to 100mA for a logic low and 500mA for a logic high. In host mode,
the input current limit is set by the programmed control bits in register 01H.
CHARGE MODE OPERATION
Charge Profile
Once a good battery with voltage below the recharge threshold has been inserted and a good adapter is
attached, the bq2415x enters charge mode. In charge mode, the IC has five control loops to regulate input
voltage, input current, charge current, charge voltage and device junction temperature. During the charging
process, all five loops are enabled and the one that is dominant takes control. The IC supports a precision Li-ion
or Li-polymer charging system for single-cell applications. Figure 27 (a) indicates a typical charge profile without
input current regulation loop. It is the traditional CC/CV charge curve, while Figure 27(b) shows a typical charge
profile when input current limiting loop is dominant during the constant current mode. In this case, the charge
current is higher than the input current so the charge process is faster than the linear chargers. The input voltage
threshold for DPM loop, input current limits, charge current, termination current, and charge voltage are all
programmable using I2C interface.
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Precharge
Phase
Current Regulation
Phase
Voltage Regulation
Phase
Regulation
Voltage
Regulation
Current
Charge Voltage
V SHORT
Charge Current
Termination
I SHORT
Precharge
(Linear Charge)
Fast Charge
(PWM Charge)
(a)
Precharge
Phase
Current Regulation
Phase
Voltage Regulation
Phase
Regulation
voltage
Charge Voltage
VSHORT
Charge Current
Termination
I SHORT
Precharge
(Linear Charge)
Fast Charge
(PWM Charge)
(b)
Figure 27. Typical Charging Profile for (a) without Input Current Limit, and (b) with Input Current Limit
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PWM Controller in Charge Mode
The IC provides an integrated, fixed 3 MHz frequency voltage-mode controller to regulate charge current or
voltage. This type of controller is used to improve line transient response, thereby, simplifying the compensation
network used for both continuous and discontinuous current conduction operation. The voltage and current loops
are internally compensated using a Type-III compensation scheme that provides enough phase margin for stable
operation, allowing the use of small ceramic capacitors with a low ESR. The device operates between 0% to
99.5% duty cycles.
The IC has back to back common-drain N-channel FETs at the high side and one N-channel FET at low side.
The input N-FET (Q1) prevents battery discharge when VBUS is lower than VCSOUT. The second high-side N-FET
(Q2) is the switching control switch. A charge pump circuit is used to provide gate drive for Q1, while a bootstrap
circuit with an external bootstrap capacitor is used to supply the gate drive voltage for Q2.
Cycle-by-cycle current limit is sensed through the FETs Q2 and Q3. The threshold for Q2 is set to a nominal 2.4A peak current. The low-side FET (Q3) also has a current limit that decides if the PWM Controller will operate in
synchronous or non-synchronous mode. This threshold is set to 100mA and it turns off the low-side N-channel
FET (Q3) before the current reverses, preventing the battery from discharging. Synchronous operation is used
when the current of the low-side FET is greater than 100mA to minimize power losses.
Battery Charging Process
At the beginning of precharge, while battery voltage is below the V(SHORT) threshold, the IC applies a short-circuit
current, I(SHORT), to the battery. When the battery voltage is above VSHORT and below VOREG, the charge current
ramps up to fast charge current, IOCHARGE, or a charge current that corresponds to the input current of IIN_LIMIT.
The slew rate for fast charge current is controlled to minimize the current and voltage over-shoot during transient.
Both the input current limit, IIN_LIMIT, and fast charge current, IOCHARGE, can be set by the host. Once the battery
voltage reaches the regulation voltage, VOREG, the charge current is tapered down as shown in Figure 27. The
voltage regulation feedback occurs by monitoring the battery-pack voltage between the CSOUT and PGND pins.
In HOST mode, the regulation voltage is adjustable (3.5V to 4.44V) and is programmed through I2C interface. In
15-minute mode, the regulation voltage is fixed at 3.54V.
The IC monitors the charging current during the voltage regulation phase. If termination is enabled, during the
normal charging process with HOST control, once the voltage at the CSOUT pin is above the battery recharge
threshold, VOREG- VRCH for the 32-ms (typical) deglitch period, and the termination charge current ITERM is
detected, the IC turns off the PWM charge and enables a discharge current, IDETECT, for a period of tDETECT (262ms typical), then checks the battery voltage. If the battery voltage is still above the recharge threshold after
tDETECT, the battery charging is complete. The battery detection routine is used to ensure termination did not
occur because the battery was removed. After 40ms (typical) for synchronization purposes of the EOC state and
the counter, the status bit and pin are updated to indicate charging has completed. The termination current level
is programmable. To disable the charge current termination, the host can set the charge termination bit (I_Term)
of charge control register to 0, refer to I2C section for detail.
A
•
•
•
new charge cycle is initiated when one of the following conditions is detected:
The battery voltage falls below the V(OREG) – V(RCH) threshold.
VBUS Power-on reset (POR), if battery voltage is below the V(LOWV) threshold.
CE bit toggle or RESET bit is set (Host controlled)
Thermal Regulation and Protection
To prevent overheating of the chip during the charging process, the IC monitors the junction temperature, TJ, of
the die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TCF. The
charge current is reduced to zero when the junction temperature increases approximately 10°C above TCF. In
any state, if TJ exceeds TSHTDWN, the IC suspends charging. In thermal shutdown mode, PWM is turned off and
all timers are frozen. Charging resumes when TJ falls below TSHTDWN by approximately 10°C.
Charge Status Output, STAT Pin
The STAT pin is used to indicate operation conditions. STAT is pulled low during charging when EN_STAT bit in
control register (00H) is set to “1”. Under other conditions, STAT pin behaves as a high impedance (open-drain)
output. Under fault conditions, a 128-µs pulse will be sent out to notify the host. The status of STAT pin at
different operation conditions is summarized in Table 1. The STAT pin can be used to drive an LED or
communicate to the host processor.
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Table 1. STAT Pin Summary
CHARGE STATE
STAT
Charge in progress and EN_STAT=1
Low
Other normal conditions
Open-drain
Charge mode faults: Timer fault, sleep mode, VBUS or battery overvoltage, poor input source,
VBUS UVLO, no battery, thermal shutdown
128-μs pulse, then open-drain
Boost mode faults: Timer fault, over load, VBUS or battery overvoltage, low battery voltage, thermal
shutdown
128-μs pulse, then open-drain
Control Bits in Charge Mode
CE Bit (Charge Mode)
The CE bit in the control register is used to disable or enable the charge process. A low logic level (0) on this bit
enables the charge and a high logic level (1) disables the charge.
RESET Bit
The RESET bit in the control register is used to reset all the charge parameters. Writing ‘1” to the RESET bit will
reset all the charge parameters to default values except the safety limit register, and RESET bit is automatically
cleared to zero once the charge parameters get reset. It is designed for charge parameter reset before charge
starts and it is not recommended to set the RESET bit while charging or boosting are in progress.
OPA_Mode Bit
OPA_MODE is the operation mode control bit. When OPA_MODE = 0, the IC operates as a charger if
HZ_MODE is set to "0", refer to Table 2 for detail. When OPA_MODE=1 and HZ_MODE=0, the IC operates in
boost mode.
Table 2. Operation Mode Summary
OPA_MODE
HZ_MODE
0
0
Charge (no fault)
Charge configure (fault, Vbus > UVLO)
High impedance (Vbus < UVLO)
OPERATION MODE
1
0
Boost (no faults)
Any fault go to charge configure mode
X
1
High impedance
CONTROL PINS IN CHARGE MODE
CD Pin (Charge Disable)
The CD pin is used to disable the charging process. When the CD pin is low, charge is enabled. When the CD
pin is high, charge is disabled and the charger enters high impedance (Hi-Z) mode.
BOOST MODE OPERATION
In host mode, when OTG pin is high (and OTG_EN bit is high thereby enabling OTG functionality) or the
operation mode bit (OPA_MODE) is set to 1, the device operates in boost mode and delivers the power to VBUS
from the battery. In normal boost mode converts the battery voltage to VBUS-B (about 5.05V) and delivers a
current as much as IBO (about 200mA) to support other USB OTG devices connected to the USB connector.
PWM Controller in Boost Mode
Similar to charge mode operation, in boost mode, the IC provides an integrated, fixed 3 MHz frequency voltagemode controller to regulate output voltage at PMID pin (VPMID). The voltage control loop is internally
compensated using a Type-III compensation scheme that provides enough phase margin for stable operation
with a wide load range and battery voltage range.
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In boost mode, the input N-FET (Q1) prevents battery discharge when VBUS pin is over loaded. Cycle-by-cycle
current limit is sensed through the internal sense FET for Q3. The cycle-by-cycle current limit threshold for Q3 is
set to a nominal 1.0-A peak current. Synchronous operation is used in PWM mode to minimize power losses.
Boost Start Up
To prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start
up.
PFM Mode at Light Load
In boost mode, under light load conditions, the IC operates in pulse skipping mode (PFM mode) to reduce the
power loss and improve the converter efficiency. During boosting, the PWM converter is turned off once the
inductor current is less than 75mA; and the PWM is turned back on only when the voltage at PMID pin drops to
about 99.5% of the rated output voltage. A unique pre-set circuit is used to make the smooth transition between
PWM and PFM mode.
Protection in Boost Mode
Output Overvoltage Protection
The IC provides a built-in over-voltage protection to protect the device and other components against damage if
the VBUS voltage goes too high. When an over-voltage condition is detected, the IC turns off the PWM
converter, resets OPA_MODE bit to 0, sets fault status bits, and sends out a fault pulse from the STAT pin. Once
VBUS drops to the normal level, the boost starts after host sets OPA_MODE to “1” or OTG pin stays in active
status.
Output Overload Protection
The IC provides a built-in over-load protection to prevent the device and battery from damage when VBUS is
over loaded. Once the over load condition is detected, Q1 operates in linear mode to limit the output current. If
the over load condition lasts for more than 30ms, the over-load fault is detected. When an over-load condition is
detected, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets fault status bits and sends out
fault pulse in STAT pin. The boost will not start until the host clears the fault register.
Battery Overvoltage Protection
During boosting, when the battery voltage is above the battery over voltage threshold, VBATMAX, or below the
minimum battery voltage threshold, VBATMIN, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets
fault status bits and sends out fault pulse in STAT pin. Once the battery voltage goes above VBATMIN, the boost
will start after the host sets OPA_MODE to “1” or OTG pin stays in active status.
STAT Pin in Boost Mode
During normal boosting operation, the STAT pin behaves as a high impedance (open-drain) output. Under fault
conditions, a 128-μs pulse is sent out to notify the host.
HIGH IMPEDANCE (Hi-Z) MODE
In Hi-Z mode, the charger stops charging and enters a low quiescent current state to conserve power. Taking the
CD pin high causes the charger to enter Hi-Z mode. When in default mode and the CD pin is low, the charger
automatically enters Hi-Z mode if
1. VBUS > UVLO and a battery with VBAT > VLOWV is inserted, or
2. VBUS falls below UVLO.
When in HOST mode and the CD is low, the charger can be placed into Hi-Z mode if the HZ-MODE control bit is
set to “1” and OTG pin is not in active status.
In order to exit Hi-Z mode, the CD pin must be low, VBUS must be higher than UVLO and the HOST must write
a "0" to the HZ-MODE control bit.
22
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SERIAL INTERFACE DESCRIPTION
I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus
through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The IC works as a slave and is compatible with the following data transfer modes, as defined in the I2C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write
mode). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements. Register contents remain intact as long as
supply voltage remains above 2.2 V (typical). I2C is asynchronous, which means that it runs off of SCL. The
device has no noise or glitch filtering on SCL, so SCL input needs to be clean. Therefore, it is recommended that
SDA changes while SCL is LOW.
The data transfer protocol for standard and fast modes is the same; therefore, they are referred to as F/S-mode
in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as HSmode. The bq24157B device supports 7-bit addressing only. The device 7-bit address is defined as ‘1101010’
(6AH).
F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 28. All I2C-compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 28. START and STOP Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 29). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 29) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 29. Bit Transfer on the Serial Interface
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The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 31). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to
prevent the slave I2C logic from getting stuck in a bad state. Attempting to read data from register addresses not
listed in this section will result in FFh being read out.
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
9
8
2
Clock Pulse for
Acknowledgement
START
Condition
Figure 30. Acknowledge on the I2C Bus™
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgement
Signal From Slave
MSB
Sr
Address
R/W
SCL
S
or
Sr
ACK
ACK
Sr
or
P
Clock Line Held Low While
Interrupts are Serviced
Figure 31. Bus Protocol
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H/S Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of
the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be
used to secure the bus in HS-mode. If a transaction is terminated prematurely, the master needs sending a
STOP condition to prevent the slave I2C logic from getting stuck in a bad state.
Attempting to read data from register addresses not listed in this section results in FFh being read out.
I2C Update Sequence
The IC requires a start condition, a valid I2C address, a register address byte, and a data byte for a single
update. After the receipt of each byte, the IC acknowledges by pulling the SDA line low during the high period of
a single clock pulse. A valid I2C address selects the IC. The IC performs an update on the falling edge of the
acknowledge signal that follows the LSB byte.
For the first update, the IC requires a start condition, a valid I2C address, a register address byte, a data byte.
For all consecutive updates, The IC needs a register address byte, and a data byte. Once a stop condition is
received, the IC releases the I2C bus, and awaits a new start conditions.
S
SLAVE ADDRESS
R/W
A
REGISTER ADDRESS
A
DATA
A/A
P
Data Transferred
(n Bytes + Acknowledge)
‘0’ (Write)
From master to IC
A
A
From IC to master
S
Sr
P
= Acknowledge (SDA LOW)
= Not acknowledge (SDA
HIGH)
= START condition
= Repeated START condition
= STOP condition
(a) F/S-Mode
F/S-Mode
S
F/S-Mode
HS-Mode
HS-MASTER CODE
A
Sr
SLAVE ADDRESS
R/W
A
REGISTER ADDRESS
A
DATA
A/A
Data Transferred
(n Bytes + Acknowledge)
‘0’ (write)
P
HS-Mode
Continues
Sr
Slave A.
(b) HS- Mode
Figure 32. Data Transfer Format in F/S Mode and H/S Mode
Slave Address Byte
MSB
X
LSB
1
1
0
1
0
1
1
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The slave address byte is the first byte received following the START condition from the master device.
Register Address Byte
MSB
LSB
0
0
0
0
0
D2
D1
D0
Following the successful acknowledgment of the slave address, the bus master will send a byte to the IC, which
contains the address of the register to be accessed. The IC contains five 8-bit registers accessible via a
bidirectional I2C-bus interface. Among them, four internal registers have read and write access; and one has only
read access.
REGISTER DESCRIPTION
Table 3. Status/Control Register (Read/Write)
Memory Location: 00, Reset State: x1xx 0xxx
BIT
NAME
READ/WRITE
FUNCTION
B7 (MSB)
TMR_RST/OTG
Read/Write
Write: TMR_RST function, write "1" to reset the safety timer (auto clear)
Read: OTG pin status, 0-OTG pin at Low level, 1-OTG pin at High level
B6
EN_STAT
Read/Write
0-Disable STAT pin function, 1-Enable STAT pin function (default 1)
B5
STAT2
Read Only
B4
STAT1
Read Only
B3
BOOST
Read Only
1-Boost mode, 0-Not in boost mode
B2
FAULT_3
Read Only
B1
FAULT_2
Read Only
B0 (LSB)
FAULT_1
Read Only
Charge mode: 000-Normal, 001-VBUS OVP, 010-Sleep mode, 011-Bad Adaptor or
VBUS<VUVLO,
100-Output OVP, 101-Thermal shutdown, 110-Timer fault, 111-No battery
Boost mode: 000-Normal, 001-VBUS OVP, 010-Over load, 011-Battery voltage is too low,
100-Battery OVP, 101-Thermal shutdown, 110-Timer fault, 111-NA
00-Ready, 01-Charge in progress, 10-Charge done, 11-Fault
Table 4. Control Register (Read/Write)
Memory Location: 01, Reset State: 0011 0000
BIT
NAME
READ/WRITE
B7 (MSB)
Iin_Limit_2
Read/Write
B6
Iin_Limit_1
Read/Write
00-USB host with 100-mA current limit, 01-USB host with 500-mA current limit, 10USB host/charger with 800-mA current limit, 11-No input current limit
B5
B4
FUNCTION
V(LOWV_2)
(1)
Read/Write
Weak battery voltage threshold: 200mV step (default 1)
V(LOWV_1)
(1)
Read/Write
Weak battery voltage threshold: 100mV step (default 1)
B3
TE
Read/Write
1-Enable charge current termination, 0-Disable charge current termination (default 0)
B2
CE
Read/Write
1-Charger is disabled, 0-Charger enabled (default 0)
B1
HZ_MODE
Read/Write
1-High impedance mode, 0-Not high impedance mode (default 0)
B0 (LSB)
OPA_MODE
Read/Write
1-Boost mode, 0-Charger mode (default 0)
(1)
The range of the weak battery voltage threshold (V(LOWV)) is 3.4 V to 3.7 V with an offset of 3.4 V and steps of 100 mV (default 3.7 V,
using bits B4-B5).
Table 5. Control/Battery Voltage Register (Read/Write)
Memory Location: 02, Reset State: 0000 1010
26
BIT
NAME
READ/WRITE
B7 (MSB)
VO(REG5)
Read/Write
Battery Regulation Voltage: 640 mV step (default 0)
FUNCTION
B6
VO(REG4)
Read/Write
Battery Regulation Voltage: 320 mV step (default 0)
B5
VO(REG3)
Read/Write
Battery Regulation Voltage: 160 mV step (default 0)
B4
VO(REG2)
Read/Write
Battery Regulation Voltage: 80 mV step (default 0)
B3
VO(REG1)
Read/Write
Battery Regulation Voltage: 40 mV step (default 1)
B2
VO(REG0)
Read/Write
Battery Regulation Voltage: 20 mV step (default 0)
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Table 5. Control/Battery Voltage Register (Read/Write)
Memory Location: 02, Reset State: 0000 1010 (continued)
BIT
•
NAME
READ/WRITE
FUNCTION
B1
OTG_PL
Read/Write
1-OTG Boost Enable with High level, 0-OTG Boost Enable with Low level (default 1);
not applicable to OTG pin control of current limit at POR in default mode
B0 (LSB)
OTG_EN
Read/Write
1-Enable OTG Pin in HOST mode, 0-Disable OTG pin in HOST mode (default 0), not
applicable to OTG pin control of current limit at POR in default mode
Charge voltage range is 3.5 V to 4.44 V with the offset of 3.5 V and steps of 20 mV (default 3.54 V), using
bits B2-B7.
Table 6. Vender/Part/Revision Register (Read only)
Memory Location: 03, Reset State: 0101 000x
BIT
NAME
READ/WRITE
B7 (MSB)
Vender2
Read Only
Vender Code: bit 2 (default 0)
FUNCTION
B6
Vender1
Read Only
Vender Code: bit 1 (default 1)
B5
Vender0
Read Only
Vender Code: bit 0 (default 0)
B4
PN1
Read Only
B3
PN0
Read Only
B2
Revision2
Read Only
B1
Revision1
Read Only
B0 (LSB)
Revision0
Read Only
For I2C Address 6AH: 01–NA, 10–bq24157, 11–NA.
011: Revision 1.0;
001: Revision 1.1;
100-111: Future Revisions
Table 7. Battery Termination/Fast Charge Current Register (Read/Write)
Memory Location: 04, Reset State: 0000 0001
BIT
NAME
READ/WRITE
B7 (MSB)
Reset
Read/Write
Write: 1-Charger in reset mode, 0-No effect, Read: always get "0"
B6
VI(CHRG3) (1)
Read/Write
Charge current sense voltage: 27.2 mV step
B5
VI(CHRG2) (1)
Read/Write
Charge current sense voltage: 13.6 mV step
B4
VI(CHRG1)
(1)
Read/Write
Charge current sense voltage: 6.8 mV step
B3
VI(CHRG0)
(1)
Read/Write
NA
B2
VI(TERM2)
(2)
Read/Write
Termination current sense voltage: 13.6 mV step (default 0)
B1
VI(TERM1) (2)
Read/Write
Termination current sense voltage: 6.8 mV step (default 0)
(2)
Read/Write
Termination current sense voltage: 3.4 mV step (default 1)
B0 (LSB)
(1)
(2)
•
VI(TERM0)
FUNCTION
See Table 11
See Table 10
Charge current sense voltage offset is 37.4mV and default charge current is 550mA, if 68-mΩ sensing
resistor is used and LOW_CHG=0.
Table 8. Special Charger Voltage/Enable Pin Status Register
Memory location: 05, Reset state: 000X X100
BIT
NAME
READ/WRITE
B7 (MSB)
NA
Read/Write
NA
FUNCTION
B6
NA
Read/Write
NA
B5
LOW_CHG
Read/Write
0 – Normal charge current sense voltage at 04H,
1 – Low charge current sense voltage of 22.1mV (default 0)
B4
DPM_STATUS
Read Only
0 – DPM mode is not active,
1 – DPM mode is active
B3
CD_STATUS
Read Only
0 – CD pin at LOW level,
1 – CD pin at HIGH level
B2
VSREG2
Read/Write
Special charger voltage: 320mV step (default 1)
B1
VSREG1
Read/Write
Special charger voltage: 160mV step (default 0)
B0 (LSB)
VSREG0
Read/Write
Special charger voltage: 80mV step (default 0)
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Special charger voltage offset is 4.2V and default special charger voltage is 4.52V.
Default charge current will be 550mA, if 68-mΩ sensing resistor is used, since default LOW_CHG=0.
Table 9. Safety Limit Register (READ/WRITE, Write only once after reset!)
Memory location: 06, Reset state: 01000000
(1)
•
•
•
•
BIT
NAME
READ/WRITE
B7 (MSB)
VMCHRG3 (1)
Read/Write
Maximum charge current sense voltage: 54.4 mV step (default 0) (2)
FUNCTION
B6
VMCHRG2 (1)
Read/Write
Maximum charge current sense voltage: 27.2 mV step (default 1)
B5
VMCHRG1 (1)
Read/Write
Maximum charge current sense voltage: 13.6 mV step (default 0)
B4
VMCHRG0
(1)
Read/Write
Maximum charge current sense voltage: 6.8 mV step (default 0)
B3
VMREG3
Read/Write
Maximum battery regulation voltage: 160 mV step (default 0)
B2
VMREG2
Read/Write
Maximum battery regulation voltage: 80 mV step (default 0)
B1
VMREG1
Read/Write
Maximum battery regulation voltage: 40 mV step (default 0)
B0 (LSB)
VMREG0
Read/Write
Maximum battery regulation voltage: 20 mV step (default 0)
Refer to Table 11
Maximum charge current sense voltage offset is 37.4 mV (550mA), default at 64.6mV (950mA) and the
maximum charge current option is 1.55A (105.4mV), if 68-mΩ sensing resistor is used.
Maximum battery regulation voltage offset is 4.2V (default at 4.2V) and maximum battery regulation voltage
option is 4.44V.
Memory location 06H resets only when V(CSOUT) drops below V(SHORT) threshold (typ. 2.05V). After reset, the
maximum values for battery regulation voltage and charge current can be programmed until any writing to
other register locks the safety limits. Programmed values exclude higher values from memory locations 02
(battery regulation voltage), and from memory location 04 (Fast charge current).
If host accesses (write command) to some other register before Safety limit register, the safety default values
are used.
APPLICATION SECTION
Charge Current Sensing Resistor Selection Guidelines
Both the termination current range and charge current range depend on the sensing resistor (RSNS). The
termination current step (IOTERM_STEP) can be calculated using Equation 1:
IO(TERM_STEP) =
VI(TERM0)
R(SNS)
(1)
Table 10 shows the termination current settings for three sensing resistors.
Table 10. Termination Current Settings for 55-mΩ, 68-mΩ, 100-mΩ Sense Resistors
BIT
VI(TERM) (mV)
I(TERM) (mA)
R(SNS) = 55mΩ
I(TERM) (mA)
R(SNS) = 68mΩ
I(TERM) (mA)
R(SNS) = 100mΩ
VI(TERM2)
13.6
247
200
136
VI(TERM1)
6.8
124
100
68
VI(TERM0)
3.4
62
50
34
Offset
3.4
62
50
34
For example, with a 68-mΩ sense resistor, V(ITERM2)=1, V(ITERM1)=0, and V(ITERM0)=1, ITERM = [ (13.6mV x 1) +
(6.8mV x 0) + (3.4mV x 1) + 3.4mV ] / 68mΩ = 200mA + 0 + 50mA + 50mA = 300mA.
The charge current step (IO(CHARGE_STEP)) is calculated using Equation 2:
IO(CHARGE_STEP) =
28
VI(CHRG0)
R(SNS)
(2)
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Table 11 shows the charge current settings for three sensing resistors.
Table 11. Charge Current Settings for 55-mΩ, 68-mΩ and 100-mΩ Sense Resistors
BIT
VI(REG) (mV)
IO(CHARGE) (mA)
R(SNS) = 55mΩ
IO(CHARGE) (mA)
R(SNS) = 68mΩ
IO(CHARGE) (mA)
R(SNS) = 100mΩ
VI(CHRG3)
54.4
989
800
544
VI(CHRG2)
27.2
495
400
272
VI(CHRG1)
13.6
247
200
136
VI(CHRG0)
6.8
124
100
68
Offset
37.4
680
550
374
For example, with a 68-mΩ sense resistor, V(CHRG3)=1, V(CHRG2)=0, V(ICHRG1)=0, and V(ICHRG0)=1, ITERM = [
(54.4mV x 1) + (27.2mV x 0) + (13.6mV x 0) + (6.8mV x 1) + 37.4mV ] / 68mΩ = 800mA + 0 + 0 + 100mA =
900mA.
Output Inductor and Capacitance Selection Guidelines
The IC provides internal loop compensation. With the internal loop compensation, the highest stability occurs
when the LC resonant frequency, fo, is approximately 40 kHz (20 kHz to 80 kHz). Equation 3 can be used to
calculate the value of the output inductor, LOUT, and output capacitor, COUT.
fo =
1
2p ´
LOUT ´ COUT
(3)
To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 4.7 μF and 47 μF is
recommended for COUT, see the application section for components selection.
POWER TOPOLOGIES
System Load After Sensing Resistor
One of the simpler high-efficiency topologies connects the system load directly across the battery pack, as
shown in Figure 33. The input voltage has been converted to a usable system voltage with good efficiency from
the input. When the input power is on, it supplies the system load and charges the battery pack at the same time.
When the input power is off, the battery pack powers the system directly.
SW
VBUS
L1
VIN
+
-
Isys
Isns
Rsns
Ichg
bq2415x
C1
PMID
+
PGND
C4
C3
System
Load
BAT
C2
Figure 33. System Load After Sensing Resistor
The advantages:
1. When the AC adapter is disconnected, the battery pack powers the system load with minimum power
dissipation. Consequently, the time that the system runs on the battery pack can be maximized.
2. It reduces the number of external path selection components and offers a low-cost solution.
3. Dynamic power management (DPM) can be achieved. The total of the charge current and the system current
can be limited to a desired value by setting the charge current value. When the system current increases, the
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charge current drops by the same amount. As a result, no potential over-current or over-heating issues are
caused by excessive system load demand.
4. The total input current can be limited to a desired value by setting the input current limit value. USB
specifications can be met easily.
5. The supply voltage variation range for the system can be minimized.
6. The input current soft-start can be achieved by the generic soft-start feature of the IC.
Design considerations and potential issues:
1. If the system always demands a high current (but lower than the regulation current), the battery charging
never terminates. Thus, the battery is always charged, and its lifetime may be reduced.
2. Because the total current regulation threshold is fixed and the system always demands some current, the
battery may not be charged with a full-charge rate and thus may lead to a longer charge time.
3. If the system load current is large after the charger has been terminated, the IR drop across the battery
impedance may cause the battery voltage to drop below the refresh threshold and start a new charge cycle.
The charger would then terminate due to low charge current. Therefore, the charger would cycle between
charging and terminating. If the load is smaller, the battery has to discharge down to the refresh threshold,
resulting in a much slower cycling.
4. In a charger system, the charge current is typically limited to about 30mA, if the sensed battery voltage is
below 2V short circuit protection threshold. This results in low power availability at the system bus. If an
external supply is connected and the battery is deeply discharged, below the short circuit protection
threshold, the charge current is clamped to the short circuit current limit. This then is the current available to
the system during the power-up phase. Most systems cannot function with such limited supply current, and
the battery supplements the additional power required by the system. Note that the battery pack is already at
the depleted condition, and it discharges further until the battery protector opens, resulting in a system
shutdown.
5. If the battery is below the short circuit threshold and the system requires a bias current budget lower than the
short circuit current limit, the end-equipment will be operational, but the charging process can be affected
depending on the current left to charge the battery pack. Under extreme conditions, the system current is
close to the short circuit current levels and the battery may not reach the fast-charge region in a timely
manner. As a result, the safety timers flag the battery pack as defective, terminating the charging process.
Because the safety timer cannot be disabled, the inserted battery pack must not be depleted to make the
application possible.
6. If the battery pack voltage is too low, highly depleted, totally dead or even shorted, the system voltage is
clamped by the battery and it cannot operate even if the input power is on.
DESIGN EXAMPLE FOR TYPICAL APPLICATION CIRCUIT
Systems Design Specifications:
•
•
•
•
1.
VBUS = 5 V
VBAT = 4.2 V (1-Cell)
I(charge) = 1.25 A
Inductor ripple current = 30% of fast charge current
Determine the inductor value (LOUT) for the specified charge current ripple:
L OUT =
VBAT ´ (VBUS - VBAT)
VBUS ´ f ´ D IL
, the worst case is when battery voltage is as close as to half of the input
voltage.
LOUT =
2.5 ´ (5 - 2.5)
5 ´ (3 ´ 106 ) ´ 1.25 ´ 0.3
(4)
LOUT = 1.11 μH
Select the output inductor to standard 1 μH. Calculate the total ripple current with using the 1-μH inductor:
30
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DIL =
VBAT ´ (VBUS - VBAT)
VBUS ´ f ´ LOUT
(5)
2.5 ´ (5 - 2.5)
DIL =
5 ´ (3 ´ 106 ) ´ (1 ´ 10-6 )
(6)
ΔIL = 0.42 A
Calculate the maximum output current:
DIL
ILPK = IOUT +
2
(7)
0.42
ILPK = 1.25 +
2
(8)
ILPK = 1.46 A
Select 2.5mm by 2mm 1-μH 1.5-A surface mount multi-layer inductor. The suggested inductor part numbers
are shown as following.
Table 12. Inductor Part Numbers
PART NUMBER
INDUCTANCE
SIZE
MANUFACTURER
LQM2HPN1R0MJ0
1 μH
2.5 x 2.0 mm
Murata
MIPS2520D1R0
1 μH
2.5 x 2.0 mm
FDK
MDT2520-CN1R0M
1 μH
2.5 x 2.0 mm
TOKO
CP1008
1 μH
2.5 x 2.0 mm
Inter-Technical
2. Determine the output capacitor value (COUT) using 40 kHz as the resonant frequency:
fo =
1
2p ´
COUT =
COUT =
LOUT ´ COUT
(9)
1
4p2 ´ f02 ´ LOUT
1
(10)
4p2 ´ (40 ´ 103 )2 ´ (1 ´ 10-6 )
(11)
COUT = 15.8 μF
Select two 0603 X5R 6.3V 10-μF ceramic capacitors in parallel i.e., Murata GRM188R60J106M.
3. Determine the sense resistor using the following equation:
V(RSNS)
R(SNS) =
I(CHARGE)
(12)
The maximum sense voltage across the sense resistor is 85 mV. In order to get a better current regulation
accuracy, V(RSNS) should equal 85mV, and calculate the value for the sense resistor.
85mV
R(SNS) =
1.25A
(13)
R(SNS) = 68 mΩ
This is a standard value. If it is not a standard value, then choose the next close value and calculate the real
charge current. Calculate the power dissipation on the sense resistor:
P(RSNS) = I(CHARGE) 2 × R(SNS)
P(RSNS) = 1.252 × 0.068
P(RSNS) = 0.106 W
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Select 0402 0.125-W 68-mΩ 2% sense resistor, i.e. Panasonic ERJ2BWGR068.
4. Measured efficiency and total power loss with different inductors are shown in Figure 34. SW node and
inductor current waveform are shown in Figure 35.
Battery Charge Efficiency
Battery Charge Loss
90
800
FDK
Efficiency - %
88
87
86
TA=25°C,
VBUS = 5 V,
VBAT = 3 V
TA=25°C,
VBUS = 5 V,
VBAT = 3 V
600
muRata
Inter-Technical
85
Inter-Technical
500
TOKO
FDK
400
muRata
300
84
200
83
82
500
700
Loss - mW
TOKO
89
600
700
800 900 1000 1100 1200 1300
Charge Current - mA
100
500
600
700
800 900 1000 1100 1200 1300
Charge Current - mA
Figure 34. Measured Efficiency and Power Loss
PCB LAYOUT CONSIDERATION
It is important to pay special attention to the PCB layout. The following provides some guidelines:
• To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed
as close as possible to the pin. The output inductor should be placed close to the IC and the output capacitor
connected between the inductor and PGND of the IC. The intent is to minimize the current path loop area
from the SW pin through the LC filter and back to the PGND pin. To prevent high frequency oscillation
problems, proper layout to minimize high frequency current path loop is critical. (See Figure 35.) The sense
resistor should be adjacent to the junction of the inductor and output capacitor. Route the sense leads
connected across the RSNS back to the IC, close to each other (minimize loop area) or on top of each other
on adjacent layers (do not route the sense leads through a high-current path). (See Figure 36.)
• Place all decoupling capacitors close to their respective IC pins and close to PGND (do not place components
such that routing interrupts power stage currents). All small control signals should be routed away from the
high current paths.
• The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, two vias for the IC PGND, one via per capacitor for smallsignal components). A star ground design approach is typically used to keep circuit block currents isolated
(high-power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A single
ground plane for this design gives good results. With this small layout and a single ground plane, there is no
ground-bounce issue, and having the components segregated minimizes coupling between signals.
• The high-current charge paths into VBUS, PMID and from the SW pins must be sized appropriately for the
maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
• Place 4.7μF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current
loop area as small as possible. Place 1μF input capacitor as close to VBUS pin and PGND pin as possible to
make high frequency current loop area as small as possible (see Figure 37).
32
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SLUSB80 – SEPTEMBER 2012
L1
VBUS
SW
R1
V BAT
High
Frequency
BAT
V IN
Current
Path
PMID
PGND
C3
C2
C1
Figure 35. High Frequency Current Path
Charge Current Direction
R SNS
To Inductor
To Capacitor and battery
Current Sensing Direction
To CSIN and CSOUT pin
Figure 36. Sensing Resistor PCB Layout
VBUS
PMID
SW
Vin+
1µF
Vin–
4.7µF
PGND
Figure 37. Input Capacitor Position and PCB Layout Example
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PACKAGE SUMMARY
CHIP SCALE PACKAGE
(Top Side Symbol For bq24157)
TIYMLLLLS
bq24157A
WCSP PACKAGE
(Top View)
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
E1
E2
E3
E4
D
E
0-Pin A1 Marker, TI-TI Letters, YM- Year Month Date Code, LLLL-Lot Trace Code, S-Assembly Site Code
CHIP SCALE PACKAGING DIMENSIONS
The bq24157 device is available in a 20-bump chip scale package (YFF, NanoFree™).
The package dimensions are:
34
D
E
Max = 2.17mm
Max = 2.03 mm
Min = 2.11 mm
Min = 1.97 mm
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Nov-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Samples
(3)
(Requires Login)
BQ24157YFFR
ACTIVE
DSBGA
YFF
20
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
BQ24157YFFT
ACTIVE
DSBGA
YFF
20
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Nov-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
BQ24157YFFR
DSBGA
YFF
20
3000
180.0
8.4
BQ24157YFFT
DSBGA
YFF
20
250
180.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.2
2.35
0.8
4.0
8.0
Q1
2.2
2.35
0.8
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Nov-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24157YFFR
DSBGA
YFF
20
3000
210.0
185.0
35.0
BQ24157YFFT
DSBGA
YFF
20
250
210.0
185.0
35.0
Pack Materials-Page 2
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