MC10EP17, MC100EP17 3.3V / 5VECL Quad Differential Driver/Receiver The MC10/100EP17 is a 4-bit differential line receiver based on the EP16 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications. Inputs of unused gates can be left open and will not affect the operation of the rest of the device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The 100 Series contains temperature compensation. • 220 ps Typical Propagation Delay • Maximum Frequency >3.0 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V • http://onsemi.com MARKING DIAGRAMS* 20 20 XXXX EP17 ALYW 1 TSSOP–20 DT SUFFIX CASE 948E 1 20 20 MCXXXEP17 AWLYYWW 1 SO–20 DW SUFFIX CASE 751D with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = –3.0 V to –5.5 V Open Input Default State XXXX XXX A L, WL Y, YY W, WW • • Safety Clamp on Inputs • Q Output Will Default LOW with Inputs Open or at VEE • VBB Output 1 = MC10 or 100 = 10 or 100 = Assembly Location = Assembly Lot = Wafer Lot = Year = Work Week *For additional information, see Application Note AND8002/D ORDERING INFORMATION Device Semiconductor Components Industries, LLC, 2002 September, 2002 – Rev. 4 1 Package Shipping MC10EP17DT TSSOP–20 75 Units/Rail MC10EP17DTR2 TSSOP–20 2500 Tape & Reel MC100EP17DT TSSOP–20 MC100EP17DTR2 TSSOP–20 2500 Tape & Reel 75 Units/Rail MC10EP17DW SO–20 38 Units/Rail MC10EP17DWR2 SO–20 1000 Tape & Reel MC100EP17DW SO–20 38 Units/Rail MC100EP17DWR2 SO–20 1000 Tape & Reel Publication Order Number: MC10EP17/D MC10EP17, MC100EP17 VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE 20 19 18 17 16 15 14 13 12 11 PIN DESCRIPTION PIN FUNCTION D[0:3]*, D[0:3]* ECL Differential Data Inputs Q[0:3], Q[0:3] ECL Differential Data Outputs VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply * Pins will default LOW when left open. 1 2 3 4 5 6 7 8 9 10 VCC D0 D0 D1 D1 D2 D2 D3 D3 VBB Figure 1. 20–Lead Pinout (Top View) and Logic Diagram ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor ESD Protection N/A Human Body Model Machine Model Charged Device Model > 2 kV > 100 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Level 1 Oxygen Index: 28 to 34 UL94 V–0 @ 0.125 in Transistor Count 259 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. MAXIMUM RATINGS (Note 2) Parameter Symbol Condition 1 Condition 2 Rating Units VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V –6 V VI PECL Mode In Input ut Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 –6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range –40 to +85 °C Tstg Storage Temperature Range –65 to +150 °C JA Thermal Resistance (Junction–to–Ambient) 0 LFPM 500 LFPM 20 TSSOP 20 TSSOP 140 100 °C/W °C/W JC Thermal Resistance (Junction–to–Case) std bd 20 TSSOP 23 to 41 °C/W JA Thermal Resistance (Junction–to–Ambient) 0 LFPM 500 LFPM 20 SOIC 20 SOIC 90 60 °C/W °C/W JC Thermal Resistance (Junction–to–Case) std bd 20 SOIC 30 to 35 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C 2. Maximum Ratings are those values beyond which device damage may occur. http://onsemi.com 2 VI VCC VI VEE MC10EP17, MC100EP17 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3) Symbol IEE Characteristic Power Supply Current Min –40°C Typ Max Min 25°C Typ Max Min 85°C Typ Max 42 50 65 44 52 66 46 54 68 Unit mA VOH Output HIGH Voltage (Note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV VOL Output LOW Voltage (Note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV VIH Input HIGH Voltage (Single–Ended) 2090 2415 2155 2480 2215 2540 mV VIL Input LOW Voltage (Single–Ended) 365 1690 1430 1755 1490 1815 mV VBB Output Voltage Reference 1790 1990 1855 2055 1915 2115 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 5) 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 A IIL Input LOW Current 1890 2.0 1955 150 2015 150 0.5 0.5 A 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –2.2 V. 4. All loading with 50 to VCC–2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6) Symbol IEE Characteristic Power Supply Current Min –40°C Typ Max Min 25°C Typ Max Min 85°C Typ Max 42 50 65 44 52 66 46 54 68 Unit mA VOH Output HIGH Voltage (Note 7) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV VOL Output LOW Voltage (Note 7) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV VIH Input HIGH Voltage (Single–Ended) 3790 4115 3855 4180 3915 4240 mV VIL Input LOW Voltage (Single–Ended) 3065 3390 3130 3455 3190 3515 mV VBB Output Voltage Reference 3490 3690 3555 3755 3615 3815 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 8) 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 A IIL Input LOW Current 3590 2.0 3655 150 3715 150 0.5 0.5 A 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to –0.5 V. 7. All loading with 50 to VCC–2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = –5.5 V to –3.0 V (Note 9) Min –40°C Typ Max Min 25°C Typ Max Min 85°C Typ Max 42 50 65 44 52 66 46 54 68 Unit mA Output HIGH Voltage (Note 10) –1135 –1010 –885 –1070 –945 –820 –1010 –885 –760 mV Output LOW Voltage (Note 10) –1935 –1810 –1685 –1870 –1745 –1620 –1810 –1685 –1560 mV VIH Input HIGH Voltage (Single–Ended) –1210 –885 –1145 –820 –1085 –760 mV VIL Input LOW Voltage (Single–Ended) –1935 –1610 –1870 –1545 –1810 –1485 mV VBB Output Voltage Reference –1510 –1310 –1445 –1245 –1385 –1185 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 11) 0.0 V IIH Input HIGH Current 150 A IIL Input LOW Current Symbol IEE Characteristic Power Supply Current VOH VOL –1410 VEE+2.0 0.0 VEE+2.0 150 0.5 –1345 0.0 VEE+2.0 150 0.5 –1285 0.5 A NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 to VCC–2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 3 MC10EP17, MC100EP17 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12) Symbol IEE Characteristic Power Supply Current Min –40°C Typ Max Min 25°C Typ Max Min 85°C Typ Max 47 55 63 50 58 66 54 62 70 Unit mA VOH Output HIGH Voltage (Note 13) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 13) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VIH Input HIGH Voltage (Single–Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single–Ended) 1355 1675 1355 1675 1355 1675 mV VBB Output Voltage Reference 1775 1975 1775 1975 1775 1975 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 14) 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 A IIL Input LOW Current 1875 2.0 1875 150 1875 150 0.5 0.5 A 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –2.2 V. 13. All loading with 50 to VCC–2.0 volts. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15) Symbol IEE Characteristic Power Supply Current Min –40°C Typ Max Min 25°C Typ Max Min 85°C Typ Max 47 55 63 50 58 66 54 62 70 Unit mA VOH Output HIGH Voltage (Note 16) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV VOL Output LOW Voltage (Note 16) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV VIH Input HIGH Voltage (Single–Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single–Ended) 3055 3375 3055 3375 3055 3375 mV VBB Output Voltage Reference 3475 3675 3475 3675 3475 3675 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 17) 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 A 3575 2.0 3575 150 3575 150 IIL Input LOW Current 0.5 0.5 0.5 A NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to –0.5 V. 16. All loading with 50 to VCC–2.0 volts. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = –5.5 V to –3.0 V (Note 18) Min –40°C Typ Max Min 25°C Typ Max Min 85°C Typ Max 47 55 63 50 58 66 54 62 70 Unit mA Output HIGH Voltage (Note 19) –1145 –1020 –895 –1145 –1020 –895 –1145 –1020 –895 mV Output LOW Voltage (Note 19) –1945 –1820 –1695 –1945 –1820 –1695 –1945 –1820 –1695 mV VIH Input HIGH Voltage (Single–Ended) –1225 –880 –1225 –880 –1225 –880 mV VIL Input LOW Voltage (Single–Ended) –1945 –1625 –1945 –1625 –1945 –1625 mV VBB Output Voltage Reference –1525 –1325 –1525 –1325 –1525 –1325 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 20) 0.0 V IIH Input HIGH Current 150 A Symbol IEE Characteristic Power Supply Current VOH VOL –1425 VEE+2.0 0.0 150 –1425 VEE+2.0 0.0 150 –1425 VEE+2.0 IIL Input LOW Current 0.5 0.5 0.5 A NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 to VCC–2.0 volts. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 MC10EP17, MC100EP17 AC CHARACTERISTICS VCC = 0 V; VEE = –3.0 V to –5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21) –40°C Symbol Min Characteristic fmax Maximum Frequency (See Figure 2 Fmax/JITTER) tPLH, tPHL Propagation Delay to Output Differential 10 Series 100 Series tJITTER Cycle–to–Cycle Jitter (See Figure 2 Fmax/JITTER) VPP Input Voltage Swing (Differential) tr tf Output Rise/Fall Times (20% – 80%) Typ 25°C Max Min >3 Q, Q Typ 85°C Max Min Typ >3 >3 200 220 275 300 .2 <1 150 800 1200 100 160 220 150 180 220 250 300 320 .2 <1 150 800 1200 100 170 230 200 200 260 290 350 360 .2 <1 ps 150 800 1200 mV 120 190 250 ps 8 700 7 600 6 500 5 400 4 300 3 ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉ ÉÉ 200 2 100 1 (JITTER) 0 2000 JITTEROUT ps (RMS) VOUTpp (mV) 800 1000 Unit GHz ps 125 150 21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC–2.0 V. 0 Max 3000 4000 FREQUENCY (MHz) Figure 2. Fmax/Jitter http://onsemi.com 5 5000 6000 MC10EP17, MC100EP17 Q D Receiver Device Driver Device Q D 50 50 V TT V TT = V CC – 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 – Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 – ECLinPS Circuit Performance at Non–Standard VIH Levels AN1405 – ECL Clock Distribution Techniques AN1406 – Designing with PECL (ECL at +5.0 V) AN1504 – Metastability and the ECLinPS Family AN1568 – Interfacing Between LVDS and ECL AN1650 – Using Wire–OR Ties in ECLinPS Designs AN1672 – The ECL Translator Guide AND8001 – Odd Number Counters Design AND8002 – Marking and Date Codes AND8009 – ECLinPS Plus Spice I/O Model Kit AND8020 – Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. http://onsemi.com 6 MC10EP17, MC100EP17 PACKAGE DIMENSIONS TSSOP–20 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E–02 ISSUE A 20X 0.15 (0.006) T U 2X K REF 0.10 (0.004) S M 20 L/2 T U V S S K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ 11 B L J J1 –U– PIN 1 IDENT SECTION N–N 1 10 0.25 (0.010) N 0.15 (0.006) T U S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. ICONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. M A –V– N F DETAIL E –W– C G D H DETAIL E 0.100 (0.004) –T– SEATING DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 PLANE SO–20 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D–05 ISSUE F A 20 X 45 h 1 10 20X B B 0.25 M T A S B S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 18X e A1 SEATING PLANE C T http://onsemi.com 7 DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0 7 MC10EP17, MC100EP17 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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